Anti-fuse device and memory thereof

Abstract

The embodiment of the invention discloses an anti-fuse device and a memory thereof. The anti-fuse device includes: an anti-fuse array including: a plurality of anti-fuse cells; the programming control circuit is coupled with the anti-fuse array through a sensing node and comprises a first transistor and an electric leakage suppression circuit, the first end of the first transistor is coupled with the sensing node, the input end of the electric leakage suppression circuit is coupled with the control end of the first transistor, and the output end of the electric leakage suppression circuit is coupled with the second end of the first transistor; wherein when programming operation is executed on the anti-fuse unit, the output end of the electric leakage suppression circuit is at a first voltage level; when the read operation is executed on the anti-fuse unit, the output end of the electric leakage suppression circuit is at a second voltage level; the second voltage level is greater than the first voltage level.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of integrated circuits, and in particular to an anti-fuse device and a memory thereof. Background Art

[0002] One-Time Programmable (OTP) devices include fuse devices and anti-fuse devices. Anti-fuse devices include multiple anti-fuse units. When the anti-fuse unit is not programmed, the anti-fuse unit is in a high impedance state, which is recorded as logic "0"; when the anti-fuse unit is programmed, the anti-fuse unit is in a low impedance state, which is recorded as logic "1".

[0003] The logic information (e.g., logic "0" or "1") stored in the anti-fuse unit can be read out by sensing the magnitude of the read electrical signal (e.g., read voltage). However, during the reading process, due to the existence of leakage, the anti-fuse unit may fail to read or data inversion may occur. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, an anti-fuse device is provided, including:

[0005] An anti-fuse array comprises: a plurality of anti-fuse units;

[0006] A programming control circuit is coupled to the anti-fuse array through a sensing node, and includes: a first transistor and a leakage suppression circuit, wherein the first end of the first transistor is coupled to the sensing node, the input end of the leakage suppression circuit is coupled to the control end of the first transistor, and the output end of the leakage suppression circuit is coupled to the second end of the first transistor; wherein, when a programming operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when a reading operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; and the second voltage level is greater than the first voltage level.

[0007] In some embodiments, the leakage suppression circuit includes at least one inverter; the inverter includes:

[0008] a second transistor, wherein a first terminal of the second transistor is coupled to a power source, a second terminal of the second transistor is coupled to an output terminal of the inverter, and a control terminal of the second transistor is coupled to a control terminal of the first transistor; wherein the power source is used to provide the second voltage level;

[0009] A third transistor, wherein a first terminal of the third transistor is coupled to the output terminal of the inverter, a second terminal of the third transistor is coupled to the ground terminal, and a control terminal of the third transistor is coupled to the control terminal of the first transistor; wherein the ground terminal is used to provide the first voltage level.

[0010] In some embodiments, the leakage suppression circuit includes a plurality of the inverters; wherein the plurality of the inverters are connected in parallel.

[0011] In some embodiments, a type of the first transistor is the same as a type of the third transistor, and a type of the first transistor is different from a type of the second transistor.

[0012] In some embodiments, a size of the first transistor is larger than a size of the second transistor.

[0013] In some embodiments, a size of the third transistor is greater than or equal to a size of the second transistor.

[0014] In some embodiments, the anti-fuse device further includes: a comparator; wherein a first input terminal of the comparator is coupled to the anti-fuse array through the sensing node, and a second input terminal of the comparator is used to receive a reference voltage.

[0015] In some embodiments, the first voltage level is a ground level;

[0016] The second voltage level is greater than the reference voltage and less than or equal to a precharge level of the sensing node.

[0017] In some embodiments, when the programming operation is performed on the anti-fuse unit, the control terminal of the first transistor is at a third voltage level; wherein the third voltage level is greater than the first voltage level, and the third voltage level is greater than the second voltage level.

[0018] According to a second aspect of the embodiments of the present disclosure, a memory is provided, comprising an anti-fuse device as described in any of the above embodiments.

[0019] In the embodiment of the present disclosure, a leakage suppression circuit is provided in the programming control circuit, and the output end of the leakage suppression circuit is connected to the second end of the first transistor. When a programming operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when a read operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; since the second voltage level is greater than the first voltage level, when a read operation is performed on the anti-fuse unit, the high level at the output end of the leakage suppression circuit can reduce the leakage of the first transistor, which is beneficial to reducing the probability of reading failure or data inversion of the anti-fuse device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a circuit structure diagram of an anti-fuse device according to an exemplary embodiment;

[0021] Figure 2 is a schematic diagram showing a read voltage of an anti-fuse device according to an exemplary embodiment;

[0022] Figure 3 is a circuit structure diagram of an anti-fuse device according to an embodiment of the present disclosure;

[0023] Figure 4 is a schematic diagram of a read voltage of an anti-fuse device according to an embodiment of the present disclosure;

[0024] Figure 5 is a circuit structure diagram of another anti-fuse device according to an embodiment of the present disclosure;

[0025] Figure 6 It is a flow chart of an operation method of an anti-fuse device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0027] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0028] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0029] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0030] Figure 1 FIG. 1 is a circuit structure diagram of an anti-fuse device 100 according to an exemplary embodiment. Figure 1As shown, the anti-fuse device 100 includes an anti-fuse array 110 and a programming control circuit 120; wherein the anti-fuse array 110 includes a plurality of anti-fuse units, for example, an anti-fuse unit 111 and an anti-fuse unit 112; and the programming control circuit 120 is used to perform a programming operation on the anti-fuse array 110. The programming control circuit 120 includes a transistor 121, and when a programming operation is performed on an anti-fuse unit selected in the anti-fuse array, the transistor 121 is turned on to provide a ground level to the selected anti-fuse unit, thereby forming a breakdown voltage difference.

[0031] The anti-fuse device 100 further includes a pre-charge circuit 130 , which can pre-charge the sensing node before the comparator 141 is enabled.

[0032] The anti-fuse device 100 further includes a read circuit 140, wherein the read circuit 140 is used to perform a read operation on the anti-fuse array 110. The read circuit includes a comparator 141, when a read operation is performed on a selected anti-fuse unit in the anti-fuse array 110, the transistor 121 is turned off, a first input terminal of the comparator 141 is used to receive a read voltage, and a second input terminal of the comparator 141 is used to receive a reference voltage.

[0033] The anti-fuse array 110 further includes column selection transistors, which are respectively connected to a plurality of column address lines. The control terminals of the column selection transistors are used to receive column address signals (eg, Y <0> , Y <1> , ...Y <n>), the column selection transistor includes an N-type transistor (NMOS), and the NMOS transistor is used to select multiple column address lines through the received column address signal; in some embodiments, the column selection transistor also includes a P-type transistor (PMOS), and the PMOS transistor is used to ground the column address line where the unselected anti-fuse unit is located, thereby avoiding accidental start-up or entering a floating state, which is beneficial to reducing the power consumption of the anti-fuse device.

[0034] However, during the reading operation, the transistor 121 may leak electricity, resulting in Figure 1 The leakage path shown in the figure causes charge leakage, which causes the read voltage to decrease over time and cannot maintain the target voltage. Figure 2 As shown by the middle curve L1, during the period from T1 to T2 (ie, the sensing period), when the value of the read voltage is lower than the fault sensing point A, the anti-fuse unit may fail to read or data inversion may occur.

[0035] In view of this, embodiments of the present disclosure provide an anti-fuse device, an operation method thereof, and a memory.

[0036] Figure 3 is a circuit structure diagram of an anti-fuse device 200 according to an embodiment of the present disclosure. Figure 3 As shown, the anti-fuse device 200 comprises:

[0037] An anti-fuse array comprises: a plurality of anti-fuse units;

[0038] The programming control circuit 220 is coupled to the anti-fuse array through the sensing node q, and includes: a first transistor 221 and a leakage suppression circuit 222, wherein the first end d of the first transistor 221 is coupled to the sensing node q, the input end b of the leakage suppression circuit 222 is coupled to the control end a of the first transistor 221, and the output end c of the leakage suppression circuit 222 is coupled to the second end e of the first transistor 221; wherein, when a programming operation is performed on the anti-fuse unit, the output end c of the leakage suppression circuit 222 is at a first voltage level; when a reading operation is performed on the anti-fuse unit, the output end c of the leakage suppression circuit 222 is at a second voltage level; and the second voltage level is greater than the first voltage level.

[0039] The anti-fuse array includes a plurality of anti-fuse units, each of which includes a programming transistor and a selection transistor, wherein the programming transistor and the selection transistor are connected in series. Figure 1 The anti-fuse unit includes a programming transistor Fs <0> 、Fs <1> and select transistor X <0> , X <1> , programming transistor Fs <0> and select transistor X <0> It can form an anti-fuse unit 111, a programming transistor Fs <1> and select transistor X <1> It can form an anti-fuse unit 112. It should be noted that the embodiment of the present disclosure has no special limitation on the number of anti-fuse units in the anti-fuse array, and a plurality of anti-fuse units arranged in an array along the row direction and the column direction can form an anti-fuse array.

[0040] The anti-fuse device also includes a plurality of row address lines and a plurality of column address lines; wherein each row address line extends in the row direction and is coupled to the control terminals of a plurality of selection transistors; each column address line extends in the column direction and is coupled to a plurality of anti-fuse units; for example, a row address line is respectively coupled to the control terminals of a plurality of selection transistors located in the same row, and a column address line is respectively coupled to a plurality of anti-fuse units located in the same column. Here, the direction in which the row address line extends can be defined as the "row direction", and the direction in which the column address line extends can be defined as the "column direction".

[0041] Reference Figure 3 As shown, the anti-fuse device also includes a plurality of column selection transistors, which are respectively connected to a plurality of column address lines. The control end of the column selection transistor is used to receive a column address signal (for example, Y <0> , Y <1> , ...Y <n>), the column selection transistor includes an N-type transistor (NMOS), and the NMOS transistor is used to select multiple column address lines through the received column address signal; in some embodiments, the column selection transistor also includes a P-type transistor (PMOS), and the PMOS transistor is used to ground the column address line where the unselected anti-fuse unit is located, thereby avoiding accidental start-up or entering a floating state, which is beneficial to reducing the power consumption of the anti-fuse device.

[0042] In some embodiments, the anti-fuse device also includes multiple row selection transistors (not shown in the figure), which are respectively connected to multiple row address lines. The control end of the row selection transistor is used to receive a row address signal for selecting at least one of the multiple row address lines. The row selection transistor includes a P-type transistor; in some embodiments, the row selection transistor also includes an N-type transistor.

[0043] The program control circuit 220 is coupled to the antifuse array through the sensing node q. For example, the program control circuit 220 is coupled to the antifuse array through the column address line. The program control circuit 220 can perform a program operation on the selected antifuse unit in the antifuse array in response to a program control signal.

[0044] In some embodiments, the anti-fuse device includes a plurality of anti-fuse arrays and a plurality of programming control circuits, each programming control circuit is respectively coupled to each anti-fuse array. For example, each column address line in the same anti-fuse array is respectively coupled to the sensing node q through a different column selection transistor, and the column address lines of different anti-fuse arrays are coupled to different sensing nodes.

[0045] In some embodiments, the anti-fuse device includes a plurality of programming control circuits, and the plurality of programming control circuits are respectively coupled to the anti-fuse array through a plurality of sensing nodes; wherein at least one of the plurality of programming control circuits includes a leakage suppression circuit. Here, the leakage suppression circuit may be provided in part of the programming control circuits, or in each programming control circuit, so as to reduce the probability of the anti-fuse device reading failure or data reversal.

[0046] The first transistor 221 includes a first terminal d, a second terminal e, and a control terminal a located between the first terminal d and the second terminal e; wherein the first terminal d is coupled to the sensing node q, the control terminal a is used to receive a programming control signal, and the second terminal e is coupled to the output terminal c of the leakage suppression circuit 222. The first transistor 221 can be a P-type transistor or an N-type transistor, the first terminal d can be the source or drain of the first transistor 221, the second terminal e can be the drain or source of the first transistor 221, and the control terminal a can be the gate of the first transistor 221. In the embodiment of the present disclosure, the first transistor 221 is described as an NMOS as an example.

[0047] The leakage suppression circuit 222 includes an input terminal b and an output terminal c, wherein the input terminal b and the control terminal a of the first transistor 221 are commonly coupled to the input terminal p of the programming control circuit 220, and the output terminal c is coupled to the second terminal e of the first transistor 221. When the anti-fuse unit is programmed, the control terminal a of the first transistor 221 receives the programming control signal and sets it to a high level, the first transistor 221 is turned on, the input terminal b of the leakage suppression circuit 222 receives the programming control signal and sets it to a high level, and outputs a low level, i.e., a first voltage level; when the anti-fuse unit is read, the control terminal a of the first transistor 221 receives the programming control signal and sets it to a low level, the first transistor 221 is turned off, the input terminal b of the leakage suppression circuit 222 receives the programming control signal and sets it to a low level, and outputs a high level, i.e., a second voltage level. Since the output terminal c of the leakage suppression circuit 222 is coupled to the second terminal e of the first transistor 221, the second terminal e of the first transistor 221 can be in a high level state when the read operation is performed, thereby reducing the charge leakage when the read operation is performed.

[0048] In the embodiment of the present disclosure, a leakage suppression circuit is provided in the programming control circuit, and the output end of the leakage suppression circuit is connected to the second end of the first transistor. When a programming operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when a read operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; since the second voltage level is greater than the first voltage level, when a read operation is performed on the anti-fuse unit, the high level at the output end of the leakage suppression circuit can reduce the leakage of the first transistor, which is beneficial to reducing the probability of reading failure or data inversion of the anti-fuse device.

[0049] In some embodiments, reference Figure 3 As shown, the leakage suppression circuit 222 includes at least one inverter 222a; the inverter 222a includes:

[0050] a second transistor 222-1, wherein a first terminal g of the second transistor 222-1 is coupled to a power source, a second terminal h of the second transistor 222-1 is coupled to an output terminal c of the inverter 222a, and a control terminal f of the second transistor 222-1 is coupled to a control terminal a of the first transistor 221; wherein the power source is used to provide a second voltage level;

[0051] The third transistor 222-2, the first terminal j of the third transistor 222-2 is coupled to the output terminal c of the inverter 222a, the second terminal k of the third transistor 222-2 is coupled to the ground terminal, and the control terminal i of the third transistor 222-2 is coupled to the control terminal a of the first transistor 221; wherein the ground terminal is used to provide a first voltage level.

[0052] In a specific embodiment, the input terminal b can be either the input terminal of the inverter 222 a or the input terminal of the leakage suppression circuit 222 , and the output terminal c can be either the output terminal of the inverter 222 a or the output terminal of the leakage suppression circuit 222 .

[0053] The second transistor 222-1 includes a first terminal g, a second terminal h, and a control terminal f located between the first terminal g and the second terminal h; wherein the first terminal g is coupled to a power supply, the power supply is used to provide a second voltage level, for example, 0.8V to 1.2V, the control terminal f is used to receive a signal from the input terminal b of the inverter 222a, for example, a programming control signal, and the second terminal h is coupled to the output terminal c of the inverter 222a. The second transistor 222-1 can be a P-type transistor or an N-type transistor, the first terminal g can be a source or a drain of the second transistor 222-1, the second terminal h can be a drain or a source of the second transistor 222-1, and the control terminal f can be a gate of the second transistor 222-1. In the embodiment of the present disclosure, the second transistor 222-1 is described as a PMOS as an example.

[0054] The third transistor 222-2 includes a first terminal j, a second terminal k, and a control terminal i located between the first terminal j and the second terminal k; wherein the first terminal j is coupled to the output terminal c of the inverter 222a, the control terminal i is used to receive a signal from the input terminal b of the inverter 222a, for example, a programming control signal, and the second terminal k is coupled to the ground terminal, and the ground terminal is used to provide a first voltage level, for example, 0V. The third transistor 222-2 can be a P-type transistor or an N-type transistor, the first terminal j can be the source or drain of the third transistor 222-2, the second terminal k can be the drain or source of the third transistor 222-2, and the control terminal i can be the gate of the third transistor 222-2. In the embodiment of the present disclosure, the third transistor 222-2 is described as an NMOS.

[0055] The control terminal f of the second transistor 222-1 and the control terminal i of the third transistor 222-2 are commonly coupled to the input terminal b of the leakage suppression circuit 222, and the input terminal b of the leakage suppression circuit 222 and the control terminal a of the first transistor 221 are commonly coupled to the input terminal p of the programming control circuit 220. In this way, the control terminal f of the second transistor 222-1 can be coupled to the control terminal a of the first transistor 221 through the input terminal b of the leakage suppression circuit 222, and the control terminal i of the third transistor 222-2 can be coupled to the control terminal a of the first transistor 221 through the input terminal b of the leakage suppression circuit 222.

[0056] Since the control terminal f of the second transistor 222-1 is coupled to the control terminal a of the first transistor 221, when the control terminal a of the first transistor 221 receives a programming control signal, the control terminal f of the second transistor 222-1 can also receive the programming control signal and be turned on or off in response to the level of the programming control signal; since the control terminal i of the third transistor 222-2 is coupled to the control terminal a of the first transistor 221, when the control terminal a of the first transistor 221 receives a programming control signal, the control terminal i of the third transistor 222-2 can also receive the programming control signal and be turned off or on in response to the level of the programming control signal.

[0057] Here, the second transistor 222-1 and the third transistor 222-2 constitute an inverter 222a.

[0058] For example, the second transistor 222-1 is a PMOS and the third transistor 222-2 is an NMOS. When the anti-fuse unit is programmed, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a high level, the first transistor 221 is turned on, the control terminal f of the second transistor 222-1 receives a programming control signal and sets it to a high level, the second transistor 222-1 is turned off, the control terminal i of the third transistor 222-2 receives a programming control signal and sets it to a high level, the third transistor 222-2 is turned on, so that the first transistor 221 is coupled to the ground terminal through the third transistor 222-2, and the second terminal e of the first transistor 221 is at a low level, that is, the first voltage level.

[0059] When a read operation is performed on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal set to a low level, the first transistor 221 is turned off, the control terminal f of the second transistor 222-1 receives a programming control signal set to a low level, the second transistor 222-1 is turned on, the control terminal i of the third transistor 222-2 receives a programming control signal set to a low level, and the third transistor 222-2 is turned off. In this way, the first transistor 221 can be coupled to the power supply through the second transistor 222-1, and the second terminal e of the first transistor 221 is at a high level, that is, the second voltage level.

[0060] It should be pointed out that when performing a read operation, the first transistor 221 may generate a leakage current, resulting in charge leakage, so that the read voltage is reduced. Here, by setting the first end g of the second transistor 222-1 to be coupled to the power supply, when performing a read operation, the first transistor 221 can be coupled to the power supply through the second transistor 222-1. The high level VDD provided by the power supply can reduce the current leakage during reading, which is beneficial to reducing the probability of anti-fuse device reading failure or data inversion due to charge leakage during the reading process.

[0061] It should be noted that the second transistor 222-1 is a PMOS and the third transistor 222-2 is an NMOS in the embodiment of the present disclosure, so as to convey the present disclosure to those skilled in the art. In other embodiments, the second transistor 222-1 may be an NMOS and the third transistor may be a PMOS.

[0062] In the embodiment of the present disclosure, an inverter is set in the programming control circuit, the inverter includes a second transistor and a third transistor, and the first end of the second transistor is coupled to the power supply, the second end of the second transistor is coupled to the output end of the inverter, the first end of the third transistor is coupled to the output end of the inverter, and the second end of the third transistor is coupled to the ground end. When performing a programming operation, the first transistor can be coupled to the ground end through the third transistor, and the ground end provides a low level; when performing a reading operation, the first transistor can be coupled to the power supply through the second transistor, and the power supply provides a high level; without affecting the programming operation of the anti-fuse unit, the charge leakage of the anti-fuse unit reading process can be reduced, thereby reducing the probability of anti-fuse device reading failure or data inversion.

[0063] In some embodiments, the type of the first transistor 221 is the same as the type of the third transistor 222-2, and the type of the first transistor 221 is different from the type of the second transistor 222-1. For example, the first transistor 221 is an N-type transistor, the second transistor 222-1 is a P-type transistor, and the third transistor 222-2 is an N-type transistor. For another example, the first transistor 221 is a P-type transistor, the second transistor 222-1 is an N-type transistor, and the third transistor 222-2 is a P-type transistor.

[0064] It is understandable that the specific types of the first transistor 221, the second transistor 222-1, and the third transistor 222-2 are not particularly limited in the embodiments of the present disclosure. It is only necessary to satisfy that the first transistor 221 and the third transistor 222-2 are of the same type, and the first transistor 221 and the second transistor 222-1 are of different types. Those skilled in the art can make reasonable choices according to actual needs. In the embodiments of the present disclosure, the first transistor 221 and the third transistor 222-2 are N-type transistors, and the second transistor 222-1 is a P-type transistor.

[0065] In some embodiments, the size of the first transistor 221 is larger than the size of the second transistor 222 - 1 .

[0066] In some embodiments, the size of the third transistor 222 - 2 is greater than or equal to the size of the second transistor 222 - 1 .

[0067] It should be noted that the sizes of the first transistor 221 and the third transistor 222-2 can be selected to be larger transistors. In some embodiments, the size of the third transistor 222-2 can be equal to the size of the second transistor 222-1. In other embodiments, the size of the third transistor 222-2 can be larger than the size of the second transistor 222-1. When performing a programming operation on the anti-fuse unit, since the sizes of the first transistor 221 and the third transistor 222-2 are larger, the conduction current of the first transistor 221 and the third transistor 222-2 can be increased, which is more conducive to the operation of the anti-fuse device.

[0068] In some embodiments, reference Figure 3 As shown, the anti-fuse device 200 further includes: a comparator 241; a first input terminal of the comparator 241 is coupled to the anti-fuse array through a sensing node q, and a second input terminal of the comparator 241 is used to receive a reference voltage.

[0069] The comparator 241 includes a first input terminal and a second input terminal, wherein the first input terminal is coupled to the anti-fuse array and is used to receive the read voltage; the second input terminal is used to receive a reference voltage; the comparator 241 also includes an output terminal, and the output voltage at the output terminal can indicate whether the read voltage at the first input terminal is greater than or less than the reference voltage at the second input terminal. For example, when the read voltage at the first input terminal is greater than the reference voltage at the second input terminal, the output voltage can be a positive voltage; when the read voltage at the first input terminal is less than the reference voltage at the second input terminal, the output voltage can be a negative voltage.

[0070] In some embodiments, the comparator 241 may be an operational amplifier for comparing the voltage read out of the first input terminal with the reference voltage of the second input terminal. Here, the voltage at the output terminal of the comparator 241 may be used to determine whether the reading is normal.

[0071] In some embodiments, reference Figure 3 As shown, the anti-fuse device 200 includes: a read circuit 240 coupled to the anti-fuse array; wherein the read circuit 240 includes a comparator 241 and other circuit structures not shown, which can be configured by those skilled in the art according to actual needs.

[0072] In some embodiments, the first voltage level is a ground level; and the second voltage level is greater than a reference voltage and less than or equal to a precharge level of the sensing node q.

[0073] In a specific embodiment, the first voltage level is 0V; and the second voltage level ranges from 0.8V to 1.2V.

[0074] In some embodiments, the anti-fuse device 200 includes: a pre-charge circuit 230 coupled to the anti-fuse array. For example, the pre-charge circuit 230 is coupled to the anti-fuse array through a sensing node q, and the pre-charge circuit 230 can perform a pre-charge operation on the sensing node q in response to a pre-charge control signal to pre-charge the sensing node q to a pre-charge level.

[0075] In some embodiments, when performing a programming operation on the anti-fuse unit, the control terminal a of the first transistor 221 is at a third voltage level; wherein the third voltage level is greater than the first voltage level, and the third voltage level is greater than the second voltage level.

[0076] In one example, the first transistor 221 is an N-type transistor, the second transistor 222-1 is a P-type transistor, and the third transistor 222-2 is an N-type transistor. When performing a programming operation on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a high level, and the second terminal e of the first transistor 221 is coupled to the ground terminal through the third transistor 222-2 and is at a first voltage level, for example, 0V, and the first voltage level is less than the high level received by the control terminal a of the first transistor 221. It can be understood that in this example, the third voltage level is a high level.

[0077] In another example, the first transistor 221 is a P-type transistor, the second transistor 222-1 is an N-type transistor, and the third transistor 222-2 is a P-type transistor. When performing a programming operation on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a low level, and the second terminal e of the first transistor 221 is coupled to the ground terminal through the third transistor 222-2 and is at a first voltage level, for example, 0V, and the first voltage level is less than the low level received by the control terminal a of the first transistor 221. It can be understood that in this example, the third voltage level is a low level.

[0078] It should be noted that the second voltage level is less than or equal to the precharge level of the sensing node. Therefore, when the anti-fuse unit is programmed, the third voltage level applied to the control terminal of the first transistor is greater than the second voltage level.

[0079] Figure 4 1 is a schematic diagram of a read voltage of an anti-fuse device according to an embodiment of the present disclosure. L2 represents a schematic diagram of a read voltage sensed when the programming control circuit includes a leakage suppression circuit in the embodiment of the present disclosure; L1 represents a schematic diagram of a read voltage sensed when the programming control circuit does not include a leakage suppression circuit.

[0080] Reference Figure 4 As shown, in the T1 to T2 stage (i.e., the sensing stage), when the programming control circuit does not include a leakage suppression circuit, the read voltage decreases over time and is lower than the fault sensing point A, and the anti-fuse unit may fail to read or data inversion may occur; when the programming control circuit includes a leakage suppression circuit, although the value of the read voltage decreases over time, it is still greater than the reference voltage, i.e., higher than the fault sensing point. It can be understood that the programming control circuit including the leakage suppression circuit provided in the embodiment of the present disclosure can reduce the charge leakage caused by the leakage of the first transistor, which is conducive to reducing the probability of the anti-fuse device failing to read or data inversion.

[0081] Figure 5 is a circuit structure diagram of another anti-fuse device according to an embodiment of the present disclosure. Figure 5 As shown, Figure 5 The first transistor 321, the precharge circuit 330 and the read circuit 340 shown in FIG. Figure 3 The first transistor 221, the precharge circuit 230 and the read circuit 240 shown in FIG. 2 are similar and will not be described in detail herein. Figure 3 The structure shown is different in that Figure 5 The leakage suppression circuit 322 in the embodiment includes at least two inverters; wherein at least two inverters are connected in parallel. Figure 5 As shown, the leakage suppression circuit 322 includes an inverter 322a, an inverter 322b and an inverter 322c. It should be noted that the number of inverters in the leakage suppression circuit 322 is not limited to Figure 5 The 3 shown can also be 2, 4 or more.

[0082] Reference Figure 5 As shown, the leakage suppression circuit 322 includes an inverter 322a, an inverter 322b and an inverter 322c. The inverter 322a includes an input terminal b and an output terminal c, the inverter 322b includes an input terminal m and an output terminal n, and the inverter 322c includes an input terminal u and an output terminal v; wherein the input terminal b of the inverter 322a, the input terminal m of the inverter 322b, and the input terminal u of the inverter 322c are all coupled to the control terminal a of the first transistor 321, and the output terminal c of the inverter 322a, the output terminal n of the inverter 322b, and the output terminal v of the inverter 322c are all coupled to the second terminal e of the first transistor 321.

[0083] In the disclosed embodiment, a plurality of inverters connected in parallel are provided in the leakage suppression circuit, so that when a programming operation is performed on the anti-fuse unit, the conduction current of the first transistor is larger, and when a reading operation is performed on the anti-fuse unit, the level of the output end of the leakage suppression circuit is higher, which can further reduce the leakage of the first transistor and is more conducive to reducing the probability of anti-fuse device reading failure or data reversal.

[0084] Based on the above anti-fuse device, an embodiment of the present disclosure further provides an operation method of the anti-fuse device.

[0085] Figure 6 is a flow chart of an operation method of an anti-fuse device according to an embodiment of the present disclosure. The anti-fuse array includes a plurality of anti-fuse units. Figure 6 As shown, the operation method at least includes the following steps:

[0086] S401: when performing a programming operation on the anti-fuse unit, turning on the first transistor and making the output end of the leakage suppression circuit at a first voltage level; wherein the first end of the first transistor is coupled to the anti-fuse array through a sensing node, the second end of the first transistor is coupled to the output end of the leakage suppression circuit, and the control end of the first transistor is coupled to the input end of the leakage suppression circuit;

[0087] S402: When performing a read operation on the anti-fuse unit, turning off the first transistor and making the output end of the leakage suppression circuit at a second voltage level; wherein the second voltage level is greater than the first voltage level.

[0088] Combination Figure 1 and Figure 3 As shown, the anti-fuse array 110 includes a plurality of anti-fuse units, each of which is composed of a programming transistor and a selection transistor, and the plurality of anti-fuse units are arranged in an array along the row direction and the column direction.

[0089] In step S401, when a programming operation is performed on the anti-fuse unit, the control terminal of the first transistor receives a programming control signal at a high level, the first transistor is turned on, the input terminal of the leakage suppression circuit receives a programming control signal at a high level, and outputs a low level, that is, a first voltage level.

[0090] In step S402, when the anti-fuse unit is read, the control terminal of the first transistor receives the programming control signal and sets it to a low level, the first transistor is turned off, the input terminal of the leakage suppression circuit receives the programming control signal and sets it to a low level, and outputs a high level, that is, a second voltage level. Since the output terminal c of the leakage suppression circuit 222 is coupled to the second terminal e of the first transistor 221, the second terminal e of the first transistor 221 can be in a high level state when the read operation is performed, thereby reducing the charge leakage when the read operation is performed.

[0091] In the embodiment of the present disclosure, when performing a programming operation on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when performing a read operation on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; since the second voltage level is greater than the first voltage level, when performing a read operation on the anti-fuse unit, the high level at the output end of the leakage suppression circuit can reduce the leakage of the first transistor, which is beneficial to reducing the probability of anti-fuse device reading failure or data inversion.

[0092] In some embodiments, the leakage suppression circuit includes at least one inverter, and the above step S401 includes: when performing a programming operation, turning off the second transistor and turning on the third transistor; wherein the inverter includes a second transistor and a third transistor, a first end of the third transistor is coupled to the output end of the inverter, a second end of the third transistor is coupled to the ground end, a control end of the third transistor is coupled to the control end of the first transistor, and the ground end is used to provide a first voltage level.

[0093] Combination Figure 3 As shown, when the anti-fuse unit performs a programming operation, the control terminal a of the first transistor 221 receives the programming control signal and sets it to a high level, the first transistor 221 is turned on, the control terminal f of the second transistor 222-1 receives the programming control signal and sets it to a high level, the second transistor 222-1 is turned off, and the control terminal i of the third transistor 222-2 receives the programming control signal and sets it to a high level, and the third transistor 222-2 is turned on. In this way, the first transistor 221 can be coupled to the ground terminal through the third transistor 222-2, and the second terminal e of the first transistor 221 is at a low level, that is, the first voltage level.

[0094] In some embodiments, the above step S402 includes: when performing a read operation, turning on the second transistor and turning off the third transistor; wherein the first end of the second transistor is coupled to a power supply, the second end of the second transistor is coupled to the output end of the inverter, the control end of the second transistor is coupled to the control end of the first transistor, and the power supply is used to provide a second voltage level.

[0095] Combination Figure 3 As shown, when the anti-fuse unit performs a read operation, the control terminal a of the first transistor 221 receives a programming control signal set to a low level, the first transistor 221 is turned off, the control terminal f of the second transistor 222-1 receives a programming control signal set to a low level, the second transistor 222-1 is turned on, the control terminal i of the third transistor 222-2 receives a programming control signal set to a low level, and the third transistor 222-2 is turned off, so that the first transistor 221 can be coupled to the power supply through the second transistor 222-1, and the second terminal e of the first transistor 221 is at a high level, that is, the second voltage level.

[0096] It should be pointed out that when performing a read operation, the first transistor 221 may generate a leakage current, resulting in charge leakage, so that the read voltage is reduced. Here, by setting the first end g of the second transistor 222-1 to be coupled to the power supply, when performing a read operation, the first transistor 221 can be coupled to the power supply through the second transistor 222-1. The high level VDD provided by the power supply can reduce the current leakage during reading, which is beneficial to reducing the probability of anti-fuse device reading failure or data inversion due to charge leakage during the reading process.

[0097] In some embodiments, the type of the first transistor is the same as the type of the third transistor, and the type of the first transistor is different from the type of the second transistor. For example, the first transistor 221 is an N-type transistor, the second transistor 222-1 is a P-type transistor, and the third transistor 222-2 is an N-type transistor. For another example, the first transistor 221 is a P-type transistor, the second transistor 222-1 is an N-type transistor, and the third transistor 222-2 is a P-type transistor.

[0098] In some embodiments, the above-mentioned turning off the second transistor and turning on the third transistor when performing a programming operation includes: applying a third voltage level to the control end of the first transistor when performing a programming operation; wherein the control end of the second transistor is coupled to the control end of the first transistor, and the control end of the third transistor is coupled to the control end of the first transistor; the third voltage level is greater than the first voltage level, and the third voltage level is greater than the second voltage level.

[0099] Combination Figure 3 As shown, in one example, the first transistor 221 is an N-type transistor, the second transistor 222-1 is a P-type transistor, and the third transistor 222-2 is an N-type transistor. When the anti-fuse unit is programmed, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a high level. The second terminal e of the first transistor 221 is coupled to the ground terminal through the third transistor 222-2 and is at a first voltage level, for example, 0V. The first voltage level is less than the high level received by the control terminal a of the first transistor 221. It can be understood that in this example, the third voltage level is a high level.

[0100] In another example, the first transistor 221 is a P-type transistor, the second transistor 222-1 is an N-type transistor, and the third transistor 222-2 is a P-type transistor. When performing a programming operation on the anti-fuse unit, the control terminal a of the first transistor 221 receives a programming control signal and sets it to a low level, and the second terminal e of the first transistor 221 is coupled to the ground terminal through the third transistor 222-2 and is at a first voltage level, for example, 0V, and the first voltage level is less than the low level received by the control terminal a of the first transistor 221. It can be understood that in this example, the third voltage level is a low level.

[0101] It should be noted that the second voltage level is less than or equal to the precharge level of the sensing node. Therefore, when the anti-fuse unit is programmed, the third voltage level applied to the control terminal of the first transistor is greater than the second voltage level.

[0102] In some embodiments, the above operation method further includes: when performing a read operation, sensing a read voltage of the anti-fuse unit. For example, when performing a read operation, using Figure 3 The read circuit shown senses a read voltage of the anti-fuse cell.

[0103] Based on the above anti-fuse device, an embodiment of the present disclosure further provides a memory, and the memory includes the anti-fuse device as in any of the above embodiments.

[0104] In the embodiments of the present disclosure, the memory may be a volatile memory, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), and a double data rate synchronous dynamic random access memory (DDR SDRAM), etc.; it may also be a non-volatile memory, such as a phase-change memory (Phase-Change Random Access Memory, PRAM), a magnetic memory (MRAM), and a resistive random access memory (RRAM), etc.

[0105] As a one-time programmable device, the anti-fuse device can be applied to DRAM and other memories, and has the obvious advantages of small size and simple process. For example, the anti-fuse device can be used in DRAM memory to store the address information of defective storage cells, thereby realizing redundant replacement (row replacement and column replacement); it can also be programmed to realize the precise adjustment of various parameters (such as voltage, current or frequency) inside the DRAM memory.

[0106] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.< / n> < / n>

Claims

1. An anti-fuse device, It is characterized in that include: An anti-fuse array comprises: a plurality of anti-fuse units; A programming control circuit is coupled to the anti-fuse array through a sensing node, and includes: a first transistor and a leakage suppression circuit, wherein the first end of the first transistor is coupled to the sensing node, the input end of the leakage suppression circuit is coupled to the control end of the first transistor, and the output end of the leakage suppression circuit is coupled to the second end of the first transistor; wherein, when a programming operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a first voltage level; when a reading operation is performed on the anti-fuse unit, the output end of the leakage suppression circuit is at a second voltage level; and the second voltage level is greater than the first voltage level.

2. The anti-fuse device according to claim 1, It is characterized in that The leakage suppression circuit includes at least one inverter; the inverter includes: a second transistor, wherein a first terminal of the second transistor is coupled to a power source, a second terminal of the second transistor is coupled to an output terminal of the inverter, and a control terminal of the second transistor is coupled to a control terminal of the first transistor; wherein the power source is used to provide the second voltage level; A third transistor, wherein a first terminal of the third transistor is coupled to the output terminal of the inverter, a second terminal of the third transistor is coupled to the ground terminal, and a control terminal of the third transistor is coupled to the control terminal of the first transistor; wherein the ground terminal is used to provide the first voltage level.

3. The anti-fuse device according to claim 2, It is characterized in that The leakage suppression circuit includes a plurality of the inverters; wherein the plurality of the inverters are connected in parallel.

4. The anti-fuse device according to claim 2, It is characterized in that The type of the first transistor is the same as the type of the third transistor, and the type of the first transistor is different from the type of the second transistor.

5. The anti-fuse device according to claim 2, It is characterized in that The size of the first transistor is larger than the size of the second transistor.

6. The anti-fuse device according to claim 2, It is characterized in that A size of the third transistor is greater than or equal to a size of the second transistor.

7. The anti-fuse device according to claim 1, It is characterized in that The anti-fuse device further comprises: A comparator; wherein a first input terminal of the comparator is coupled to the anti-fuse array through the sensing node, and a second input terminal of the comparator is used to receive a reference voltage.

8. The anti-fuse device according to claim 7, It is characterized in that The first voltage level is a ground level; The second voltage level is greater than the reference voltage and less than or equal to a precharge level of the sensing node.

9. The anti-fuse device according to claim 1, It is characterized in that When the programming operation is performed on the anti-fuse unit, the control terminal of the first transistor is at a third voltage level; wherein the third voltage level is greater than the first voltage level, and the third voltage level is greater than the second voltage level.

10. A memory, It is characterized in that The invention comprises the anti-fuse device as claimed in any one of claims 1 to 9.

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