Groove type IGBT (Insulated Gate Bipolar Translator) device with back buffer layer and preparation method thereof

Abstract

The invention provides a trench type IGBT device with a back buffer layer and a preparation method thereof, and the method employs an epitaxial wafer substrate with a substrate supporting layer, and carries out the phosphorus ion and / or hydrogen ion implantation from the back surface after the substrate supporting layer is thinned, so as to enable the thickness of a part below the substrate supporting layer to be converted into a buffer sublayer with a higher doping concentration. Therefore, the buffer layer of the IGBT device is jointly formed by the buffer sub-layer and the residual substrate supporting layer, and the IGBT device with the buffer layer structure can effectively avoid the problem of large high-temperature electric leakage of the IGBT device which purely forms the buffer layer by the epitaxial substrate. The problem that short-circuit oscillation is prone to occurring in a low-voltage short-circuit test of an IGBT device with a buffer layer formed by purely using hydrogen injection for multiple times can be solved, and meanwhile the problems that an IGBT device with a buffer layer formed by purely using phosphorus injection is poor in EMI resistance and low in performance can also be solved.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a trench IGBT device with a back buffer layer and a preparation method thereof. Background Art

[0002] Power semiconductor devices, also known as power electronic devices, are the core devices for power electronic devices to achieve power conversion and circuit control. The main uses include frequency conversion, rectification, voltage conversion, power amplification and power control, and they also have energy-saving effects. Power semiconductor devices are widely used in power electronics fields such as mobile communications, consumer electronics, new energy transportation, rail transportation, industrial control, power generation and distribution, covering low, medium and high power levels. There are many types of power semiconductors, such as IGBT, VDMOS, and CoolMOS. The most representative semiconductor power device is IGBT.

[0003] IGBT is a device composed of MOSFET and bipolar transistor, with MOSFET as input and PNP transistor as output. Therefore, IGBT can be regarded as Darlington transistor with MOSFET input. IGBT has the advantages of high input impedance, low drive circuit power, simple drive, fast switching speed and low switching loss of MOSFET, and has the advantages of high current density, strong current handling capacity and low on-saturation voltage drop of bipolar power transistor. Therefore, it has been more and more widely used in modern power electronics technology. Since the early 1980s, it has been widely studied at home and abroad. At present, IGBT has broad application prospects and is widely used in new energy vehicles, industrial frequency conversion, photovoltaics, smart grids and locomotives. With the continuous development of IGBT technology, higher requirements are undoubtedly placed on the performance of IGBT.

[0004] At present, most IGBT devices use a back buffer layer structure. The two mainstream back buffer layer formation methods are: method one is to use multiple hydrogen injections combined with furnace annealing (such as Figure 1 The second method is to use multiple phosphorus implantation combined with laser annealing process to form (as shown in Figure 2 As shown). The IGBT device using the buffer layer formed by method 1 has the advantages of low turn-off loss and strong anti-EMI capability, but the IGBT device using the buffer layer is prone to short-circuit oscillation in the low-voltage short-circuit test. The IGBT device using method 2 to form the buffer layer is not prone to short-circuit oscillation in the full voltage level (low voltage to high voltage) short-circuit test, but the performance of the IGBT device is not as good as the IGBT device using method 1 to form the buffer layer, and the anti-EMI capability is also poor. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, an object of the present invention is to provide a trench IGBT device with a back buffer layer and a method for preparing the same, so as to solve the problem that the method for preparing the buffer layer of the IGBT device in the prior art cannot simultaneously take into account the performance of the IGBT device and the fact that short-circuit oscillations are not prone to occur in full voltage level short-circuit tests.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a trench IGBT device with a back buffer layer, the preparation method comprising the following steps:

[0007] An N-type epitaxial wafer substrate is provided, wherein the epitaxial wafer substrate comprises an N-type substrate support layer and an N-type voltage-resistant layer in order from bottom to top; wherein the doping concentration of the substrate support layer is greater than the doping concentration of the voltage-resistant layer, and the substrate support layer is divided into a constant doping region with a constant doping concentration and a variable doping region with a gradually decreasing doping concentration from bottom to top;

[0008] Performing a front process of the IGBT device on the front side of the voltage-resistant layer;

[0009] thinning the substrate support layer at the back side;

[0010] Ion implantation and annealing activation are performed on the back side of the thinned substrate support layer to form a buffer layer located above and a P-type collector region located below; wherein the method for forming the buffer layer comprises: phosphorus ion and / or hydrogen ion implantation and annealing activation are performed on the back side of the thinned substrate support layer to form a buffer sublayer, the preset thickness is less than the thickness of the thinned substrate support layer, the buffer sublayer and the remaining thickness of the substrate support layer form the buffer layer of the IGBT device, and when phosphorus ion and hydrogen ion implantation are performed on the back side of the thinned substrate support layer, the ion implantation depth of the phosphorus ion is less than the ion implantation depth of the hydrogen ion;

[0011] A collector metal layer is formed on the back side of the collector region.

[0012] Optionally, the collector region is firstly ion-implanted and annealed to activate the back side of the thinned substrate support layer; and then the buffer sublayer is ion-implanted and annealed to activate the back side of the thinned substrate support layer.

[0013] Optionally, phosphorus ion implantation is performed once or twice at a preset thickness on the back side of the thinned substrate support layer, followed by annealing and activation to form the buffer sublayer; or hydrogen ion implantation is performed once or twice at a preset thickness on the back side of the thinned substrate support layer, followed by annealing and activation to form the buffer sublayer; or phosphorus ion implantation and hydrogen ion implantation are performed once and annealing and activation are performed once at a preset thickness on the back side of the thinned substrate support layer, followed by annealing and activation to form the buffer sublayer.

[0014] Optionally, the upper surface of the buffer sublayer does not exceed the upper surface of the constant doping region of the substrate support layer; or the upper surface of the buffer sublayer is flush with the upper surface of the constant doping region of the substrate support layer; or the upper surface of the buffer sublayer extends into the variable doping region of the substrate support layer.

[0015] Furthermore, each time the phosphorus ion is implanted, the energy is 200KeV to 2000KeV, and the implantation dose is 1e11cm -2 ~1e13cm -2 Each time the hydrogen ion implantation energy is 200KeV to 500KeV, the implantation dose is 1e14cm -2 ~5e14 cm -2 .

[0016] Furthermore, the ion implantation of phosphorus ions is activated by laser annealing; the ion implantation of hydrogen ions is activated by furnace annealing, the annealing temperature is 300° C. to 550° C., and the annealing time is 0.5 h to 5 h.

[0017] Optionally, the collector region is formed by boron ion implantation and annealing activation; wherein the boron ion implantation is activated by laser annealing, the boron ion implantation energy is 20KeV to 60KeV, and the implantation dose is 5e12cm -2 ~1e14cm -2 .

[0018] Optionally, the gate structure of the front structure of the IGBT device is a trench gate and further includes a dummy trench gate.

[0019] Further, the virtual trench gate is electrically connected to the trench gate; or the virtual trench gate is electrically connected to the N-type emitter region.

[0020] The present invention also provides a trench IGBT device with a back side buffer layer, which is prepared by using any one of the above methods for preparing a trench IGBT device with a back side buffer layer.

[0021] As described above, the trench IGBT device with a back buffer layer of the present invention and the preparation method thereof adopt an epitaxial wafer substrate with a substrate support layer, and after thinning the substrate support layer, phosphorus ions and / or hydrogen ions are implanted therein from the back side to convert the thickness of the portion below the substrate support layer into a buffer sublayer with a relatively higher doping concentration, so that the buffer sublayer and the remaining substrate support layer together constitute the buffer layer of the IGBT device. The IGBT device with this buffer layer structure can effectively avoid the problem of large high-temperature leakage of IGBT devices whose buffer layers are formed solely by epitaxial substrates, and can also avoid the problem of short-circuit oscillations that easily occur in low-voltage short-circuit tests of IGBT devices that simply use multiple hydrogen injections to form a buffer layer. At the same time, it can also avoid the problem of poor EMI resistance and low performance of IGBT devices that simply use phosphorus injection to form a buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The doping profile curve between the doping concentration and depth of the buffer layer of the IGBT device formed by multiple hydrogen implantations is shown.

[0023] Figure 2 The doping profile curve between the doping concentration and depth of the buffer layer of the IGBT device formed by phosphorus implantation is shown.

[0024] Figure 3 It shows a schematic cross-sectional structure diagram of an N-type epitaxial wafer substrate provided in the method for preparing a trench IGBT device with a back buffer layer of the present invention.

[0025] Figure 4 Display as Figure 3 The doping profile curve between the doping concentration and depth of the epitaxial wafer substrate, wherein the extension direction of the depth is from the back side of the epitaxial wafer substrate to the front side.

[0026] Figure 5 It is a schematic diagram of the cross-sectional structure after the front side process of the IGBT device is performed in the method for preparing the trench IGBT device with a back side buffer layer of the present invention.

[0027] Figure 6 and Figure 7 Shown are schematic cross-sectional structures of two examples after thinning the back side substrate support layer in the method for preparing a trench IGBT device with a back side buffer layer of the present invention.

[0028] Figure 8 It is a schematic cross-sectional structure diagram of an example after forming a buffer layer, a collector region and a collector metal layer in the method for preparing a trench IGBT device with a back buffer layer of the present invention.

[0029] Fig. 9 and Fig.10 Display as Figure 8A doping profile curve between the doping concentration and depth of the buffer layer, wherein the extending direction of the depth is from the back side to the front side of the epitaxial wafer substrate.

[0030] Fig.11 It is a schematic cross-sectional structure diagram of another example after forming a buffer layer, a collector region and a collector metal layer in the method for preparing a trench IGBT device with a back side buffer layer of the present invention.

[0031] Fig.12 Display as Fig.11 A doping profile curve between the doping concentration and depth of the buffer layer, wherein the extending direction of the depth is from the back side to the front side of the epitaxial wafer substrate.

[0032] Fig.13 It is a schematic cross-sectional structure diagram of another example after forming a buffer layer, a collector region and a collector metal layer in the method for preparing a trench IGBT device with a back buffer layer of the present invention.

[0033] Fig.14 Display as Fig.13 A doping profile curve between the doping concentration and depth of the buffer layer, wherein the extending direction of the depth is from the back side to the front side of the epitaxial wafer substrate.

[0034] Fig.15 Shown are breakdown voltage curves of IGBT devices formed using three different buffer layers at 175°C.

[0035] Fig.16 Shown are the electric field distribution curves of IGBT devices formed using three different buffer layers.

[0036] Component number description

[0037] 10 Epitaxial wafer substrate

[0038] 11. Substrate support layer

[0039] 110 Constant doping region

[0040] 111 Varying doping region

[0041] 12 Pressure-resistant layer

[0042] 13 IGBT device front structure

[0043] 130 Carrier storage layer

[0044] 131 Body Area

[0045] 132 emitter region

[0046] 133 emitter metal layer

[0047] 134 Conductive contact holes

[0048] 135 Trench Gate

[0049] 136 Virtual Trench Gate

[0050] 137 Dielectric layer

[0051] 14 Buffer layer

[0052] 140 Buffer sublayer

[0053] 15 Collector region

[0054] 16 Collector metal layer DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0057] See also Figures 3 to 16 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0058] This embodiment provides a method for preparing a trench IGBT device with a back buffer layer, the method comprising the following steps:

[0059] S1. Provide an N-type epitaxial wafer substrate, wherein the epitaxial wafer substrate comprises an N-type substrate support layer and an N-type voltage-resistant layer from bottom to top; wherein the doping concentration of the substrate support layer is greater than the doping concentration of the voltage-resistant layer, and the substrate support layer is divided into a constant doping region with a constant doping concentration and a variable doping region with a gradually decreasing doping concentration from bottom to top;

[0060] S2, performing a front process of the IGBT device on the front side of the voltage-resistant layer;

[0061] S3, thinning the substrate support layer at the back side;

[0062] S4, performing ion implantation and annealing activation on the back side of the thinned substrate support layer to form a buffer layer located above and a P-type collector region located below; wherein the method for forming the buffer layer comprises: performing phosphorus ion and / or hydrogen ion implantation and annealing activation on a preset thickness on the back side of the thinned substrate support layer to form a buffer sublayer, wherein the preset thickness is less than the thickness of the thinned substrate support layer, the buffer sublayer and the remaining thickness of the substrate support layer form the buffer layer of the IGBT device, and when performing phosphorus ion and hydrogen ion implantation on the back side of the thinned substrate support layer, the ion implantation depth of the phosphorus ion is less than the ion implantation depth of the hydrogen ion;

[0063] S5. Forming a collector metal layer on the back side of the collector region.

[0064] Since a substrate support layer with a relatively high doping concentration is first formed during the epitaxial growth of the epitaxial wafer substrate and then a voltage-resistant layer with a relatively low doping concentration is formed, when the voltage-resistant layer is formed, due to thermal diffusion, doping ions in a portion of the substrate support layer close to the voltage-resistant layer will diffuse from a high-concentration region to a low-concentration region, thereby forming the substrate support layer into a constant doping region with a relatively high and constant concentration at the bottom and a variable doping region with a relatively small and variable concentration at the top. The preparation method of the trench IGBT device with a back buffer layer of this embodiment adopts an epitaxial wafer substrate with the substrate support layer, and after thinning the substrate support layer, performs phosphorus ion doping on the back of the substrate support layer. And / or hydrogen ion implantation is performed to convert part of the thickness below the substrate support layer into a buffer sublayer with a relatively higher doping concentration, so that the buffer sublayer and the remaining substrate support layer together constitute the buffer layer of the IGBT device. The IGBT device with this buffer layer structure can effectively avoid the problem of large high-temperature leakage of IGBT devices whose buffer layer is formed solely by an epitaxial substrate, and can also avoid the problem of short-circuit oscillation in low-voltage short-circuit testing of IGBT devices whose buffer layer is formed solely by multiple hydrogen implantations. At the same time, it can also avoid the problem of poor EMI resistance and low performance of IGBT devices whose buffer layer is formed solely by phosphorus implantation.

[0065] The method for preparing a trench IGBT device with a back side buffer layer according to the present embodiment will be described in detail below with reference to the specific drawings.

[0066] like Figure 3 and Figure 4As shown, firstly, step S1 is performed to provide an N-type epitaxial wafer substrate 10, wherein the epitaxial wafer substrate 10 includes an N-type substrate support layer 11 and an N-type voltage-resistant layer 12 from bottom to top; wherein the doping concentration of the substrate support layer 11 is greater than the doping concentration of the voltage-resistant layer 12 (such as Figure 4 As shown), the substrate support layer 11 is divided from bottom to top into a constant doping region 110 with a constant doping concentration and a variable doping region 111 with a gradually decreasing doping concentration.

[0067] It should be noted here that the constant doping concentration of the constant doping area 110 refers to the fact that the doping concentration remains unchanged in the theoretical doping design, but in the actual process preparation process, due to reasons such as design accuracy and instability of process parameters, the constant doping concentration may have certain fluctuations, which are all unintentional changes and are allowable fluctuations within the range of process accuracy and should fall within the protection range of the constant doping concentration described in this embodiment.

[0068] In the preparation method of the trench IGBT device with a back buffer layer of this embodiment, the N type can be formed by doping the semiconductor material with VA group elements, such as phosphorus doping, but it is not limited to this. Other N type ions can also achieve the formation of N type doping type, and the specific selection is based on actual needs.

[0069] The material of the epitaxial wafer substrate 10 can be any semiconductor material suitable for preparing IGBT devices, such as silicon, germanium, silicon carbide, gallium arsenide or gallium nitride, etc. In this embodiment, the material of the epitaxial wafer substrate 10 is selected as silicon material. In addition, the specific doping concentration and thickness of the voltage-resistant layer 12 in the epitaxial wafer substrate 10 depend on the voltage-resistant requirements of the IGBT device, and are specifically set according to actual needs.

[0070] The epitaxial wafer substrate 10 is generally prepared by an existing conventional epitaxial process, such as a CVD process or a single crystal pulling process. During the preparation process, a substrate support layer 11 and a voltage-resistant layer 12 with different doping concentrations are formed. Due to the different doping concentrations, when preparing the voltage-resistant layer 12, the doping ions of the substrate support layer 11 with a larger doping concentration will diffuse to the voltage-resistant layer 12 with a lower doping concentration, so that the substrate support layer 11 is formed into a constant doping region 110 with a larger and constant concentration at the bottom and a variable doping region 111 with a relatively smaller and variable concentration at the top (such as Figure 4 shown).

[0071] It should be noted here that the extension direction of the depth in the doping profile curve between doping concentration and depth in this embodiment refers to the back side of the epitaxial wafer substrate 10 as the starting zero point, that is, extending from the back side of the epitaxial wafer substrate 10 to the front side as the extension direction.

[0072] like Figure 5As shown, step S2 is then performed to perform a front surface process of the IGBT device on the front surface of the voltage-resistant layer 12 .

[0073] The front process can be implemented using conventional manufacturing technology of existing IGBT devices, and the gate structure formed is a trench gate. The buffer layer prepared by the preparation method of this embodiment has the most obvious effect on improving the short-circuit oscillation problem of IGBT devices with virtual trench gates in the front structure.

[0074] As an example, Figure 5 As shown, the front structure of the IGBT device prepared by the front process of the IGBT device includes, from bottom to top, an N-type carrier storage layer 130, a P-type body region 131, an N-type emitter region 132 and an emitter metal layer 133; and also includes: a trench gate 135, a dummy trench gate 136, a conductive contact hole 134 and a dielectric layer 137; wherein,

[0075] The trench gate 135 and the dummy trench gate 136 include a trench and a gate insulating layer and a gate conductive layer formed in the trench. The trench gate 135 and the dummy trench gate 136 extend from the surface of the emitter region 132 to the voltage-resistant layer 12.

[0076] The emitter region 132 surrounds the outer periphery of the trench gate 135 and extends downward from the surface of the body region 131;

[0077] The conductive contact hole 134 includes a contact hole and a conductive material filling the contact hole, and the conductive contact hole 134 contacts the emitter region 132 and extends upward from the body region 131 to connect with the emitter metal layer 133;

[0078] The dielectric layer 137 covers the trench gate 135 , the dummy trench gate 136 , and the emitter region 132 .

[0079] The virtual trench gate 136 may be electrically connected to the trench gate 135 , or may be electrically connected to the emitter region 132 , and may be specifically designed according to actual needs.

[0080] like Figure 6 and Figure 7 As shown, step S3 is then performed to thin the substrate support layer 11 at the back side.

[0081] As an example, the epitaxial wafer substrate 10 is first turned over, and then the substrate support layer 11 is thinned. Conventional backside thinning processes such as CMP, dry etching or wet etching may be used.

[0082] Since the substrate support layer 11 is divided into a constant doping region 110 with a constant doping concentration and a variable doping region 111 with a gradually decreasing doping concentration, in the thinning process of this step, the thickness H of the remaining substrate support layer 11 is designed according to actual needs. Figure 6 Only a portion of the thickness of the constant doping region 110 is thinned, and the remaining portion of the constant doping region 110 and the variable doping region 111 are used as the basis for subsequent doping, such as Figure 7 The constant doping region 110 is completely thinned and removed, and even the variable doping region 111 of a certain thickness may be thinned and removed as needed, leaving only the remaining variable doping region 111 as a basis for subsequent doping.

[0083] like Figure 8 As shown, step S4 is then performed, in which ion implantation and annealing activation are performed on the back side of the thinned substrate support layer 11 to form a buffer layer 14 located above and a P-type collector region 15 located below; wherein the method for forming the buffer layer 14 comprises: implanting phosphorus ions and / or hydrogen ions at a preset thickness on the back side of the thinned substrate support layer 11 and annealing activation to form a buffer sublayer 140, wherein the preset thickness is less than the thickness of the thinned substrate support layer 11, the buffer sublayer 140 and the remaining thickness of the substrate support layer form the buffer layer 14 of the IGBT device, and when phosphorus ions and hydrogen ions are implanted on the back side of the thinned substrate support layer, the ion implantation depth of the phosphorus ions is less than the ion implantation depth of the hydrogen ions.

[0084] As an example, the formation order of the collector region 15 and the buffer layer 14 is not strictly limited. The collector region 15 can be formed first and then the buffer layer 14; or the buffer layer 14 can be formed first and then the collector region 15. In this embodiment, the ion implantation and annealing activation of the collector region 15 are performed on the back side of the thinned substrate support layer first; and then the ion implantation and annealing activation of the buffer sublayer 140 are performed on the back side of the thinned substrate support layer. The collector region 15 is P-type, and the P-type can be formed by doping semiconductor materials with IIIA group elements, such as boron doping, but it is not limited to this. Other P-type ions can also achieve the formation of this doping type, and the specific selection is based on actual needs. When the collector region 15 is formed by boron ion implantation and annealing activation, the ion implantation of the boron ions is activated by laser annealing, and the ion implantation energy of the boron ions is 20KeV~60KeV, and the implantation dose is 5e12cm -2 ~1e14cm -2 .

[0085] What needs to be explained here is Fig. 9 , Fig.10 , Fig.12 , Fig.14In FIG. 1 , point A represents the upper surface position of the constant doping region 110 , point B represents the lower surface position of the voltage-resistant layer 12 , and point C represents the upper surface position of the buffer sublayer 140 .

[0086] like Figure 8 As shown, as an example, the upper surface of the buffer sublayer 140 does not exceed the upper surface of the constant doping region 110 of the substrate support layer. At this time, the buffer layer 14 includes a variable doping region 111, a constant doping region 110 and a buffer sublayer 140 from top to bottom. The structure of the buffer layer 14 can be obtained by Figure 6 The structure of the substrate support layer 11 is formed by doping. Fig. 9 and Fig.10 Shown Figure 8 The doping profile curve between the doping concentration and depth of the buffer layer 14 is shown in FIG. Fig. 9 and Fig.10 As can be seen from FIG. 1 , the buffer sublayer 140 is formed by doping the back side of the constant doping region 110 with a preset thickness, wherein Fig. 9 The buffer sublayer 140 having one doping peak is formed by one ion implantation. Fig.10 The buffer sublayer 140 with two doping peaks Q1 and Q2 is formed by two ion implantations. The distance between point C and point A is 0.1 μm to 15 μm.

[0087] like Fig.11 As shown in FIG. 1 , as another example, the upper surface of the buffer sublayer 140 is flush with the upper surface of the constant doping region 110 of the substrate support layer 11. That is, the buffer sublayer 140 is formed by doping the entire constant doping region 110. At this time, the buffer layer 14 includes the variable doping region 111 and the buffer sublayer 140 from top to bottom. The structure of the buffer layer 14 can also be obtained by Figure 6 The structure of the substrate support layer 11 is formed by doping. Fig.12 for Fig.11 The doping profile curve between the doping concentration and depth of the buffer layer 14 is shown, and the buffer sublayer 140 with one doping peak is formed by one ion implantation.

[0088] like Fig.13 As shown in FIG. 1 , as another example, the upper surface of the buffer sublayer 140 extends into the variable doping region 111 of the substrate support layer 11. At this time, the buffer layer 14 includes the variable doping region 111 and the buffer sublayer 140 from top to bottom. The structure of the buffer layer 14 can be obtained by Figure 6 The structure of the substrate support layer 11 is formed by doping, and the Figure 7 The structure of the substrate support layer 11 is formed by doping. Figure 6When the buffer sublayer 140 is formed by doping the entire constant doping region 110 and the variable doping region 111 of a certain thickness, Figure 7 When the buffer sublayer 140 is formed by doping on the structure of the substrate support layer 11, the buffer sublayer 140 is formed by doping and transforming a part of the thickness of the variable doping region 111. Fig.14 for Fig.13 The doping profile curve between the doping concentration and depth of the buffer layer 14 is a buffer sublayer 140 having a doping peak formed by a single ion implantation. Fig.14 It can be seen that the upper surface position C of the buffer sublayer 140 has exceeded the upper surface position A of the constant doping region 110. The distance between point C and point A is 0.1 μm to 10 μm, and the distance between point C and point B is 3 μm to 30 μm.

[0089] As an example, the buffer sublayer 140 can be formed by implanting phosphorus ions only to a preset thickness on the back side of the thinned substrate support layer 11 and annealing to activate it; it can also be formed by implanting hydrogen ions only to a preset thickness on the back side of the thinned substrate support layer 11 and annealing to activate it; it can also be formed by implanting phosphorus ions and hydrogen ions to a preset thickness on the back side of the thinned substrate support layer 11 and annealing to activate it. In addition, the formation of the buffer sublayer 140 is generally carried out by no more than 2 ion implantations, for example, when only phosphorus ions are implanted, 1 to 2 phosphorus ion implantations and annealing to activate it are performed to form the buffer sublayer 140, or when only hydrogen ions are implanted, 1 to 2 hydrogen ion implantations and annealing to activate it are performed to form the buffer sublayer 140, or when phosphorus ions are implanted in combination with hydrogen ions, 1 phosphorus ion implantation and 1 hydrogen ion implantation and annealing to activate it are performed to form the buffer sublayer 140. Preferably, the ion implantation energy of the phosphorus ions each time is 200KeV to 2000KeV, and the implantation dose is 1e11cm -2 ~1e13cm -2 Each time the hydrogen ion implantation energy is 200KeV to 500KeV, the implantation dose is 1e14cm -2 ~5e14 cm -2 Optimally, the phosphorus ion implantation is activated by laser annealing; the hydrogen ion implantation is activated by furnace annealing, the annealing temperature is 300° C. to 550° C., and the annealing time is 0.5 h to 5 h.

[0090] like Fig.13 As shown, step S5 is finally performed to form a collector metal layer 16 on the back side of the collector region 15 .

[0091] As an example, a metal sputtering process may be used to form the collector metal layer 16. Typically, the collector metal layer 16 is an aluminum-titanium-nickel-silver stacked structure (Al / Ti / Ni / Ag) from top to bottom.

[0092] In order to clearly reflect the performance of the trench IGBT device with a back buffer layer prepared by the method for preparing the trench IGBT device with a back buffer layer of this embodiment, three IGBT devices with different buffer layers are prepared by the existing conventional process: the first H-FS, using multiple hydrogen injections combined with furnace tube annealing to form the buffer layer, and the remaining structures of the IGBT device are prepared by the existing conventional process; the second P-FS, using multiple phosphorus injections combined with furnace tube annealing to form the buffer layer, and the remaining structures of the IGBT device are prepared by the existing conventional process; the third Epi-FS, the buffer layer is formed by the epitaxial substrate alone, and the remaining structures of the IGBT device are prepared by the existing conventional process. The performance, breakdown voltage at high temperature and IGBT electric field distribution during short-circuit test of the three IGBT devices with different buffer layers are compared with the trench IGBT device with a back buffer layer prepared by the method for preparing the trench IGBT device with a back buffer layer of this embodiment, wherein the buffer sublayer 140 of the buffer layer in this embodiment is prepared by hydrogen injection combined with furnace tube annealing and combined with the substrate support layer to form the buffer layer 14, which is marked as Epi+H-FS. As can be seen from Table 1, the performance of the trench IGBT device prepared by the method for preparing the buffer layer of this embodiment is comparable to that of the trench IGBT device formed by hydrogen ion implantation combined with furnace annealing, indicating that the performance of the trench IGBT device with a back side buffer layer prepared by the method for preparing the trench IGBT device with a back side buffer layer of this embodiment is better. Fig.15 As shown in FIG. 1 , the breakdown voltage curves of IGBT devices formed with three different buffer layers at a high temperature of 175°C are shown. It can be seen that the high temperature leakage of the trench IGBT device of this embodiment is significantly improved, which is basically comparable to the trench IGBT device formed with a buffer layer formed by hydrogen ion implantation combined with furnace annealing. Fig.16 As shown in the figure, the electric field distribution of the IGBT device formed by three different buffer layers during the short-circuit test, the horizontal axis 0μm is the front of the IGBT device, the horizontal axis 65μm is the back of the IGBT device, the electric field on the back of the IGBT device with the phosphorus buffer layer (P-FS) is lower than the electric field at 6μm on the front of the IGBT device, so it is not easy to have short-circuit oscillation; while the electric field on the back of the IGBT device with the hydrogen buffer layer (H-FS) is higher than the electric field at 6μm on the front of the IGBT device, so it is easy to have short-circuit oscillation; the electric field on the back of the IGBT device with the epitaxial hydrogen injection buffer layer (Epi+H-FS) is equivalent to the electric field at 6μm on the front of the IGBT device, so it is not easy to have short-circuit oscillation.

[0093] Table 1: Comparison of performance parameters of IGBT devices with two different buffer layer structures

[0094] FS (buffer layer) form Vcesat / V Eoff / mJ Vpeak / V H-FS 1.48 2.13 715 Epi+F-FS 1.48 2.15 705

[0095] From Table 1, Fig.15 and Fig.16 It can be seen that the trench IGBT device with a back buffer layer prepared by the method for preparing a trench IGBT device with a back buffer layer of this embodiment can effectively avoid the problem of large high-temperature leakage of IGBT devices whose buffer layer is formed solely by an epitaxial substrate, and can also avoid the problem of short-circuit oscillation in low-voltage short-circuit tests of IGBT devices whose buffer layer is formed solely by multiple hydrogen injections. At the same time, it can also avoid the problem of poor EMI resistance and low performance of IGBT devices whose buffer layer is formed solely by phosphorus injection.

[0096] This embodiment also provides a trench IGBT device with a back side buffer layer, and the IGBT device can be prepared by using the method for preparing a trench IGBT device with a back side buffer layer of this embodiment.

[0097] In summary, the present invention provides a trench IGBT device with a back buffer layer and a preparation method thereof, which uses an epitaxial wafer substrate with a substrate support layer, and after thinning the substrate support layer, phosphorus ions and / or hydrogen ions are implanted from the back to convert the thickness of the lower part of the substrate support layer into a buffer sublayer with a relatively higher doping concentration, so that the buffer sublayer and the remaining substrate support layer together constitute the buffer layer of the IGBT device. The IGBT device with the buffer layer structure can effectively avoid the problem of high-temperature leakage of the IGBT device with a buffer layer formed solely by an epitaxial substrate, and can also avoid the problem of short-circuit oscillation in the low-voltage short-circuit test of the IGBT device that simply uses multiple hydrogen injections to form a buffer layer, and can also avoid the problem of poor EMI resistance and low performance of the IGBT device that simply uses phosphorus injection to form a buffer layer. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a trench IGBT device with a back buffer layer, characterized in that: The preparation method comprises the following steps: An N-type epitaxial wafer substrate is provided, wherein the epitaxial wafer substrate comprises an N-type substrate support layer and an N-type voltage-resistant layer in order from bottom to top; wherein the doping concentration of the substrate support layer is greater than the doping concentration of the voltage-resistant layer, and the substrate support layer is divided into a constant doping region with a constant doping concentration and a variable doping region with a gradually decreasing doping concentration from bottom to top; Performing a front process of the IGBT device on the front side of the voltage-resistant layer; thinning the substrate support layer at the back side; Ion implantation and annealing activation are performed on the back side of the thinned substrate support layer to form a buffer layer located above and a P-type collector region located below; wherein the method for forming the buffer layer comprises: phosphorus ion and / or hydrogen ion implantation and annealing activation are performed on the back side of the thinned substrate support layer to form a buffer sublayer, the preset thickness is less than the thickness of the thinned substrate support layer, the buffer sublayer and the remaining thickness of the substrate support layer form the buffer layer of the IGBT device, and when phosphorus ion and hydrogen ion implantation are performed on the back side of the thinned substrate support layer, the ion implantation depth of the phosphorus ion is less than the ion implantation depth of the hydrogen ion; A collector metal layer is formed on the back side of the collector region.

2. The method for preparing a trench IGBT device with a back side buffer layer according to claim 1, characterized in that: First, ion implantation and annealing activation of the collector region are performed on the back side of the thinned substrate support layer; and then ion implantation and annealing activation of the buffer sublayer are performed on the back side of the thinned substrate support layer.

3. The method for preparing a trench IGBT device with a back side buffer layer according to claim 1, characterized in that: Performing phosphorus ion implantation once or twice at a preset thickness on the back side of the thinned substrate support layer and annealing to activate the layer to form the buffer sublayer; or performing one to two hydrogen ion implantations at a preset thickness on the back side of the thinned substrate support layer and annealing to activate the layer to form the buffer sublayer; Alternatively, one phosphorus ion implantation and one hydrogen ion implantation are performed at a preset thickness on the back side of the thinned substrate support layer, followed by annealing and activation to form the buffer sublayer.

4. The method for preparing a trench IGBT device with a back side buffer layer according to claim 1, characterized in that: The upper surface of the buffer sublayer does not exceed the upper surface of the constant doping region of the substrate support layer; or the upper surface of the buffer sublayer is flush with the upper surface of the constant doping region of the substrate support layer; or the upper surface of the buffer sublayer extends into the variable doping region of the substrate support layer.

5. The method for preparing a trench IGBT device with a back side buffer layer according to any one of claims 1 to 4, characterized in that: Each time, the phosphorus ion implantation energy is 200KeV to 2000KeV, and the implantation dose is 1e11cm -2 ~1e13cm -2 Each time the hydrogen ion implantation energy is 200KeV to 500KeV, the implantation dose is 1e14cm -2 ~5e14 cm -2 .

6. The method for preparing a trench IGBT device with a back side buffer layer according to claim 5, characterized in that: The phosphorus ion implantation is activated by laser annealing; the hydrogen ion implantation is activated by furnace tube annealing, the annealing temperature is 300° C. to 550° C., and the annealing time is 0.5 h to 5 h.

7. The method for preparing a trench IGBT device with a back side buffer layer according to claim 5, characterized in that: The collector region is formed by boron ion implantation and annealing activation; wherein the boron ion implantation is activated by laser annealing, the boron ion implantation energy is 20KeV to 60KeV, and the implantation dose is 5e12cm -2 ~1e14cm -2 .

8. The method for preparing a trench IGBT device with a back side buffer layer according to claim 1, characterized in that: The gate structure of the front structure of the IGBT device is a trench gate, and also includes a dummy trench gate.

9. The method for preparing a trench IGBT device with a back side buffer layer according to claim 8, characterized in that: The virtual trench gate is electrically connected to the trench gate; or the virtual trench gate is electrically connected to the N-type emitter region.

10. A trench IGBT device with a back buffer layer, characterized in that: The device is prepared by the method for preparing a trench IGBT device with a back side buffer layer as claimed in any one of claims 1 to 9.

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