Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a common electrode layer; the pixel electrode layer is located on the side, away from the data lines, of the common electrode layer and comprises a plurality of pixel electrode rows extending in the first direction. The pixel electrode row comprises a plurality of pixel electrode groups arranged along the first direction; the pixel electrode group comprises two pixel electrodes, and any pixel electrode in the pixel electrode group crosses the other pixel electrode and is electrically connected with the data line through the transistor; at least one of the common electrode layer and the pixel electrode layer comprises a plurality of first wires extending along the second direction; the first wire is electrically connected with the common electrode, and the orthographic projection of the first wire on the substrate covers the orthographic projection of the data line on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] At the same resolution, the dual gate pixel architecture can reduce the number of source drivers by half compared to the single gate pixel architecture, thereby reducing IC costs, serving as an effective low-cost solution. Summary of the invention

[0003] The present invention provides an array substrate and a display panel. The array substrate comprises:

[0004] substrate;

[0005] Multiple transistors;

[0006] A plurality of gate line groups are located on one side of the substrate, the gate line groups comprising: two gate lines extending along the first direction;

[0007] Multiple data lines;

[0008] A common electrode layer, located on a side of the data line away from the substrate; the common electrode layer includes a plurality of common electrodes;

[0009] A pixel electrode layer, located at a side of the common electrode layer away from the data line, comprising: a plurality of pixel electrode rows extending along a first direction; the pixel electrode rows comprising a plurality of pixel electrode groups arranged along the first direction; the gate line group being located in an area between adjacent pixel electrode rows, the pixel electrode group being located in an area formed by the intersection of the gate line group and the data line; the pixel electrode group comprising two pixel electrodes, and any one of the pixel electrodes in the pixel electrode group being electrically connected to the data line through the transistor across the other pixel electrode;

[0010] Among them, at least one of the common electrode layer and the pixel electrode layer includes: a plurality of first wirings extending along the second direction; the first wirings are electrically connected to the common electrodes, and the orthographic projection of the first wirings on the substrate covers the orthographic projection of the data lines on the substrate.

[0011] In a possible implementation manner, the first wiring is located in the pixel electrode layer;

[0012] The common electrode layer has a first hollow; the orthographic projection of the first wiring on the substrate overlaps with the orthographic projection of the first hollow on the substrate.

[0013] In a possible implementation manner, the first wiring is disconnected at the position of the gate line group.

[0014] In a possible implementation manner, the common electrode extends along the first direction and is arranged along the second direction, and an orthographic projection of the common electrode on the substrate and a region between adjacent gate line groups are within the orthographic projection of the substrate;

[0015] The common electrode has a connecting portion at at least one end of the first hollow portion, and the common electrode is electrically connected to the first wiring through a first via hole at the connecting portion.

[0016] In a possible implementation manner, an extension length of the first routing line is greater than an extension length of the first hollowing out.

[0017] In a possible implementation manner, the orthographic projection of the first trace on the substrate covers the orthographic projection of the first hollow on the substrate, and covers the orthographic projection of the connecting portion on the substrate.

[0018] In a possible implementation manner, the orthographic projection of the first wiring on the substrate covers the orthographic projection of a portion of the common electrode on both sides of the first hollow on the substrate.

[0019] In a possible implementation manner, the orthographic projection of the first wiring on the substrate does not overlap with the orthographic projection of the common electrodes on both sides of the first hollow on the substrate.

[0020] In a possible implementation manner, the first wiring is located in the common electrode layer and is an integrally connected structure with the common electrode.

[0021] In a possible implementation manner, the orthographic projection of the outer edge of the pixel electrode on the substrate coincides with the outer edge of the data line on the substrate.

[0022] In a possible embodiment, the array substrate also includes: a plurality of second routing lines, and a plurality of second via groups; the second via group includes: two second vias; the two second vias of the second via group are respectively located on both sides of the gate line group, and on different sides of the second routing line; the common electrodes on both sides of the gate line group are electrically connected to the second routing line through the two second vias of the second via group.

[0023] In a possible implementation manner, the second wiring and the data line are in the same layer and material; the array substrate further includes: an organic insulating layer located between the data line and the common electrode layer, and a passivation layer located between the common electrode layer and the pixel electrode layer; the pixel electrode layer further includes: an overlap portion;

[0024] The second via hole penetrates the passivation layer and the organic insulating layer, and exposes a portion of the second wiring and a portion of the common electrode. The overlapping portion contacts the common electrode and the second wiring through the second via hole.

[0025] In a possible implementation, the common electrode has a recessed portion at the location of the second via hole; the second via hole is partially overlapped with the recessed portion in an orthographic projection on the substrate, and partially overlapped with the common electrode on a side of the recessed portion away from the gate line group.

[0026] In a possible implementation manner, the second wiring is located on a side of the common electrode layer facing the substrate, and is in direct contact with the common electrode.

[0027] The embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram comparing the Single gate pixel architecture and the Dual gate pixel architecture;

[0029] Figure 2 This is the timing diagram of the dual gate pixel architecture in a monochrome red screen;

[0030] Figure 3 Schematic diagrams of two Dual gate pixel architectures provided for embodiments of the present disclosure;

[0031] Figure 4 It is a schematic diagram when the display panel is refreshed;

[0032] Figure 5 This is a schematic diagram of data signal jump between frames of RG mixed color screen;

[0033] Figure 6 This is a schematic diagram of the vertical color stripes produced when the RG color mixing screen is used;

[0034] Figure 7 is a schematic diagram of the vertical crosstalk pattern;

[0035] Figure 8 It is a schematic diagram of the vertical crosstalk pattern when the data signal jumps between frames;

[0036] Fig. 9 It is a schematic diagram of a vertical crosstalk pattern that is partially bright and partially dark when the data signal jumps between frames;

[0037] Fig.10 It is a schematic diagram of the array substrate structure and process flow of the related technology;

[0038] Fig.11 for Fig.10 A schematic cross-sectional view at the data line location;

[0039] Fig. 12A This is one of the schematic top views of the array substrate provided in the embodiment of the present disclosure;

[0040] Fig. 12B for Fig. 12A Schematic diagram of a single film layer in the middle grid line layer;

[0041] Fig. 12C for Fig. 12A Schematic diagram of a single film layer of the data line layer;

[0042] Fig.12D for Fig. 12A Schematic diagram of a single film layer of the common electrode layer;

[0043] Fig.12E for Fig. 12A Schematic diagram of a single film layer of the pixel electrode layer;

[0044] Fig.12F for Fig. 12A Schematic diagram of the cross section along the dotted line e1;

[0045] Figure 12G A cross-sectional schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0046] Fig.13A A second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0047] Fig. 13B for Fig.13A A partial enlarged schematic diagram of

[0048] Fig. 13C for Fig.13A A schematic cross-sectional view along the dotted line e2;

[0049] Fig.13D for Fig.13A A schematic cross-sectional view along the dotted line e3;

[0050] Fig.13E for Fig. 13B A schematic cross-sectional view along the dotted line e4;

[0051] Fig.14A A third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0052] Fig. 14B for Fig.14A A schematic cross-sectional view along the dashed line e5;

[0053] Fig.15One of the cross-sectional schematic diagrams of a display panel provided for the implementation of the present disclosure;

[0054] Fig.16 A fingerprint of a display panel structure diagram provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0057] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0058] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0059] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0060] Combination Figure 1 As shown in the figure, the Dual gate pixel architecture has halved the number of data lines (Data) and doubled the number of gate lines (Gate) compared to the Single Gate pixel architecture, so the pixel charging time for each row is also halved. In other words, the Dualgate pixel architecture saves the number of ICs at the expense of the pixel charging rate. Insufficient pixel charging rate will bring some problems related to image quality, such as common red, green and blue monochrome images or mixed color images, such as monochrome red (R), monochrome green (G), monochrome blue (B), red and green mixed color (yellow), red and blue mixed color (magenta), blue and green mixed color (indigo) will have horizontal or vertical stripes because some pixels have a long pre-charge charging time and some pixels do not have a short pre-charge charging time. Figure 1 Take the Dualgate pixel architecture on the right for example: the high level of each row of gate lines will last for 4 hours (taking 4 hours as an example, 2 hours / 3 hours / 4 hours / 5 hours / 6 hours / 7 hours / 8 hours are actually applicable), and the gate signals corresponding to sub-pixels R1 / R2 / R3 / R4 are G1 / G2 / G3 / G4 respectively. See the timing diagram Figure 2. The last 1H of the 4H high level time of G1 / G2 / G3 / G4 is the actual data charging time of R1 / R2 / R3 / R4, and the previous 3H are pre-charging time. D1 / D2 / D3 are the data signals of R1 / R2&R3 / R4 respectively; for the three red sub-pixels R1 / R2 / R4, the data line level is inconsistent with the charging level of the red sub-pixel in the first H time of their charging, so pre-charging cannot be achieved, that is, the actual charging time of each red sub-pixel is 1H (1H=1.85us in 8K Dual gate 60Hz products), and considering the signal line delay, the actual charging time is shorter than 1.85us; for R3, the data signal in the first H time of its charging is the data of R2, and R3 and R2 need to charge the same data, which is equivalent to the charging time of R3 is 2H, which will cause R3 to have a higher charging rate than R1 / 2 / 4, resulting in uneven brightness of the screen.

[0061] In the dual gate pixel architecture, some pixel architectures are all long-connected pixel architectures (each data line drives a sub-pixel at intervals, so the path from the data line to the sub-pixel it actually drives is longer, hence the name), such as Figure 3 As shown in the figure, the colors of the sub-pixels connected to the same Data line are consistent. When displaying monochrome or mixed-color images, these two architectures will not cause horizontal, vertical, or diagonal stripes due to different pre-charging times, but there are other problems. The main problem is the mixed-color vertical stripes caused by the parasitic capacitance Cpd between the data line and the pixel electrode, as well as the V-crosstalk problem.

[0062] The mechanism of color mixing vertical lines caused by parasitic capacitance Cpd coupling: combined Figure 4 , Figure 5 , Figure 6As shown, the display panel is charged row by row from the bonding opposite side area (DPO) to the bonding area (DP). The pixels on the DP side of this frame (N frame) have just been charged. After a short blanking period between frames, the polarity of the next frame Data is reversed and the pixels on the DPO side begin to be charged. The polarity reversal △Vdata between frames causes the DP side pixel voltage Vpixel to jump through Cpd coupling (△Vpixel=Cpd*△Vdata / Ctotal The voltage jump of the pixel on the DP side lasts for nearly one frame, so the pixel on the DP side is most affected by the polarity switching between Data frames; take RG color mixing as an example: the voltage of D1 / D2 / D4 / D5 that charges R and G jumps when the frame switches, and the voltage of D3 / D6 that charges B does not jump when the frame switches. The R and G pixel electrodes next to D1 / D2 / D4 / D5 will be pulled by the Data jump, and the "-" pixel will be pulled down, and the "+" pixel will be pulled up, and both will become brighter; the R and G pixels next to D3 / D6 are not pulled, and the brightness remains unchanged, resulting in the following Figure 6 Shown are alternating light and dark vertical stripes.

[0063] Parasitic capacitance Cpd coupling leads to V-crosstalk mechanism: For example Figure 7 As shown, the grayscale 127 is used as the background, and the grayscale 255 is displayed in the middle. The grayscale 255 pattern occupies 1 / 2 of the vertical length of the entire display panel in the vertical direction (V). Figure 8 The data line in the V-crosstalk pattern is shown in Figure 7 Schematic diagram of voltage jump at different positions of the display panel, V-Crosstalk phenomenon caused by parasitic capacitance Cpd coupling Fig. 9 As shown in FIG. 1 , the display panel may appear partially dark and partially bright in the vertical direction. Fig. 9 In the figure, area ① will be dark due to coupling, and area ③ will be bright due to coupling.

[0064] The use of all long-connected dual gate pixel architecture can improve the shaking head problem through high resolution and high refresh rate. Figure 3As shown, the Dual gate pixel architecture with all long connections is adopted, and the same polarity of two columns of sub-pixels is presented on the entire display panel, because the voltage setting of the common electrode is difficult to satisfy that the brightness of all sub-pixels is completely consistent at the same grayscale, especially the sub-pixels with positive polarity relative to the common electrode and the sub-pixels with negative polarity relative to the common electrode, when displaying the same grayscale, the brightness of the sub-pixels to achieve display will be different, and this inconsistency will cause shaking head lines (referring to the human eye being in a non-static state, some frames will be missed, so that the eyes continue to see positive frames or negative frames, and some bright and dark alternating lines will appear); the Dual gate display architecture with all long connections widens the interval between bright and dark, and the human eye is more likely to recognize this difference, so it will aggravate the shaking head line phenomenon; but if this design is used on a higher resolution (PPI) display panel, the shaking head line phenomenon will be reduced because the sub-pixel size is reduced; or the human eye will not be able to distinguish this difference in time through high refresh rate.

[0065] Based on this high refresh rate and high PPI display panel, in order to ensure the high transmittance and driving capability requirements of the display panel, a high transmittance-Advanced Dimension Switch (HADS) display mode is usually adopted, and an organic film is used in the process to reduce the load of the data signal line. Figure 10-11 As shown, the pixel plan and process flow of HADS are usually Fig.10 As shown in FIG. 1 , the process of the TFT substrate is Gate metal → insulating layer → semiconductor layer → source-drain metal layer (including data line) → organic film insulating layer ORG → transparent pixel electrode → insulating layer → common electrode layer; because the characteristic of the HADS pixel mode is that the transparent common electrode should completely cover the data line to shield the electric field of the data line, so that the black matrix area blocked above the data line can be small (the black matrix in this pixel structure is only used to prevent the color filter color resistance of adjacent sub-pixels from cross-color when the alignment deviation between the color filter substrate and the array substrate is large) to achieve the improvement of the pixel aperture ratio; placing the ORG layer after the source-drain metal layer can reduce the parasitic capacitance between the data line and the common electrode covering it, which can reduce the load of the data line and improve the pixel charging rate on the one hand; on the other hand, it can also reduce the coupling effect of the data line jump on the common electrode and reduce the risk of H-crosstalk; the cross-sectional view of this pixel structure above the data line is shown in FIG. Fig.11 As shown, in order to ensure the light transmittance efficiency of the pixel, the projection of the edge of the pixel electrode is set between two patterns of the common electrode layer (referring to the common electrode layer, between the pattern covering the data line and the adjacent common electrode pattern). However, with such a setting, there is still a large lateral parasitic capacitance Cpd between the data line through the organic insulating layer and the pixel electrode.

[0066] See also Figures 12A-12F As shown, Fig. 12B for Fig. 12A Schematic diagram of a single film layer in the middle gate line layer. Fig. 12C for Fig. 12A Schematic diagram of a single film layer of the data line layer. Fig.12D for Fig. 12A Schematic diagram of a single film layer of the common electrode layer. Fig.12E for Fig. 12A Schematic diagram of a single film layer of the pixel electrode layer. Fig.12F for Fig. 12A The cross-sectional schematic diagram along the dotted line e1 in FIG. 1 shows an array substrate provided by an embodiment of the present disclosure, which includes:

[0067] Substrate 1;

[0068] A plurality of transistors T;

[0069] A plurality of gate line groups 20 are located on one side of the substrate 1, and the gate line group 20 includes: two gate lines 2 extending along a first direction X;

[0070] Multiple data lines 3;

[0071] The common electrode layer 40 is located on the side of the data line 3 away from the substrate 1; the common electrode layer 40 includes a plurality of common electrodes 4;

[0072] The pixel electrode layer 50 is located on the side of the common electrode layer 40 away from the data line 3, and includes: a plurality of pixel electrode rows 500 extending along the first direction X; the pixel electrode rows 500 include a plurality of pixel electrode groups PZ arranged along the first direction X; the gate line group 20 is located in the area between adjacent pixel electrode rows 500, and the pixel electrode group PZ is located in the area formed by the intersection of the gate line group 20 and the data line 3; the pixel electrode group PZ includes two pixel electrodes 5, and any pixel electrode 5 in the pixel electrode group PZ is electrically connected to the data line 3 through the transistor T across the other pixel electrode 5;

[0073] Among them, at least one of the common electrode layer 40 and the pixel electrode layer 50 includes: multiple first wirings 6 extending along the second direction Y; the first wirings 6 are electrically connected to the common electrode 4, and the orthographic projection of the first wirings 6 on the substrate 1 covers the orthographic projection of the data lines 3 on the substrate 1.

[0074] In the embodiment of the present disclosure, any pixel electrode 5 in the pixel electrode group PZ is electrically connected to the data line 3 through the transistor T across another pixel electrode 5, that is, a pixel architecture with all long connections, which can avoid image quality problems such as horizontal stripes, vertical stripes, and diagonal stripes caused by different pre-charging times when displaying monochrome or mixed color images; moreover, in the embodiment of the present disclosure, the array substrate includes a first wiring 6 electrically connected to the common electrode 4 and covering the data line 3, which can have a high aperture ratio, high transmittance, and high pixel charging rate, and reduce horizontal crosstalk; in addition, the pixel electrode layer 50 is located on the side of the common electrode layer 40 away from the data line 3, which can make the pixel electrode 5 and the data line 3 farther apart in the direction perpendicular to the substrate 1, with more insulating layers in between, which can reduce the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3, and improve the vertical stripes and vertical crosstalk problems caused by the parasitic capacitance Cpd when displaying monochrome or mixed color images.

[0075] In one possible implementation, combining Figure 3 As shown, in the embodiment of the present disclosure, the sub-pixels electrically connected to the same data line can have the same color. That is, the color resistance of the same color can be set in the corresponding area of ​​the color filter substrate at each pixel electrode area electrically connected to the same data line through the transistor, so that the sub-pixels electrically connected to the same data line have the same color.

[0076] The array substrate of the disclosed embodiment can be applied to display products with high resolution and high refresh rate; in the disclosed embodiment, it can be adapted to display products with a resolution (PPI) ≥ 27-inch 4K, that is, products with a PPI of 160 or more; it can be adapted to display panels with a refresh rate ≥ 120Hz. That is, in the disclosed embodiment, the resolution of the display panel can be 160 or more, and the refresh rate can be higher than 120Hz. The disclosed embodiment is suitable for high refresh rate or high resolution products. For low cost considerations, the Dual gate pixel architecture with all long connections is used to avoid the horizontal and vertical stripes of the monochrome and mixed color caused by the charging rate in the Dual gate pixel architecture display products of the prior art, and for the high transmittance HADS pixel architecture, it is proposed to reduce or eliminate the parasitic capacitance Cpd between the pixel electrode and the data line, so as to improve the poor image quality problem caused by the coupling of the parasitic capacitance Cpd in the Dual gate pixel architecture with all long connections.

[0077] In one possible implementation, combining Figures 12A-12FAs shown, the first wiring 6 is located in the pixel electrode layer 50; the common electrode layer 40 has a first hollow 41; the orthographic projection of the first wiring 6 on the substrate 1 overlaps with the orthographic projection of the first hollow 41 on the substrate 1. In the disclosed embodiment, the first wiring 6 is located in the pixel electrode layer 50, and the common electrode layer 40 has a first hollow 41 at the position of the data line 3, wherein the combination of the first wiring 6 and the common electrode 4 can cover the data line 3, and can shield the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3; and, the dielectric layer at the overlapping position of the data line 3 and the common electrode is a superposition of the organic film layer 92 and the passivation layer 93, which reduces the parasitic capacitance between the data line 3 and the common electrode (the first wiring 6) covering it, thereby reducing the load of the data line, improving the pixel charging rate, and also reducing the coupling effect of the voltage polarity jump of the data line 3 on the common electrode, reducing the problem of horizontal crosstalk.

[0078] In one possible implementation, see Figures 12A-12F As shown, the orthographic projection shape of the first hollow 41 on the substrate 1 may be consistent with the shape of the data line 3 at that position. For example, if the data line 3 is bent, the first hollow 41 is also bent.

[0079] In one possible implementation, see Figures 12A-12F As shown, the first routing line 6 is disconnected at the position of the gate line group 20. In the disclosed embodiment, the first routing line 6 covering the data line 3 does not need to completely cover the entire data line 3, and can be disconnected at the position of the gate line group 20, that is, at the position of the black matrix corresponding to the color film substrate covering the gate line group 20, the first routing line 6 may not cover the data line 3, further reducing the parasitic capacitance between the common electrode layer 40 and the data line 3, reducing the load of the data line, and the light leakage of the data line 3 at this position will be covered by the black matrix parallel to the gate line 2, and there will be no risk of light leakage.

[0080] In one possible implementation, see Figures 12A-12F As shown, the common electrode 4 extends along the first direction X and is arranged along the second direction Y, and the orthographic projection of the common electrode 4 on the substrate 1, and the area between the adjacent gate line groups 20 is within the orthographic projection of the substrate 1; the common electrode 4 has connecting portions 42 at both ends of the first hollow 41, and the common electrode 4 is connected to the first wiring 6 through the first via K1 at the connecting portion 42. In the disclosed embodiment, the common electrode 4 has a connecting portion 42 at at least one end of the first hollow 41, that is, in the second direction Y, the first hollow 41 does not penetrate the common electrode 4, so that the common electrodes 4 located on both sides of the first hollow 41 in the first direction X can be electrically connected, avoiding the increase in the manufacturing process of the array substrate when the common electrodes 4 in the first direction X are connected through other structures, and increasing the cost of the array substrate.

[0081] In a possible implementation manner, the common electrode 4 has connecting portions 42 at both ends of the first hollow 41, which can improve the reliability of the connection between the first trace 6 and the common electrode 4. Fig. 12A As shown, the first wiring 6 between two adjacent gate line groups 20 can be connected to the common electrode 4 through two first vias K1. The two first vias K1 can be located on different sides of the first wiring 6 to avoid occupying too large an area of ​​the same pixel electrode 5 when they are set on the same side, thereby affecting the normal display of the pixel electrode 5.

[0082] In one possible implementation, see Figures 12A-12F As shown, the extension length d3 of the first wiring 6 is greater than the extension length d4 of the first hollow 41. In this way, the first wiring 6 can be electrically connected to the connection portion 42 at the connection portion 42 at both ends of the first hollow 41.

[0083] In one possible implementation, see Figures 12A-12F As shown, the orthographic projection of the first wiring 61 on the substrate 1 covers the orthographic projection of the first hollow 41 on the substrate 1, and covers the orthographic projection of the connecting portion 42 on the substrate. In this way, the first wiring 6 can be electrically connected to the connecting portion 42 at the positions of the connecting portions 42 at both ends of the first hollow 41.

[0084] In one possible implementation, see Fig.12F As shown, the width d1 of the first hollow 41 in the first direction X is greater than the width d2 of the first wiring 6 in the first direction X. In this way, in the overlapping area of ​​the data line 3 and the common electrode layer 40, the dielectric layer at each position is a superposition of the organic film layer 92 and the passivation layer 93, which can minimize the parasitic capacitance between the data line 3 and the common electrode (first wiring 6) covering it, thereby reducing the load of the data line, improving the pixel charging rate, and reducing the coupling effect of the voltage polarity jump of the data line 3 on the common electrode, thereby reducing the problem of horizontal crosstalk.

[0085] In one possible implementation, see Fig.12F As shown, the orthographic projection of the first wiring 6 on the substrate covers the orthographic projection of part of the common electrode 4 on both sides of the first hollow 41 on the substrate 1. That is, there may be an overlapping area S between the first wiring 6 and the common electrode 4 on both sides of the first hollow 41, so that the combination of the first wiring 6 and the common electrode 4 can completely shield the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3.

[0086] In some pixel designs, the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3 does not need to be completely eliminated. As long as it is reduced to a certain limit, the poor image quality caused by the full long connection dual gate pixel architecture can be avoided, and there is a higher requirement for reducing the load of the data line 3. In a possible implementation, see Figure 12G As shown, the orthographic projection of the first wiring 6 on the substrate 1 does not overlap with the orthographic projection of the common electrodes 4 on both sides of the first hollow 41 on the substrate 1, that is, in a plane parallel to the substrate 1, the distance between the edges of the common electrodes 4 on both sides of the first hollow 41 and the edges of the data line 3 is enlarged. In this way, the coupling capacitance between the data line 3 and the common electrode layer 40 can be further reduced, the load of the data line can be reduced, the pixel charging rate can be improved, and the coupling effect of the voltage polarity jump of the data line 3 on the common electrode can be reduced, thereby reducing the problem of horizontal crosstalk.

[0087] In one possible implementation, see Figure 13A-13E As shown, the first wiring 6 is located in the common electrode layer 40, and is an integrally connected structure with the common electrode 4. In the disclosed embodiment, the first wiring 6 is located in the common electrode layer 40, and is an integrally connected structure with the common electrode 4. The common electrode 4 can cover the data line 3, completely shielding the electric field of the data line 3. There is no parasitic capacitance between the upper pixel electrode 5 and the data line 3, and the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3 can be eliminated; the upper pixel electrode layer 50 is not provided with a pattern for shielding the data line 3, and the pixel electrodes 5 of two adjacent sub-pixels can be closer (the minimum distance is based on the process without short circuit, usually the distance is ≥3um), which can increase the aperture ratio of the display panel.

[0088] In one possible implementation, see Fig. 13C As shown, the orthographic projection of the outer edge w1 of the pixel electrode 5 on the substrate 1 coincides with the outer edge w2 of the data line 3 on the substrate 1. In this way, the aperture ratio of the display panel can be improved.

[0089] In one possible implementation, see Figures 12A-12F , Figure 13A-13E As shown, the array substrate further includes: a plurality of second routing lines 7, and a plurality of second via hole groups K20; the second via hole group K20 includes: two second via holes K2; the two second via holes K2 of the second via hole group K20 are respectively located on both sides of the gate line group 2, and are located on different sides of the second routing line 7; the common electrodes 4 on both sides of the gate line group 20 are electrically connected to the second routing line 7 through the two second via holes K2 of the second via hole group K20. In this way, the common electrodes 4 on both sides of the gate line group 20 can be connected together through the second routing line 7.

[0090] In one possible implementation, see Figures 12A-12F , Figure 13A-13EAs shown, the second via hole K2 may be located at a region where the gate line group 20 and the data line 3 intersect.

[0091] In one possible implementation, see Figures 12A-12F , Figure 13A-13E As shown, the second wiring 7 and the data line 3 are made of the same layer and the same material; the array substrate also includes: an organic insulating layer 92 located between the data line 3 and the common electrode layer 40, and a passivation layer 93 located between the common electrode layer 40 and the pixel electrode layer 50; the pixel electrode layer 40 also includes: an overlapping portion 51; a second via K2 penetrates the passivation layer 93 and the organic insulating layer 92, and exposes a portion of the second wiring 7, and exposes a portion of the common electrode 4, and the overlapping portion 51 contacts the common electrode 4 and the second wiring 7 through the second via K2.

[0092] In one possible implementation, see Figures 12A-12F , Figure 13A-13E As shown, the second routing line 7 may include a second routing main portion 71 and a second routing extension portion 72; wherein the orthographic projection of the second routing extension portion 72 on the substrate 1 may overlap with the orthographic projection of the overlapping portion 51 on the substrate 1 to achieve electrical connection with the common electrode 4 through the second routing extension portion 72.

[0093] In one possible implementation, see Figures 12A-12D , Fig. 13B As shown, the common electrode 4 has a recessed portion 43 at the position of the second via hole K2; the orthographic projection of the second via hole K2 on the substrate 1 partially overlaps with the recessed portion 43, and partially overlaps with the common electrode 4 on the side of the recessed portion 43 away from the gate line group 20. In the disclosed embodiment, the common electrode 4 has a recessed portion 43 at the position of the second via hole K2, which can facilitate the contact between the overlapping portion 51 located in the upper layer and the second wiring 7 of the lower layer, avoiding the shielding of the common electrode 4 located in the middle layer, so that the overlapping portion 51 of the upper layer cannot contact the second wiring 7 of the lower layer; moreover, the second via hole K2 partially exposes the second wiring 7, and partially exposes the common electrode 4, half of which is used for connecting the second wiring 7 with the overlapping portion 51, and the other half is used for connecting the common electrode 4 with the overlapping portion 51, which helps to reduce the area of ​​the second via hole and increase the aperture ratio of the display panel.

[0094] In one possible implementation, see Figure 14A-14B As shown, the second wiring 7 is located on the side of the common electrode layer 40 facing the substrate 1, and is in direct contact with the common electrode 4. In the disclosed embodiment, the second wiring 7 is located on the side of the common electrode layer 40 facing the substrate 1, and is in direct contact with the common electrode 4. When the resolution and refresh rate of the display panel are high, the uniformity of the common electrode voltage can be improved; moreover, the second wiring 7 and the common electrode 4 do not need to be connected by vias, but can be in direct contact, so the connectivity is better, and the area of ​​the vias is saved, and the light transmittance of the pixels can also be improved.

[0095] In one possible implementation, see Fig.16 As shown, the common electrode layer 40 may also be disposed on a side of the pixel electrode layer 50 away from the substrate 1 , and the parasitic capacitance Cpd between the data line 3 and the pixel electrode 5 may be reduced by increasing the lateral distance between the pixel electrode 5 and the data line 3 .

[0096] Based on the same inventive concept, the present disclosure also provides a display panel, see Fig.15 As shown, it includes an array substrate as provided in an embodiment of the present disclosure, and also includes a color filter substrate arranged opposite to the array substrate, the color filter substrate may include: a color filter substrate 95, a black matrix 96 located on the side of the color filter substrate 95 facing the array substrate, and a color filter layer located on the side of the black matrix 96 facing the array substrate, the color filter layer may include: a first color resistance 971, a second color resistance 972, and a third color resistance (not shown in the figure). The first color resistance 971 can be a red color resistance, the second color resistance 972 can be a green color resistance, and the third color resistance can be a blue color resistance. Optionally, the positive projection of the black matrix 96 on the substrate 1 can cover the positive projection of the gate line group 20 on the substrate 1; optionally, the color filter substrate may not be provided with a black matrix or a black matrix with a narrower line width at the position corresponding to the data line 3, that is, the data line 3 can be covered by the first wiring 6 to shield the electric field on the data line 3 and shield the leakage light.

[0097] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided in the embodiment of the present disclosure. The implementation of the display device can refer to the embodiment of the above-mentioned display panel, and the repeated parts will not be repeated. The display device can be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The other essential components of the display device should be understood by ordinary technicians in the field, and will not be repeated here, nor should they be used as a limitation to the present disclosure.

[0098] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0099] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An array substrate, in, include: substrate; Multiple transistors; A plurality of gate line groups are located on one side of the substrate, the gate line groups comprising: two gate lines extending along the first direction; Multiple data lines; A common electrode layer, located on a side of the data line away from the substrate; the common electrode layer includes a plurality of common electrodes; A pixel electrode layer, located at a side of the common electrode layer away from the data line, comprising: a plurality of pixel electrode rows extending along a first direction; the pixel electrode rows comprising a plurality of pixel electrode groups arranged along the first direction; the gate line group being located in an area between adjacent pixel electrode rows, the pixel electrode group being located in an area formed by the intersection of the gate line group and the data line; the pixel electrode group comprising two pixel electrodes, and any one of the pixel electrodes in the pixel electrode group being electrically connected to the data line through the transistor across the other pixel electrode; Among them, at least one of the common electrode layer and the pixel electrode layer includes: a plurality of first wirings extending along the second direction; the first wirings are electrically connected to the common electrodes, and the orthographic projection of the first wirings on the substrate covers the orthographic projection of the data lines on the substrate.

2. The array substrate according to claim 1, in, The first wiring is located at the pixel electrode layer; The common electrode layer has a first hollow; the orthographic projection of the first wiring on the substrate overlaps with the orthographic projection of the first hollow on the substrate.

3. The array substrate according to claim 2, in, The first wiring is disconnected at the position of the gate line group.

4. The array substrate according to claim 2 or 3, in, The common electrode extends along the first direction and is arranged along the second direction, and the orthographic projection of the common electrode on the substrate and the area between the adjacent gate line groups are within the orthographic projection of the substrate; The common electrode has a connecting portion at at least one end of the first hollow portion, and the common electrode is electrically connected to the first wiring through a first via hole at the connecting portion.

5. The array substrate according to any one of claims 2 to 4, in, An extension length of the first routing line is greater than an extension length of the first hollowing out.

6. The array substrate according to any one of claims 2 to 5, in, The orthographic projection of the first routing line on the substrate covers the orthographic projection of the first hollow on the substrate, and covers the orthographic projection of the connecting portion on the substrate.

7. The array substrate according to any one of claims 2 to 6, in, The orthographic projection of the first wiring on the substrate covers the orthographic projection of a portion of the common electrode on both sides of the first hollow on the substrate.

8. The array substrate according to any one of claims 2 to 4, in, The orthographic projection of the first wiring on the substrate does not overlap with the orthographic projection of the common electrodes on both sides of the first hollowing out on the substrate.

9. The array substrate according to claim 1, in, The first wiring is located in the common electrode layer and is integrally connected with the common electrode.

10. The array substrate according to claim 9, in, The orthographic projection of the outer edge of the pixel electrode on the substrate coincides with the outer edge of the data line on the substrate.

11. The array substrate according to any one of claims 3 to 10, in, The array substrate also includes: multiple second routing lines and multiple second via groups; the second via group includes: two second vias; the two second vias of the second via group are respectively located on both sides of the gate line group and on different sides of the second routing line; the common electrodes on both sides of the gate line group are electrically connected to the second routing line through the two second vias of the second via group.

12. The array substrate according to claim 11, in, The second wiring is made of the same layer and material as the data line; the array substrate further comprises: an organic insulating layer between the data line and the common electrode layer, and a passivation layer between the common electrode layer and the pixel electrode layer; the pixel electrode layer further comprises: an overlap portion; The second via hole penetrates the passivation layer and the organic insulating layer, and exposes a portion of the second wiring and a portion of the common electrode. The overlapping portion contacts the common electrode and the second wiring through the second via hole.

13. The array substrate according to claim 12, in, The common electrode has a recessed portion at the position of the second via hole; the orthographic projection of the second via hole on the substrate partially overlaps with the recessed portion and partially overlaps with the common electrode on a side of the recessed portion away from the gate line group.

14. The array substrate according to claim 11, in, The second wiring is located on a side of the common electrode layer facing the substrate and is in direct contact with the common electrode.

15. A display panel, in, It comprises the array substrate as described in any one of claims 1 to 14.

Images