Heterogeneous integrated N-well super-junction silicon carbide MOSFET structure and preparation method thereof

Abstract

The invention relates to a super-junction silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure of a heterogeneous integrated N well and a preparation method of the super-junction silicon carbide MOSFET structure. The structure comprises a semiconductor substrate of a first conduction type; the first column region of the first conduction type and the second column region of the second conduction type are formed above the semiconductor substrate, and the first column region and the second column region are mutually staggered to form a super junction structure. The super-junction structure is different from a common super-junction structure, the common super-junction structure needs to consider the compromise relation of conduction and depletion of a device in three parts of JFET, channel and Pwell, but the super-junction structure can be completely approximate to the design of the concentration and width of a P column and an N column, and under the specific concentration of the P / N column, the concentration of the P column and the width of the N column can be greatly reduced. P + and Pwell regions in the device can be completely replaced by the P columns.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a heterogeneous integrated N-well super junction silicon carbide MOSFET structure and a preparation method thereof. Background Art

[0002] Silicon carbide (Si li con Carbide) high-voltage power devices have better electrothermal properties than traditional silicon devices and can work normally in harsh environments. Therefore, they have broad application prospects in photovoltaic power generation, electric vehicles, aerospace and other fields.

[0003] For silicon carbide MOSFET devices, the current main development direction is to achieve a continuous reduction in specific on-resistance by reducing the cell size and improving the process. However, due to the limitations of the characteristic process of power devices, the technical difficulty and cost of cell size miniaturization and advanced process development are rapidly increasing. At the same time, there is a "one-dimensional limit" problem in the on-resistance and blocking voltage of the device, that is, as the blocking voltage of the device increases, the doping concentration of the drift region decreases and the thickness increases, resulting in a sharp increase in the on-resistance of the device. In order to break through the "one-dimensional limit" of power semiconductor devices, the charge balance principle can be used to construct a superjunction structure, which greatly optimizes the contradiction between the on-resistance and blocking voltage of the SiC MOSFET device.

[0004] At present, there are three technical routes for silicon carbide MOSFET devices:

[0005] (1) Planar gate SiC MOSFET: It has the characteristics of high reliability and is the mainstream SiC power switch device on the market, but it has certain bottlenecks in cell miniaturization;

[0006] (2) Trench-gate SiC MOSFET: It has great advantages in achieving cell size miniaturization, but the high gate oxide electric field strength at the bottom of the trench poses a serious risk to device reliability;

[0007] (3) Superjunction SiC MOSFET: The superjunction structure achieves low on-resistance while maintaining high voltage by alternating P-type and N-type doped regions in the SiC matrix. It is suitable for fast switching applications with high energy efficiency and high power density. However, due to its larger pn junction area, it has some problems with the reverse current and reverse recovery time of the internal diode. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a heterogeneous integrated N-well super junction silicon carbide MOSFET structure and a preparation method thereof in view of the above shortcomings, so as to break through the performance limit of the existing silicon carbide MOSFET.

[0009] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0010] A heterogeneous integrated N-well super junction silicon carbide MOSFET structure, comprising:

[0011] a semiconductor substrate of a first conductivity type;

[0012] A first column region of a first conductivity type and a second column region of a second conductivity type are formed above the semiconductor substrate, wherein the first column region and the second column region are interlaced to form a super junction structure;

[0013] A shielding region is formed on the surface of the second column region, a first trench is opened in the shielding region, a source region of a first conductivity type is formed in the first trench, and the source region is in contact with the first column region to form a heterojunction structure;

[0014] A source metal is formed above the first column region and the second column region, and the source metal is in contact with the shielding region and a portion of the source region;

[0015] A gate structure is formed between the first column region, the second column region and the source metal, and the gate structure is in contact with a portion of the source region and a portion of the second column region;

[0016] A drain metal is formed below the semiconductor substrate.

[0017] Furthermore, the first column region includes a drift region and a carrier storage region arranged sequentially from bottom to top.

[0018] Furthermore, the outer sides of the shielding region and the source region are covered with a well region of the second conductivity type, and the side surface of the well region extends to the first column region;

[0019] The surface of the well region is spaced from the surface of the first column region, a channel is formed by the space, the carrier storage region and the source region are in contact through the channel to form a heterojunction, and by applying voltage to the gate structure, the surface energy band of the carrier storage region can be adjusted to make the carrier storage region and the source region conductive; or there is no space between the surface of the well region and the surface of the first column region, that is, no channel is formed.

[0020] Furthermore, the gate structure includes a gate oxide and a polysilicon gate, the gate oxide is formed on the surface of the first column region, the second column region and the source region, the gate oxide is in contact with the first column region, the second column region and the source region, and the polysilicon gate is formed on the surface of the gate oxide.

[0021] Furthermore, the gate structure further includes an interlayer dielectric formed between the polysilicon gate and the source metal.

[0022] Furthermore, an insulating layer is provided between the source metal and the first column region.

[0023] Furthermore, the first conductivity type is N type, the second conductivity type is P type, and the shielding region is a P+ region.

[0024] Furthermore, the first column region and the second column region are made of silicon carbide, and the source region is made of polycrystalline silicon.

[0025] A method for preparing a heterogeneously integrated N-well superjunction silicon carbide MOSFET comprises the following steps:

[0026] Step S1, forming silicon carbide of a first conductivity type on a semiconductor substrate of a first conductivity type;

[0027] Step S2, etching on silicon carbide to form a second groove;

[0028] Step S3, forming silicon carbide of a second conductivity type in the second trench to obtain a first column region and a second column region, and forming a super junction structure;

[0029] Step S4, forming a shielding region of the second conductivity type on the second pillar region through an ion implantation process, and forming a carrier storage region on the second pillar region;

[0030] Step S5, etching to form a first trench on the surface of the shielding region, and filling the first trench with polysilicon of the first conductivity type to obtain a source region;

[0031] Step S6, forming gate oxide by thermal oxidation above the source region and the second pillar region;

[0032] Step S7, depositing a polysilicon gate and an interlayer dielectric on the gate oxide to form a MOS structure;

[0033] Step S8, depositing source metal in the region between adjacent polysilicon gates, and making the source metal contact the source region;

[0034] Step S9, gate opening;

[0035] Step S10, depositing a thick source metal layer on the interlayer dielectric to form a source structure;

[0036] Step S11, forming a drain metal below the semiconductor substrate.

[0037] Furthermore, before step S4, the following steps are also included:

[0038] Step S3.5: implanting ions of the first conductivity type into the surface of the first column region, and performing high-temperature annealing and activation to form a well region of the second conductivity type on the first column region.

[0039] After adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0040] 1. The superjunction structure of the present invention is different from the common superjunction structure. The common superjunction structure needs to consider the compromise relationship between conduction and depletion of the device in the three parts of JFET-channel-Pwell, but the superjunction structure of the present invention can be completely approximated by the design of the concentration and width of the P column and the N column. Under the specific concentration of the P / N column, the P+ and Pwell regions in the device can be completely replaced by the P column;

[0041] 2. The gate design of the present invention can be shorter than the general split gate. The general split gate structure needs to consider the strong electric field in the JFET region, but the gate structure of the present invention can reduce the influence of the strong electric field of the JFET by reducing the cell size;

[0042] 3. The sidewall of the source region (i.e., the sidewall of the first trench) of the present invention contacts the second pillar region to form a heterojunction, which can shorten or omit the channel to reduce the cell size. At the same time, an N-type accumulation channel is used to replace the inversion channel, which greatly improves the channel mobility and achieves a significant reduction in the device specific on-resistance;

[0043] When the device is forward blocked, the protection of the shielding area and the well area can be combined to reduce the leakage current of the device. When the device is reverse-conducting, the voltage drop of the heterojunction forward conduction is lower, which can greatly reduce the reverse conduction loss of the device and inhibit the bipolar degradation caused by the conduction of the body diode. At the same time, the heterojunction stores fewer excess carriers, and the reverse recovery characteristics of the device are better.

[0044] 4. The present invention can utilize the gate to control the height of the heterojunction barrier to achieve the opening and closing of the control device;

[0045] 5. The present invention can omit the P well as required, and use the P+ region to shield and protect the bottom of the source region. At the same time, the P+ region completely surrounds the source region, which can greatly reduce the turn-on of the parasitic NPN transistor and improve the reliability of the device;

[0046] 6. The preparation method of the present invention is compatible with the preparation process of traditional planar gate silicon carbide MOSFET devices.

[0047] The present invention is described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 FIG. 4 is a device structure diagram of an embodiment of the present invention.

[0049] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0050] 1. semiconductor substrate; 2. first column region; 21. drift region; 22. carrier storage region; 3. second column region; 41. shielding region; 42. first trench; 43. source region; 44. well region; 45. channel; 5. source metal; 51. insulating layer; 6. gate structure; 61. gate oxide; 62. polysilicon gate; 63. interlayer dielectric; 64. gate dielectric; 7. drain metal DETAILED DESCRIPTION

[0051] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0052] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", "clockwise" and "counterclockwise" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0053] Embodiment 1:

[0054] like Figure 1 As shown, a heterogeneous integrated N-well super junction silicon carbide MOSFET structure includes:

[0055] N-type semiconductor substrate 1.

[0056] A first column region 2 and a second column region 3 are formed on a semiconductor substrate 1, the first column region 2 and the second column region 3 are alternately arranged to form a super junction structure, the first column region 2 is made of N-type silicon carbide, and the second column region 3 is made of P-type silicon carbide;

[0057] After N-type silicon carbide is formed on the semiconductor substrate 1, a second trench is etched on the surface thereof, and the second trench penetrates the back side of the N-type silicon carbide, and then P-type silicon carbide (P column) is epitaxially grown in the second trench, thereby forming a super junction structure;

[0058] The first stud region 2 includes a drift region 21 and a carrier storage region 22 arranged sequentially from bottom to top.

[0059] A shielding region 41 is formed above the second column region 3. The shielding region 41 is a P+ region. A first trench 42 is etched on the surface of the second column region 41. The first trench 42 is filled with N-type polysilicon, so that a source region 43 is formed in the first trench 42. The shielding region 41 covers the outer side of the first trench 42 to form shielding protection.

[0060] The sidewall of the first trench 42 contacts the first column region 2, so that the N-type polysilicon contacts the N-type silicon carbide to form a heterojunction;

[0061] The heterojunction formed by N-type polysilicon and N-type silicon carbide has a certain barrier height, which makes the device in a normally-off state when no gate voltage is applied;

[0062] When a positive voltage exceeding the threshold voltage is applied to the gate, the barrier height of silicon carbide in the heterojunction decreases, the silicon carbide MOSFET device is turned on, and the electrons in the source region 43 enter the drain after passing through the channel 45, the carrier storage region 22, the drift region 21 and the semiconductor substrate 1;

[0063] When the gate voltage is lower than the device threshold voltage, the SiC MOSFET device is turned off;

[0064] When a high voltage is applied to the drain of the device, the PN junction composed of the P-well region 44, the P+ shielding region 41 and the N-type drift region 21 is reverse biased to withstand the blocking voltage, and the reverse biased heterojunction can also reduce the leakage current of the device;

[0065] When the drain and source of the device are subjected to reverse voltage, the heterojunction formed by N-type polysilicon and N-type silicon carbide is forward-conducted, and the device conducts reverse current. Since the forward voltage drop of the heterojunction is low, the reverse voltage drop of the silicon carbide MOSFET device is low, which can simultaneously suppress the bipolar degradation caused by the conduction of the body diode; since the heterojunction formed by N-type polysilicon and N-type silicon carbide is unipolar (only electrons work as carriers), the reverse recovery characteristics of the device are better.

[0066] The shielding region 41 and the outer side of the first trench 42 are covered with a P-well region 44, and the well region 44 and the shielding region 41 are sequentially covered on the outer side of the first trench 42 to shield and protect the N-type polysilicon in the first trench 42;

[0067] The well region 44 and the shielding region 41 surround the N-type polysilicon to form shielding protection. The upper surface of the well region 44 is spaced a certain distance from the upper surface of the first column region 2. The spacing with a lateral distance forms a channel 45 of the silicon carbide MOSFET device. The N-type polysilicon and the N-type silicon carbide form a heterojunction, so that the device is in a normally-off state when no gate voltage is applied.

[0068] The above structure utilizes the method of controlling the height of the heterojunction barrier by the gate to realize the on and off control of the MOSFET device, which can significantly shorten or eliminate the channel in the traditional planar gate structure, and can use an accumulation channel to replace the inversion channel in the traditional structure, thereby improving the mobility of the channel and reducing the device's specific on-resistance.

[0069] A source metal 5 is formed above the first column region 2 and the second column region 3 , and an insulating layer 51 is provided between the source metal 5 and the first column region 2 . The insulating layer 51 is a SiO 2 thin film and is used to prevent the first column region 2 and the source metal 5 from short-circuiting.

[0070] A gate structure 6 is formed between the first column region 2, the second column region 3 and the source metal 5, and the gate structure 6 includes a gate oxide 61, a polysilicon gate 62 and an interlayer dielectric 63. The gate oxide 61 is formed on the surface of the first column region 2 and the source region 43, and is in contact with the first column region 2 and the source region 43. The polysilicon gate 62 is formed on the surface of the gate oxide 61 (a gate dielectric 64 can be deposited between the gate oxide 61 and the polysilicon gate 62, or can be omitted), and the side and top surfaces of the polysilicon gate 62 are formed with an interlayer dielectric 63.

[0071] The gate can adopt a split gate structure. In this embodiment, the opening of the channel actually only requires N-type silicon carbide to provide a longitudinal voltage in the gate region, so that its energy band bending is less than or equal to the energy band of the heterojunction under the gate voltage. In theory, the length of the gate can be shortened from the length of the traditional structure to only allow the N-type silicon carbide energy band in the heterojunction to bend and turn on the device. This design can greatly reduce the gate-drain capacitance of the device and improve the switching characteristics of the device.

[0072] A drain metal 7 is formed below the semiconductor substrate 1 .

[0073] A method for preparing a heterogeneously integrated N-well superjunction silicon carbide MOSFET comprises the following steps:

[0074] (1) forming N-type silicon carbide on an N-type semiconductor substrate 1 to obtain a drift region 21 having the same conductivity type as the semiconductor substrate 1;

[0075] (2) etching a second trench on the N-type silicon carbide, wherein the bottom end of the second trench penetrates the N-type silicon carbide;

[0076] (3) epitaxially growing P-type silicon carbide in the second trench, thereby forming a first column region 2 and a second column region 3, namely, an N column and a P column, constituting a super junction structure;

[0077] (4) using ion implantation, high temperature annealing and activation to form a P-well region 44 on the first column region 2;

[0078] (5) forming a carrier storage region 22 on the surface of the first column region 2 and a shielding region 41 on the surface of the second column region 3 through an ion implantation process;

[0079] (6) etching a first trench 42 in the shielding region 41 and filling the first trench 42 with N-type polysilicon to form a source region 43;

[0080] (7) A thin gate oxide 61 is formed on the source region 43 and the second stud region 3 by a thermal oxidation process, and the gate oxide 61 is in contact with a portion of the second stud region 3 and a portion of the source region 43;

[0081] (8) Depositing a high-k dielectric such as Al2O3 on the gate oxide 61 to form a gate dielectric layer 64; (This step and this layer can be omitted as needed)

[0082] (9) depositing a polysilicon gate 62 and an interlayer dielectric 63 on the gate dielectric 64 or the gate oxide 61 to form a MOS structure;

[0083] (10) depositing source metal 5 in the region between adjacent polysilicon gates 62, and making the source metal 5 contact the source region 43;

[0084] (11) Gate opening;

[0085] (12) depositing a thick source metal 5 on the polysilicon gate 62 (interlayer dielectric) to form a source structure;

[0086] (13) Formation of surface protection structures such as TEOS and PI;

[0087] (14) thinning the back side of the semiconductor substrate 1;

[0088] (15) A drain metal 7 is formed on the back side of the semiconductor substrate 1 to form a drain structure.

[0089] Embodiment 2:

[0090] In this embodiment, based on the first embodiment, the well region 44 is omitted, and step (4) in the above-mentioned preparation process is also omitted.

[0091] In the case where the channel does not need to be retained, the well region 44 can be removed to reduce the mask and an ion implantation process. In this case, the shielding region 41 (P+ region) is directly used to form a shielding protection for the N-type polysilicon in the first trench 42. Since the P+ region forms a full surrounding protection for the N-type polysilicon, the concentration of the P+ region is relatively high, which can greatly suppress the parasitic NPN transistor inside the silicon carbide MOSFET device, thereby improving the reliability of the device.

[0092] The above is an example of the best implementation of the present invention, and the parts not described in detail are common knowledge of ordinary technicians in the field. The protection scope of the present invention shall be based on the content of the claims, and any equivalent transformation based on the technical enlightenment of the present invention is also within the protection scope of the present invention.

Claims

1. A heterogeneous integrated N-well superjunction silicon carbide MOSFET structure, characterized in that: include: A semiconductor substrate (1) of a first conductivity type; A first column region (2) of a first conductivity type and a second column region (3) of a second conductivity type are formed above the semiconductor substrate (1), wherein the first column region (2) and the second column region (3) are interlaced to form a super junction structure; A shielding region (41) is formed on the surface of the second column region (3), a first groove (42) is formed in the shielding region (41), a source region (43) of a first conductivity type is formed in the first groove (42), and the source region (43) is in contact with the first column region (2) to form a heterojunction structure; A source metal (5) is formed above the first column region (2) and the second column region (3), and the source metal (5) is in contact with the shielding region (41) and a portion of the source region (43); A gate structure (6) is formed between the first column region (2), the second column region (3) and the source metal (5), and the gate structure (6) is in contact with a portion of the source region (43) and a portion of the first column region (2); A drain metal (7) is formed below the semiconductor substrate (1).

2. The heterogeneous integrated N-well superjunction silicon carbide MOSFET structure according to claim 1, characterized in that: The first column region (2) comprises a drift region (21) and a carrier storage region (22) which are arranged in sequence from bottom to top.

3. The heterogeneous integrated N-well superjunction silicon carbide MOSFET structure according to claim 2, characterized in that: The outer sides of the shielding region (41) and the source region (43) are covered with a well region (44) of the second conductivity type, and the side surface of the well region (44) extends to the first column region (2); The surface of the well region (44) is spaced from the surface of the first column region (2), the space forming a channel (45), the carrier storage region (22) and the source region (43) contact each other through the channel (45) to form a heterojunction, and by applying a voltage to the gate structure (6), the surface energy band of the carrier storage region (22) can be adjusted to make the carrier storage region (22) and the source region (43) conductive; or the surface of the well region (44) and the surface of the first column region (2) have no space, i.e., no channel (45) is formed.

4. The heterogeneous integrated N-well superjunction silicon carbide MOSFET structure according to claim 1, characterized in that: The gate structure (6) comprises a gate oxide (61) and a polysilicon gate (62); the gate oxide (61) is formed on the surfaces of the first column region (2), the second column region (3) and the source region (43); the gate oxide (61) is in contact with the first column region (2), the second column region (3) and the source region (43); and the polysilicon gate (62) is formed on the surface of the gate oxide (61).

5. The heterogeneous integrated N-well superjunction silicon carbide MOSFET structure according to claim 4, characterized in that: The gate structure (6) further comprises an interlayer dielectric (63), wherein the interlayer dielectric (63) is formed between the polysilicon gate (62) and the source metal (5).

6. The heterogeneous integrated N-well superjunction silicon carbide MOSFET structure according to claim 1, characterized in that: An insulating layer (51) is provided between the source metal (5) and the first column region (2).

7. The heterogeneous integrated N-well superjunction silicon carbide MOSFET structure according to any one of claims 1 to 6, characterized in that: The first conductivity type is N type, the second conductivity type is P type, and the shielding area (41) is a P+ area.

8. The heterogeneous integrated N-well superjunction silicon carbide MOSFET structure according to any one of claims 1 to 6, characterized in that: The first column region (2) and the second column region (3) are made of silicon carbide, and the source region (43) is made of polycrystalline silicon.

9. A method for preparing a heterogeneously integrated N-well superjunction silicon carbide MOSFET, characterized in that: The following steps are involved: Step S1, forming silicon carbide of a first conductivity type on a semiconductor substrate (1) of a first conductivity type; Step S2, etching on silicon carbide to form a second groove; Step S3, forming silicon carbide of a second conductivity type in the second trench to obtain a first column region (2) and a second column region (3), and forming a super junction structure; Step S4, forming a shielding region (41) of the second conductivity type on the second pillar region (3) and forming a carrier storage region (22) on the second pillar region (3) through an ion implantation process; Step S5, etching the surface of the shielding region (41) to form a first trench (42), and filling the first conductive type polysilicon in the first trench (42) to obtain a source region (43); Step S6, forming a gate oxide (61) by thermal oxidation above the source region (43) and the second pillar region (3); Step S7, depositing a polysilicon gate (62) and an interlayer dielectric (63) on the gate oxide (61) to form a MOS structure; Step S8, depositing a source metal (5) in the region between adjacent polysilicon gates (62), and making the source metal (5) contact the source region (43); Step S9, gate opening; Step S10, depositing a thick source metal layer (5) on the interlayer dielectric (63) to form a source structure; Step S11, forming a drain metal (7) below the semiconductor substrate (1).

10. The method for preparing a heterogeneously integrated N-well superjunction silicon carbide MOSFET according to claim 9, characterized in that: Before step S4, the following steps are also included: Step S3.5, implanting ions of the first conductivity type into the surface of the first column region (2), and performing high temperature annealing and activation to form a well region (44) of the second conductivity type on the first column region (2).

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