Anti-radiation reinforced silicon carbide MOSFET structure and preparation method thereof

Abstract

The invention relates to an anti-radiation reinforced silicon carbide MOSFET structure and a preparation method thereof, the structure comprises drain electrode metal, an N substrate, N-type silicon carbide and source electrode metal which are sequentially laminated from bottom to top, a polysilicon gate is arranged between the source electrode metal and the N-type silicon carbide, gate oxide is formed between the polysilicon gate and the N-type silicon carbide, and the gate oxide is formed between the N-type silicon carbide and the source electrode metal. A source electrode region is formed on the surface of the N-type silicon carbide, the surface of the source electrode region is in contact with gate oxide and source electrode metal, a groove is formed in the surface of the N-type silicon carbide, the groove is located below a polysilicon gate and filled with first N-type polysilicon, a first shielding region is formed on the surface of the N-type silicon carbide, and a second shielding region is formed on the surface of the N-type silicon carbide. And the first shielding region coats the outer side of the groove. According to the invention, the anti-single-particle gate penetration capability and the anti-single-particle radiation capability of the silicon carbide MOSFET device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a radiation-resistant reinforced silicon carbide MOSFET structure and a preparation method thereof. Background Art

[0002] Silicon carbide (Si li con Carbide) high-voltage power devices have better electrothermal properties than traditional silicon devices and can work normally in more harsh environments. Therefore, they have broad application prospects in photovoltaic power generation, electric vehicles, aerospace and other fields.

[0003] In the field of aerospace, radiation hardening is a major problem. Current SiC power devices often experience single-particle burnout when the blocking voltage is less than 1 / 3 and the LET is no higher than 10MeV.cm2 / mg, which is far lower than theoretical expectations. Single-particle radiation usually involves complex electrothermal coupling responses inside the device. When heavy ions bombard the power device, a large number of electron-hole pairs are generated along the motion trajectory. These electron-hole pairs drift under the action of the electric field, forming a large instantaneous current inside the device. Some electrons and holes will also accumulate at both ends of the device, thereby reconstructing the electric field inside the device, resulting in strong electric field breakdown in the local part of the device, such as single-particle gate breakdown. In addition, this large amount of electron-hole movement and strong electric field coupling generate huge instantaneous heat inside the device, which may cause single-particle burnout in the local part of the device. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a radiation-hardened silicon carbide MOSFET structure and a preparation method thereof in view of the above shortcomings.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A radiation-hardened silicon carbide MOSFET structure includes a drain metal, an N substrate, an N-type silicon carbide and a source metal stacked sequentially from bottom to top.

[0007] A polysilicon gate is arranged between the source metal and the N-type silicon carbide, and a gate oxide is formed between the polysilicon gate and the N-type silicon carbide.

[0008] A source region is formed on the surface of the N-type silicon carbide, and the surface of the source region is in contact with the gate oxide and the source metal.

[0009] A groove is formed on the surface of the N-type silicon carbide, the groove is located below the polysilicon gate, the groove is filled with a first N-type polysilicon, and the first N-type polysilicon is in contact with the source metal.

[0010] A first shielding region is formed on the surface of the N-type silicon carbide, and the first shielding region covers the outer side of the trench.

[0011] Furthermore, the first shielding region is a P-type doped region.

[0012] Furthermore, the source region includes an N-well groove opened on the surface of the N-type silicon carbide and a second N-type polysilicon filled in the N-well groove.

[0013] A second shielding region is formed on the surface of the N-type silicon carbide, the second shielding region covers the outer side of the source region, one side of the N-well groove is in contact with the N-type silicon carbide, and the second N-type polysilicon and the N-type silicon carbide form a heterojunction structure.

[0014] Furthermore, the second shielding region is a P+ region.

[0015] Furthermore, a P-well region is formed on the N-type silicon carbide, and the P-well region covers the outer sides of the second shielding region and the source region;

[0016] The surface of the P-well region is spaced apart from the surface of the N-type silicon carbide, and the space with a lateral distance forms a channel in contact between the N-type silicon carbide and the second N-type polysilicon; or the surface of the P-well region is not spaced apart from the surface of the N-type silicon carbide, i.e., there is no channel.

[0017] Furthermore, the N-type silicon carbide includes an N buffer layer, an N-type drift layer and a carrier storage layer arranged in sequence from top to bottom, and the trench, the first shielding region, the source region, the second shielding region and the P-well region are all located in the carrier storage layer.

[0018] Furthermore, an interlayer dielectric is formed between the polysilicon gate and the source metal.

[0019] Furthermore, a gate dielectric is formed between the gate oxide and the polysilicon gate.

[0020] A method for preparing a radiation-hardened silicon carbide MOSFET comprises the following steps:

[0021] Step S1, forming N-type silicon carbide on an N substrate;

[0022] Step S2, implanting carrier storage layer ions, P-type doping ions and P+ ions into the N-type silicon carbide, and performing high temperature annealing and activation to form a carrier storage layer, a first shielding region and a second shielding region on the N-type silicon carbide;

[0023] Step S3, etching the surface of the N-type silicon carbide to form a groove and an N-well groove, and filling the groove and the N-well groove with a first N-type polysilicon and a second N-type polysilicon respectively;

[0024] Step S4, thermally oxidizing the N-type silicon carbide to form a gate oxide;

[0025] Step S5, depositing a polysilicon gate and an interlayer dielectric on the gate oxide to form a MOS structure;

[0026] Step S6, depositing source metal in the region between adjacent polysilicon gates, and making the source metal contact the second N-type polysilicon;

[0027] Step S7, gate opening;

[0028] Step S8, depositing a thick source metal layer on the interlayer dielectric to form a source structure;

[0029] Step S9: forming a drain metal below the N substrate.

[0030] Furthermore, in the step S2, before high temperature annealing and activation, P-well ions are implanted into the N-type silicon carbide to form a P-well region on the N-type silicon carbide after high temperature annealing and activation.

[0031] After adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0032] (1) The present invention introduces a trench structure on the device, and the sidewalls and bottom of the trench are provided with a P-type doped region, and the trench is filled with N-type polysilicon. The trench structure can transfer the strong electric field at the gate oxide interface to the bottom position of the carrier storage layer, so as to greatly reduce the electric field strength in the gate oxide, thereby improving the single particle gate penetration resistance of the silicon carbide MOSFET device;

[0033] (2) The P-type doped regions at the bottom and sidewalls of the trench enhance the extraction efficiency of holes near the carrier storage layer at the moment of heavy ion bombardment, which can quickly and efficiently remove the electron-hole pairs generated by heavy ion bombardment, reduce the current and radiation response time generated by single particle radiation, and effectively improve the single particle radiation resistance of SiC MOSFET;

[0034] (3) The introduction of the trench structure can enhance the pinch-off effect of the carrier storage layer at high blocking voltages. Without affecting the voltage blocking capability of the device, the doping concentration of the carrier storage layer can be increased to significantly improve the recombination efficiency of holes and electrons at the moment of single-particle radiation through the carrier storage layer with a higher doping concentration and the second N-type polysilicon short-circuited with the source metal, thereby improving the radiation resistance of the silicon carbide MOSFET device;

[0035] (4) By introducing an N buffer layer on the back of N-type SiC, the transient peak electric field strength on the back of N-type SiC is reduced, the breakdown of the N-type high-low junction on the back is suppressed, and the single-particle radiation resistance of SiC MOSFET devices is effectively improved;

[0036] (5) The present invention uses N-type polysilicon to form a source electrode, and N-type polysilicon and N-type silicon carbide form a heterojunction. The heterojunction makes the device in a normally-off state when no gate voltage is applied. The structure uses a method of controlling the height of the heterojunction barrier by the gate to achieve the on and off control of the silicon carbide MOSFET device, which can shorten or omit the channel in the traditional planar gate structure, thereby achieving the miniaturization of the silicon carbide MOSFET device cell;

[0037] While retaining the channel, the inversion channel is replaced by an N-type accumulation channel, which greatly improves the channel mobility and reduces the specific on-resistance of the silicon carbide MOSFET device.

[0038] (6) The present invention can omit the P-well as required. In the absence of the P-well region, the P+ region completely wraps the bottom of the N-well groove to achieve shielding protection. At the same time, the P+ region completely surrounds the N-well, which can greatly reduce the turn-on of the parasitic NPN transistor and improve the reliability of the device.

[0039] (7) The heterojunction formed by N-type polysilicon and N-type silicon carbide is reverse biased when the device is forward blocked, and can be combined with the shielding protection of the P-well / P+ to reduce the leakage current of the device. When the device is reverse-conducting, the forward conduction voltage drop of the heterojunction is lower, which can greatly reduce the reverse conduction loss of the silicon carbide MOSFET device and inhibit the bipolar degradation caused by the conduction of the body diode. At the same time, the heterojunction stores less excess carriers, and the reverse recovery characteristics of the silicon carbide MOSFET device are better.

[0040] The present invention is described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 FIG. 4 is a device structure diagram of an embodiment of the present invention.

[0042] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0043] 1. Drain metal; 2. N substrate; 3. N-type silicon carbide; 3a. N buffer layer; 3b. N-type drift layer; 3c. Carrier storage layer; 31. Groove; 32. First shielding region; 33. Second shielding region; 34. P-well region; 35. Channel; 4. Source metal; 5. Polysilicon gate; 51. Gate oxide; 52. Interlayer dielectric; 53. Gate dielectric; 6. Source region; 61. N-well groove; 62. Second N-type polysilicon; 7. First N-type polysilicon. DETAILED DESCRIPTION

[0044] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0045] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", "clockwise" and "counterclockwise" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0046] Embodiment 1:

[0047] like Figure 1 As shown, a radiation-hardened silicon carbide MOSFET structure includes a drain metal 1, an N substrate 2, an N-type silicon carbide 3 and a source metal 4 stacked from bottom to top.

[0048] A polysilicon gate 5 is formed between the N-type silicon carbide 3 and the source metal 4 , a gate oxide 51 is formed between the polysilicon gate 5 and the N-type silicon carbide 3 (a gate dielectric 52 may be deposited between the gate oxide 51 and the polysilicon gate 5 , or may be omitted), and an interlayer dielectric 53 is formed between the polysilicon gate 5 and the source metal 4 .

[0049] The N-type silicon carbide 3 includes an N-buffer layer 3 a , an N-type drift layer 3 b , and a carrier storage layer 3 c arranged in sequence from bottom to top.

[0050] A groove 31 is etched on the N-type silicon carbide 3, and the groove 31 is filled with the first N-type polysilicon 7. The groove 31 is located below the polysilicon gate 5. A first shielding area 32 is formed on the surface of the N-type silicon carbide 3. The first shielding area 32 is a P-type doped area. The first shielding area 32 is coated on the outside of the groove 31 to form a shielding protection for the first N-type polysilicon 7.

[0051] Specifically, the first N-type polysilicon 7 needs to be grounded. Through layout design, the first N-type polysilicon 7 is short-circuited with the source metal 4, thereby achieving the grounding of the first N-type polysilicon 7 ( Figure 1 It is a plan view, and the contact between the first N-type polysilicon 7 and the source metal 4 is not shown).

[0052] The trench structure can transfer the strong electric field at the gate oxide interface to the bottom of the carrier storage layer, greatly reducing the electric field strength in the thin gate oxide, thereby improving the ability of silicon carbide MOSFET devices to resist single particle gate penetration;

[0053] At the same time, the P-type doping area at the bottom and sidewall of the trench (i.e., the second shielding area) increases the hole extraction path area in the active area, enhances the hole extraction efficiency in the body at the moment of heavy ion bombardment, can quickly and efficiently remove the electron-hole pairs generated by heavy ion bombardment, reduce the current and radiation response time generated by single particle radiation, and effectively improve the single particle radiation resistance of silicon carbide MOSFET;

[0054] In addition, due to the introduction of the trench structure, the pinch-off effect of the carrier storage layer at high blocking voltage is enhanced. And the doping concentration of the carrier storage layer is increased without affecting the voltage blocking capability of the device. The carrier storage layer with a higher doping concentration and the second N-type polysilicon short-circuited with the source in the N-well groove can greatly improve the recombination efficiency of holes and electrons at the moment of single-particle radiation, further improve the excess carrier extraction speed, and thus further improve the radiation resistance of silicon carbide MOSFET.

[0055] Furthermore, since an N buffer layer 3a is introduced on the back side of the N-type silicon carbide 3, the transient peak electric field intensity on the back side of the N-type silicon carbide 3 is reduced, and the breakdown of the back side N-type high-low junction is suppressed, thereby effectively improving the single particle radiation resistance capability.

[0056] A source region 6 is provided on the N-type silicon carbide 3, and the source region 6 includes an N-well groove 61 and a second N-type polysilicon 62. An N-well groove 61 is etched on the N-type silicon carbide 3, and the N-well groove 61 is located below the left / right side of the polysilicon gate 5. The second N-type polysilicon 62 is filled in the N-well groove 61, and the second N-type polysilicon 62 is in contact with the N-type silicon carbide 3 to form a heterojunction structure. The surface of the second N-type polysilicon 62 is in contact with the source metal 4 and the gate oxide 51.

[0057] A second shielding region 33 and a P-well region 34 are also formed on the N-type silicon carbide 3 . The second shielding region 33 and the P-well region 34 are sequentially coated on the outside of the N-well groove 61 to shield and protect the second N-type polysilicon 62 .

[0058] In order to solve the technical difficulties in cell miniaturization of existing planar gate silicon carbide MOSFET devices, in this embodiment, an N-well groove 61 is etched on the N-type silicon carbide 3, and a second N-type polysilicon 62 is filled in the N-well groove 61 as a source, and the P+ region and the P-well region surround the second N-type polysilicon 62 to form shielding protection. The upper surface of the P-well region 34 is spaced a certain distance from the upper surface of the N-type silicon carbide 3, and the gap with a lateral distance forms a channel 35 of the silicon carbide MOSFET device. The second N-type polysilicon 62 and the N-type silicon carbide 3 form a heterojunction, so that the device is in a normally-off state when no gate voltage is applied.

[0059] The above structure utilizes the method of controlling the height of the heterojunction barrier by the gate to realize the on and off control of the MOSFET device, which can significantly shorten or eliminate the channel in the traditional planar gate structure, and can use an accumulation channel to replace the inversion channel in the traditional structure, thereby improving the mobility of the channel and reducing the device's specific on-resistance.

[0060] The heterojunction formed by the second N-type polysilicon 62 and the N-type silicon carbide 3 has a certain barrier height, so that the device is in a normally-off state when no gate voltage is applied;

[0061] When a positive voltage exceeding the threshold voltage is applied to the gate, the barrier height of the heterojunction decreases, the silicon carbide MOSFET device is turned on, and the electrons in the second N-type polysilicon 62 pass through the channel 35, the carrier storage layer 3c, the N-type drift layer 3b, the N buffer layer 3a and the N substrate 2 and enter the drain metal 1;

[0062] When the gate voltage is lower than the device threshold voltage, the SiC MOSFET device is turned off;

[0063] When a high voltage is applied to the drain of the device, the PN junction composed of the P-well region and the P+ region (i.e., the second shielding region) and the N-type drift layer 3b is reverse biased to withstand the blocking voltage, and the reverse biased heterojunction can also reduce the leakage current of the device;

[0064] When the drain and source of the device are subjected to reverse voltage, the heterojunction formed by the second N-type polysilicon 62 and the N-type silicon carbide 3 is forward-conducted, and the device conducts reverse current. Since the forward conduction voltage drop of the heterojunction is low, the reverse conduction voltage drop of the silicon carbide MOSFET device is low, which can simultaneously suppress the bipolar degradation caused by the conduction of the body diode; since the heterojunction formed by the second N-type polysilicon 62 and the N-type silicon carbide 3 is unipolar (only electrons work as carriers), the reverse recovery characteristics of the device are better.

[0065] Specifically, the channel 35 , the first N-type polysilicon 7 , the source region 6 , the first shielding region 32 , the second shielding region 33 and the P-well region 34 are all located in the carrier storage layer 3 c .

[0066] A method for preparing a radiation-hardened silicon carbide MOSFET comprises the following steps:

[0067] 1. Silicon carbide wafer preparation, that is, forming N-type silicon carbide 3 on the surface of N substrate 2;

[0068] 2. P-well ions, P+ ions, P-type doping ions and carrier storage layer ions are implanted on the N-type silicon carbide 3, and then high-temperature annealing and activation are performed to form a carrier storage layer 3c, a first shielding region 32, a second shielding region 33 and a P-well region 34 on the N-type silicon carbide;

[0069] 3. Etching an N-well groove 61 and a trench 31 on the N-type silicon carbide 3, and filling the trench 31 with a first N-type polysilicon 7, and filling the N-well groove 61 with a second N-type polysilicon 62;

[0070] 4. Forming a thin gate oxide layer 51 on the N-type silicon carbide 3 by thermal oxidation;

[0071] 5. Deposit a high-k dielectric such as Al2O3 on the gate oxide 51 to form a second gate dielectric 53 (this layer and this step can be omitted);

[0072] 6. Depositing a polysilicon gate 5 and an interlayer dielectric 52 on the gate oxide 51 or the gate dielectric 53 to form a MOS structure;

[0073] 7. Deposit source metal 4 between adjacent polysilicon gates 5, and make the source metal contact with the second N-type polysilicon 62;

[0074] 8. Gate opening;

[0075] 9. Deposit a thick source metal 4 on the polysilicon gate 5 to form a source structure;

[0076] 10. Form surface protection structures such as TEOS and PI;

[0077] 11. Thinning the back side of N substrate 2;

[0078] 12. A drain metal 1 is formed on the back side of the N substrate 2 to form a drain structure.

[0079] The production process of the radiation-hardened silicon carbide MOSFET device in this embodiment is largely compatible with the production process of the traditional planar gate silicon carbide MOSFET device, and only the N-well and trench etching steps and the step of filling polysilicon into the N-well and trench need to be adjusted.

[0080] Embodiment 2:

[0081] In this embodiment, the P-well region 34 is omitted based on the first embodiment.

[0082] In this embodiment, the process step of implanting P-well ions on the N-type silicon carbide 3 is omitted, so that the P-well region 34 is omitted.

[0083] In the case where the channel does not need to be retained, the P-well region 34 can be removed at the same time to reduce the mask and an ion implantation process. In this case, the P+ region (second shielding region 33) is directly used to form a shielding protection for the second N-type polysilicon 62 in the N-well groove 61. Since the P+ region forms a full surrounding protection for the bottom of the second N-type polysilicon 62, the ion concentration of the P+ region is very high, and the parasitic NPN transistor inside the silicon carbide MOSFET device will be greatly suppressed, thereby improving the reliability of the device.

[0084] The above is an example of the best implementation of the present invention, and the parts not described in detail are common knowledge of ordinary technicians in the field. The protection scope of the present invention shall be based on the content of the claims, and any equivalent transformation based on the technical enlightenment of the present invention is also within the protection scope of the present invention.

Claims

1. A radiation hardened silicon carbide MOSFET structure, characterized in that: The invention comprises a drain metal (1), an N substrate (2), an N-type silicon carbide (3) and a source metal (4) which are stacked in sequence from bottom to top. A polysilicon gate (5) is arranged between the source metal (4) and the N-type silicon carbide (3), and a gate oxide (51) is formed between the polysilicon gate (5) and the N-type silicon carbide (3). A source region (6) is formed on the surface of the N-type silicon carbide (3), and the surface of the source region (6) is in contact with the gate oxide (51) and the source metal (4). A groove (31) is provided on the surface of the N-type silicon carbide (3), the groove (31) is located below the polysilicon gate (5), the groove (31) is filled with a first N-type polysilicon (7), and the first N-type polysilicon (7) is in contact with the source metal (4). A first shielding region (32) is formed on the surface of the N-type silicon carbide (3), and the first shielding region (32) covers the outer side of the groove (31).

2. The radiation hardened silicon carbide MOSFET structure according to claim 1, characterized in that: The first shielding region (32) is a P-type doped region.

3. The radiation hardened silicon carbide MOSFET structure according to claim 1, characterized in that: The source region (6) comprises an N-type well groove (61) opened on the surface of the N-type silicon carbide (3) and a second N-type polysilicon (62) filled in the N-type well groove (61). A second shielding region (33) is formed on the surface of the N-type silicon carbide (3), the second shielding region (33) covers the outside of the source region (6), one side of the N-well groove (61) is in contact with the N-type silicon carbide (3), and the second N-type polysilicon (62) and the N-type silicon carbide (3) form a heterojunction structure.

4. The radiation hardened silicon carbide MOSFET structure according to claim 3, characterized in that: The second shielding area (33) is a P+ area.

5. The radiation hardened silicon carbide MOSFET structure according to claim 3 or 4, characterized in that: A P-well region (34) is formed on the N-type silicon carbide (3), and the P-well region (34) covers the outer side of the second shielding region (33) and the source region (6); There is a gap between the surface of the P-well region (34) and the surface of the N-type silicon carbide (3), and the P-well region (34) wraps around the second shielding region (33), and the gap with a lateral distance forms a channel (35) in contact with the N-type silicon carbide (3) and the second N-type polysilicon (62); or there is no gap between the surface of the P-well region (34) and the surface of the N-type silicon carbide (3), that is, there is no channel.

6. The radiation hardened silicon carbide MOSFET structure according to claim 5, characterized in that: The N-type silicon carbide (3) comprises an N-buffer layer (3a), an N-type drift layer (3b) and a carrier storage layer (3c) which are arranged in sequence from top to bottom, and the trench (31), the first shielding region (32), the source region (6), the second shielding region (33) and the P-well region (34) are all located in the carrier storage layer (3c).

7. The radiation hardened silicon carbide MOSFET structure according to claim 1, characterized in that: An interlayer dielectric (52) is formed between the polysilicon gate (5) and the source metal (4).

8. The radiation hardened silicon carbide MOSFET structure according to claim 1, characterized in that: A gate dielectric (53) is formed between the gate oxide (51) and the polysilicon gate (5).

9. A method for preparing a radiation-hardened silicon carbide MOSFET, characterized in that: The following steps are involved: Step S1, forming N-type silicon carbide (3) on an N substrate (2); Step S2, implanting carrier storage layer ions, P-type doping ions and P+ ions into the N-type silicon carbide (3), and performing high temperature annealing and activation to form a carrier storage layer (3c), a first shielding region (32) and a second shielding region (33) on the N-type silicon carbide (3); Step S3, etching the surface of the N-type silicon carbide (3) to form a groove (31) and an N-well groove (61), and filling the groove (31) and the N-well groove (61) with a first N-type polysilicon (7) and a second N-type polysilicon (62), respectively; Step S4, forming a gate oxide (51) by thermal oxidation on the N-type silicon carbide (3); Step S5, depositing a polysilicon gate (5) and an interlayer dielectric (52) on the gate oxide (51) to form a MOS structure; Step S6, depositing a source metal (4) in a region between adjacent polysilicon gates (5), and making the source metal (4) contact the second N-type polysilicon (62); Step S7, gate opening; Step S8, depositing a thick source metal layer (4) on the interlayer dielectric (52) to form a source structure; Step S9: forming a drain metal (1) below the N substrate (2).

10. The method for preparing a radiation hardened silicon carbide MOSFET according to claim 9, characterized in that: In the step S2, before high temperature annealing and activation, P well ions are implanted into the N type silicon carbide (3), so as to form a P well region (34) on the N type silicon carbide (3) after high temperature annealing and activation.

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