High-speed high-voltage comparator

Abstract

The invention provides a high-speed high-voltage comparator, which is suitable for an analog-to-digital conversion circuit and comprises a front signal voltage conversion module, a middle signal amplification module and a rear signal latch module which are connected in sequence, devices contained in the front signal voltage conversion module are all high-voltage devices, receive high-voltage input signals, convert the high-voltage input signals into low-voltage input signals and send the low-voltage input signals to the middle signal amplification module. The middle signal amplification module comprises multiple stages of cascaded amplifiers, devices included in the middle signal amplification module are low-voltage devices, and the middle signal amplification module is used for amplifying low-voltage input signals, generating middle-stage analog signals and sending the middle-stage analog signals to the rear signal latch module; devices included in the rear signal latch module are low-voltage devices, controlled by clock signals and used for converting the intermediate-stage analog signals into digital signals and outputting the digital signals. The high-speed and high-voltage comparator can meet the high-speed and high-voltage application requirements. And the noise is low, the mismatch is small, and the anti-interference capability is strong.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-speed high-voltage comparator. Background Art

[0002] Analog-to-digital conversion circuits rely heavily on high-speed comparators, but their application scenarios include processing high-voltage (5V, 3V) input signals. However, 5V and 3V devices cannot meet the requirements of high-speed signal processing of 100MHz. Only 1.1V devices can do this, so a new comparator structure is needed. Summary of the invention

[0003] The object of the present invention is to provide a high-speed high-voltage comparator that can meet the application requirements of high-speed and high-voltage.

[0004] To achieve the above object, the present invention provides the following technical solutions: The present invention provides a high-speed high-voltage comparator, which comprises a pre-signal voltage conversion module, a middle signal amplification module, a post-signal latch module, and a voltage generating circuit for providing a low-voltage power supply to the middle signal amplification module and the post-signal latch module, which are connected in sequence; the components contained in the pre-signal voltage conversion module are all high-voltage components, which receive a high-voltage input signal, convert it into a low-voltage input signal, and send it to the middle signal amplification module; the middle signal amplification module comprises a multi-stage cascaded amplifier, the components contained in it are all low-voltage components, which amplify the low-voltage input signal to generate an intermediate-stage analog signal, and send it to the post-signal latch module; the components contained in the post-signal latch module are all low-voltage components, which are controlled by a clock signal to convert the intermediate-stage analog signal into a digital signal and output it.

[0005] In one embodiment, the front signal voltage conversion module includes a zeroth PMOS tube, a first PMOS tube, a second PMOS tube, a first resistor, and a second resistor. The source end of the zeroth PMOS tube is connected to a high voltage power supply, the gate end of the zeroth PMOS tube is connected to a zeroth bias voltage, the drain end of the zeroth PMOS tube is connected to the source end of the first PMOS tube and the source end of the second PMOS tube, the gate end of the first PMOS tube and the gate end of the second PMOS tube jointly constitute a first signal input end to receive the high voltage input signal, the drain end of the first PMOS tube is grounded via the first resistor, the drain end of the second PMOS tube is grounded via the second resistor, and the drain end of the first PMOS tube and the drain end of the second PMOS tube jointly constitute a first signal output end to output the low voltage input signal.

[0006] In one embodiment, the intermediate signal amplification module includes a first-stage amplifier, a second-stage amplifier, ..., an N-stage amplifier, where N is a positive integer greater than or equal to three, and the first-stage amplifier includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a third resistor, and a fourth resistor. The source end of the third PMOS tube is connected to the low voltage power supply, the gate end of the third PMOS tube is connected to the first bias voltage, the drain end of the third PMOS tube is connected to the source end of the fourth PMOS tube and the source end of the fifth PMOS tube, the gate end of the fourth PMOS tube and the gate end of the fifth PMOS tube jointly constitute a second signal input end to receive a second input signal, the drain end of the fourth PMOS tube is grounded via the third resistor, the drain end of the fifth PMOS tube is grounded via the fourth resistor, and the drain end of the fourth PMOS tube and the drain end of the fifth PMOS tube jointly constitute a second signal output end to output a second output signal.

[0007] In one embodiment, the second-stage amplifier includes a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The source end of the sixth PMOS tube is connected to the low voltage power supply, the gate end of the sixth PMOS tube is connected to the second bias voltage, the drain end of the sixth PMOS tube is connected to the source end of the seventh PMOS tube and the source end of the eighth PMOS tube, and the gate end of the seventh PMOS tube and the gate end of the eighth PMOS tube together constitute a third signal input end. , connected to the second signal output end, receiving a third input signal, and the gate end of the seventh PMOS tube is connected to the drain end of the fifth PMOS tube via the first capacitor, the gate end of the eighth PMOS tube is connected to the drain end of the fourth PMOS tube via the second capacitor, and the gate end of the seventh PMOS tube is connected to the fifth bias voltage via the first switch, the gate end of the eighth PMOS tube is connected to the fifth bias voltage via the second switch, the drain end of the seventh PMOS tube is connected to the source end of the ninth PMOS tube, the drain end of the eighth PMOS tube is connected to the source end of the tenth PMOS tube, and the gate end of the ninth PMOS tube and the gate end of the tenth PMOS tube are connected to the third bias voltage, The drain end of the ninth PMOS tube is connected to the drain end of the first NMOS tube, the drain end of the tenth PMOS tube is connected to the drain end of the second NMOS tube, the drain end of the ninth PMOS tube and the drain end of the tenth PMOS tube together constitute a third signal output end, outputting a third output signal, the gate end of the first NMOS tube and the gate end of the second NMOS tube are connected to a fourth bias voltage, the source end of the first NMOS tube is connected to the drain end of the third NMOS tube, the source end of the third NMOS tube is grounded, the source end of the second NMOS tube is connected to the drain end of the fourth NMOS tube, the source end of the fourth NMOS tube is grounded, the gate end of the third NMOS tube and the gate end of the fourth NMOS tube are connected to the drain end of the fourth NMOS tube, The gate ends of the third and fourth NMOS tubes are connected to the drain end of the ninth PMOS tube via the third capacitor, the gate ends of the third and fourth NMOS tubes are connected to the drain end of the tenth PMOS tube via the fourth capacitor, the gate ends of the third and fourth NMOS tubes are connected to the sixth bias voltage via the third and fourth switches connected in series, the drain end of the ninth PMOS tube is connected to the common mode voltage via the fifth and sixth switches connected in series, the drain end of the tenth PMOS tube is connected to the common mode voltage via the seventh and eighth switches connected in series, the fifth capacitor is connected between the connection point of the third and fourth switches and the connection point of the fifth and sixth switches,The sixth capacitor is connected between the connection point of the third switch and the fourth switch and the connection point of the seventh switch and the eighth switch.

[0008] In one embodiment, the structure of the N-th stage amplifier is the same as the structure of the second-stage amplifier, and the N-th stage amplifier has a fourth signal input terminal, a fourth signal output terminal, a seventh capacitor, and an eighth capacitor. The fourth signal input terminal receives a fourth input signal and is connected to the third signal output terminal via the seventh capacitor and the eighth capacitor. The fourth signal output terminal outputs a fourth output signal.

[0009] In one embodiment, the post-signal latch module includes a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth capacitor, and a tenth capacitor, the source end of the sixteenth PMOS tube is connected to the low voltage power supply, the gate end of the sixteenth PMOS tube is connected to the latch signal, the drain end of the sixteenth PMOS tube is connected to the source end of the seventeenth PMOS tube, the gate end of the sixteenth PMOS tube is connected to the latch signal, and the drain end of the sixteenth PMOS tube is connected to the source end of the seventeenth PMOS tube. The source end of the eighteenth PMOS tube, the gate end of the seventeenth PMOS tube, and the gate end of the eighteenth PMOS tube jointly constitute a fifth signal input end, receive the fifth input signal, are connected to the fourth signal output end via the ninth capacitor and the tenth capacitor, and the gate end of the seventeenth PMOS tube is connected to the fifth bias voltage via the ninth switch, the gate end of the eighteenth PMOS tube is connected to the fifth bias voltage via the tenth switch, the drain end of the seventeenth PMOS tube is connected to the source end of the nineteenth PMOS tube and the drain end of the ninth NMOS tube, and the source end of the ninth NMOS tube is connected to the drain end of the ninth NMOS tube. The drain end of the eighteenth PMOS tube is connected to the source end of the twentieth PMOS tube and the drain end of the fourteenth NMOS tube, the source end of the fourteenth NMOS tube is grounded, the gate end of the nineteenth PMOS tube is connected to the gate end of the eleventh NMOS tube, the drain end of the twelfth NMOS tube, and the drain end of the thirteenth NMOS tube, the source end of the thirteenth NMOS tube is grounded, the gate end of the twentieth PMOS tube is connected to the gate end of the twelfth NMOS tube, the drain end of the eleventh NMOS tube, and the drain end of the tenth NMOS tube, the source end of the tenth NMOS tube is grounded The drain end of the nineteenth PMOS tube is connected to the drain end of the eleventh NMOS tube, the drain end of the twentieth PMOS tube is connected to the drain end of the twelfth NMOS tube, the drain end of the nineteenth PMOS tube and the drain end of the twentieth PMOS tube jointly constitute a fifth signal output end, which outputs a fifth output signal, the drain end of the eleventh NMOS tube and the source end of the twelfth NMOS tube are grounded, and the gate end of the ninth NMOS tube, the gate end of the tenth NMOS tube, the gate end of the thirteenth NMOS tube, and the gate end of the fourteenth NMOS tube are all connected to the latch signal.

[0010] In one embodiment, the high-speed high-voltage comparator further includes a digital logic circuit, which is connected to the post-signal latch module, receives a signal output by the post-signal latch module, and processes the signal to generate a comparison result.

[0011] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The high-speed high-voltage comparator of the present invention can meet the application requirements of high-speed and high-voltage, and has low noise, small mismatch and strong anti-interference ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A structural block diagram of a high-speed high-voltage comparator provided in the first embodiment of the present invention; Figure 2 for Figure 1 The internal circuit diagram of the mid-front signal voltage conversion module; Figure 3 for Figure 1 The internal circuit diagram of the center signal amplifier module; Figure 4 for Figure 1 Internal circuit diagram of the middle and rear signal latch module; Figure 5 The figure is a schematic diagram of the transmission process of various signals involved in the high-speed high-voltage comparator of the present invention. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present invention. It should be noted that the description order of the following embodiments is not used as a limitation on the preferred order of the embodiments of the present invention. In the following embodiments, the description of each embodiment has its own emphasis. For the parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0015] See also Figure 1As shown, the first embodiment of the present invention provides a high-speed high-voltage comparator, which is suitable for an analog-to-digital conversion circuit. The high-speed high-voltage comparator includes a pre-signal voltage conversion module 101, a mid-signal amplification module 200, a post-signal latch module 301, and a voltage generation circuit 400 that provides a low-voltage power supply LVDD for the mid-signal amplification module 200 and the post-signal latch module 301, which are connected in sequence; the devices included in the pre-signal voltage conversion module 101 are all high-voltage devices, which receive a high-voltage input signal, convert it into a low-voltage input signal, and send it to the mid-signal amplification module 200; the mid-signal amplification module 200 includes a multi-stage cascade amplifier, and the devices included are all low-voltage devices, which amplify the low-voltage input signal to generate an intermediate-level analog signal, and send it to the post-signal latch module 301; the devices included in the post-signal latch module 301 are all low-voltage devices, which are controlled by a clock signal to convert the intermediate-level analog signal into a digital signal and output it.

[0016] First of all, the high voltage and low voltage described in the present invention are relative to each other. In a specific embodiment, the high voltage is 5V or 3V, and the low voltage is 1.1V. High speed means that the frequency of the signal to be processed reaches 80MHz or even higher.

[0017] See also Figure 2 As shown, in one embodiment, the front signal voltage conversion module 101 includes a zeroth PMOS transistor PM0, a first PMOS transistor PM1, a second PMOS transistor PM2, a first resistor R1, and a second resistor R2. The source end of the zeroth PMOS transistor PM0 is connected to a high voltage power supply, the gate end of the zeroth PMOS transistor PM0 is connected to a zeroth bias voltage, the drain end of the zeroth PMOS transistor PM0 is connected to the source end of the first PMOS transistor PM1 and the source end of the second PMOS transistor PM2, the gate end of the first PMOS transistor PM1 and the gate end of the second PMOS transistor PM2 jointly constitute a first signal input end, receiving the high voltage input signal, which can also be called a first input signal ip1, in1, the drain end of the first PMOS transistor PM1 is grounded via the first resistor R1, the drain end of the second PMOS transistor PM2 is grounded via the second resistor R2, the drain end of the first PMOS transistor PM1 and the drain end of the second PMOS transistor PM2 jointly constitute a first signal output end, outputting the low voltage input signal, which can also be called a first output signal op1, on1. Furthermore, it is explained here that the signals described in the present invention all include two paths in pairs, so each signal is represented by two element numbers (one positive p and one negative n) to simplify the description of the entire text.

[0018] In a specific embodiment, the three PMOS of the front signal voltage conversion module 101 are all 5V devices and can withstand 5V input signals. The resistance values ​​of the first resistor R1 and the second resistor R2 are equal, both are R. When the input voltage of the first input signal ip1, in1 is 5V, the corresponding input PMOS is cut off, and the voltage of the other channel is 0V, the corresponding PMOS is turned on, then the current (Idd) flows into the load resistor (R) of the turned-on PMOS. The parameter setting requires Idd*R<1.1V*(1+10%) to meet the voltage requirements of the devices used in the mid-signal amplification module 200. So the voltage drop of this resistor is Idd*R≈1.1V, and the voltage drop on the load resistor of the other channel is ≈0*R≈0V. It is a continuously working amplifier and is not affected by the system clock.

[0019] Please refer to Figure 1 , Figure 3 As shown, in one embodiment, the mid-stage signal amplification module 200 includes a first-stage amplifier 201, a second-stage amplifier 202, ..., an N-th stage amplifier 203, N is a positive integer greater than or equal to three, the first-stage amplifier 201 includes a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a third resistor R3, and a fourth resistor R4, the source end of the third PMOS tube PM3 is connected to the low voltage power supply LVDD, the gate end of the third PMOS tube PM3 is connected to the first bias voltage bias1, and the third PMOS tube PM3 The drain end is connected to the source end of the fourth PMOS tube PM4 and the source end of the fifth PMOS tube PM5, the gate end of the fourth PMOS tube PM4 and the gate end of the fifth PMOS tube PM5 jointly constitute a second signal input end, receiving a second input signal, the drain end of the fourth PMOS tube PM4 is grounded via the third resistor R3, the drain end of the fifth PMOS tube PM5 is grounded via the fourth resistor R4, the drain end of the fourth PMOS tube PM4 and the drain end of the fifth PMOS tube PM5 jointly constitute a second signal output end, outputting a second output signal op2, on2.

[0020] The mid-signal amplifier module 200 is composed of several stages of open-loop amplifier modules, and has the characteristics of large gain, small noise, and small mismatch. In a specific embodiment, its active devices are all 1.1V. The structure of the first-stage amplifier 201 is the same as that of the front-stage signal voltage conversion module 101, and the purpose is to produce an output with less noise. It is also a continuously working amplifier and is not affected by the system clock. The structure of the following several stages only needs to meet the overall gain requirements, and the specific structure can be determined according to the process parameters.

[0021] Please continue reading Figure 3As shown, in one embodiment, the second-stage amplifier 202 includes a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6, the source end of the sixth PMOS transistor PM6 is connected to the low voltage power supply LVDD, and the first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The gate end of the sixth PMOS tube PM6 is connected to the second bias voltage bias2, the drain end of the sixth PMOS tube PM6 is connected to the source end of the seventh PMOS tube PM7 and the source end of the eighth PMOS tube PM8, the gate end of the seventh PMOS tube PM7 and the gate end of the eighth PMOS tube PM8 together constitute a third signal input end, which is connected to the second signal output end to receive the third input signal ip3, in3, and the gate end of the seventh PMOS tube PM7 is connected to the drain end of the fifth PMOS tube PM5 via the first capacitor C1, and the eighth PMOS The gate end of the seventh PMOS tube PM8 is connected to the drain end of the fourth PMOS tube PM4 via the second capacitor C2, and the gate end of the seventh PMOS tube PM7 is connected to the fifth bias voltage bias5 via the first switch K1, the gate end of the eighth PMOS tube PM8 is connected to the fifth bias voltage bias5 via the second switch K2, the drain end of the seventh PMOS tube PM7 is connected to the source end of the ninth PMOS tube PM9, the drain end of the eighth PMOS tube PM8 is connected to the source end of the tenth PMOS tube PM10, the gate ...1, the gate end of the ninth PMOS tube PM9, the drain end of the eighth PMOS tube PM8 is connected to the source end of the tenth PMOS tube PM12, the gate end of the ninth PMOS tube PM9, the drain end of the eighth PMOS tube PM8 is connected to the source end of the tenth PMOS tube PM13, the gate end of the ninth PMOS tube PM9, the drain end of the eighth PMOS tube PM8 is connected to the source end of the tenth PMOS tube PM14, the gate end of the eighth PMOS tube PM8 is connected to the fifth bias voltage bias5 via the first switch K1, the gate end of the eighth PMOS tube PM8 is connected to the fifth bias voltage bias5 via the second switch K2 The gate terminal of the tenth PMOS tube PM10 is connected to the third bias voltage bias3, the drain terminal of the ninth PMOS tube PM9 is connected to the drain terminal of the first NMOS tube NM1, the drain terminal of the tenth PMOS tube PM10 is connected to the drain terminal of the second NMOS tube NM2, the drain terminal of the ninth PMOS tube PM9 and the drain terminal of the tenth PMOS tube PM10 jointly constitute a third signal output terminal, outputting a third output signal op3, on3, the gate terminal of the first NMOS tube NM1 and the gate terminal of the second NMOS tube NM2 are connected to a fourth bias voltage bias4, The source end of the first NMOS transistor NM1 is connected to the drain end of the third NMOS transistor NM3, the source end of the third NMOS transistor NM3 is grounded, the source end of the second NMOS transistor NM2 is connected to the drain end of the fourth NMOS transistor NM4, the source end of the fourth NMOS transistor NM4 is grounded, the gate end of the third NMOS transistor NM3 and the gate end of the fourth NMOS transistor NM4 are connected to the drain end of the ninth PMOS transistor PM9 via the third capacitor C3, the gate end of the third NMOS transistor NM3 and the gate end of the fourth NMOS transistor NM4 are connected to the drain end of the tenth PMOS transistor PM10 via the fourth capacitor C4, and the gate end of the third NMOS transistor NM3 is connected to the drain end of the tenth PMOS transistor PM10 via the fourth capacitor C4. , the gate end of the fourth NMOS tube NM4 is connected to the sixth bias voltage bias6 via the third switch K3 and the fourth switch K4 connected in series, the drain end of the ninth PMOS tube PM9 is connected to the common mode voltage via the fifth switch K5 and the sixth switch K6 connected in series, the drain end of the tenth PMOS tube PM10 is connected to the common mode voltage via the seventh switch K7 and the eighth switch K8 connected in series, the fifth capacitor C5 is connected between the connection point of the third switch K3 and the fourth switch K4 and the connection point of the fifth switch K5 and the sixth switch K6, and the sixth capacitor C6 is connected between the connection point of the third switch K3 and the fourth switch K4 and the connection point of the seventh switch K7 and the eighth switch K8. Figure 3 In the specific embodiment shown, the common mode voltage is 0.55V.

[0022] The input end of the second stage amplifier 202 is connected in series with a capacitor that suppresses the output mismatch voltage (OS) of the previous stage. Before processing the signal, the gate of the input MOS is set to the same bias voltage, that is, the voltage of the third input signal ip3, in3 capacitor is the same at this time. The output mismatch voltage (OS) of the previous two stages of amplifiers is stored at the other end of the capacitor, that is, the second output signal op2, on2. During the formal signal processing process, the output mismatch voltage (OS) of the first two stages of amplifiers will not affect the comparison result of this stage of amplifier.

[0023] The second stage amplifier 202 uses a capacitor switch type output stage common mode voltage clamping structure. Because it processes high-speed signals, the output common mode potential will not be greatly offset due to leakage.

[0024] Please continue to refer to Figure 1 , Figure 3As shown, in one embodiment, the structure of the Nth stage amplifier 203 is the same as the structure of the second stage amplifier 202, and the Nth stage amplifier 203 has a fourth signal input terminal, a fourth signal output terminal, a seventh capacitor C7, and an eighth capacitor C8. The fourth signal input terminal receives a fourth input signal ip4,in4, and is connected to the third signal output terminal via the seventh capacitor C7 and the eighth capacitor C8. The fourth signal output terminal outputs a fourth output signal op4,on4.

[0025] Each amplifier after the second-stage amplifier 202 can adopt the same structure as the second-stage amplifier 202. Figure 3 In the specific embodiment shown, in order to shorten the transmission time of the signal, the center signal amplification module 200 adopts a total of 3-stage amplifiers. According to the needs of the actual application scenario, those skilled in the art can easily adjust the number of cascades, that is, the number of amplifier stages (that is, the number of amplification stages) can be increased or decreased, and the structure of the amplifier can also be flexibly selected in exchange for the corresponding signal conversion speed and design complexity. For example, the center signal amplification module 200 can also adopt a 2-stage amplifier, so that the input end (fifth signal input end) of the rear signal latch module 301 to be described later is not connected to the fourth signal output end, but to the third signal output end.

[0026] See also Figure 4As shown, in one embodiment, the post-signal latch module 301 includes a sixteenth PMOS transistor PM16, a seventeenth PMOS transistor PM17, an eighteenth PMOS transistor PM18, a nineteenth PMOS transistor PM19, a twentieth PMOS transistor PM20, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a thirteenth NMOS transistor NM13, a fourteenth NMOS transistor NM14, a ninth capacitor C9, and a tenth capacitor C10, the source end of the sixteenth PMOS transistor PM16 is connected to the low voltage power supply LVDD, and the gate end of the sixteenth PMOS transistor PM16 is connected to the latch signal The drain end of the sixteenth PMOS tube PM16 is connected to the source end of the seventeenth PMOS tube PM17 and the source end of the eighteenth PMOS tube PM18, and the gate end of the seventeenth PMOS tube PM17 and the gate end of the eighteenth PMOS tube PM18 together constitute a fifth signal input end, receiving a fifth input signal ip5, in5, and connected to the fourth signal output end via the ninth capacitor C9 and the tenth capacitor C10, and the gate end of the seventeenth PMOS tube PM17 is connected to the fifth bias voltage bias5 via the ninth switch K9, and the gate end of the eighteenth PMOS tube PM18 is connected to the fifth bias voltage bias5 via the tenth switch K10. bias5 is pressed, the drain end of the seventeenth PMOS tube PM17 is connected to the source end of the nineteenth PMOS tube PM19 and the drain end of the ninth NMOS tube NM9, the source end of the ninth NMOS tube NM9 is grounded, the drain end of the eighteenth PMOS tube PM18 is connected to the source end of the twentieth PMOS tube PM20 and the drain end of the fourteenth NMOS tube NM14, the source end of the fourteenth NMOS tube NM14 is grounded, the gate end of the nineteenth PMOS tube PM19 is connected to the gate end of the eleventh NMOS tube NM11, the drain end of the twelfth NMOS tube NM12 and the drain end of the thirteenth NMOS tube NM13, the thirteenth NMOS The source end of the transistor NM13 is grounded, the gate end of the twentieth PMOS transistor PM20 is connected to the gate end of the twelfth NMOS transistor NM12, the drain end of the eleventh NMOS transistor NM11, and the drain end of the tenth NMOS transistor NM10, the source end of the tenth NMOS transistor NM10 is grounded, the drain end of the nineteenth PMOS transistor PM19 is connected to the drain end of the eleventh NMOS transistor NM11, the drain end of the twentieth PMOS transistor PM20 is connected to the drain end of the twelfth NMOS transistor NM12, the drain end of the nineteenth PMOS transistor PM19 and the drain end of the twentieth PMOS transistor PM20 jointly constitute a fifth signal output end, which outputs a fifth output signal op5,on5, the drain end of the eleventh NMOS tube NM11 and the source end of the twelfth NMOS tube NM12 are grounded, and the gate end of the ninth NMOS tube NM9, the gate end of the tenth NMOS tube NM10, the gate end of the thirteenth NMOS tube NM13, and the gate end of the fourteenth NMOS tube NM14 are all connected to the latch signal latch. ,

[0027] The post-signal latch module 301 is the last stage of the comparator of the present invention, and its active devices are all 1.1V. Controlled by the clock signal, the analog signal is completely converted into a 1.1V digital signal and maintained. In order to suppress the influence of the mismatch voltage of the termination signal amplifier, a pair of capacitors are also connected in series at the input end. Of course, according to actual needs, the post-signal latch module 301 can also adopt a structure as long as it can achieve the functions required by the present invention.

[0028] The voltage generating circuit 400 (regulator) that provides a low voltage (1.1V) power supply does not have a very strict accuracy requirement. The voltage generating circuit 400 provides a low voltage power supply LVDD for the mid-signal amplification module 200 and the post-signal latch module 301, thereby improving the PSRR (power supply ripple rejection ratio) of this part of the circuit.

[0029] Finally, in one embodiment, the high-speed high-voltage comparator of the present invention further includes a digital logic circuit, which is connected to the post-signal latch module 301, receives the signal output by the post-signal latch module 301, i.e., the fifth output signal op5, on5, and processes it to generate a comparison result.

[0030] See below Figure 5 , briefly describe the transmission process of the signals involved in the comparator of the present invention. In order to simplify the text, the component numbers of each signal are directly used for description, and it is assumed that before T0, the potentials of the signals ip1 and in1 are the same, =2.5V. op1-on1 = ip2–in2 = (0.55V+OS1)-0.55V. op2-on2 = (Vdc2+α*OS1+OS2)-Vdc2. Vdc2 is the common mode voltage of the second stage output, and α is the gain of the second stage. ip3-in3 = bias5-bias5 = 0. op3-on3 = (bias6+OS3)-bias6. ip4-in4 = bias5-bias5 =0. op4-on4 = (bias6+OS4)-bias6. ip5-in5 = bias5-bias5 =0. op5-on5 = 0V-0V = 0V. OS1, OS2, OS3, and OS4 are the mismatch voltages of each amplifier stage.

[0031] After T0, the input signal changes, ip1-in1 = (2.5V+△)-(2.5V-△). op1-on1 = (0.55V+OS1+△1)-(0.55V-△1). ip2–in2 = OS1+2*△1. op2-on2 = (Vdc2+α*OS1+OS2+△2)-(Vdc2-△2). ip3-in3 = 2*△2. op3-on3 = (bias6+OS3+△3)-(bias6-△3). ip4-in4 = 2*△3. op4-on4 = (bias6+OS4+△4)-(bias6-△4). ip5-in5 = 2*△4. op5-on5 = 1.1V. It can be seen that the OS of each level is suppressed and will not affect the next level. However, because the cascade amplifier has a large gain, the maximum value of its intrinsic OS is also limited. In the above description, △ represents the change in the single-ended input signal, and △1, △2, △3, and △4 represent the voltage of the signal after being amplified at the single end. Figure 5 , assuming OS1 = OS2 = OS3 = OS4.

[0032] Each stage of the signal amplifier circuit has a PMOS as the current source of this stage, and their gate terminals are connected to a fixed voltage to ensure a stable and continuous supply current and good power supply voltage noise suppression capability. The application environment of this comparator usually has two stages: the first stage, signal preparation, comparator setting; the second stage, signal input, comparator comparison. In these two stages, the first stage of the front signal voltage conversion module 101 and the middle signal amplifier module 200 will reflect the voltage changes of the signals ip1, in1 to op1, on1, op2, on2 in real time. At the same time, its own mismatch voltage will eventually be reflected in real time to op2, on2. Because it is a multi-stage amplification, in order to reduce the interference of the mismatch voltage on the signal comparison result, the mismatch voltage elimination structure is adopted in the third, fourth and fifth stages. For example, a series capacitor is inserted between the third-stage input ip3, in3 and the second-stage output op2, on2, and a series switch is built between ip3, in3 and bias5.

[0033] Usually in the first stage of the comparator, ip1 and in1 are also set to the same voltage. Ideally, after the preamplifier circuit, op1=on1=0.5*1.1V becomes op1=on1=0.5*1.1V. After op1 and on1 pass through the first stage of the intermediate signal amplifier module 200, op2=on2=0.5*1.1V. But in fact, op2 and on2 contain the mismatch information of the two stages of amplifier modules. Figure 5As shown, even if ip1=in1, due to the mismatch effect, the voltages of op1, on1 and op2, on2 cannot be equal. In the structure of the present invention, the switch between ip3, in3 and bias5 is closed at this time, so that ip3=in3=bias5, eliminating the influence of the non-zero mismatch voltage on op2, on2 on the input signal of this stage. Similarly, ip4, in4, ip5, in5 use the same method to eliminate the influence of the non-zero mismatch voltage of op3, on3, op4, on4 on the amplifier module of this stage, that is, ip4=in4=bias5, ip5=in5=bias5. Even so, it is necessary to control the intrinsic mismatch voltage of each stage within a certain range. Therefore, under the premise of ensuring the function is realized, the power consumption and area of ​​each amplifier stage will not be very small, and the gain cannot be too large. This needs to be ensured by adopting corresponding structures according to different process parameters. PM16 of the post-signal latch module 301 is in the cut-off state at this stage, and no current can flow from VDD through it to the source end on PM17, PM18. At the same time, NM9, NM10, NM13, and NM14 are in the on state, pulling the voltage of op5, on5 and op5x, on5x (intermediate nodes, drain terminals on PM17 and PM18) to 0 potential.

[0034] In the second stage of the comparator, the switches between ip3, in3, ip4, in4, ip5, in5 and bias5 are first disconnected to make them floating. Because of the parasitic capacitance of these nodes, the voltage of these nodes will not change significantly in a short time, that is, it will not affect the comparison result. Then the voltage of the input signal ip1, in1 changes, and the corresponding op1, on1 also changes. As mentioned above, by controlling the current and load resistance, the maximum signal range of op1, on1 is 0V to 1.1V. Similarly, op2, on2 also changes accordingly. This change is coupled to ip3, in3 through the series capacitor between op2, on2 and ip3, in3. Through the amplification function of this stage, op3, on3 has a corresponding change. Similarly, this change is coupled to ip4, in4 through the series capacitor between op3, on3 and ip4, in4, and then through the amplification module of this stage, op4, on4 has a new assigned voltage signal. The same change process is also transmitted to ip5, in5. Because the gain of the previous stage amplifier is sufficient, the minimum input signal that meets the specifications on ip1, in1 will show a voltage on ip5, in5 that is much larger than the equivalent input mismatch voltage of this stage. After ip5, in5 reaches a sufficiently stable voltage, the latch clock signal is started so that PM16 can provide a sufficiently large current. At the same time, the gate voltages of NM9, NM10, NM13, and NM14 are pulled to 0, causing these four NMOS to enter the cut-off state. In this transient state, the voltages of op5, on5 and op5x, on5x remain at 0V. Next, because ip5, in5 are different, the on-resistances of PM17 and PM18 are different, so the currents injected into op5x, on5x through PM17, PM18 are also different, and the voltage rise speeds of op5x, on5x are also different. During this voltage rise process, the Vgs of PM19 or PM20 corresponding to the node with faster rise will be larger, and Ron will be smaller, resulting in a smaller corresponding Vds, that is, the node voltage at the drain end of this PMOS will also rise faster. The node voltage corresponding to the other path rises more slowly. When the voltages of these two nodes are greater than the threshold voltage of NMOS, the voltage difference will further lead to different discharge capabilities of NM11 and NM12, thereby accelerating the change in the voltage difference. Figure 5As shown in, (Vip5>Vin5) → (Vopx5>Vonx5) → (Vgs_PM20>Vgs_PM19) → (Vop5>Von5) →(Vgs_NM11>Vgs_NM12) → (Ids_NM11>Ids_NM12) → … → (PM20 is on, NM12 is off, PM9 is off, NM11 is on) → (Vop5≈1.1V, Von5=0) → The comparison process is over. At this time, the result can be stored and output through some digital logic circuits. Usually, this output form is a single-ended signal output, and a clock signal matching its phase is output together to facilitate subsequent circuit processing.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The high-speed high-voltage comparator of the present invention can meet the application requirements of high-speed and high-voltage, and has low noise, small mismatch and strong anti-interference ability.

[0036] The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims. In addition, the specification uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. The content of this specification should not be understood as a limitation on the present invention.

Claims

1. A high-speed high-voltage comparator suitable for analog-to-digital conversion circuit, characterized in that: The high-speed high-voltage comparator includes a pre-signal voltage conversion module, a mid-signal amplification module, a post-signal latch module, and a voltage generating circuit that provides a low-voltage power supply for the mid-signal amplification module and the post-signal latch module, which are connected in sequence; the devices contained in the pre-signal voltage conversion module are all high-voltage devices, which receive high-voltage input signals, convert them into low-voltage input signals, and send them to the mid-signal amplification module; the mid-signal amplification module includes a multi-stage cascade amplifier, and the devices contained are all low-voltage devices, which amplify the low-voltage input signals to generate intermediate-level analog signals, and send them to the post-signal latch module; the devices contained in the post-signal latch module are all low-voltage devices, which are controlled by a clock signal to convert the intermediate-level analog signals into digital signals and output them.

2. The high-speed high-voltage comparator according to claim 1, characterized in that: The front signal voltage conversion module includes a zeroth PMOS tube, a first PMOS tube, a second PMOS tube, a first resistor, and a second resistor. The source end of the zeroth PMOS tube is connected to a high voltage power supply, the gate end of the zeroth PMOS tube is connected to a zeroth bias voltage, the drain end of the zeroth PMOS tube is connected to the source end of the first PMOS tube and the source end of the second PMOS tube, the gate end of the first PMOS tube and the gate end of the second PMOS tube jointly constitute a first signal input end to receive the high voltage input signal, the drain end of the first PMOS tube is grounded via the first resistor, the drain end of the second PMOS tube is grounded via the second resistor, and the drain end of the first PMOS tube and the drain end of the second PMOS tube jointly constitute a first signal output end to output the low voltage input signal.

3. The high-speed high-voltage comparator according to claim 2, characterized in that: The intermediate signal amplification module includes N amplifiers, which are respectively a first-stage amplifier, a second-stage amplifier, and an N-stage amplifier, where N is a positive integer greater than or equal to three. The first-stage amplifier includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a third resistor, and a fourth resistor. The source end of the third PMOS tube is connected to the low-voltage power supply, the gate end of the third PMOS tube is connected to the first bias voltage, the drain end of the third PMOS tube is connected to the source end of the fourth PMOS tube and the source end of the fifth PMOS tube, the gate end of the fourth PMOS tube and the gate end of the fifth PMOS tube jointly constitute a second signal input end to receive a second input signal, the drain end of the fourth PMOS tube is grounded via the third resistor, the drain end of the fifth PMOS tube is grounded via the fourth resistor, and the drain end of the fourth PMOS tube and the drain end of the fifth PMOS tube jointly constitute a second signal output end to output a second output signal.

4. The high-speed high-voltage comparator according to claim 3, characterized in that: The second-stage amplifier includes a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The source end of the sixth PMOS tube is connected to the low voltage power supply, the gate end of the sixth PMOS tube is connected to the second bias voltage, the drain end of the sixth PMOS tube is connected to the source end of the seventh PMOS tube and the source end of the eighth PMOS tube, and the gate end of the seventh PMOS tube and the gate end of the eighth PMOS tube together constitute a third signal input end, which is connected to the second signal output end and receives the first three input signals, and the gate end of the seventh PMOS tube is connected to the drain end of the fifth PMOS tube via the first capacitor, the gate end of the eighth PMOS tube is connected to the drain end of the fourth PMOS tube via the second capacitor, and the gate end of the seventh PMOS tube is connected to the fifth bias voltage via the first switch, the gate end of the eighth PMOS tube is connected to the fifth bias voltage via the second switch, the drain end of the seventh PMOS tube is connected to the source end of the ninth PMOS tube, the drain end of the eighth PMOS tube is connected to the source end of the tenth PMOS tube, the gate end of the ninth PMOS tube and the gate end of the tenth PMOS tube are connected to the third bias voltage, and the drain end of the ninth PMOS tube is connected to the drain end of the first NMOS tube, The drain end of the tenth PMOS tube is connected to the drain end of the second NMOS tube, the drain end of the ninth PMOS tube and the drain end of the tenth PMOS tube jointly constitute a third signal output end, outputting a third output signal, the gate end of the first NMOS tube and the gate end of the second NMOS tube are connected to a fourth bias voltage, the source end of the first NMOS tube is connected to the drain end of the third NMOS tube, the source end of the third NMOS tube is grounded, the source end of the second NMOS tube is connected to the drain end of the fourth NMOS tube, the source end of the fourth NMOS tube is grounded, the gate end of the third NMOS tube and the gate end of the fourth NMOS tube are jointly connected to the drain end of the ninth PMOS tube via the third capacitor, and the third NMOS tube is connected to the drain end of the ninth PMOS tube. The gate end of the S tube and the gate end of the fourth NMOS tube are commonly connected to the drain end of the tenth PMOS tube via the fourth capacitor, the gate end of the third NMOS tube and the gate end of the fourth NMOS tube are connected to the sixth bias voltage via the third switch and the fourth switch connected in series, the drain end of the ninth PMOS tube is connected to the common mode voltage via the fifth switch and the sixth switch connected in series, the drain end of the tenth PMOS tube is connected to the common mode voltage via the seventh switch and the eighth switch connected in series, the fifth capacitor is connected between the connection point of the third switch and the fourth switch and the connection point of the fifth switch and the sixth switch, and the sixth capacitor is connected between the connection point of the third switch and the fourth switch and the connection point of the seventh switch and the eighth switch.

5. The high-speed high-voltage comparator according to claim 4, characterized in that: The structure of the N-th stage amplifier is the same as that of the second-stage amplifier. The N-th stage amplifier has a fourth signal input terminal, a fourth signal output terminal, a seventh capacitor, and an eighth capacitor. The fourth signal input terminal receives a fourth input signal and is connected to the third signal output terminal via the seventh capacitor and the eighth capacitor. The fourth signal output terminal outputs a fourth output signal.

6. The high-speed high-voltage comparator according to claim 5, characterized in that: The post-signal latch module comprises a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth capacitor, and a tenth capacitor. The source end of the sixteenth PMOS tube is connected to the low voltage power supply, the gate end of the sixteenth PMOS tube is connected to the latch signal, the drain end of the sixteenth PMOS tube is connected to the source end of the seventeenth PMOS tube, the gate end of the eighteenth PMOS tube is connected to the latch signal, and ... The gate end of the seventeenth PMOS tube and the gate end of the eighteenth PMOS tube jointly constitute a fifth signal input end, receive a fifth input signal, are connected to the fourth signal output end via the ninth capacitor and the tenth capacitor, and the gate end of the seventeenth PMOS tube is connected to the fifth bias voltage via a ninth switch, the gate end of the eighteenth PMOS tube is connected to the fifth bias voltage via a tenth switch, the drain end of the seventeenth PMOS tube is connected to the source end of the nineteenth PMOS tube and the drain end of the ninth NMOS tube, the source end of the ninth NMOS tube is grounded, and the The drain end of the eighteenth PMOS tube is connected to the source end of the twentieth PMOS tube and the drain end of the fourteenth NMOS tube, the source end of the fourteenth NMOS tube is grounded, the gate end of the nineteenth PMOS tube is connected to the gate end of the eleventh NMOS tube, the drain end of the twelfth NMOS tube, and the drain end of the thirteenth NMOS tube, the source end of the thirteenth NMOS tube is grounded, the gate end of the twentieth PMOS tube is connected to the gate end of the twelfth NMOS tube, the drain end of the eleventh NMOS tube, and the drain end of the tenth NMOS tube, the source end of the tenth NMOS tube is connected to The drain end of the nineteenth PMOS tube is connected to the drain end of the eleventh NMOS tube, the drain end of the twentieth PMOS tube is connected to the drain end of the twelfth NMOS tube, the drain end of the nineteenth PMOS tube and the drain end of the twentieth PMOS tube jointly constitute a fifth signal output end, which outputs a fifth output signal, the drain end of the eleventh NMOS tube and the source end of the twelfth NMOS tube are grounded, and the gate end of the ninth NMOS tube, the gate end of the tenth NMOS tube, the gate end of the thirteenth NMOS tube, and the gate end of the fourteenth NMOS tube are all connected to the latch signal.

7. The high-speed high-voltage comparator according to claim 1, characterized in that: The high-speed high-voltage comparator further comprises a digital logic circuit, which is connected to the post-signal latch module, receives the signal output by the post-signal latch module, and processes the signal to generate a comparison result.

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