Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. A semiconductor memory device and a method of manufacturing the same, the semiconductor memory device including: a gate stack on a substrate, the gate stack including interlayer insulating layers and conductive patterns alternately stacked in a vertical direction; a channel structure passing through the gate stack and having an upper end portion protruding above the gate stack; a memory layer surrounding sidewalls of the channel structure; and a source layer formed on the gate stack. The channel structure includes a core insulating layer extending in a vertical direction in a central region of the channel structure, and a channel layer surrounding sidewalls of the core insulating layer, the channel layer being formed to be lower than the core insulating layer and the memory layer in the vertical direction.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202210093821.9 (application date: January 26, 2022, invention name: semiconductor memory device and manufacturing method thereof). Technical Field

[0002] The present disclosure relates to electronic devices, and more particularly, to a semiconductor memory device of a vertical channel structure and a method for manufacturing the same. Background Art

[0003] Recently, the paradigm of computer environment has shifted to ubiquitous computing standard, whereby computer system can be used almost anywhere at any time. As a result, the use of portable electronic devices such as mobile phones, digital cameras and notebook computers has increased rapidly. Such portable electronic devices generally use semiconductor memory systems, which use memory devices, i.e., data storage devices. The data storage devices can be used as primary storage devices or auxiliary storage devices of the portable electronic devices.

[0004] The advantages of a data storage device using a semiconductor memory device are that stability and durability are excellent, information access speed is very fast because there is no mechanical drive, and power consumption is low. As examples of memory systems having these advantages, data storage devices include universal serial bus (USB) memory devices, memory cards with various interfaces, solid state drives (SSDs), etc.

[0005] Semiconductor memory devices are generally classified as either volatile memory devices or nonvolatile memory devices.

[0006] The read speed and write speed of non-volatile memory devices are relatively slow, however, non-volatile memory devices can maintain stored data even when the power supply is cut off. Therefore, non-volatile memory devices are used to store data that must be maintained regardless of the power supply. Non-volatile memory devices may include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is generally classified as NOR type or NAND type. Summary of the invention

[0007] Embodiments of the present disclosure provide a semiconductor memory device and a method for manufacturing the same that are capable of more uniformly forming a process junction region for connecting a channel layer and a source layer of a vertical channel structure.

[0008] According to an embodiment of the present disclosure, a semiconductor memory device includes: a gate stack on a substrate, the gate stack including interlayer insulating layers and conductive patterns alternately stacked in a vertical direction; a channel structure that passes through the gate stack and has an upper end protruding above the gate stack; a memory layer that surrounds the sidewall of the channel structure; and a source layer that is formed on the gate stack. The channel structure includes a core insulating layer extending in a vertical direction in a central region of the channel structure and a channel layer surrounding the sidewall of the core insulating layer, the channel layer being lower in the vertical direction than the core insulating layer and the memory layer.

[0009] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes: forming a memory cell array on a substrate, so that the memory cell array includes a gate stack, a core insulating layer, a channel layer and a memory layer, the gate stack includes an interlayer insulating layer and a conductive pattern alternately stacked in a vertical direction, the core insulating layer passes through the gate stack and has an end extending into the substrate, the channel layer surrounds the sidewall and the end of the core insulating layer, and the memory layer extends from the area between the channel layer and the gate stack to the area between the end of the channel layer and the substrate. The method also includes: removing the substrate to expose the memory layer. The method additionally includes: exposing the core insulating layer by etching the exposed memory layer and the channel layer, and forming an opening between the upper end of the memory layer and the upper end of the core insulating layer by etching the exposed memory layer and the channel layer so that the upper surface height of the channel layer is lower than the upper surface height of the gate stack. The method also includes: forming a first source layer to surround the protrusion of the core insulating layer and the upper surface of the gate stack and fill the opening.

[0010] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes: forming a memory cell array on a substrate, so that the memory cell array includes a gate stack, a core insulating layer, a channel layer and a memory layer, the gate stack includes an interlayer insulating layer and a conductive pattern alternately stacked in a vertical direction, the core insulating layer passes through the gate stack and has an end extending into the substrate, the channel layer surrounds the sidewall and end of the core insulating layer, and the memory layer extends from the area between the channel layer and the gate stack to the area between the end of the channel layer and the substrate. The method also includes: removing the substrate to expose the memory layer, and exposing the core insulating layer by etching the exposed memory layer and channel layer. The method additionally includes: forming a first source layer and a buffer layer on the entire structure including the core insulating layer, and then performing a planarization process to make the uppermost surface uniform. The method also includes forming a junction region by performing an ion implantation process on the upper end of the channel layer, and performing a heat treatment process on the first source layer and the junction region after removing the buffer layer.

[0011] According to an embodiment of the present technology, during a process for connecting a channel layer and a source layer of a vertical channel structure, an opening can be formed by etching the channel layer, and the source layer can be filled in the opening to electrically connect the channel layer and the source layer. In addition, by forming a buffer layer for an ion implantation process on the source layer and then performing an ion implantation process, a junction region can be formed to have a uniform depth in the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 2 is an example Figure 1 Circuit diagram of a memory cell array.

[0014] Figure 3 is a perspective view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 4 is an example Figure 1 A cross-sectional view of a memory cell array.

[0016] FIG. 5A to FIG. 5F , Figure 6 , Figure 7 and FIG. 8A to FIG. 8F is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Fig. 9 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0018] Fig.10 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The specific structural description or functional description of the embodiments according to the concept of the present disclosure disclosed in this specification or this application is only exemplified to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings in order to describe them in sufficient detail to allow those skilled in the art to implement the technical ideas of the present disclosure.

[0021] Figure 1 is a block diagram illustrating a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0022] Reference Figure 1 , a semiconductor memory device 10 includes a peripheral circuit PC and a memory cell array 20 .

[0023] The peripheral circuit PC may be configured to control a program operation for storing data in the memory cell array 20 , a read operation for outputting data stored in the memory cell array 20 , and an erase operation for erasing data stored in the memory cell array 20 .

[0024] In an implementation, the peripheral circuit PC may include a voltage generator 31 , a row decoder 33 , a control circuit 35 , and a page buffer group 37 .

[0025] The memory cell array 20 may include a plurality of memory blocks. The memory cell array 20 may be connected to the row decoder 33 through word lines WL, and may be connected to the page buffer group 37 through bit lines BL.

[0026] The control circuit 35 may control the voltage generator 31 , the row decoder 33 , and the page buffer group 37 in response to the command CMD and the address ADD.

[0027] The voltage generator 31 may generate various operation voltages such as an erase voltage, a ground voltage, a program voltage, a verification voltage, a pass voltage, and a read voltage for program operations, read operations, and erase operations in response to control of the control circuit 35 .

[0028] The row decoder 33 may select a memory block in response to the control of the control circuit 35. The row decoder 33 may be configured to apply an operating voltage to a word line WL connected to the selected memory block.

[0029] The page buffer group 37 may be connected to the memory cell array 20 through the bit line BL. The page buffer group 37 may temporarily store data received from an input / output circuit (not shown) during a program operation in response to the control of the control circuit 35. The page buffer group 37 may sense a voltage or current of the bit line BL during a read operation or a verification operation in response to the control of the control circuit 35. The page buffer group 37 may select the bit line BL in response to the control of the control circuit 35.

[0030] Structurally, the memory cell array 20 may overlap a portion of the peripheral circuit PC.

[0031] Figure 2 is an example Figure 1 A circuit diagram of a memory cell array 20 is shown.

[0032] Reference Figure 2, the memory cell array 20 may include a plurality of cell strings CS1 and CS2 connected between a source line SL and a plurality of bit lines BL. The plurality of cell strings CS1 and CS2 may be commonly connected to a plurality of word lines WL1 to WLn.

[0033] Each of the plurality of cell strings CS1 and CS2 may include at least one source select transistor SST connected to a source line SL, at least one drain select transistor DST connected to a bit line BL, and a plurality of memory cells MC1 to MCn connected in series between the source select transistor SST and the drain select transistor DST.

[0034] The gates of the plurality of memory cells MC1 to MCn may be respectively connected to a plurality of word lines WL1 to WLn spaced apart and stacked from each other. The plurality of word lines WL1 to WLn may be disposed between a source selection line SSL and two or more drain selection lines DSL1 and DSL2. The two or more drain selection lines DSL1 and DSL2 may be spaced apart from each other at the same height.

[0035] A gate of the source select transistor SST may be connected to a source select line SSL. A gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST.

[0036] The source line SL may be connected to the source of the source selection transistor SST. The drain of the drain selection transistor DST may be connected to a bit line corresponding to the drain of the drain selection transistor DST.

[0037] A plurality of cell strings CS1 and CS2 may be divided into string groups connected to two or more drain selection lines DSL1 and DSL2, respectively. Cell strings connected to the same bit line may be independently controlled by different drain selection lines. In addition, cell strings connected to the same drain selection line may be independently controlled by different bit lines.

[0038] In an embodiment, the two or more drain selection lines DSL1 and DSL2 may include a first drain selection line DSL1 and a second drain selection line DSL2. The plurality of cell strings CS1 and CS2 may include a first cell string CS1 of a first string group connected to the first drain selection line DSL1 and a second cell string CS2 of a second string group connected to the second drain selection line DSL2.

[0039] Figure 3 is a perspective view schematically illustrating a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0040] Reference Figure 3 , the semiconductor memory device 10 may include a peripheral circuit PC disposed on a substrate SUB and a gate stack GST overlapping the peripheral circuit PC.

[0041] Each of the gate stacks GST may include a source select line SSL, a plurality of word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 separated from each other at the same height by a separation structure DSM.

[0042] The source selection line SSL and the plurality of word lines WL1 to WLn may extend in a first direction X and a second direction Y and may be formed in a flat plate shape parallel to the upper surface of the substrate SUB. The first direction X may be a direction in which an X-axis of an XYZ Cartesian coordinate system points, and the second direction Y may be a direction in which a Y-axis of the XYZ Cartesian coordinate system points.

[0043] The plurality of word lines WL1 to WLn may be spaced apart from each other and stacked in a third direction Z. The third direction Z may be a direction in which a Z axis of an XYZ Cartesian coordinate system points. The plurality of word lines WL1 to WLn may be disposed between two or more drain selection lines DSL1 and DSL2 and a source selection line SSL.

[0044] The gate stacks GST may be separated from each other by the slits SI. The separation structure DSM may be formed to be shorter than the slits SI in the third direction Z and may overlap the plurality of word lines WL1 to WLn.

[0045] Each of the separation structure DSM and the slit SI may extend in a straight line shape, a sawtooth shape, or a wave shape. The width of each of the separation structure DSM and the slit SI may be variously changed according to a design rule.

[0046] The source select line SSL according to an embodiment may be disposed closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL2 .

[0047] The semiconductor memory device 10 may include a source line SL disposed between a gate stack GST and a peripheral circuit PC, wherein a plurality of bit lines BL are spaced farther from the peripheral circuit PC than the source line SL. The gate stack GST may be disposed between the plurality of bit lines BL and the source line SL.

[0048] Figure 4 is an example Figure 1 FIG. 2 is a cross-sectional view of a memory cell array 20 .

[0049] Reference Figure 4 In the memory cell array 20 , the lower structure U and the upper structure T may be bonded to each other, and the source line structure SL may be disposed on the upper structure T.

[0050] The upper structure T may include gate stacks GST separated by the slits SI, channel structures CH passing through the gate stacks GST, a memory layer ML extending along a sidewall of each channel structure CH, a bit line 41 disposed under the gate stacks GST, and a first connection structure C1.

[0051] The gate stack GST may include an interlayer insulating layer ILD and conductive patterns CP1 to CPn alternately stacked in a vertical direction. Each of the conductive patterns CP1 to CPn may include various conductive materials, such as a doped silicon layer, a metal layer, a metal silicide layer, and a barrier layer, and may include two or more types of conductive materials. For example, each of the conductive patterns CP1 to CPn may include tungsten and a titanium nitride layer (TiN) surrounding the surface of the tungsten. Tungsten is a low-resistance metal and can reduce the resistance of the conductive patterns CP1 to CPn. The titanium nitride layer TiN may be a barrier layer and may prevent direct contact between tungsten and the interlayer insulating layer ILD.

[0052] Among the conductive patterns CP1 to CPn, the first conductive pattern CP1 adjacent to the bit line 41 may be used as a drain selection line DSL. In another embodiment, two or more conductive patterns adjacent to the bit line 41 and continuously stacked may be used as drain selection lines. Among the conductive patterns CP1 to CPn, the nth conductive pattern CPn adjacent to the first source layer SL1 and the second source layer SL2 may be used as a source selection line SSL. In another embodiment, two or more conductive patterns adjacent to the first source layer SL1 and the second source layer SL2 and sequentially stacked may be used as source selection lines. Conductive patterns (e.g., CP2 to CPn-1) adjacent to each other in a vertical direction and disposed between the drain selection line and the source selection line may be used as the conductive patterns described above with reference to Figure 2 Word lines WL1 to WLn are described.

[0053] The channel structure CH may pass through the gate stack GST in the vertical direction, and one end of the channel structure CH may be formed to protrude beyond the top of the gate stack GST. The channel structure CH may be formed as a hollow type. The channel structure CH may include a core insulating layer 11 filling the central region of the channel structure CH, a doped semiconductor layer 13 located at the lower end of the core insulating layer 11, and a channel layer 15 surrounding the surface of the core insulating layer 11 and the doped semiconductor layer 13. The channel layer 15 serves as a channel region of a cell string corresponding thereto. The channel layer 15 may be formed of a semiconductor material. In an embodiment, the channel layer 15 may include a silicon layer. Dopants may be implanted into the uppermost portion of the channel layer 15, that is, the portion of the channel layer corresponding to the source select transistor, by an ion implantation process. The channel structure CH may be formed to protrude beyond the interlayer insulating layer ILD disposed on the uppermost portion of the gate stack GST. The end of the channel structure CH protruding beyond the interlayer insulating layer ILD disposed on the uppermost portion of the gate stack GST may be formed only by the core insulating layer 11. For example, the channel layer 15 may be formed to have a height lower than the interlayer insulating layer ILD disposed on the uppermost portion of the gate stack GST. For example, the channel layer 15 may be formed to have a height lower than the interlayer insulating layer ILD disposed on the uppermost portion of the gate stack GST and equal to or higher than the conductive pattern used as the source selection line.

[0054] The memory layer ML may be formed to surround the surface of the channel structure CH. The memory layer ML may include a tunnel insulating layer TI surrounding the channel layer 15 of the channel structure CH, a data storage layer DS surrounding the tunnel insulating layer TI, and a blocking insulating layer BI surrounding the data storage layer DS. The memory layer ML may extend in a vertical direction and may extend longer than the channel layer 15. That is, the memory layer ML may be formed to have a height higher than the channel layer 15. That is, the channel layer 15 may be disposed between the memory layer ML and the core insulating layer 11 and may have a height lower than the memory layer ML and the core insulating layer 11. Therefore, an opening may be formed at the uppermost portion of the core insulating layer 11 and the memory layer ML by the height of the channel layer 15, and the first source layer SL1 may be filled in the opening. The memory layer ML may be formed to have the same height as the interlayer insulating layer ILD disposed on the uppermost portion of the gate stack GST. The memory layer ML may be defined as a component included in the channel structure CH.

[0055] The bit line 41 may be disposed under the gate stack GST and connected to the channel structure CH through a contact plug 31 passing through the plurality of insulating layers 21, 25, and 27. The bit line 41 may be spaced apart from the substrate SUB by the first insulating structure 51 and the second insulating structure 81.

[0056] The first connection structure 1st_CS may include a first insulating structure 51 and a first connection structure C1 formed inside the first insulating structure 51. The first connection structure C1 may include various conductive patterns 63, 65, and 67. The first insulating structure 51 may include two or more insulating layers 51A to 51D stacked between the bit line 41 and the second insulating structure 81.

[0057] The lower structure U may include a complementary metal oxide semiconductor (CMOS) circuit structure CMOS including a plurality of transistors TR formed on a substrate SUB, and a second connection structure 2nd_CS formed on the CMOS circuit structure CMOS.

[0058] The second connection structure 2nd_CS may include a second insulating structure 81 formed on the substrate SUB and a second connection structure C2 formed inside the second insulating structure 81. Each second connection structure C2 may include various conductive patterns 83, 85, 87, 89, and 91 buried in the second insulating structure 81. The second insulating structure 81 may include two or more insulating layers 81A to 81D sequentially stacked.

[0059] The upper structure T and the lower structure U may be bonded to each other through a bonding process. For example, the exposed conductive pattern 67 of the first connection structure 1nd_CS of the upper structure T and the exposed conductive pattern 91 of the second connection structure 2nd_CS of the lower structure U may be disposed to face each other and may adhere to each other. The conductive pattern 67 and the conductive pattern 91 may be defined as a bonding metal.

[0060] The source line structure SL may be disposed on the upper structure T. The source line structure SL may include a first source layer SL1 and a second source layer SL2. The first source layer SL1 may be formed of a doped polysilicon layer. The first source layer SL1 may be formed along the surface of the interlayer insulating layer ILD, the memory layer ML, and the core insulating layer 11 disposed on the uppermost portion. The first source layer SL1 may be formed to fill the opening between the upper portion of the memory layer ML and the upper portion of the core insulating layer 11 formed by the height of the channel layer 15. The first source layer SL1 may be formed to contact the uppermost surface of the channel layer 15. The second source layer SL2 may be formed on the first source layer SL1 and may be formed of a metal material having a low resistance. For example, the second source layer SL2 may be formed of titanium nitride (TiN) or tungsten (W) to reduce the resistance of the source line structure. In addition, the second source layer SL2 may be formed using copper (Cu), and may also include tantalum (Ta) or tantalum nitride (TaN) on the upper and lower surfaces of the second source layer SL2 as a barrier layer.

[0061] The source line structure SL can be used as Figure 2 The source line SL.

[0062] FIG. 5A to FIG. 5F , Figure 6 , Figure 7 and FIG. 8A to FIG. 8F is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0063] FIG. 5A to FIG. 5F is a cross-sectional view illustrating a step of forming a memory cell array, a first line array, and a first connection structure on a first substrate.

[0064] Reference Figure 5A , the first material layers 111 and the second material layers 113 may be alternately stacked layer by layer on the first substrate 101 .

[0065] The first substrate 101 may be formed of a material having an etching rate different from those of the first material layer 111 and the second material layer 113. For example, the first substrate 101 may include silicon.

[0066] In an embodiment, the first material layer 111 may be used for Figure 4 The second material layer 113 may be formed of a material having an etching rate different from that of the first material layer 111. For example, the first material layer 111 may include silicon oxide, and the second material layer 113 may include silicon nitride. The following figures illustrate an embodiment in which the first material layer 111 is formed of an insulating material and the second material layer 113 is formed of a sacrificial layer, but the present disclosure is not limited thereto. The physical properties of the first material layer 111 and the second material layer 113 may be changed in various ways. For example, the first material layer 111 may be a material used for the above reference. Figure 4 The insulating material of the interlayer insulating layer ILD described above, and the second material layer 113 may be the insulating material used in the above reference Figure 4 The conductive materials of the conductive patterns CP1 to CPn are described.

[0067] Reference Figure 5B , a first mask pattern 121 including a first opening 125 may be formed on the stacked structure of the first material layer 111 and the second material layer 113. Thereafter, a channel hole 115 passing through the first material layer 111 and the second material layer 113 may be formed through the first opening 125 of the first mask pattern 121. The channel hole 115 may extend inwardly to a partial depth of the first substrate 101. The channel hole 115 may be formed in various shapes according to an etchant used to form the channel hole 115.

[0068] In an embodiment, the channel hole 115 may be formed using a first etchant. The etching speed of the first material layer 111 and the second material layer 113 with respect to the first etchant may be faster than the etching speed of the first substrate 101 with respect to the first etchant. As a result, the width of the end of the channel hole 115 extending into the first substrate 101 may be formed to be narrower than the width of the channel hole 115 passing through the first material layer 111 and the second material layer 113.

[0069] Reference Figure 5C , a memory layer 137 and a channel structure 147 may be formed in the channel hole 115 . Sidewalls of the channel structure 147 and ends of the channel structure 147 extending into the first substrate 101 may be surrounded by the memory layer 137 .

[0070] Forming the memory layer 137 may include sequentially stacking a blocking insulating layer 135, a data storage layer 133, and a tunnel insulating layer 131 on the surface of the channel hole 115. The blocking insulating layer 135, the data storage layer 133, and the tunnel insulating layer 131 may include the same as described above. Figure 4 The blocking insulating layer BI, the data storage layer DS, and the tunnel insulating layer TI are described as the same material. The memory layer 137 may be formed in a line shape, and a central area of ​​the channel hole 115 may be defined by the memory layer 137 .

[0071] Thereafter, a channel layer 141 may be formed on the surface of the memory layer 137 to form a channel structure 147. The channel layer 141 may include a semiconductor layer serving as a channel region. For example, the channel layer 141 may include undoped polysilicon.

[0072] In an embodiment, the channel layer 141 may be formed in a line shape, and the central area of ​​the channel hole 115 may include a portion not filled with the channel layer 141. When the channel layer 141 is formed in a line shape, forming the channel structure 147 may include filling the central area of ​​the channel hole 115 on the channel layer 141 with the core insulating layer 143, etching a portion of the core insulating layer 143 to define a recessed area in a portion of the central area of ​​the channel hole 115, and filling the recessed area with the doped semiconductor layer 145. The core insulating layer 143 may include an oxide, and the doped semiconductor layer 145 may include a conductive dopant. The conductive dopant may include an n-type dopant for a junction. The conductive dopant may include a reversely doped p-type dopant.

[0073] In another embodiment, the channel layer 141 may be formed to fill the central region of the channel hole 115, and the core insulating layer 143 and the doped semiconductor layer 145 may be omitted. When the core insulating layer 143 and the doped semiconductor layer 145 are omitted, forming the channel structure 147 may further include doping a conductive dopant into the channel layer 141.

[0074] Reference Figure 5D , in removing Figure 5C After forming the first mask pattern 121 as shown, a first insulating layer 151 may be formed.

[0075] Subsequently, a slit 153 may be formed. The slit 153 may pass through the first insulating layer 151 and through the stacked structure of the first material layer 111 and the second material layer 113. The slit 153 may correspond to Figure 4 The slits S1 are shown. Subsequently, a horizontal space 155 may be defined by selectively removing the second material layer 113 exposed by the slits 153. The horizontal space 155 may be defined between the first material layers 111 adjacent in the vertical direction.

[0076] Reference Figure 5E , respectively filled with the third material layer 157 through the slit 153 Figure 5D The horizontal space 155 shown. The third material layer 157 can be the above reference Figure 4 The third material layer 157 may fill the horizontal space 155 to surround the channel structure 147 and the memory layer 137 .

[0077] As described above, the gate stack 150 may be formed on the first substrate 101 by replacing the second material layer 113 as a sacrificial layer with the third material layer 157 as a conductive pattern. The gate stack 150 may include a structure in which the first material layer 111 as an interlayer insulating layer and the third material layer 157 as a conductive pattern are alternately stacked. The channel structure 147 may pass through the gate stack 150 and extend into the first substrate 101. The memory layer 137 may extend from a region between the channel structure 147 and the gate stack 150 to a region between an end of the channel structure 147 and the first substrate 101.

[0078] Including the above reference Figure 2 The memory blocks of the plurality of cell strings CS1 and CS2 described above can be referred to as FIG. 5A to FIG. 5E Each cell string may include a drain select transistor DST and memory cells MC1 to MCn connected in series, as described above. Figure 3 As mentioned above. Figure 3 The drain selection transistor DST and the memory cells MC1 to MCn described may be defined in Figure 5E The channel structure 147 shown is an intersection of the third material layer 157 as a conductive pattern, and can be connected in series through the channel structure 147 .

[0079] Subsequently, the sidewall insulating layer 161 may be formed to cover the sidewalls of the gate stack 150. Thereafter, the second insulating layer 163 extending to fill the inside of the slit 153 and covering the sidewall insulating layer 161 and the first insulating layer 151 may be formed.

[0080] Reference Fig. 5F , a third insulating layer 171 may be formed on the second insulating layer 163. Subsequently, a contact plug 173 may be formed through the third insulating layer 171 or through the third insulating layer 171 and the second insulating layer 163. The contact plug 173 may extend to contact the channel structure 147.

[0081] Subsequently, a first line array 175 may be formed. The first line array 175 may be a bit line connected to the contact plug 173. Thereafter, a first insulating structure 181 covering the first line array 175 may be formed. The first insulating structure 181 may include two or more insulating layers 181A, 181B, 181C, and 181D. First connection structures 185, 189, 191, and 193 may be buried in the first insulating structure 181, and the first connection structures 185, 189, 191, and 193 may be electrically connected through a contact plug (not shown).

[0082] The first connection structures 185 , 189 , 191 , and 193 may include a first bonding metal having a surface exposed to the outside of the first insulation structure 181 .

[0083] Figure 6 is a cross-sectional view illustrating a step of forming a CMOS circuit and a second connection structure on a second substrate.

[0084] Reference Figure 6 The method may include forming a plurality of transistors 200 constituting a CMOS circuit on a second substrate 201 .

[0085] The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial layer formed by a selective epitaxial growth method.

[0086] Each transistor 200 may be formed in an active region of a second substrate 201 separated by an isolation layer 203. Each transistor 200 may include a gate insulating layer 207 and a gate electrode 209 stacked on an active region corresponding thereto, and junctions 205a and 205b formed in the active region on both sides of the gate electrode 209. The junctions 205a and 205b may include conductive dopants for implementing the transistors corresponding thereto. The junctions 205a and 205b may include at least one of an n-type dopant and a p-type dopant.

[0087] After forming a plurality of transistors 200 , a second connection structure 220 connected to the transistors 200 constituting the CMOS circuit and a second insulating structure 211 covering the second connection structure 220 and the transistors 200 may be formed.

[0088] The second insulating structure 211 may include two or more insulating layers 211A, 211B, 211C, and 211D. The second connection structures 220 may be buried in the second insulating structure 211. Each second connection structure 220 may include a plurality of conductive patterns 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structure 220 are not limited to the examples shown in the drawings and may be changed in various ways.

[0089] The conductive patterns 213 , 215 , 217 , 219 , 221 , and 223 represent the second connection structure 220 and may include a second bonding metal having a surface exposed to the outside of the second insulation structure 211 .

[0090] Figure 7 is a cross-sectional view illustrating a step of joining a first connection structure and a second connection structure to each other.

[0091] Reference Figure 7 The first substrate 101 and the second substrate 201 are aligned so that the first bonding metal of the first connection structure 193 on the first substrate 101 and the second bonding metal of the second connection structure 223 on the second substrate 201 can contact each other. The first bonding metal and the second bonding metal may include various metals and may include, for example, copper.

[0092] Thereafter, the first bonding metal of the first connection structure 193 and the second bonding metal of the second connection structure 223 adhere to each other. To this end, after applying heat to the first bonding metal and the second bonding metal, the first bonding metal and the second bonding metal may be hardened. The present disclosure is not limited thereto, and various processes for connecting the first connection structure 193 and the second connection structure 223 may be introduced.

[0093] FIG. 8A to FIG. 8F 1 is a cross-sectional view illustrating a structure in which a source line connected to a plurality of cell strings is formed on the gate stack 150 .

[0094] Reference Fig. 8A , you can remove Figure 7 The first substrate 101 is shown. The memory layer 137 may be used as an etch stop layer when the first substrate 101 is removed. Therefore, the channel structure 147 protruding beyond the gate stack 150 may be protected by the memory layer 137.

[0095] Reference Figure 8B, the memory layer 137 protruding over the gate stack 150 may be removed to expose the channel layer 141. The exposed channel layer 141 may protrude over the gate stack 150. The upper surface height of the memory layer 137 may be equal to or lower than the upper surface height of the gate stack 150.

[0096] Afterwards, refer to Figure 8B The process steps are described by using an enlarged view of the area A indicated in FIG.

[0097] Reference Figure 8C , the channel layer 141 exposed by etching the memory layer 137 is etched to expose the protrusion of the core insulating layer 143. At this time, the opening OP is formed by controlling the etching process to etch the upper end portion of the channel layer between the tunnel insulating layer 131 and the core insulating layer 143. That is, the etching process may be performed to etch the exposed channel layer 141, and the channel layer 141 may be etched so that the height of the channel layer 141 is similar to that of the conductive pattern used as the source selection line located at the uppermost portion.

[0098] Reference Fig.8D , a first source layer 177 is formed along the upper surface of the entire structure including the exposed surface of the core insulating layer 143. At this time, the first source layer 177 is formed to fill Figure 8C Thus, the first source layer 177 is in direct contact with the uppermost portion of the channel layer 141. The first source layer 177 may be formed of a doped polysilicon layer.

[0099] Reference Fig. 8E , a buffer layer 178 is formed on the first source layer 177, and a planarization process is performed so that an upper height of the buffer layer 178 is uniform. The buffer layer 178 may be formed of an oxide layer.

[0100] Thereafter, an ion implantation process is performed to implant dopants into the channel layer 141 serving as a channel of the source select transistor to form a junction region. Since the ion implantation depth becomes uniform by the buffer layer 178 during the ion implantation process, the ion implantation region can be controlled.

[0101] Reference Fig.8F , in removing Fig. 8E After the buffer layer 178 is shown, a local heat treatment process using a laser is performed to activate the junction region. The target region of the heat treatment process may include a junction region between the first source layer 177 and the channel layer 141 where the dopant is implanted.

[0102] Thereafter, a second source layer 179 is formed on the first source layer 177. The second source layer 179 may be formed on the first source layer 177 and may be formed of a metal material having a low resistance. For example, the second source layer 179 may be formed of titanium nitride (TiN) or tungsten (W) to reduce the resistance of the source line structure. In addition, the second source layer 179 may be formed using copper (Cu) and may further include tantalum (Ta) or tantalum nitride (TaN) on the upper and lower surfaces of the second source layer 179 as a barrier layer.

[0103] As described above, according to an embodiment of the present disclosure, after an opening is formed by etching the channel layer, the opening can be filled with a first source layer to directly connect the channel layer and the source layer. In addition, after forming the buffer layer, an ion implantation process can be performed to uniformly form a junction region. In addition, the junction region can be activated by performing a local heat treatment process using a laser.

[0104] Fig. 9 is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0105] Reference Fig. 9 , the memory system 1100 includes a semiconductor memory device 1120 and a memory controller 1110 .

[0106] The semiconductor memory device 1120 may be a multi-chip package composed of a plurality of flash memory chips. Figures 1 to 4 A semiconductor memory device is described.

[0107] The memory controller 1110 may be configured to control the semiconductor memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol of a host connected to the memory system 1100. In addition, the error correction block 1114 detects and corrects errors included in data read from the semiconductor memory device 1120, and the memory interface 1115 performs an interface connection with the semiconductor memory device 1120. In addition, the memory controller 1110 may further include a read-only memory (ROM) storing code data for interfacing with the host.

[0108] The above-mentioned memory system 1100 may be a memory card or a solid state disk (SSD) in which a semiconductor memory device 1120 and a memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., a host) through one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0109] Fig.10 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0110] Reference Fig.10 , the computing system 1200 may include a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. In addition, when the computing system 1200 is a mobile device, a battery for providing an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may also be included.

[0111] Although the detailed description of the present disclosure describes specific embodiments, various changes and modifications are possible without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above embodiments, but should be determined by the appended claims and their equivalents.

[0112] CROSS-REFERENCE TO RELATED APPLICATIONS

[0113] This application claims priority to Korean Patent Application No. 10-2021-0076987, filed on Jun. 14, 2021, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: A gate stack on a substrate, the gate stack comprising interlayer insulating layers and conductive patterns alternately stacked in a vertical direction; a channel structure passing through the gate stack and having an upper end protruding above the gate stack; a memory layer surrounding a sidewall of the channel structure; as well as a source layer formed on the gate stack, Wherein, the channel structure comprises: a core insulating layer extending in the vertical direction in a central region of the trench structure; and a channel layer, the channel layer surrounding a side wall of the core insulating layer, the channel layer being lower than the memory layer in the vertical direction, Wherein, the source layer is formed into a multi-layer structure.

2. The semiconductor memory device according to claim 1, wherein The source layer comprises: a first source layer formed along a surface of an upper portion of the gate stack and a protruding upper end portion of the channel structure; and A second source layer is formed on the first source layer.

3. The semiconductor memory device according to claim 2, wherein: The first source layer fills a space between an upper end portion of the memory layer and an upper end portion of the core insulating layer.

4. The semiconductor memory device according to claim 2, wherein: The first source layer is directly connected to an upper end portion of the channel layer.

5. The semiconductor memory device according to claim 1, wherein: The channel layer includes an undoped polysilicon layer.

6. The semiconductor memory device according to claim 2, wherein: The first source layer includes a doped polysilicon layer.

7. The semiconductor memory device according to claim 6, wherein: The second source layer includes a metal material.

8. The semiconductor memory device according to claim 1, wherein: The upper surface height of the channel layer is lower than the upper surface height of the gate stack.

9. The semiconductor memory device according to claim 1, wherein: The upper surface height of the channel layer is lower than the upper surface height of the memory layer.

10. The semiconductor memory device according to claim 1, wherein The upper surface height of the channel layer is equal to or higher than an uppermost conductive pattern serving as a selection line among the conductive patterns.

11. The semiconductor memory device according to claim 1, wherein: The height of the upper surface of the memory layer is equal to or lower than the height of the upper surface of the gate stack.

12. A semiconductor memory device, comprising: A gate stack on a substrate, the gate stack comprising interlayer insulating layers and conductive patterns alternately stacked in a vertical direction; a channel structure passing through the gate stack and having an upper end protruding above the gate stack; a memory layer surrounding a sidewall of the channel structure; as well as a source layer formed on the gate stack, Wherein, the channel structure comprises: a core insulating layer extending in the vertical direction in a central region of the trench structure; and a channel layer surrounding a sidewall of the core insulating layer, wherein the core insulating layer comprises a protrusion extending into the source layer, and Wherein, the source layer is formed into a multi-layer structure.

13. The semiconductor memory device according to claim 12, wherein: The source layer comprises: a first source layer surrounding the protrusion of the core insulating layer; and A second source layer has a flat upper surface on the first source layer.

14. The semiconductor memory device according to claim 13, wherein: The first source layer extends between the core insulating layer and the memory layer.

15. The semiconductor memory device according to claim 12, wherein: The channel layer is lower than the core insulating layer and the memory layer in the vertical direction.

16. The semiconductor memory device according to claim 12, wherein: The source layer comprises: a first source layer formed along a surface of an upper portion of the gate stack and the protrusion of the core insulating layer; and A second source layer is formed on the first source layer.

17. The semiconductor memory device according to claim 16, wherein: The first source layer fills a space between an upper end portion of the memory layer and an upper end portion of the core insulating layer.

18. The semiconductor memory device according to claim 16, wherein: The first source layer is directly connected to an upper end portion of the channel layer.

19. The semiconductor memory device according to claim 12, wherein: The channel layer includes an undoped polysilicon layer.

20. The semiconductor memory device according to claim 13, wherein: The first source layer includes a doped polysilicon layer.

21. The semiconductor memory device according to claim 13, wherein: The second source layer includes a metal material.

22. The semiconductor memory device according to claim 12, wherein: The upper surface height of the channel layer is lower than the upper surface height of the gate stack.

23. The semiconductor memory device according to claim 12, wherein: The upper surface height of the channel layer is lower than the upper surface height of the memory layer.

24. The semiconductor memory device according to claim 12, wherein: The upper surface height of the channel layer is equal to or higher than an uppermost conductive pattern serving as a selection line among the conductive patterns.

25. The semiconductor memory device according to claim 12, wherein: The height of the upper surface of the memory layer is equal to or lower than the height of the upper surface of the gate stack.

26. The semiconductor memory device according to claim 12, further comprising: a bit line connected to a lower end of the channel structure; A conductive connection line, the conductive connection line is arranged in a lower layer of the bit line; An insulating structure, the insulating structure surrounding the conductive connecting wire; as well as A conductive connection structure penetrates the insulating structure and connects the conductive connection line to a complementary metal oxide semiconductor (CMOS) circuit.

27. The semiconductor memory device according to claim 12, further comprising: a bit line connected to a lower end of the channel structure; a first connection structure connected to the bit line; a second connection structure connected to the first connection structure; as well as a complementary metal oxide semiconductor (CMOS) circuit formed on the substrate and connected to the second connection structure, The first connection structure includes a first bonding metal, the second connection structure includes a second bonding metal, and the first bonding metal and the second bonding metal are bonded to each other.

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