Digital-analog integrated memristor and preparation method and application thereof

Abstract

The invention discloses a digital-analog integrated memristor and a preparation method and application thereof, and belongs to the technical field of memristors. Comprising a substrate layer, a first resistive layer, a second resistive layer and a top electrode layer, the first resistive layer is arranged on the substrate layer, the second resistive layer is arranged on the first resistive layer, and the top electrode layer is arranged on the second resistive layer; wherein the first resistive layer and the second resistive layer form a tantalum oxide-tungsten oxide heterojunction. The preparation is simple, the film uniformity is high, digital-analog coexistence of the memristor can be realized in a single device, and later integration and application of the memristor are facilitated; the problems that in the prior art, the memristor preparation process is complex, performance fluctuates, and repeatability is low are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of memristors, and in particular to a digital-analog integrated memristor and a preparation method and application thereof. Background Art

[0002] The statements in this section merely mention background art related to the present invention and do not necessarily constitute prior art.

[0003] Memristors have the characteristics of simple structure and high density, making them a candidate for high-performance memory and low-power brain-inspired computing chips. Semiconductor devices are facing the memory wall and power consumption wall. Memristor-based memory computing can potentially overcome the current computer bottleneck and achieve hardware breakthroughs.

[0004] According to the conduction type, memristors can be divided into mutant memristors and gradual memristors. Under the action of an external electric field, mutant memristors can achieve high-density, low-power storage, and gradual memristors are ideal synaptic bionic components. In addition, memristor arrays can build more integrated neural network structures, thereby improving the efficiency of neural networks. A single device combines analog resistance switches and multi-level digital resistance switches to further improve the integration of the system. The memristor-based pattern recognition system can also be used to realize the recognition and processing of biological signal data.

[0005] However, existing memristors still have the following problems:

[0006] (1) The device preparation process is complicated, which increases the difficulty of preparation. At the same time, during the preparation process, the thickness of the prepared film is difficult to control, resulting in performance fluctuations and low repeatability, which is not conducive to the construction of an artificial neural network with stable artificial synaptic characteristics.

[0007] (2) The linear characteristics of long-term potentiation (LTP) and long-term depression (LTD) in artificial synaptic properties are poor, which affects their application in simulating neural networks.

[0008] (3) Most of the work focuses on optimizing digital characteristics or analog characteristics alone. In practical applications, having only digital characteristics or analog characteristics is not conducive to circuit integration.

[0009] (4) Memristors have not been effectively applied in practical scenarios. Summary of the invention

[0010] In order to address the deficiencies in the prior art, the present invention provides a digital-analog integrated memristor and a preparation method and application thereof. The designed oxide-based memristor has a simple preparation process and high film uniformity. By adjusting the voltage, conversion between digital and analog can be achieved.

[0011] In a first aspect, the present invention provides a digital-analog integrated memristor;

[0012] A digital-analog integrated memristor comprises a substrate layer, a first resistive switching layer, a second resistive switching layer and a top electrode layer;

[0013] The first resistive switching layer is disposed on the substrate layer, the second resistive switching layer is disposed on the first resistive switching layer, and the top electrode layer is disposed on the second resistive switching layer;

[0014] The first resistive switching layer and the second resistive switching layer form a tantalum oxide-tungsten oxide heterojunction.

[0015] In a second aspect, the present invention provides a method for preparing a digital-analog integrated memristor;

[0016] A method for preparing a digital-analog integrated memristor comprises the following steps:

[0017] providing a substrate layer;

[0018] Using tantalum pentoxide to sputter on the substrate layer to form a first resistive layer;

[0019] Using a metal tungsten target to sputter on the first resistive layer to form a second resistive layer;

[0020] Using a metal silver target to sputter on the second resistive layer to form a top electrode layer;

[0021] The first resistive switching layer and the second resistive switching layer form a tantalum oxide-tungsten oxide heterojunction.

[0022] In a third aspect, the present invention provides a brain wave emotion recognition system based on a digital-analog integrated memristor;

[0023] A brain wave emotion recognition system based on a digital-analog integrated memristor, comprising a digital-analog integrated memristor and a processor, wherein a trained brain wave emotion recognition model is deployed on the processor;

[0024] Wherein, the weight parameters of the brain wave emotion recognition model are updated according to the normalized conductance weight of the digital-analog integrated memristor.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The technical solution provided by the present invention provides a digital-analog integrated memristor, which has a simple preparation process and high film uniformity, and can achieve conversion between digital and analog by adjusting the voltage; a single device combined with an analog resistance switch and a multi-level digital resistance switch can further improve the integration of the system.

[0027] 2. The technical solution provided by the present invention is to prepare a resistive switching layer by inserting a Ta2O5 / WO3 heterojunction after the WO3 layer, so that the prepared memristor has excellent bipolar resistance switching performance, including multi-level resistance state, high switching ratio, long retention time, and high linearity long-term potentiation (LTP) and long-term depression (LTD) performance. This feature can be applied to artificial neural networks to realize the function of brain wave emotion recognition. Users can input brain wave signal data into the model, and then calibrate specific features at the beginning of the signal, such as identifying emotional states. The neural network model can also effectively analyze emotional states and help researchers understand individual emotional changes.

[0028] 3. The technical solution provided by the present invention uses a magnetron sputtering method to prepare a thin film with uniform and dense characteristics during the device preparation process, and a memristor with stable performance and good artificial synaptic characteristics is prepared by this method. By modifying the device resistive layer structure and the preparation parameters during the resistive layer preparation process, a digital-analog integrated memristor with good performance is studied, which is of great significance for promoting the development of neuromorphic systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0030] Figure 1 A schematic diagram of the structure of a digital-analog integrated memristor provided in an embodiment of the present invention;

[0031] Figure 2 A forward pulse scan IV diagram of a digital-analog integrated memristor provided in an embodiment of the present invention;

[0032] Figure 3 A forward pulse scan IV diagram of a digital-analog integrated memristor provided in an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of the pulse amplitude-dependent plasticity of the digital-analog integrated memristor provided in an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the pulse width dependence plasticity of the digital-analog integrated memristor provided in an embodiment of the present invention;

[0035] Figure 6 A schematic diagram of the plasticity dependence of the pulse time interval of the digital-analog integrated memristor provided in an embodiment of the present invention;

[0036] Figure 7A schematic diagram of the long-term synaptic plasticity (including LTP and LTD) of the digital-analog integrated memristor provided in an embodiment of the present invention;

[0037] Figure 8 An IV scan test diagram of the digital-analog integrated memristor provided in an embodiment of the present invention when the limiting current is 1 mA;

[0038] Fig. 9 A schematic diagram of the retention characteristics of high and low resistance states of the digital-analog integrated memristor provided in an embodiment of the present invention when the limiting current is 1 mA;

[0039] Fig.10 An IV scan test diagram of the digital-analog integrated memristor provided in an embodiment of the present invention when the limiting current is 10ma;

[0040] Fig.11 An application flow chart of brain wave emotion recognition of the digital-analog integrated memristor provided in an embodiment of the present invention;

[0041] Fig.12 A schematic diagram showing the application of brain wave emotion recognition of the digital-analog integrated memristor provided in an embodiment of the present invention;

[0042] Fig.13 Schematic diagram of the EEG emotion recognition model of the digital-analog integrated memristor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used in the present invention have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0044] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0045] Combination Figure 1-Figure 13 In the first aspect, the present embodiment provides a digital-analog integrated memristor, which includes a substrate layer, a first resistive layer, a second resistive layer and a top electrode layer; the first resistive layer is arranged on the substrate layer, the second resistive layer is arranged on the first resistive layer, and the top electrode layer is arranged on the second resistive layer; wherein the first resistive layer and the second resistive layer form a tantalum oxide-tungsten oxide heterojunction.

[0046] The above-mentioned digital-analog integrated memristor can realize sudden and gradual conversion, that is, by adjusting the voltage, the conversion between analog and digital can be realized; specifically, within the low voltage range (such as 0-2V), the applied voltage can cause a small change in the resistance state of the memristor, and by adjusting the voltage size and application time, different charge distribution patterns can be formed in the memristor, thereby realizing analog signal processing.

[0047] At low voltages, the migration of charge within the memristor causes a gradual change in resistance. When the voltage exceeds a threshold, the migration of ions within the material causes a sudden jump in resistance. This abrupt process causes the memristor to switch from analog mode to digital mode, that is, to switch between two stable resistance states.

[0048] For example, when the voltage exceeds a certain threshold (such as 4V), the resistance value of the memristor may suddenly change, causing it to switch from analog mode to digital mode. The sudden effect of the memristor allows it to maintain two stable resistance states for a long time even without power.

[0049] In some embodiments, the first resistive layer is a Ta2O5 film formed by sputtering a tantalum pentoxide target, and the second resistive layer is a WO3 film formed by sputtering a tungsten target. The thickness of the first resistive layer is 18nm to 25nm, and the thickness of the second resistive layer is 110nm to 300nm.

[0050] By inserting the Ta2O5 / WO3 heterojunction after the WO3 layer, the digital mode memristor exhibits superior bipolar resistance switching performance, including multi-level resistance states, high switching ratio, long retention time, and highly linear long-term potentiation (LTP) and long-term depression (LTD) performance.

[0051] Specifically, in the P-Si / Ta2O5 / WO3 / Ag structure, the single-layer Ta2O5 exhibits unipolarity, and the insertion of WO3 improves the overall resistance switching performance. The WO3 layer forms conductive filaments (CFs) under voltage, and the lower barrier of WO3 makes it easy to form conductive filaments when a positive voltage is applied, and these filaments will break when a negative voltage is applied, thereby allowing bipolar resistance switching.

[0052] Under different current limiting conditions, such as 100μA and 1mA, the formation mechanism of conductive filaments in the WO3 layer will be different. Under low current conditions, fewer conductive filaments may be formed, while under high current conditions, more conductive filaments will be formed. This change allows the device to exhibit different resistance states under different current conditions.

[0053] The WO3 layer provides an effective conductive filament formation region that can form multiple resistance states under different current conditions. The Ta2O5 layer enhances the significance of resistance switching through a high potential barrier, making the change of resistance state more obvious and achieving a high on-off ratio.

[0054] The thicker WO3 layer provides more space to form and maintain conductive filaments, which increases the stability of the device in the low resistance state; the high potential barrier of the Ta2O5 layer provides additional stability during resistance switching. In the high resistance state (HRS), the high potential barrier prevents the spontaneous formation and breakage of conductive filaments, thereby extending the retention time.

[0055] The thicker design of the WO3 layer and the higher redox reaction stability enable the formation of stable conductive filaments under different voltage and current conditions; stable conductive filaments help maintain consistent conductivity levels over a long period of time, thereby achieving highly linear LTP and LTD performance. The high potential barrier provided by the Ta2O5 layer helps to suppress sudden conductivity changes during the resistance state switching process, thereby stabilizing the long-term conductivity state. The high potential barrier plays an important role in maintaining LTP and LTD performance, preventing unnecessary conductivity changes. The presence of the Ta2O5 layer helps to reduce the degradation and recombination of the conductive filaments in the WO3 layer, thereby enhancing the linearity of LTP and LTD.

[0056] In a second aspect, based on the above-mentioned digital-analog integrated memristor, this embodiment provides a method for preparing a digital-analog integrated memristor, comprising the following steps:

[0057] Step 1: Provide a substrate layer.

[0058] Step 2: sputtering tantalum pentoxide on the substrate layer to form a first resistive switching layer.

[0059] Step 3: Sputtering the first resistive layer using a metal tungsten target to form a second resistive layer.

[0060] Step 4, using a metal silver target to sputter on the second resistive layer to form a top electrode layer;

[0061] The first resistive layer and the second resistive layer form a tantalum oxide-tungsten oxide heterojunction.

[0062] In some embodiments, the step of providing a substrate layer is specifically as follows: commercial P-type Si substrate is cleaned for 10 minutes under ultrasonic wave action with ethanol and deionized water in sequence to remove oil and impurity particles on the surface of the P-type Si substrate, and then dried with nitrogen to ensure a clean and dry substrate.

[0063] In some embodiments, tantalum pentoxide is used to sputter on the substrate layer to form a first resistive layer. Specifically, the chamber is evacuated and argon gas with a volume flow rate of 20ccm to 30ccm and oxygen gas with a volume flow rate of 5sccm to 8sccm are introduced. Under the conditions of a working pressure of 1Pa to 2Pa and a radio frequency power of 80W to 100W, tantalum pentoxide target is used for sputtering for 20min to 30min to obtain a Ta2O5 thin film.

[0064] In some embodiments, a metal tungsten target is used to sputter on the first resistive layer to form a second resistive layer. Specifically, the chamber is evacuated and argon gas with a volume flow rate of 20ccm to 30ccm and oxygen gas with a volume flow rate of 5sccm to 8sccm are introduced. Under the conditions of a working pressure of 1Pa to 2Pa and a DC power of 80W to 100W, a metal tungsten target is used for sputtering for 8min to 20min to obtain a WO3 film.

[0065] In some embodiments, a metal silver target is used to sputter on the second resistive layer to form a top electrode layer. Specifically, the chamber is evacuated and argon gas is introduced. Under the conditions of a working pressure of 1Pa to 1.5Pa and a DC power of 45W to 55W, a metal mask is modified and sputtering is performed using a metal silver target for 12min to 17min.

[0066] In the digital-analog integrated memristor, LTP is mainly determined by the formation and stability of the conductive filaments. The formation of the conductive filaments is caused by the application of an electric field to cause the conductive ions (such as silver ions) to migrate and aggregate in the WO3 layer to form a stable conductive channel. The stability of these conductive channels directly affects the strength and durability of the memory effect. Stable conductive filaments can maintain a resistance state for a long time, thereby enhancing the LTP performance. An appropriate amount of oxygen vacancies contributes to the migration of silver ions and the formation of conductive filaments, but too much oxygen vacancies may affect the process of filament breakage, resulting in instability of the filaments. Therefore, in this embodiment, the oxygen vacancy concentration of the WO3 layer is adjusted by adjusting the ratio of argon and oxygen. The higher the oxygen concentration, the lower the oxygen vacancy concentration. By changing the concentration of oxygen vacancies, the stability of the filaments can be optimized, thereby adjusting the LTP performance.

[0067] Adjusting the thickness of the Ta2O5 and WO3 layers can affect the formation and fracture of the filaments. A thicker WO3 layer can help the formation of the filaments, while a moderate thickness of the Ta2O5 layer helps the stability and fracture performance of the filaments. Therefore, in the preparation method described in this embodiment, the thickness of the first resistive layer and the second resistive layer is adjusted by adjusting the sputtering time.

[0068] The crystallinity of the Ta2O5 layer will also affect the LTP performance of the digital-analog integrated memristor. Higher crystallinity usually means fewer defects and better charge transfer characteristics, which helps to form stable filaments. However, too high crystallinity may affect the formation of conductive filaments, so it is necessary to find a balance between performance improvement and conductive filament formation. Therefore, in this embodiment, when preparing the Ta2O5 layer, the crystallinity of the Ta2O5 layer is adjusted by regulating the substrate heating temperature. Experiments have shown that when the substrate heating temperature is 500 degrees, the Ta2O5 layer is partially crystallized, achieving a balance between performance improvement and conductive filament formation.

[0069] Example 1

[0070] The preparation method of the digital-analog integrated memristor has the following specific steps:

[0071] (1) Commercial P-type Si substrates were cleaned for 10 min under ultrasonic wave with ethanol and deionized water respectively to remove oil and impurity particles on the surface of the P-type Si substrate. Subsequently, nitrogen was used to blow dry the substrate to ensure a clean and dry substrate layer.

[0072] (2) Prepare the first resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon gas and oxygen with volume flow rates of 30 ccm and 8 sccm were introduced, and under the conditions of working pressure of 1.5 Pa and RF power of 90 W, tantalum pentoxide (Ta2O5) target was used for sputtering for 20 min to obtain Ta2O5 film with a thickness of 18 nm.

[0073] (3) Prepare the second resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 30 sccm and 15 sccm respectively were introduced, and under the conditions of working pressure of 1.5 Pa and DC power of 90 W, a metal tungsten (W) target was used for sputtering for 20 min to obtain a WO3 film with a thickness of 300 nm.

[0074] (4) Prepare the top electrode layer, pass argon gas with a volume flow rate of 20 sccm for protection, and under the conditions of a working pressure of 1 Pa and a DC power of 50 W, modify the metal mask and use a metal silver (Ag) target for sputtering for 15 minutes to obtain an Ag dome electrode, completing the preparation of a tantalum oxide-tungsten oxide heterojunction memristor.

[0075] The digital-analog integrated memristor manufactured by the method for manufacturing the digital-analog integrated memristor described in Example 1 has only analog characteristics.

[0076] Example 2

[0077] The preparation method of the digital-analog integrated memristor has the following specific steps:

[0078] (1) Commercial P-type Si substrates were cleaned for 10 min under ultrasonic wave action using ethanol and deionized water in turn to remove oil and impurity particles on the surface of the P-type Si substrate. Subsequently, nitrogen was used to blow dry the substrate to ensure a clean and dry substrate.

[0079] (2) Prepare the first resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon gas with a volume flow rate of 30 ccm and 8 sccm and oxygen gas were introduced, and under the conditions of a working pressure of 1.5 Pa and a radio frequency power of 100 W, tantalum pentoxide (Ta2O5) target was used for sputtering for 30 min to obtain a Ta2O5 film with a thickness of 30 nm.

[0080] (3) Prepare the second resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 30 sccm and 15 sccm respectively were introduced, and under the conditions of working pressure of 1.5 Pa and DC power of 90 W, a metal tungsten (W) target was used for sputtering for 15 min to obtain a WO3 film with a thickness of 225 nm.

[0081] (4) Prepare the top electrode layer, pass argon gas with a volume flow rate of 20 sccm for protection, and under the conditions of a working pressure of 1 Pa and a DC power of 50 W, modify the metal mask and use a metal silver (Ag) target for sputtering for 15 minutes to obtain an Ag dome electrode, completing the preparation of a tantalum oxide-tungsten oxide heterojunction memristor.

[0082] The digital-analog integrated memristor manufactured by the method for manufacturing the digital-analog integrated memristor described in Example 2 has only analog characteristics.

[0083] Example 3

[0084] The preparation method of the digital-analog integrated memristor has the following specific steps:

[0085] (1) Commercial P-type Si substrates were cleaned for 10 min under ultrasonic wave action using ethanol and deionized water in turn to remove oil and impurity particles on the surface of the P-type Si substrate. Subsequently, nitrogen was used to blow dry the substrate to ensure a clean and dry substrate.

[0086] (2) Prepare the first resistive switching layer and evacuate the chamber to a pressure of 3×10 -3Pa, argon gas with a volume flow rate of 30 ccm and 8 sccm and oxygen gas were introduced, and under the conditions of a working pressure of 1.5 Pa and a radio frequency power of 100 W, tantalum pentoxide (Ta2O5) target was used for sputtering for 30 min to obtain a Ta2O5 film with a thickness of 30 nm.

[0087] (3) Prepare the second resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 30 sccm and 15 sccm respectively were introduced, and under the conditions of working pressure of 1.5 Pa and DC power of 90 W, a metal tungsten (W) target was used for sputtering for 12 min to obtain a WO3 film with a thickness of 180 nm.

[0088] (4) Prepare the top electrode, pass argon gas with a volume flow rate of 20 sccm for protection, and under the conditions of a working pressure of 1 Pa and a DC power of 50 W, modify the metal mask and use a metal silver (Ag) target for sputtering for 15 minutes to obtain an Ag dome electrode, completing the preparation of a tantalum oxide-tungsten oxide heterojunction memristor.

[0089] The digital-analog integrated memristor manufactured by the method for manufacturing the digital-analog integrated memristor described in Example 3 has only analog characteristics.

[0090] Example 4

[0091] The preparation method of the digital-analog integrated memristor has the following specific steps:

[0092] (1) Commercial P-type Si substrates were cleaned for 10 min under ultrasonic wave action using ethanol and deionized water in turn to remove oil and impurity particles on the surface of the P-type Si substrate. Subsequently, nitrogen was used to blow dry the substrate to ensure a clean and dry substrate.

[0093] (2) Prepare the first resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon gas and oxygen with volume flow rates of 30 ccm and 8 sccm were introduced, and under the conditions of working pressure of 1.5 Pa and RF power of 90 W, tantalum pentoxide (Ta2O5) target was used for sputtering for 30 min to obtain Ta2O5 film with a thickness of 25 nm.

[0094] (3) Prepare the second resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 30 sccm and 15 sccm respectively were introduced, and under the conditions of working pressure of 1.5 Pa and DC power of 80 W, a metal tungsten (W) target was used for sputtering for 8 min to obtain a WO3 film with a thickness of 110 nm.

[0095] (4) Prepare the top electrode layer, pass argon gas with a volume flow rate of 20 sccm for protection, and under the conditions of a working pressure of 1 Pa and a DC power of 50 W, modify the metal mask and use a metal silver (Ag) target for sputtering for 15 minutes to obtain an Ag dome electrode, completing the preparation of a tantalum oxide-tungsten oxide heterojunction memristor.

[0096] The digital-analog integrated memristor prepared by the preparation method described in Example 4 has unstable digital characteristics; the LTP and LTD curves of the digital-analog integrated memristor are obtained by testing the electrical performance of the digital-analog integrated memristor, and its linearity is evaluated using methods such as the Pearson correlation coefficient.

[0097] The Pearson correlation coefficient (r) was used to quantify the linearity of LTP and LTD. The r value of the LTP curve was 0.94382, and the r value of the LTD curve was -0.80245.

[0098] Example 5

[0099] The preparation method of the digital-analog integrated memristor has the following specific steps:

[0100] (1) Commercial P-type Si substrates were cleaned for 10 min under ultrasonic wave action using ethanol and deionized water in turn to remove oil and impurity particles on the surface of the P-type Si substrate. Subsequently, nitrogen was used to blow dry the substrate to ensure a clean and dry substrate.

[0101] (2) Prepare the first resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, the substrate heating temperature is 500 degrees, argon gas and oxygen with a volume flow rate of 30ccm and 8sccm are introduced, and under the conditions of a working pressure of 1.5Pa and a RF power of 90W, tantalum pentoxide (Ta2O5) target is used for sputtering for 30min to obtain a Ta2O5 film with a thickness of 30nm.

[0102] (3) Prepare the second resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 30 sccm and 15 sccm respectively were introduced, and under the conditions of working pressure of 1.5 Pa and DC power of 80 W, a metal tungsten (W) target was used for sputtering for 8 min to obtain a WO3 film. The thickness of the Ta2O5 film was 125 nm.

[0103] (4) Prepare the top electrode layer, pass argon gas with a volume flow rate of 20 sccm for protection, and under the conditions of a working pressure of 1 Pa and a DC power of 50 W, modify the metal mask and use a metal silver (Ag) target for sputtering for 15 minutes to obtain an Ag dome electrode, completing the preparation of a tantalum oxide-tungsten oxide heterojunction memristor.

[0104] The LTP and LTD linearities of the digital-analog integrated memristor prepared by the preparation method described in Example 5 were quantified by the Pearson correlation coefficient (r). The r value of the LTP curve was 0.95246, and the r value of the LTD curve was -0.89486.

[0105] Example 6

[0106] The preparation method of the digital-analog integrated memristor has the following specific steps:

[0107] (1) Commercial P-type Si substrates were cleaned for 10 min under ultrasonic wave action using ethanol and deionized water in turn to remove oil and impurity particles on the surface of the P-type Si substrate. Subsequently, nitrogen was used to blow dry the substrate to ensure a clean and dry substrate.

[0108] (2) Prepare the first resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, the substrate heating temperature is 500 degrees, argon gas and oxygen with a volume flow rate of 20 ccm and 5 sccm are introduced, and under the conditions of a working pressure of 1.3 Pa and a RF power of 90 W, a tantalum pentoxide (Ta2O5) target is used for sputtering for 30 minutes to obtain a Ta2O5 film with a thickness of 32 nm.

[0109] (3) Prepare the second resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 20 sccm and 15 sccm respectively were introduced, and under the conditions of working pressure of 1.3 Pa and DC power of 80 W, a metal tungsten (W) target was used for sputtering for 8 min to obtain a WO3 film with a thickness of 130 nm.

[0110] (4) Prepare the top electrode layer, pass argon gas with a volume flow rate of 20 sccm for protection, and under the conditions of a working pressure of 1 Pa and a DC power of 50 W, modify the metal mask and use a metal silver (Ag) target for sputtering for 15 minutes to obtain an Ag dome electrode, completing the preparation of a tantalum oxide-tungsten oxide heterojunction memristor.

[0111] The LTP and LTD linearities of the digital-analog integrated memristor prepared by the preparation method described in Example 6 were quantified by the Pearson correlation coefficient (r). The r value of the LTP curve was 0.93267, and the r value of the LTD curve was -0.80125.

[0112] Example 7

[0113] The preparation method of the digital-analog integrated memristor has the following specific steps:

[0114] (1) Commercial P-type Si substrates were cleaned for 10 min under ultrasonic wave action using ethanol and deionized water in turn to remove oil and impurity particles on the surface of the P-type Si substrate. Subsequently, nitrogen was used to blow dry the substrate to ensure a clean and dry substrate.

[0115] (2) Prepare the first resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, the substrate heating temperature is 500 degrees, argon and oxygen with volume flow rates of 30 ccm and 5 sccm are introduced, and under the conditions of working pressure of 1.5 Pa and RF power of 90 W, tantalum pentoxide (Ta2O5) target is used for sputtering for 30 min to obtain Ta2O5 film, and the thickness of Ta2O5 film is 25 nm.

[0116] (3) Prepare the second resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 20 sccm and 8 sccm respectively were introduced, and under the conditions of working pressure of 1.2 Pa and DC power of 80 W, a metal tungsten (W) target was used for sputtering for 8 min to obtain a WO3 film with a thickness of 120 nm.

[0117] (4) Prepare the top electrode layer, pass argon gas with a volume flow rate of 20 sccm for protection, and under the conditions of a working pressure of 1 Pa and a DC power of 50 W, modify the metal mask and use a metal silver (Ag) target for sputtering for 15 minutes to obtain an Ag dome electrode, completing the preparation of a tantalum oxide-tungsten oxide heterojunction memristor.

[0118] The LTP and LTD linearities of the digital-analog integrated memristor prepared by the preparation method described in Example 7 were quantified by the Pearson correlation coefficient (r). The r value of the LTP curve was 0.95386, and the r value of the LTD curve was -0.89609.

[0119] Example 8

[0120] The preparation method of the digital-analog integrated memristor has the following specific steps:

[0121] (1) Commercial P-type Si substrates were cleaned for 10 min under ultrasonic wave with ethanol and deionized water respectively to remove oil and impurity particles on the surface of the P-type Si substrate. Subsequently, nitrogen was used to blow dry the substrate to ensure a clean and dry substrate layer.

[0122] (2) Prepare the first resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 30 ccm and 8 sccm were introduced, the substrate heating temperature was 500 degrees, and under the conditions of working pressure of 1.5 Pa and RF power of 90 W, tantalum pentoxide (Ta2O5) target was used for sputtering for 30 min to obtain Ta2O5 film with a thickness of 30 nm.

[0123] (3) Prepare the second resistive switching layer and evacuate the chamber to a pressure of 3×10 -3 Pa, argon and oxygen with volume flow rates of 20 sccm and 8 sccm respectively were introduced, and under the conditions of working pressure of 1.2 Pa and DC power of 80 W, a metal tungsten (W) target was used for sputtering for 8 min to obtain a WO3 film with a thickness of 120 nm.

[0124] (4) Prepare the top electrode layer, pass argon gas with a volume flow rate of 20 sccm for protection, and under the conditions of a working pressure of 1 Pa and a DC power of 50 W, modify the metal mask and use a metal silver (Ag) target for sputtering for 15 minutes to obtain an Ag dome electrode, completing the preparation of a tantalum oxide-tungsten oxide heterojunction memristor.

[0125] The LTP and LTD linearities of the digital-analog integrated memristor prepared by the preparation method described in Example 8 were quantified by the Pearson correlation coefficient (r). The r value of the LTP curve was 0.98472, and the r value of the LTD curve was -0.90368.

[0126] In a third aspect, based on the digital-analog integrated memristor, this embodiment provides a brain wave emotion recognition system based on the digital-analog integrated memristor.

[0127] Electroencephalogram (EEG) signals are helpful for identifying emotions, and compared with speech or facial expressions, they provide high accuracy for emotion recognition; traditional brain wave emotion recognition systems usually require high computing power and storage resources, which leads to high power consumption and system cost. Therefore, this embodiment provides a brain wave emotion recognition system based on a digital-analog integrated memristor. The memristor is a low-power, high-efficiency artificial synaptic device that can effectively reduce the demand for computing and storage, thereby reducing power consumption and system cost; the high linearity of LTP and LTD enables the memristor to show better linear response when adjusting weights; it can help the neural network to more accurately capture and extract emotional features in brain wave signals, thereby improving the accuracy of emotion recognition.

[0128] The brain wave emotion recognition system based on the digital-analog integrated memristor includes the digital-analog integrated memristor and a processor, on which a trained brain wave emotion recognition model is deployed; here, the analog characteristics of the digital-analog integrated memristor are applied.

[0129] Among them, the weight parameters of the brain wave emotion recognition model are updated according to the normalized conductance weight of the digital-analog integrated memristor. Specifically, it includes:

[0130] (1) Obtain the conductance values ​​of the digital-analog integrated memristor and normalize the obtained conductance values ​​to ensure that they are within a standardized range (e.g., between 0 and 1). The purpose of normalization is to make the conductance values ​​between different memristors comparable and consistent with the weight range of the neural network.

[0131] (2) Replace the normalized conductance value with the weight value in the neural network. This process synchronizes the memristor weights in the physical device with the weights of the neural network.

[0132] (3) When the neural network is trained or inferred, the replaced memristor weights are used for calculation. Normalization ensures the calculation accuracy and consistency of these weights, thereby improving the performance of the neural network.

[0133] The digital-analog integrated memristor used in this embodiment has high linearity LTP and LTD characteristics. High linearity means that the conductance changes consistently and predictably with the increase or decrease of voltage pulses. High linearity LTP and LTD means that when the weights are updated, the conductance of the memristor can accurately reflect the cumulative effect of the input pulses, ensuring that the changes in weights in the neural network are highly controllable and consistent.

[0134] Furthermore, the EEG emotion recognition model includes an input layer, a convolutional neural network, a long short-term memory network and a fully connected layer, which are connected in sequence.

[0135] Specifically, first, the model receives EEG data and extracts spatial features through CNN, including two convolutional layers and two maximum pooling layers. Then, the output of CNN enters the LSTM module to model the time series data and enhance the ability to capture time series information. Finally, the output of the LSTM module is classified through the fully connected layer to complete the EEG classification task. This model fully utilizes the advantages of CNN and LSTM to achieve effective feature extraction and classification in spatial features and time series information.

[0136] The spatial features extracted by CNN are combined with the time series modeling of LSTM to improve the recognition accuracy of complex emotional patterns.

[0137] In this embodiment, the DEEP dataset is selected for classification and recognition task training. The input of the network is preprocessed. The EEG data comes from a device with 4 frequency bands, each of which contains 32 features. Each 128-dimensional vector is divided into 4 sub-vectors, and each sub-vector is converted into a 9*9 matrix form and then input into the DEEP dataset for testing.

[0138] The description of each embodiment in the above embodiments has different emphases. For parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0139] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A digital-analog integrated memristor, characterized in that: It includes a substrate layer, a first resistive switching layer, a second resistive switching layer and a top electrode layer; The first resistive switching layer is disposed on the substrate layer, the second resistive switching layer is disposed on the first resistive switching layer, and the top electrode layer is disposed on the second resistive switching layer; The first resistive switching layer and the second resistive switching layer form a tantalum oxide-tungsten oxide heterojunction.

2. The digital-analog integrated memristor according to claim 1, characterized in that: The first resistive switching layer is a Ta2O5 thin film formed by sputtering a tantalum pentoxide target, and the second resistive switching layer is a WO3 thin film formed by sputtering a metal tungsten target.

3. A method for preparing a digital-analog integrated memristor, characterized in that: The steps include: providing a substrate layer; Using tantalum pentoxide to sputter on the substrate layer to form a first resistive layer; Using a metal tungsten target to sputter on the first resistive layer to form a second resistive layer; Using a metal silver target to sputter on the second resistive layer to form a top electrode layer; The first resistive switching layer and the second resistive switching layer form a tantalum oxide-tungsten oxide heterojunction.

4. The method for preparing a digital-analog integrated memristor according to claim 3, characterized in that: The method of using tantalum pentoxide to sputter on the substrate layer to form the first resistive layer is specifically as follows: the chamber is evacuated and argon and oxygen are introduced, and under the conditions of a working pressure of 1Pa to 2Pa and a radio frequency power of 80W to 100W, a tantalum pentoxide target is used for sputtering for 20min to 30min to obtain a Ta2O5 film.

5. The method for preparing a digital-analog integrated memristor according to claim 4, characterized in that: The volume flow rate of the argon gas is 20 ccm to 30 ccm, and the volume flow rate of the oxygen gas is 5 sccm to 8 sccm.

6. The method for preparing a digital-analog integrated memristor according to claim 3, characterized in that: The method of using a metal tungsten target to sputter on the first resistive layer to form the second resistive layer is specifically as follows: evacuating the chamber and introducing argon and oxygen, and under the conditions of a working pressure of 1Pa to 2Pa and a DC power of 80W to 100W, using a metal tungsten target to perform sputtering for 8min to 20min to obtain a WO3 film.

7. The method for preparing a digital-analog integrated memristor according to claim 6, characterized in that: The volume flow rate of the argon gas is 20 ccm to 30 ccm, and the volume flow rate of the oxygen gas is 5 sccm to 8 sccm.

8. The method for preparing a digital-analog integrated memristor according to claim 3, characterized in that: The method of using a metal silver target to sputter on the second resistive layer to form a top electrode layer is specifically as follows: evacuating the chamber and introducing argon gas, and under the conditions of a working pressure of 1Pa to 1.5Pa and a DC power of 45W to 55W, sputtering is performed using a metal silver target through a modified metal mask and continues for 12min to 17min.

9. The brain wave emotion recognition system based on digital-analog integrated memristor is characterized by: It includes a digital-analog integrated memristor and a processor, on which a trained brain wave emotion recognition model is deployed; Wherein, the weight parameters of the brain wave emotion recognition model are updated according to the normalized conductance weight of the digital-analog integrated memristor.

10. The brain wave emotion recognition system based on digital-analog integrated memristor according to claim 9, characterized in that: The brain wave emotion recognition model includes an input layer, a convolutional neural network, a long short-term memory network and a fully connected layer which are connected in sequence.

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