Through-type multilayer ceramic capacitor

Abstract

The invention provides a through-type multilayer ceramic capacitor which can avoid manufacturing defects caused by miniaturization of the through-type multilayer ceramic capacitor and can prevent a plurality of external electrodes arranged on a laminated body from being close to each other. A through-type multilayer ceramic capacitor according to the present invention is provided with: a laminated body including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the first main surface and the second main surface are opposite to each other in the stacking direction, the first side surface and the second side surface are opposite to each other in the width direction orthogonal to the stacking direction, and the first end surface and the second end surface are opposite to each other in the length direction orthogonal to the stacking direction and the width direction. A first internal electrode layer that is drawn out from among the plurality of internal electrode layers to the first end surface and the second end surface; a second internal electrode layer which is led out from among the plurality of internal electrode layers to the first side surface and the second side surface; a first external electrode disposed on the first end surface and connected to the first internal electrode layer; a second external electrode disposed on the second end surface and connected to the first internal electrode layer; a third external electrode disposed on the first side surface and connected to the second internal electrode layer; and a fourth external electrode disposed on the second side surface and connected to the second internal electrode layer, the first external electrode having: a first plating layer disposed on the first end surface; and a first band electrode disposed on the first end surface and disposed at a length shorter than the length of the first plating layer in the width direction, the second external electrode having: a second plating layer disposed on the second end surface, and a first band electrode disposed on the second end surface and disposed at a length shorter than the length of the first plating layer in the width direction; and a second band electrode disposed on the second end surface and disposed at a length shorter than the length of the second plating layer in the width direction, the third external electrode having: a third plating layer disposed on the first side surface; and a third band electrode disposed on the first side surface and disposed at a length shorter than the length of the third plating layer in the longitudinal direction, the fourth external electrode having: a fourth plating layer disposed on the second side surface, and a third band electrode disposed on the third side surface and disposed at a length shorter than the length of the third plating layer in the longitudinal direction; and a fourth band electrode disposed on the second side surface and having a length shorter than the length of the fourth plating layer in the longitudinal direction.

Description

Technical Field

[0001] The present invention relates to a through-type multilayer ceramic capacitor. Background Art

[0002] For example, a through-type multilayer ceramic capacitor having a structure as described in Patent Document 1 is known as a decoupling capacitor for stabilizing a power supply voltage supplied to an integrated circuit (IC) device operating at high speed or as a noise countermeasure component for a power supply line.

[0003] The through-type laminated ceramic capacitor described in Patent Document 1 has a general structure, and is provided with a ceramic substrate (laminate), which has an outer surface including a first main surface and a second main surface facing each other, a first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other. Inside the ceramic substrate, a plurality of first internal electrodes and second internal electrodes are alternately arranged in the stacking direction. Moreover, both ends of the first internal electrode are led out to the first end surface and the second end surface, and both ends of the second internal electrode are led out to the first side surface and the second side surface. Moreover, a first terminal electrode is provided at one end of the ceramic substrate and is connected to one end of the first internal electrode. In addition, a second terminal electrode is provided at the other end of the ceramic substrate and is connected to the other end of the first internal electrode. Furthermore, a third terminal electrode is provided in the middle portion of the ceramic substrate and is connected to the second internal electrode.

[0004] In recent years, the miniaturization of electronic devices such as mobile phones and portable music players has been progressing. Along with this, the miniaturization of ceramic electronic components mounted in the miniaturized electronic devices has also been progressing, and the demand for miniaturization of through-type multilayer ceramic capacitors such as those described in Patent Document 1 has also become stronger.

[0005] Prior Art Literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2000-58376 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] However, in the case of further miniaturization of the through-type multilayer ceramic capacitor as disclosed in Patent Document 1, not only the distance between the first terminal electrode and the third terminal electrode and the distance between the second terminal electrode and the third terminal electrode of the through-type multilayer ceramic capacitor are shortened, but also the control of coating of the internal electrode and the external electrode becomes difficult. As a result, short circuit failure and transition may occur.

[0010] Therefore, a main object of the present invention is to provide a through-type multilayer ceramic capacitor that can avoid manufacturing problems caused by downsizing of the through-type multilayer ceramic capacitor and can prevent a plurality of external electrodes arranged in a stacked body from being close to each other.

[0011] Technical solutions to solve problems

[0012] The through-type laminated ceramic capacitor according to the present invention is a through-type laminated ceramic capacitor, namely, comprising: a laminated body including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction; a first internal electrode layer led out to the first end surface and the second end surface among the plurality of internal electrode layers; a second internal electrode layer led out to the first side surface and the second side surface among the plurality of internal electrode layers; a first external electrode arranged on the first end surface and connected to the first internal electrode layer; a second external electrode arranged on the second end surface and connected to the first internal electrode layer; a third external electrode arranged on the first side surface and connected to the second internal electrode layer; The first external electrode comprises: a first plated layer arranged on the first end face; and a first strip electrode arranged on the first end face and arranged with a length shorter than the length in the width direction of the first plated layer; the second external electrode comprises: a second plated layer arranged on the second end face; and a second strip electrode arranged on the second end face and arranged with a length shorter than the length in the width direction of the second plated layer; the third external electrode comprises: a third plated layer arranged on the first side face; and a third strip electrode arranged on the first side face and arranged with a length shorter than the length in the length direction of the third plated layer; the fourth external electrode comprises: a fourth plated layer arranged on the second side face; and a fourth strip electrode arranged on the second side face and arranged with a length shorter than the length in the length direction of the fourth plated layer.

[0013] In the through-type multilayer ceramic capacitor according to the present invention, the first external electrode comprises: a first plating layer arranged on a first end surface; and a first strip electrode arranged on the first end surface and arranged with a length shorter than the length in the width direction of the first plating layer, the second external electrode comprises: a second plating layer arranged on the second end surface; and a second strip electrode arranged on the second end surface and arranged with a length shorter than the length in the width direction of the second plating layer, and the third external electrode comprises: a third plating layer arranged on a first side surface; and a third strip electrode arranged on the first side surface and arranged with a length shorter than the length in the width direction of the second plating layer. The fourth external electrode is arranged with a length shorter than the length of the third plating layer in the longitudinal direction, and includes: the fourth plating layer arranged on the second side surface; and the fourth strip electrode arranged on the second side surface and arranged with a length shorter than the length of the fourth plating layer in the longitudinal direction, so that the first external electrode and the second external electrode do not go around the first side surface and the second side surface, so that the distance between the first external electrode and the second external electrode and the third external electrode can be sufficiently ensured, and the distance between the first external electrode and the second external electrode and the fourth external electrode can be sufficiently ensured. Therefore, in the through-type multilayer ceramic capacitor, the occurrence of short circuit failure and transition can be suppressed.

[0014] Furthermore, in the through-type multilayer ceramic capacitor according to the present invention, since the first to fourth external electrodes have the above-mentioned structure, it is not necessary to narrow the width of the first internal electrode layer led to the first end face and the second end face and the width of the second internal electrode layer led to the first side face and the second side face. Thus, it is possible to maintain a state in which the width of the first lead electrode portion of the first internal electrode layer and the width of the second lead electrode portion are sufficiently ensured, and the width of the third lead electrode portion and the fourth lead electrode portion of the second internal electrode layer are sufficiently ensured, so that not only the control of printing at the coating surface of the internal electrode layer becomes easy, but also the deterioration of ESL (equivalent series resistance) and direct current resistance (Rdc) can be suppressed.

[0015] Effects of the Invention

[0016] According to the present invention, it is possible to provide a through-type multilayer ceramic capacitor which can avoid manufacturing problems caused by downsizing of the through-type multilayer ceramic capacitor and can avoid a plurality of external electrodes arranged in a laminated body from being close to each other.

[0017] The above-mentioned object, other objects, features and advantages of the present invention will become more apparent from the following description of the mode for carrying out the invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is an external perspective view showing an example of a feedthrough multilayer ceramic capacitor according to the first embodiment of the present invention.

[0019] Figure 2 It is a plan view showing an example of a feedthrough multilayer ceramic capacitor according to the first embodiment of the present invention.

[0020] Figure 3 It is a front view showing an example of a feedthrough multilayer ceramic capacitor according to the first embodiment of the present invention.

[0021] Figure 4 This is an external perspective view showing a state where a plating layer and strip electrodes are arranged on a laminated body of a through-type laminated ceramic capacitor according to the first embodiment of the present invention.

[0022] Figure 5 yes Figure 2 Cross-sectional view at line V-V.

[0023] Figure 6 yes Figure 2 Cross-sectional view at line VI-VI.

[0024] Figure 7 yes Figure 5 Cross-sectional view taken along line VII-VII.

[0025] Figure 8 yes Figure 5 Cross-sectional view at line VIII-VIII.

[0026] Fig. 9 It is an external perspective view showing an example of a feedthrough multilayer ceramic capacitor according to a second embodiment of the present invention.

[0027] Fig.10 This is an external perspective view showing a state where a plating layer and strip electrodes are arranged on a laminated body of a through-type laminated ceramic capacitor according to a second embodiment of the present invention.

[0028] Fig.11 yes Fig. 9 Cross-sectional view taken along line XI-XI.

[0029] Fig.12 yes Fig. 9 Cross-sectional view at line XII-XII.

[0030] Fig.13 yes Fig.11 Cross-sectional view at line XIII-XIII.

[0031] Fig.14 yes Fig.11 Cross-sectional view at line XIV-XIV. DETAILED DESCRIPTION

[0032] A. First Embodiment

[0033] 1. Through-type multilayer ceramic capacitors

[0034] A feedthrough multilayer ceramic capacitor according to a first embodiment of the present invention will be described.

[0035] Figure 1 It is an external perspective view showing an example of a feedthrough multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 2 It is a plan view showing an example of a feedthrough multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 3 It is a front view showing an example of a feedthrough multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 4 This is an external perspective view showing a state where a plating layer and strip electrodes are arranged on a laminated body of a through-type laminated ceramic capacitor according to the first embodiment of the present invention. Figure 5 yes Figure 2 Cross-sectional view at line V-V. Figure 6 yes Figure 2 Cross-sectional view at line VI-VI. Figure 7 yes Figure 5 Cross-sectional view taken along line VII-VII. Figure 8 yes Figure 5 Cross-sectional view at line VIII-VIII.

[0036] like Figure 1 As shown, the through-type multilayer ceramic capacitor 10 includes a laminated body 12 and external electrodes 30 .

[0037] (1) Laminated body

[0038] The laminate 12 includes a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 16 laminated on the dielectric layers 14. The dielectric layers 14 and the internal electrode layers 16 are laminated in a lamination direction x.

[0039] The stack 12 has a roughly rectangular parallelepiped shape. The stack 12 has the first main surface 12a and the second main surface 12b opposite to each other in the stacking direction x, the first side surface 12c and the second side surface 12d opposite to each other in the width direction y orthogonal to the stacking direction x, and the first end surface 12e and the second end surface 12f opposite to each other in the length direction z orthogonal to the stacking direction x and the width direction y. In addition, the dimension in the length direction z of the stack 12 is not necessarily longer than the dimension in the width direction y. In the stack 12, the corners and the ridges are rounded. In addition, the so-called corners are the parts where three adjacent faces of the stack intersect, and the so-called ridges are the parts where two adjacent faces of the stack intersect. In addition, it is also possible to form concave-convex portions on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0040] The laminate 12 has an inner layer portion 18 including a single or multiple dielectric layers 14 and multiple internal electrode layers 16 arranged thereon. The inner layer portion 18 includes the internal electrode layer 16 located closest to the first main surface 12a in the stacking direction x to the internal electrode layer 16 located closest to the second main surface 12b. The internal electrode layer 16 includes the first internal electrode layer 16a extending to the first end surface 12e and the second end surface 12f and the second internal electrode layer 16b extending to the first side surface 12c and the second side surface 12d. In the inner layer portion 18, the multiple first internal electrode layers 16a and the second internal electrode layers 16b are opposed to each other via the dielectric layer 14. The inner layer portion 18 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0041] The laminate 12 has a first principal surface side outer layer portion 20a, which is located on the first principal surface 12a side and is formed by a plurality of dielectric layers 14 located between the first principal surface 12a and the outermost surface of the inner layer portion 18 on the first principal surface 12a side and a straight line on the outermost surface.

[0042] Similarly, the stack 12 has a second main surface side outer layer portion 20b, which is located on the second main surface 12b side and is formed by a plurality of dielectric layers 14 located between the second main surface 12b and the outermost surface on the second main surface 12b side of the inner layer portion 18 and a straight line on the outermost surface.

[0043] Furthermore, the laminate 12 has a first side surface outer layer portion 22a located on the first side surface 12c side and formed of a plurality of dielectric layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0044] Similarly, the laminate 12 has a second side outer layer portion 22b located on the second side 12d side and formed of a plurality of dielectric layers 14 located between the second side 12d and the outermost surface of the inner layer portion 18 on the second side 12d side.

[0045] Furthermore, the laminate 12 has a first end surface side outer layer portion 24 a located on the first end surface 12 e side and formed of a plurality of dielectric layers 14 located between the first end surface 12 e and the outermost surface of the inner layer portion 18 on the first end surface 12 e side.

[0046] Similarly, the laminate 12 has a second end surface side outer layer portion 24b, which is located on the second end surface 12f side and is formed of a plurality of dielectric layers 14 located between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0047] The first main surface side outer layer portion 20a is located on the first main surface 12a side. The first main surface side outer layer portion 20a is an aggregate of a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The dielectric layer 14 used in the first main surface side outer layer portion 20a may be the same as the dielectric layer 14 used in the internal layer portion 18.

[0048] The second main surface side outer layer portion 20b is located on the second main surface 12b side. The second main surface side outer layer portion 20b is an aggregate of a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The dielectric layer 14 used in the second main surface side outer layer portion 20b may be the same as the dielectric layer 14 used in the internal layer portion 18.

[0049] The stacked body 12 has an opposing electrode portion 19. The opposing electrode portion 19 is a portion where a first opposing electrode portion 26a of a first internal electrode layer 16a described later and a second opposing electrode portion 26b of a second internal electrode layer 16b described later face each other. The opposing electrode portion 19 is configured as a part of the inner layer portion 18. In addition, the opposing electrode portion 19 is also referred to as a capacitor effective portion.

[0050] The first side surface outer layer portion 22 a is a portion including the dielectric layer 14 located between the counter electrode portion 19 and the first side surface 12 c .

[0051] The second side surface outer layer portion 22 b is a portion including the dielectric layer 14 located between the counter electrode portion 19 and the second side surface 12 d .

[0052] In addition, the first side surface outer layer portion 22a and the second side surface outer layer portion 22b are also referred to as W intervals or side intervals.

[0053] The first end surface side outer layer portion 24 a is a portion including the dielectric layer 14 located between the counter electrode portion 19 and the first end surface 12 e .

[0054] The second end surface side outer layer portion 24 b is a portion including the dielectric layer 14 located between the counter electrode portion 19 and the second end surface 12 f .

[0055] In addition, the first end surface side outer layer portion 24a and the second end surface side outer layer portion 24b are also referred to as an L interval or an end interval.

[0056] The size of the laminate 12 is not particularly limited.

[0057] The dielectric layer 14 can be formed of a dielectric material such as a ceramic material. As such a dielectric material, for example, a dielectric ceramic containing a component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. In the case of containing the above-mentioned dielectric material as a main component, a material to which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound whose content is less than that of the main component can be added, for example, according to the desired characteristics of the laminate 12.

[0058] The thickness of the dielectric layer 14 after firing is preferably 0.30 μm or more and 2.0 μm or less. The number of laminated dielectric layers 14 is preferably 15 or more and 1000 or less. The number of dielectric layers 14 is the sum of the number of dielectric layers 14 of the inner layer portion 18 and the number of dielectric layers 14 of the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b.

[0059] The laminate 12 includes a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are buried and alternately arranged at equal intervals with the dielectric layer 14 interposed therebetween along the lamination direction x of the laminate 12.

[0060] like Figure 7 As shown in the figure, the first internal electrode layer 16a includes a first opposing electrode portion 26a opposed to the second internal electrode layer 16b via the dielectric layer 14, a first lead electrode portion 28a led from the first opposing electrode portion 26a to the surface of the first end face 12e of the stacked body 12, and a second lead electrode portion 28b led from the first opposing electrode portion 26a to the surface of the second end face 12f of the stacked body 12. Specifically, the first lead electrode portion 28a is exposed on the surface of the first end face 12e of the stacked body 12, and the second lead electrode portion 28b is exposed on the surface of the second end face 12f of the stacked body 12. Therefore, the first internal electrode layer 16a is not exposed on the surfaces of the first side face 12c and the second side face 12d of the stacked body 12.

[0061] The shapes of the first opposing electrode portion 26a and the first and second lead-out electrode portions 28a and 28b are not particularly limited, but are preferably short rectangular shapes. However, the shapes of the first opposing electrode portion 26a and the first and second lead-out electrode portions 28a and 28b may also have rounded corners.

[0062] In addition, the length of the first lead electrode portion 28a and the second lead electrode portion 28b in the width direction y can be formed to be the same length as the length of the first opposing electrode portion 26a in the width direction y, or can be formed to be a length shorter than the length of the first opposing electrode portion 26a in the width direction y.

[0063] Furthermore, the first lead electrode portion 28a may have a tapered shape in which the length in the width direction y becomes narrower toward the first end face 12e, and the second lead electrode portion 28b may have a tapered shape in which the length in the length direction z becomes narrower toward the second end face 12f.

[0064] like Figure 8 As shown, the second internal electrode layer 16b is substantially cross-shaped and includes a second opposing electrode portion 26b opposed to the first internal electrode layer 16a via the dielectric layer 14, a third lead electrode portion 28c led from the second opposing electrode portion 26b to the surface of the first side surface 12c of the stacked body 12, and a fourth lead electrode portion 28d led from the second opposing electrode portion 26b to the surface of the second side surface 12d of the stacked body 12. Specifically, the third lead electrode portion 28c is exposed on the surface of the first side surface 12c of the stacked body 12, and the fourth lead electrode portion 28d is exposed on the surface of the second side surface 12d of the stacked body 12. Therefore, the second internal electrode layer 16b is not exposed on the surface of the first end surface 12e and the surface of the second end surface 12f of the stacked body 12.

[0065] The shapes of the second opposing electrode portion 26b and the third and fourth extraction electrode portions 28c and 28d are not particularly limited, but are preferably short rectangular shapes. However, the shapes of the second opposing electrode portion 26b and the third and fourth extraction electrode portions 28c and 28d may also have rounded corners.

[0066] Preferably, the relationship between the dimension A of the second opposing electrode portion 26b in the length direction z connecting the edge on the first end face 12e side and the edge on the second end face 12f side and the dimension B of the third lead-out electrode portion 28c and the fourth lead-out electrode portion 28d in the length direction z connecting the edge on the first end face 12e side and the edge on the second end face 12f side is A≥B.

[0067] Furthermore, the third lead electrode portion 28c may have a tapered shape in which the length in the longitudinal direction z becomes narrower toward the first side surface 12c, and the fourth lead electrode portion 28d may have a tapered shape in which the length in the longitudinal direction z becomes narrower toward the second side surface 12d.

[0068] The first internal electrode layer 16a and the second internal electrode layer 16b may be alternately stacked with the dielectric layer 14 interposed therebetween, or a plurality of dielectric layers 14 having the first internal electrode layer 16a may be stacked before stacking the dielectric layer 14 having the second internal electrode layer 16b. In this way, the stacking pattern of the internal electrode layer 16 can be changed according to the capacitance value to be achieved.

[0069] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0070] Sn may exist at the interface between the dielectric layer 14 and the internal electrode layer 16. When Sn exists at the interface between the dielectric layer 14 and the internal electrode layer 16, Sn may exist in a layered form parallel to the internal electrode layer 16, or may be dispersed. In addition, Sn may be dissolved in the internal electrode layer 16, or may exist in the dielectric layer 14.

[0071] Preferably, the total number of the first internal electrode layers 16 a and the second internal electrode layers 16 b is 15 or more and 500 or less.

[0072] The thickness of the first internal electrode layer 16a is preferably not less than 0.3 μm and not more than 1.0 μm.

[0073] The thickness of the second internal electrode layer 16 b is preferably not less than 0.3 μm and not more than 1.0 μm.

[0074] (2) External electrodes

[0075] External electrodes 30 are arranged on the first end face 12 e side and the second end face 12 f side and on the first side face 12 c side and the second side face 12 d side of the stacked body 12 .

[0076] The external electrode 30 includes a plating layer 32 and a strip electrode 34. In addition, the external electrode 30 includes an upper plating layer 36 so as to cover the plating layer 32 and the strip electrode 34. In addition, the external electrode 30 does not necessarily need to include the upper plating layer 36.

[0077] The external electrode 30 includes a first external electrode 30 a , a second external electrode 30 b , a third external electrode 30 c , and a fourth external electrode 30 d .

[0078] The first external electrode 30a is arranged on the first end surface 12e and connected to the first internal electrode layer 16a. The first external electrode 30a includes a first plated layer 32a and a first strip electrode 34a. The first plated layer 32a is arranged on the first end surface 12e. The first strip electrode 34a is arranged on the first end surface 12e and has a length shorter than the length of the first plated layer 32a in the width direction y. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a.

[0079] The second external electrode 30b is arranged on the second end face 12f and connected to the first internal electrode layer 16a. The second external electrode 30b includes a second plating layer 32b and a second strip electrode 34b. The second plating layer 32b is arranged on the second end face 12f. The second strip electrode 34b is arranged on the second end face 12f and has a length shorter than the length of the second plating layer 32b in the width direction y. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 28b of the first internal electrode layer 16a.

[0080] The third external electrode 30c is arranged on the first side surface 12c and connected to the second internal electrode layer 16b. The third external electrode 30c includes a third plated layer 32c and a third strip electrode 34c, wherein the third plated layer 32c is arranged on the first side surface 12c, and the third strip electrode 34c is arranged on the first side surface 12c and has a length shorter than the length of the third plated layer 32c in the longitudinal direction z. In this case, the third external electrode 30c is electrically connected to the third lead electrode portion 28c of the second internal electrode layer 16b.

[0081] The fourth external electrode 30d is arranged on the second side surface 12d and connected to the second internal electrode layer 16b. The fourth external electrode 30d includes a fourth plating layer 32d and a fourth strip electrode 34d. The fourth plating layer 32d is arranged on the second side surface 12d. The fourth strip electrode 34d is arranged on the second side surface 12d and has a length shorter than the length of the fourth plating layer 32d in the longitudinal direction z. In this case, the fourth external electrode 30d is electrically connected to the fourth lead electrode portion 28d of the second internal electrode layer 16b.

[0082] In the laminate 12, the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b are opposed to each other via the dielectric layer 14, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode layer 16a and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 16b, showing the characteristics of a capacitor.

[0083] The first plating layer 32a is arranged to cover the first internal electrode layer 16a, and the first strip electrode 34a is arranged on the first plating layer 32a and the surface of the first end face 12e.

[0084] The second plating layer 32b is arranged so as to cover the first internal electrode layer 16a, and the second strip electrode 34b is arranged on the second plating layer 32b and the surface of the second end face 12f.

[0085] The third plating layer 32c is arranged so as to cover the second internal electrode layer 16b, and the third strip electrode 34c is arranged on the third plating layer 32c and the surface of the first side surface 12c.

[0086] The fourth plating layer 32d is arranged so as to cover the second internal electrode layer 16b, and the fourth strip electrode 34d is arranged on the fourth plating layer 32d and the surface of the second side surface 12d.

[0087] like Figure 4 As shown, the plating layer 32 is arranged to cover the internal electrode layer 16 exposed on the surface of the laminate 12 .

[0088] The first plating layer 32a is arranged to cover the first internal electrode layer 16a that is led out to the first end face 12e and exposed. At this time, the first plating layer 32a directly covers the first lead electrode portion 28a of the first internal electrode layer 16a exposed at the first end face 12e. In addition, the first plating layer 32a is directly and continuously arranged on the dielectric layer 14 (that is, on the surface of the laminated body 12) located between the plurality of first internal electrode layers 16a exposed at the first end face 12e.

[0089] The second plating layer 32b is arranged to cover the first internal electrode layer 16a that is led out to the second end face 12f and exposed. At this time, the second plating layer 32b is directly covered on the second lead electrode portion 28b of the first internal electrode layer 16a exposed at the second end face 12f. In addition, the second plating layer 32b is directly and continuously arranged on the dielectric layer 14 (that is, on the surface of the laminate 12) located between the plurality of first internal electrode layers 16a exposed at the second end face 12f.

[0090] The third plating layer 32c is arranged to cover the second internal electrode layer 16b that is led out to the first side surface 12c and exposed. At this time, the third plating layer 32c directly covers the third lead-out electrode portion 28c of the second internal electrode layer 16b exposed on the first side surface 12c. In addition, the third plating layer 32c is directly and continuously arranged on the dielectric layer 14 (that is, on the surface of the laminated body 12) located between the plurality of second internal electrode layers 16b exposed on the first side surface 12c.

[0091] The fourth plating layer 32d is arranged to cover the second internal electrode layer 16b that is led out to the second side surface 12d and exposed. At this time, the fourth plating layer 32d directly covers the fourth lead electrode portion 28d of the second internal electrode layer 16b exposed on the second side surface 12d. In addition, the fourth plating layer 32d is directly and continuously arranged on the dielectric layer 14 (that is, on the surface of the laminated body 12) located between the plurality of second internal electrode layers 16b exposed on the second side surface 12d.

[0092] The plating layer 32 may include at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. Among them, the plating layer 32 is preferably a Cu plating layer. This can effectively prevent the plating solution and water from penetrating into the laminate 12.

[0093] In addition, the metal of the first internal electrode layer 16 a and the second internal electrode layer 16 b may be diffused into the first to fourth plating layers 32 a to 32 d .

[0094] The lengths of the first plating layer 32 a and the second plating layer 32 b in the width direction y are smaller than the length of the laminate 12 in the width direction y.

[0095] The lengths of the first plating layer 32 a and the second plating layer 32 b in the stacking direction x are smaller than the length of the stacked body 12 in the stacking direction x.

[0096] The lengths of the third plating layer 32 c and the fourth plating layer 32 d in the longitudinal direction z are smaller than the length of the laminated body 12 in the longitudinal direction z.

[0097] The lengths of the third plating layer 32 c and the fourth plating layer 32 d in the stacking direction x are smaller than the length of the stacked body 12 in the stacking direction x.

[0098] Thus, the first to fourth plating layers 32a to 32d can be arranged within the surfaces of the end faces 12e, 12f and the side faces 12c, 12d of the stack 12, so that the distance between the first external electrode 30a and the second external electrode 30b and the third external electrode 30c and the distance between the first external electrode 30a and the second external electrode 30b and the fourth external electrode 30d can be more fully ensured, and the occurrence of short circuit defects and transitions can be more effectively suppressed.

[0099] The first to fourth plating layers 32a to 32d may be formed in a plurality of layers.

[0100] The thickness of each of the first to fourth plating layers 32 a to 32 d is preferably 2 μm or more and 30 μm or less.

[0101] like Figure 4As shown, the tape electrode 34 is arranged on the surface of the plating layer 32 arranged on the surface of the laminate 12 .

[0102] The first strip electrode 34a is arranged on the surface of the first plating layer 32a arranged on the first end surface 12e. The length of the first strip electrode 34a in the width direction y is shorter than the length of the first plating layer 32a in the width direction y.

[0103] The second strip electrode 34b is arranged on the surface of the second plating layer 32b arranged on the second end surface 12f. The length of the second strip electrode 34b in the width direction y is shorter than the length of the second plating layer 32b in the width direction y.

[0104] The third strip electrode 34c is arranged on the surface of the third plating layer 32c arranged on the first side surface 12c. The length of the third strip electrode 34c in the longitudinal direction z is shorter than the length of the third plating layer 32c in the longitudinal direction z.

[0105] The fourth strip electrode 34d is arranged on the surface of the fourth plating layer 32d arranged on the second side surface 12d. The length of the fourth strip electrode 34d in the longitudinal direction y is shorter than the length of the fourth plating layer 32d in the longitudinal direction z.

[0106] It is preferable that the first to fourth strip electrodes 34 a to 34 d are respectively arranged to extend to a portion on the first main surface 12 a and a portion on the second main surface 12 b .

[0107] That is, the first strip electrode 34a is preferably extended from the first end surface 12e so as to be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0108] The second strip electrode 34b is preferably extended from the second end surface 12f so as to be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0109] The third strip electrode 34c is preferably extended from the first side surface 12c so as to be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0110] The fourth belt electrode 34d is preferably extended from the second side surface 12d so as to be disposed also on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0111] Thus, the through-type multilayer ceramic capacitor 10 can be easily and stably mounted on a mounting substrate.

[0112] Preferably, the length of the first and second strip electrodes 34 a and 34 b in the width direction y is 20% or more and 95% or less of the length of the first and second plating layers 32 a and 32 b in the width direction y.

[0113] In addition, preferably, the length of the third strip electrode 34c and the fourth strip electrode 34d in the longitudinal direction z is 10% or more and 95% or less of the length of the third plating layer 32c and the fourth plating layer 32d in the longitudinal direction z.

[0114] Thus, it is possible to sufficiently ensure the mountability of the through-type multilayer ceramic capacitor 10 on the mounting substrate.

[0115] Here, a method for measuring the lengths of the first and second plating layers 32a and 32b along the width direction y and the lengths of the third and fourth plating layers 32c and 32d along the longitudinal direction z will be described.

[0116] Regarding the method for measuring the length of the first plating layer 32a and the second plating layer 32b along the width direction y, and the method for measuring the length of the third plating layer 32c and the fourth plating layer 32d along the length direction z, first, grinding is performed until the position of 1 / 2T in the stacking direction x of the through-type multilayer ceramic capacitor 10 is reached so that it is approximately parallel to the first main surface 12a or the second main surface 12b, thereby exposing the LW surface as the grinding section.

[0117] Then, in the exposed LW surface as the polished section, the lengths of the first plating layer 32a and the second plating layer 32b along the width direction y, and the lengths of the third plating layer 32c and the fourth plating layer 32d along the length direction z are measured using a microscope, and the respective measurement results are used as the lengths of the first plating layer 32a and the second plating layer 32b along the width direction y, and the lengths of the third plating layer 32c and the fourth plating layer 32d along the length direction z.

[0118] Furthermore, a method for measuring the lengths of the first and second strip electrodes 34 a and 34 b along the width direction y and the lengths of the third and fourth strip electrodes 34 c and 34 d along the longitudinal direction z will be described.

[0119] Regarding the method for measuring the length of the first electrode 34a and the second electrode 34b along the width direction y, and the method for measuring the length of the third electrode 34c and the fourth electrode 34d along the length direction z, first, grinding is performed until the position of 1 / 2T in the stacking direction x of the through-type stacked ceramic capacitor 10 is reached so that it is approximately parallel to the first main surface 12a or the second main surface 12b, thereby exposing the LW surface as the grinding section.

[0120] Then, in the exposed LW surface which is a polished section, the lengths of the first electrode 34a and the second electrode 34b along the width direction y, and the lengths of the third electrode 34c and the fourth electrode 34d along the length direction z are measured using a microscope, and the respective measurement results are used as the lengths of the first electrode 34a and the second electrode 34b along the width direction y, and the lengths of the third electrode 34c and the fourth electrode 34d along the length direction z.

[0121] The belt electrode 34 includes at least one selected from a sintered layer, a conductive resin layer, a thin film layer, and the like.

[0122] Hereinafter, each structure in the case where the strip electrode 34 is formed as the above-mentioned sintered layer, conductive resin layer, and thin film layer will be described.

[0123] (Sintered layer)

[0124] In the present embodiment, the ribbon electrode 34 is a sintered layer.

[0125] The sintered layer contains a glass component and a metal component. The glass component of the sintered layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. As the metal component of the sintered layer, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. is contained. The sintered layer can also be a plurality of layers. The sintered layer is a layer in which a conductive paste containing a glass component and a metal component is applied to the stacked body 12 and sintered. The sintered layer can be a layer in which the stacked small pieces having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the stacked small pieces are sintered at the same time, or it can be a layer in which a conductive paste is applied to the stacked body 12 and sintered after the stacked small pieces having the internal electrode layer 16 and the dielectric layer 14 are sintered to obtain the stacked body 12. When the laminated sheets having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminated sheets are simultaneously fired, the sintered layer is preferably formed by firing a material to which a dielectric material is added instead of a glass component.

[0126] The sintered layer may also be formed of a plurality of layers.

[0127] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center portion in the stacking direction x of the first strip electrode 34a located on the first end face 12e is preferably about 3 μm or more and 70 μm or less, for example.

[0128] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center portion in the stacking direction x of the second electrode 34b located on the second end face 12f is preferably about 3 μm or more and 70 μm or less, for example.

[0129] The thickness of the first strip electrode 34a located on a portion of the first main surface 12a and the second main surface 12b in the central portion in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f in the stacking direction x connecting the first main surface 12a and the second main surface 12b is preferably, for example, greater than 3 μm and less than 40 μm.

[0130] In addition, the thickness of the second electrode 34b located on a portion of the first main surface 12a and the second main surface 12b in the stacking direction x connecting the first main surface 12a and the second end surface 12f at the central portion in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f is preferably greater than 3 μm and less than 40 μm.

[0131] The thickness of the first electrode 34a located on a portion of the first side surface 12c and the second side surface 12d in the width direction y connecting the first side surface 12c and the second side surface 12d at the center in the length direction z connecting the first end surface 12e and the second end surface 12f is preferably, for example, greater than 3 μm and less than 40 μm.

[0132] In addition, the thickness of the second electrode 34b located on a portion of the first side 12c and the second side 12d in the width direction y connecting the first side 12c and the second side 12d at the center in the length direction z connecting the first end face 12e and the second end face 12f is preferably greater than 3 μm and less than 40 μm.

[0133] (Conductive resin layer)

[0134] When a conductive resin layer is provided as the strip electrode 34 , the conductive resin layer may be disposed on the sintered layer so as to cover the sintered layer, or may be directly disposed on the plating layer 32 and the laminated body 12 .

[0135] The conductive resin layer contains metal and thermosetting resin.

[0136] The conductive resin layer contains a thermosetting resin and is therefore more flexible than a conductive layer composed of, for example, a plated film or a sintered product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the through-type multilayer ceramic capacitor 10, the conductive resin layer functions as a buffer layer and can prevent cracks from being generated in the through-type multilayer ceramic capacitor 10.

[0137] As the metal contained in the conductive resin layer, Ag, Cu, Ni, Sn, Bi, or an alloy containing these can be used.

[0138] In addition, metal powder coated with Ag on the surface of the metal powder can also be used. When using metal powder coated with Ag on the surface of the metal powder, it is preferred to use Cu, Ni, Sn, Bi or alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest specific resistance among metals and is therefore suitable as an electrode material, and Ag is a precious metal and therefore does not oxidize and has high weather resistance. In addition, it is also because the metal of the base material can be made cheap while maintaining the above-mentioned characteristics of Ag.

[0139] Furthermore, as the metal contained in the conductive resin layer, metal obtained by subjecting Cu and Ni to an oxidation-proof treatment can be used.

[0140] In addition, as the metal contained in the conductive resin layer, metal powder coated with Sn, Ni, or Cu on the surface of the metal powder can also be used. When using metal powder coated with Sn, Ni, or Cu on the surface of the metal powder, Ag, Cu, Ni, Sn, Bi, or alloy powder thereof is preferably used as the metal powder.

[0141] The metal contained in the conductive resin layer mainly bears the electrical conductivity of the conductive resin layer. Specifically, the conductive fillers are in contact with each other, thereby forming an electrical path inside the conductive resin layer.

[0142] The metal contained in the conductive resin layer may be a spherical metal, a flat metal, or the like. It is preferred that a spherical metal powder and a flat metal powder be mixed for use.

[0143] As the resin of the conductive resin layer, various known thermosetting resins can be used, such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0144] In addition, the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as a base resin, various known compounds such as phenols, amines, acid anhydrides, imidazoles, active esters, and amide-imides can be used as the curing agent for the epoxy resin.

[0145] The conductive resin layer may be a plurality of layers.

[0146] The thickness of the conductive resin layer located at the first end surface 12 e and the second end surface 12 f and located at the center of the stacking direction x of the stacked body 12 is preferably about 10 μm or more and 150 μm or less, for example.

[0147] (Thin film layer)

[0148] When the strip electrode 34 is formed of a thin film layer, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in which metal particles are deposited.

[0149] The external electrode 30 preferably includes an upper plating layer 36 .

[0150] The upper plating layer 36 includes first to fourth upper plating layers 36a to 36d.

[0151] The first upper plating layer 36a is arranged on the first end surface 12e side so as to cover the first plating layer 32a and the first strip electrode 34a.

[0152] The second upper plating layer 36b is arranged on the second end surface 12f side so as to cover the second plating layer 32b and the second strip electrode 34b.

[0153] The third upper plating layer 36c is arranged on the first side surface 12c side so as to cover the third plating layer 32c and the third strip electrode 34c.

[0154] The fourth upper plating layer 36d is arranged on the second side surface 12d side so as to cover the fourth plating layer 32d and the fourth strip electrode 34d.

[0155] Each of the upper plating layers 36 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0156] The upper plating layer 36 may also be formed of a plurality of layers.

[0157] Preferably, the upper plating layer 36 is preferably a two-layer structure of a Ni plating layer and a Sn plating layer. The Ni plating layer can prevent the strip electrode 34 from being corroded by the solder when the through-type multilayer ceramic capacitor 10 is mounted, and the Sn plating layer can improve the wettability of the solder when the through-type multilayer ceramic capacitor 10 is mounted, and the through-type multilayer ceramic capacitor 10 can be easily mounted on the mounting substrate. In this way, by forming the upper plating layer 36 with multiple layers, the reliability and mounting performance of the through-type multilayer ceramic capacitor 10 can be further improved efficiently.

[0158] The thickness of each upper plating layer 36 is preferably 2 μm or more and 15 μm or less.

[0159] The dimension of the through-type multilayer ceramic capacitor 10 including the stack 12 and the first to fourth external electrodes 30a to 30d in the length direction z is set to L dimension, the dimension of the through-type multilayer ceramic capacitor 10 including the stack 12 and the first to fourth external electrodes 30a to 30d in the stacking direction x is set to T dimension, and the dimension of the through-type multilayer ceramic capacitor 10 including the stack 12 and the first to fourth external electrodes 30a to 30d in the width direction y is set to W dimension.

[0160] The dimensions of the through-type laminated ceramic capacitor 10 are not particularly limited, but the L dimension in the length direction z is 0.4 mm or more and 2.0 mm or less, the W dimension in the width direction y is 0.2 mm or more and 1.25 mm or less, and the T dimension in the stacking direction x is 0.1 mm or more and 2.0 mm or less. In addition, the dimensions of the through-type laminated ceramic capacitor 10 can be measured using a microscope.

[0161] exist Figure 1 In the through-type multilayer ceramic capacitor 10 shown in FIG. 1 , the first external electrode 30a comprises: a first plating layer 32a, which is arranged on the first end face 12e; and a first strip electrode 34a, which is arranged on the first end face 12e and is arranged with a length shorter than the length of the first plating layer 32a in the width direction y. The second external electrode 30b comprises: a second plating layer 32b, which is arranged on the second end face 12f; and a second strip electrode 34b, which is arranged on the second end face 12f and is arranged with a length shorter than the length of the second plating layer 32b in the width direction y. The third external electrode 30c comprises: a third plating layer 32c, which is arranged on the first side face 12c; and a third strip electrode 34c, which is arranged on the first side face 12c and is arranged with The fourth external electrode 30d is configured with a length shorter than the length of the third plating layer 32c in the length direction z. The fourth external electrode 30d includes: the fourth plating layer 32d, which is arranged on the second side surface 12d; and the fourth strip electrode 34d, which is arranged on the second side surface 12d and is configured with a length shorter than the length of the fourth plating layer 32d in the length direction z. Therefore, the first external electrode 30a and the second external electrode 30b do not go around the first side surface 12c and the second side surface 12d, so that the distance between the first external electrode 30a and the second external electrode 30b and the third external electrode 30c can be sufficiently ensured, and the distance between the first external electrode 30a and the second external electrode 30b and the fourth external electrode 30d can be sufficiently ensured. Therefore, in the through-type multilayer ceramic capacitor 10, the occurrence of short circuit failure and transition can be suppressed.

[0162] In addition, Figure 1In the through-type multilayer ceramic capacitor 10 shown, the first external electrodes 30a to the fourth external electrodes 30d have the above-mentioned structure, so it is not necessary to narrow the width of the first internal electrode layer 16a led to the first end face 12e and the second end face 12f and the width of the second internal electrode layer 16b led to the first side face 12c and the second side face 12d. As a result, it is possible to maintain a state in which the width of the first lead electrode portion 28a and the width of the second lead electrode portion 28b of the first internal electrode layer 16a are sufficiently ensured, and the width of the third lead electrode portion 28c and the fourth lead electrode portion 28d of the second internal electrode layer 16b are sufficiently ensured, so that not only the control of printing on the coating surface of the internal electrode layer 16 becomes easy, but also the deterioration of ESL (equivalent series resistance) and direct current resistance (Rdc) can be suppressed.

[0163] 2. Method for manufacturing a feedthrough multilayer ceramic capacitor

[0164] Next, a method for manufacturing the through-type multilayer ceramic capacitor according to the first embodiment will be described.

[0165] First, a dielectric sheet for a dielectric layer and a conductive paste for an internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0166] Then, a conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer and a dielectric sheet having a pattern of the second internal electrode layer are prepared.

[0167] More specifically, a screen plate for printing the pattern of the first internal electrode layer and a screen plate for printing the pattern of the second internal electrode layer can be prepared separately, and the internal electrode layer of the present invention can be printed using a printer capable of printing on the two screen plates separately. Here, the sheets printed with the pattern of the first internal electrode layer and the pattern of the second internal electrode layer are stacked so as to obtain a desired structure, thereby manufacturing the portion to be the inner layer.

[0168] Next, a predetermined number of dielectric sheets for outer layers on which the pattern of the internal electrode layer is not printed are stacked, thereby forming a portion that becomes the outer layer portion on the second main surface side. Then, the portion that becomes the inner layer portion manufactured by the above method is stacked on the portion that becomes the outer layer portion on the second main surface side manufactured by the above method. Then, a predetermined number of dielectric sheets for outer layers on which the pattern of the internal electrode layer is not printed are stacked on the portion that becomes the inner layer portion, thereby forming a portion that becomes the outer layer portion on the first main surface side. Thus, a laminated sheet is manufactured.

[0169] Next, the laminated sheets are pressed in the laminating direction by isostatic pressing or the like, thereby producing a laminated block.

[0170] Then, the stacked block is cut into a given size to cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0171] Next, the stacked small pieces are fired to produce the stacked body 12. The firing temperature depends on the materials of the dielectric layer and the internal electrode layer, but is preferably 900°C or higher and 1400°C or lower.

[0172] Next, the plating layer 32 is formed on the laminated body 12 obtained by firing.

[0173] Specifically, the first plating layer 32a is formed on the first end face 12e of the laminate 12, the second plating layer 32b is formed on the second end face 12f, the third plating layer 32c is formed on the first side face 12c, and the fourth plating layer 32d is formed on the second side face 12d. Figure 1 In the through-type multilayer ceramic capacitor 10 shown, the first to fourth plating layers 32a to 32d are formed of Cu plating layers.

[0174] As a specific method for forming the first to fourth plating layers 32 a to 32 d , the method described below can be used.

[0175] That is, the first internal electrode layer 16a exposed on the first end face 12e and the second end face 12f of the laminate 12 is plated to form the first plated layer 32a and the second plated layer 32b. Similarly, the second internal electrode layer 16b exposed on the first side face 12c and the second side face 12d of the laminate 12 is plated to form the third plated layer 32c and the fourth plated layer 32d. When performing the plating process, either electrolytic plating or electroless plating can be used, but electroless plating has the following disadvantages, that is, in order to increase the deposition speed of the plating layer, pretreatment with a catalyst or the like is required, and the process becomes complicated. Therefore, electrolytic plating is usually preferably used.

[0176] Next, the strip electrode 34 is formed on the plated layer 32 .

[0177] Specifically, a first electrode 34a is formed on the first plating layer 32a and on the first end face 12e of the stack 12, a second electrode 34b is formed on the second plating layer 32b and on the second end face 12f of the stack 12, a third plating layer 32c is formed on the third plating layer 32c and on the first side face 12c of the stack 12, and a fourth plating layer 32d is formed on the fourth plating layer 32d and on the second side face 12d of the stack 12.

[0178] (In the case of a sintered layer)

[0179] When the first to fourth strip electrodes 34a to 34d are formed by sintered layers, a conductive paste containing a glass component and a metal component is applied to the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d, and then sintered to form sintered layers as the strip electrodes 34. The sintering temperature at this time is preferably 700°C or higher and 900°C or lower. Figure 1 In the through-type multilayer ceramic capacitor 10 shown, the strip electrode 34 is formed of a sintered layer.

[0180] Here, various methods can be used as a method of forming the tape electrode 34 from a sintered layer.

[0181] For example, as a method of forming the strip electrode 34 by the sintered layer, a process method of extruding the conductive paste from the slit and applying it can be used. In the case of this process method, by increasing the amount of the conductive paste extruded, the first strip electrode 34a and the second strip electrode 34b can be formed not only on the first end surface 12e and the second end surface 12f, but also on a part of the first main surface 12a and a part of the second main surface 12b, and the third strip electrode 34c and the fourth strip electrode 34d can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0182] In addition, in the process of pressing the conductive paste out from the slit and applying it, by controlling the width of the slit, it is possible to form the first strip electrode 34a arranged with a length shorter than the length of the first plating layer 32a in the width direction y, and the second strip electrode 34b arranged with a length shorter than the length of the second plating layer 32b in the width direction y. Similarly, by controlling the width of the slit, it is possible to form the third strip electrode 34c arranged with a length shorter than the length of the third plating layer 32c in the length direction z, and the fourth strip electrode 34d arranged with a length shorter than the length of the fourth plating layer 32d in the length direction z.

[0183] As a method of forming the strip electrode 34 from a sintered layer, a roll transfer method can also be used. In the case of the roll transfer method, when the first strip electrode 34a and the second strip electrode 34b are formed not only on the first end surface 12e and the second end surface 12f, but also on a part of the first main surface 12a and a part of the second main surface 12b, the first strip electrode 34a and the second strip electrode 34b can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roll transfer. Furthermore, in the case of the roller transfer method, when the third electrode 34c and the fourth electrode 34d are formed not only on the first side surface 12c and the second side surface 12d, but also on a portion of the first main surface 12a and a portion of the second main surface 12b, the pressing pressure during the roller transfer is increased, thereby enabling the third electrode 34c and the fourth electrode 34d to be formed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0184] In addition, in the roller transfer method, by controlling the width of the groove of the roller, it is possible to form the first strip electrode 34a arranged with a length shorter than the length of the first plating layer 32a in the width direction y, and the second strip electrode 34b arranged with a length shorter than the length of the second plating layer 32b in the width direction y. Similarly, by controlling the width of the groove of the roller, it is possible to form the third strip electrode 34c arranged with a length shorter than the length of the third plating layer 32c in the length direction z, and the fourth strip electrode 34d arranged with a length shorter than the length of the fourth plating layer 32d in the length direction z.

[0185] Then, a sintering process is performed to form a sintered layer as the ribbon electrode 34. The temperature of the sintering process at this time is preferably 700°C or more and 900°C or less.

[0186] (Conductive resin layer)

[0187] When the strip electrode 34 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed directly on the plating layer 32 or on the surface of a formed sintered layer.

[0188] As a method for forming a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the plating layer 32 or the strip electrode 34 arranged on the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d, and heat-treated at a temperature of 250°C to 550°C to thermally cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, it is preferable to suppress the oxygen concentration to 100 ppm or less.

[0189] As a method for applying the conductive resin paste, similar to the method of forming the band electrode 34 from a sintered layer, for example, a process method of applying the conductive resin paste by squeezing it out from a slit or a roll transfer method can be used.

[0190] (Thin film layer)

[0191] When the strip electrode 34 is formed of a thin film layer, masking can be performed to form the strip electrode by a thin film forming method such as sputtering or evaporation at the location where the external electrode 30 is to be formed. The strip electrode 34 formed of a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0192] Next, upper plating layer 36 is formed on the surface of plating layer 32 and the surface of electrode strip 34 as needed. In addition, upper plating layer 36 may be arranged not only on the surface of plating layer 32 and the surface of electrode strip 34 but also on the surface of laminate 12.

[0193] In the present embodiment, a Ni plating layer and a Sn plating layer are formed on the upper plating layer 36. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, a drum plating method. When performing the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating has the following disadvantages, that is, in order to increase the deposition speed of the plating layer, it is necessary to perform pretreatment using a catalyst, etc., and the process becomes complicated. Therefore, electrolytic plating is usually preferably used.

[0194] The through-type multilayer ceramic capacitor 10 according to the present embodiment is manufactured as described above.

[0195] B. Second Embodiment

[0196] 1. Through-type multilayer ceramic capacitors

[0197] A feedthrough multilayer ceramic capacitor according to a second embodiment of the present invention will be described.

[0198] Fig. 9It is an external perspective view showing an example of a feedthrough multilayer ceramic capacitor according to a second embodiment of the present invention. Fig.10 This is an external perspective view showing a state where a plating layer and strip electrodes are arranged on a laminated body of a through-type laminated ceramic capacitor according to a second embodiment of the present invention. Fig.11 yes Fig. 9 Cross-sectional view taken along line XI-XI. Fig.12 yes Fig. 9 Cross-sectional view at line XII-XII. Fig.13 yes Fig.11 Cross-sectional view at line XIII-XIII. Fig.14 yes Fig.11 A cross-sectional view of the line XIV-XIV. Figures 9 to 14 In the through-type multilayer ceramic capacitor 110 shown in FIG. Figures 1 to 8 The same parts as those of the feedthrough multilayer ceramic capacitor 10 are denoted by the same reference numerals, and their description is omitted. The feedthrough multilayer ceramic capacitor 110 according to the second embodiment is different from the feedthrough multilayer ceramic capacitor 10 according to the first embodiment in the structure of the external electrodes.

[0199] like Figures 9 to 14 As shown, the through-type multilayer ceramic capacitor 110 includes, for example, a laminated body 12 and an external electrode 130 .

[0200] (1) Laminated body

[0201] The laminate 12 includes a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 16 .

[0202] The material of the dielectric layer 14 in the through-type multilayer ceramic capacitor 110 is the same as that of the through-type multilayer ceramic capacitor 10 , and thus the description thereof is omitted.

[0203] The thickness of the dielectric layer 14 after firing is also the same as that of the feedthrough multilayer ceramic capacitor 10 , and therefore the description thereof will be omitted.

[0204] The laminate 12 includes a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are buried and alternately arranged at equal intervals with the dielectric layer 14 interposed therebetween along the lamination direction x of the laminate 12.

[0205] like Fig.13As shown, the first internal electrode layer 16a includes a first opposing electrode portion 26a opposing to the second internal electrode layer 16b via the dielectric layer 14, a first lead electrode portion 28a extending from the first opposing electrode portion 26a to the surface of the first end face 12e of the stack 12, and a second lead electrode portion 28b extending from the first opposing electrode portion 26a to the surface of the second end face 12f of the stack 12.

[0206] like Fig.14 As shown, the second internal electrode layer 16b is roughly cross-shaped and includes a second opposing electrode portion 26b opposite to the first internal electrode layer 16a via the dielectric layer 14, a third lead electrode portion 28c led from the second opposing electrode portion 26b to the surface of the first side surface 12c of the stack 12, and a fourth lead electrode portion 28d led from the second opposing electrode portion 26b to the surface of the second side surface 12d of the stack 12.

[0207] (2) External electrodes

[0208] External electrodes 130 are arranged on the first end face 12 e side, the second end face 12 f side, the first side face 12 c side, and the second side face 12 d side of the stacked body 12 .

[0209] The external electrode 130 includes a plating layer 32 and a strip electrode 34. The plating layer 32 is arranged to cover the strip electrode 34. In addition, the external electrode 130 includes an upper plating layer 36 so as to cover the plating layer 32. In addition, the upper plating layer 36 is not necessarily included in the external electrode 130.

[0210] The external electrode 130 includes a first external electrode 130 a , a second external electrode 130 b , a third external electrode 130 c , and a fourth external electrode 130 d .

[0211] The first external electrode 130a is arranged on the first end surface 12e and connected to the first internal electrode layer 16a. The first external electrode 130a is arranged to cover the first internal electrode layer 16a, and includes: a first strip electrode 34a arranged on the first end surface 12e; and a first plating layer 32a arranged on the first end surface 12e and arranged on the first strip electrode 34a and the first internal electrode layer 16a. In this case, the first external electrode 130a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a. The length of the first strip electrode 34a in the width direction y is smaller than the length of the first plating layer 32a in the width direction y.

[0212] The second external electrode 130b is arranged on the second end surface 12f and connected to the first internal electrode layer 16a. The second external electrode 130b is arranged to cover the first internal electrode layer 16a, and includes: a second strip electrode 34b arranged on the second end surface 12f; and a second plating layer 32b arranged on the second end surface 12f, and arranged on the second strip electrode 34b and the first internal electrode layer 16a. In this case, the second external electrode 130b is electrically connected to the second lead electrode portion 28b of the first internal electrode layer 16a. The length of the second strip electrode 34b in the width direction y is smaller than the length of the second plating layer 32b in the width direction y.

[0213] The third external electrode 130c is arranged on the first side surface 12c and connected to the second internal electrode layer 16b. The third external electrode 130c is arranged to cover the second internal electrode layer 16b, and includes: a third strip electrode 34c arranged on the first side surface 12c; and a third plating layer 32c arranged on the first side surface 12c and arranged on the third strip electrode 34c and the second internal electrode layer 16b. In this case, the third external electrode 130c is electrically connected to the third lead electrode portion 28c of the second internal electrode layer 16b. The length of the third strip electrode 34c in the longitudinal direction z is smaller than the length of the third plating layer 32c in the longitudinal direction z.

[0214] The fourth external electrode 130d is arranged on the second side surface 12d and connected to the second internal electrode layer 16b. The fourth external electrode 130d is arranged to cover the second internal electrode layer 16b, and includes: a fourth strip electrode 34d arranged on the second side surface 12d; and a fourth plating layer 32d arranged on the second side surface 12d and arranged on the fourth strip electrode 34d and the second internal electrode layer 16b. In this case, the fourth external electrode 130d is electrically connected to the fourth lead electrode portion 28d of the second internal electrode layer 16b. The length of the fourth strip electrode 34d in the longitudinal direction z is smaller than the length of the fourth plating layer 32d in the longitudinal direction z.

[0215] In the laminate 12, the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b are opposed to each other via the dielectric layer 14, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 130a and the second external electrode 130b connected to the first internal electrode layer 16a and the third external electrode 130c and the fourth external electrode 130d connected to the second internal electrode layer 16b, showing the characteristics of a capacitor.

[0216] like Fig.10 As shown, the tape electrode 34 is arranged to cover the internal electrode layer 16 exposed on the surface of the stacked body 12 .

[0217] The first strip electrode 34 a is arranged to cover the first internal electrode layer 16 a that is drawn out to the first end surface 12 e and exposed.

[0218] The second strip electrode 34b is arranged to cover the first internal electrode layer 16a which is drawn out to the second end face 12f and exposed.

[0219] The third strip electrode 34c is arranged to cover the second internal electrode layer 16b that is drawn out to the first side surface 12c and exposed.

[0220] The fourth strip electrode 34d is arranged to cover the second internal electrode layer 16b that is drawn out to the second side surface 12d and exposed.

[0221] like Fig.10 As shown, the plating layer 32 is arranged to cover the internal electrode layer 16 and the strip electrode 34 exposed on the surface of the laminate 12 .

[0222] The first plating layer 32a is arranged on the first end surface 12e side so as to cover the first strip electrode 34a and the first internal electrode layer 16a drawn out to the first end surface 12e and exposed.

[0223] The second plating layer 32b is arranged on the second end face 12f side so as to cover the second strip electrode 34b and the first internal electrode layer 16a drawn out to the second end face 12f and exposed.

[0224] The third plating layer 32c is arranged on the first side surface 12c side so as to cover the third strip electrode 34c and the second internal electrode layer 16b drawn out to the first side surface 12c and exposed.

[0225] The fourth plating layer 32d is arranged on the second side surface 12d side so as to cover the fourth strip electrode 34d and the second internal electrode layer 16b drawn out to the second side surface 12d and exposed.

[0226] Thus, the first electrode 34a, the second electrode 34b, the third electrode 34c and the fourth electrode 34d are pre-arranged on the surface of the stack 12, so that the portion that becomes the starting point of the growth of the plating when forming the first plating layer 32a to the fourth plating layer 32d can be ensured in advance, so the first plating layer 32a to the fourth plating layer 32d can be formed in a short time.

[0227] The lengths of the first plating layer 32 a and the second plating layer 32 b in the width direction y are smaller than the length of the laminate 12 in the width direction y.

[0228] The lengths of the first plating layer 32 a and the second plating layer 32 b in the stacking direction x are smaller than the length of the stacked body 12 in the stacking direction x.

[0229] The lengths of the third plating layer 32 c and the fourth plating layer 32 d in the longitudinal direction z are smaller than the length of the laminated body 12 in the longitudinal direction z.

[0230] The lengths of the third plating layer 32 c and the fourth plating layer 32 d in the stacking direction x are smaller than the length of the stacked body 12 in the stacking direction x.

[0231] The external electrode 130 preferably includes an upper plating layer 36 .

[0232] The upper plating layer 36 includes first to fourth upper plating layers 36a to 36d.

[0233] The first upper plating layer 36a is arranged on the first end surface 12e side so as to cover the first plating layer 32a.

[0234] The second upper plating layer 36b is arranged on the second end surface 12f side so as to cover the second plating layer 32b.

[0235] The third upper plating layer 36c is arranged on the first side surface 12c side so as to cover the third plating layer 32c.

[0236] The fourth upper plating layer 36d is arranged on the second side surface 12d side so as to cover the fourth plating layer 32d.

[0237] In addition, the materials of the plated layer 32 , the strip electrode 34 , and the upper plated layer 36 in the through-type multilayer ceramic capacitor 110 are the same as those of the through-type multilayer ceramic capacitor 10 , and thus the description thereof is omitted.

[0238] In this Fig. 9 The through-type multilayer ceramic capacitor 110 shown in the figure can achieve the same effects as those of the through-type multilayer ceramic capacitor 10 described above.

[0239] 2. Method for manufacturing a feedthrough multilayer ceramic capacitor

[0240] Next, a method for manufacturing the through-type multilayer ceramic capacitor according to the second embodiment will be described.

[0241] First, a dielectric sheet for a dielectric layer and a conductive paste for an internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0242] Then, a conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer and a dielectric sheet having a pattern of the second internal electrode layer are prepared.

[0243] More specifically, a screen plate for printing the pattern of the first internal electrode layer and a screen plate for printing the pattern of the second internal electrode layer can be prepared separately, and the internal electrode layer of the present invention can be printed using a printer capable of printing on the two screen plates separately. Here, the sheets printed with the pattern of the first internal electrode layer and the pattern of the second internal electrode layer are stacked so as to obtain a desired structure, thereby manufacturing the portion to be the inner layer.

[0244] Next, a predetermined number of dielectric sheets for outer layers on which the pattern of the internal electrode layer is not printed are stacked, thereby forming a portion that becomes the outer layer portion on the second main surface side. Then, the portion that becomes the inner layer portion manufactured by the above method is stacked on the portion that becomes the outer layer portion on the second main surface side manufactured by the above method. Then, a predetermined number of dielectric sheets for outer layers on which the pattern of the internal electrode layer is not printed are stacked on the portion that becomes the inner layer portion, thereby forming a portion that becomes the outer layer portion on the first main surface side. Thus, a laminated sheet is manufactured.

[0245] Next, the laminated sheets are pressed in the laminating direction by isostatic pressing or the like, thereby producing a laminated block.

[0246] Then, the stacked block is cut into a given size to cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0247] Next, the stacked small pieces are fired to produce the stacked body 12. The firing temperature depends on the materials of the dielectric layer and the internal electrode layer, but is preferably 900°C or higher and 1400°C or lower.

[0248] Next, the strip electrodes 34 constituting the external electrodes 130 are formed on the fired laminated body 12 .

[0249] Specifically, a first electrode 34a is formed on the first end face 12e of the stack 12, a second electrode 34b is formed on the second end face 12f of the stack 12, a third plating layer 32c is formed on the first side face 12c of the stack 12, and a fourth plating layer 32d is formed on the second side face 12d of the stack 12.

[0250] (In the case of a sintered layer)

[0251] When the first to fourth strip electrodes 34a to 34d are formed by sintered layers, a conductive paste containing a glass component and a metal component is applied to the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d, and then sintered to form sintered layers as the strip electrodes 34. The sintering temperature at this time is preferably 700°C or higher and 900°C or lower. Fig. 9 In the through-type multilayer ceramic capacitor 110 shown, the strip electrode 34 is formed of a sintered layer.

[0252] Here, various methods can be used as a method of forming the tape electrode 34 from a sintered layer.

[0253] For example, as a method of forming the strip electrode 34 by the sintered layer, a process method of extruding the conductive paste from the slit and applying it can be used. In the case of this process method, by increasing the amount of the conductive paste extruded, the first strip electrode 34a and the second strip electrode 34b can be formed not only on the first end surface 12e and the second end surface 12f, but also on a part of the first main surface 12a and a part of the second main surface 12b, and the third strip electrode 34c and the fourth strip electrode 34d can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0254] In addition, in the process of pressing the conductive paste out from the slit and applying it, by controlling the width of the slit, it is possible to form the first strip electrode 34a arranged with a length shorter than the length of the first plating layer 32a in the width direction y, and the second strip electrode 34b arranged with a length shorter than the length of the second plating layer 32b in the width direction y. Similarly, by controlling the width of the slit, it is possible to form the third strip electrode 34c arranged with a length shorter than the length of the third plating layer 32c in the length direction z, and the fourth strip electrode 34d arranged with a length shorter than the length of the fourth plating layer 32d in the length direction z.

[0255] As a method of forming the strip electrode 34 from a sintered layer, a roll transfer method can also be used. In the case of the roll transfer method, when the first strip electrode 34a and the second strip electrode 34b are formed not only on the first end surface 12e and the second end surface 12f, but also on a part of the first main surface 12a and a part of the second main surface 12b, the first strip electrode 34a and the second strip electrode 34b can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roll transfer. Furthermore, in the case of the roller transfer method, when the third electrode 34c and the fourth electrode 34d are formed not only on the first side surface 12c and the second side surface 12d, but also on a portion of the first main surface 12a and a portion of the second main surface 12b, the pressing pressure during the roller transfer is increased, thereby enabling the third electrode 34c and the fourth electrode 34d to be formed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0256] In addition, in the roller transfer method, by controlling the width of the groove of the roller, it is possible to form the first strip electrode 34a arranged with a length shorter than the length of the first plating layer 32a in the width direction y, and the second strip electrode 34b arranged with a length shorter than the length of the second plating layer 32b in the width direction y. Similarly, by controlling the width of the groove of the roller, it is possible to form the third strip electrode 34c arranged with a length shorter than the length of the third plating layer 32c in the length direction z, and the fourth strip electrode 34d arranged with a length shorter than the length of the fourth plating layer 32d in the length direction z.

[0257] Then, a sintering process is performed to form a sintered layer as the ribbon electrode 34. The temperature of the sintering process at this time is preferably 700°C or more and 900°C or less.

[0258] (Conductive resin layer)

[0259] When the strip electrode 34 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed directly on the laminate 12 or on the surface of a formed sintered layer.

[0260] As a method for forming a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d or the strip electrode 34, and heat-treated at a temperature of 250°C to 550°C to thermally cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, it is preferable to suppress the oxygen concentration to 100 ppm or less.

[0261] As a method for applying the conductive resin paste, similar to the method of forming the band electrode 34 from a sintered layer, for example, a process method of applying the conductive resin paste by squeezing it out from a slit or a roll transfer method can be used.

[0262] (Thin film layer)

[0263] When the strip electrode 34 is formed of a thin film layer, masking can be performed to form the strip electrode by a thin film forming method such as sputtering or evaporation at a location where the external electrode 130 is to be formed. The strip electrode 34 formed of a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0264] Next, the plating layer 32 is formed on the strip electrode 34 and on the internal electrode layer 16 exposed from the laminated body 12 .

[0265] Specifically, the first plated layer 32a is formed on the first strip electrode 34a and on the first internal electrode layer 16a that is led out to the first end face 12e of the stack 12 and exposed, the second plated layer 32b is formed on the second strip electrode 34b and on the first internal electrode layer 16a that is led out to the second end face 12f and exposed, the third plated layer 32c is formed on the third strip electrode 34c and on the second internal electrode layer 16b that is led out to the first side face 12c and exposed, and the fourth plated layer 32d is formed on the fourth strip electrode 34d and on the second internal electrode layer 16b that is led out to the second side face 12d and exposed. Fig. 9 In the through-type multilayer ceramic capacitor 110 shown, the first to fourth plating layers 32a to 32d are formed of Cu plating layers.

[0266] As a specific method for forming the first to fourth plating layers 32 a to 32 d , the method described below can be used.

[0267] That is, the first plated layer 32a and the second plated layer 32b are formed by plating the first and second strip electrodes 34a and 34b and the first internal electrode layer 16a exposed on the first end face 12e and the second end face 12f of the stack 12. Similarly, the third and fourth plated layers 32c and 32d are formed by plating the third and fourth strip electrodes 34c and 34d and the second internal electrode layer 16b exposed on the first side face 12c and the second side face 12d of the stack 12. When performing the plating process, either electrolytic plating or electroless plating can be used, but electroless plating has the following disadvantages, that is, in order to increase the deposition speed of the plating layer, it is necessary to perform pretreatment using a catalyst, etc., and the process becomes complicated. Therefore, electrolytic plating is usually preferred.

[0268] Next, as necessary, the upper plating layer 36 is formed on the surface of the plating layer 32. In addition, the upper plating layer 36 may be arranged not only on the surface of the plating layer 32 but also on the surface of the laminate 12.

[0269] In the present embodiment, a Ni plating layer and a Sn plating layer are formed on the upper plating layer 36. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, a drum plating method. When performing the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating has the following disadvantages, that is, in order to increase the deposition speed of the plating layer, it is necessary to perform pretreatment using a catalyst, etc., and the process becomes complicated. Therefore, electrolytic plating is usually preferably used.

[0270] Furthermore, as described above, the embodiments of the present invention are disclosed through the above description, but the present invention is not limited thereto.

[0271] That is, various changes can be made to the above-described embodiments with respect to mechanism, shape, material, number, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these are all included in the present invention.

[0272] <1>

[0273] A through-type multilayer ceramic capacitor having:

[0274] A laminate comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction;

[0275] a first internal electrode layer, which is led out to the first end surface and the second end surface among the plurality of internal electrode layers;

[0276] a second internal electrode layer, which is led out to the first side surface and the second side surface among the plurality of internal electrode layers;

[0277] a first external electrode disposed on the first end surface and connected to the first internal electrode layer;

[0278] a second external electrode disposed on the second end surface and connected to the first internal electrode layer;

[0279] a third external electrode disposed on the first side surface and connected to the second internal electrode layer; and

[0280] a fourth external electrode disposed on the second side surface and connected to the second internal electrode layer;

[0281] in,

[0282] The first external electrode comprises: a first plating layer disposed on the first end surface; and a first strip electrode disposed on the first end surface and having a length shorter than a length of the first plating layer in the width direction.

[0283] The second external electrode comprises: a second plating layer disposed on the second end surface; and a second strip electrode disposed on the second end surface and having a length shorter than a length of the second plating layer in the width direction.

[0284] The third external electrode comprises: a third plating layer disposed on the first side surface; and a third strip electrode disposed on the first side surface and having a length shorter than a length of the third plating layer in the longitudinal direction.

[0285] The fourth external electrode includes: a fourth plating layer disposed on the second side surface; and a fourth strip electrode disposed on the second side surface and having a length shorter than a length of the fourth plating layer in the longitudinal direction.

[0286] <2>

[0287] The feedthrough multilayer ceramic capacitor according to <1>,

[0288] The lengths of the first plating layer and the second plating layer in the width direction are smaller than the length of the laminate in the width direction.

[0289] The lengths of the first plating layer and the second plating layer in the stacking direction are smaller than the length of the stacked body in the stacking direction.

[0290] The lengths of the third plating layer and the fourth plating layer in the longitudinal direction are smaller than the length of the laminate in the longitudinal direction.

[0291] The lengths of the third plating layer and the fourth plating layer in the stacking direction are smaller than the length of the stacked body in the stacking direction.

[0292] <3>

[0293] The feedthrough multilayer ceramic capacitor according to <1> or <2>,

[0294] The first plating layer and the second plating layer are arranged to cover the first internal electrode layer,

[0295] The third plating layer and the fourth plating layer are arranged to cover the second internal electrode layer,

[0296] The first strip electrode is arranged on the first plating layer and on the surface of the first end face,

[0297] The second strip electrode is arranged on the second plating layer and on the surface of the second end face,

[0298] The third strip electrode is arranged on the third plating layer and on the surface of the first side surface.

[0299] The fourth belt electrode is arranged on the fourth plating layer and on the surface of the second side surface.

[0300] <4>

[0301] The feedthrough multilayer ceramic capacitor according to <1> or <2>,

[0302] The first strip electrode and the second strip electrode are arranged to cover the first internal electrode layer.

[0303] The third strip electrode and the fourth strip electrode are arranged to cover the second internal electrode layer.

[0304] The first plating layer is arranged on the first strip electrode and the first internal electrode layer.

[0305] The second plating layer is arranged on the second strip electrode and the first internal electrode layer,

[0306] The third plating layer is arranged on the third strip electrode and the second internal electrode layer.

[0307] The fourth plating layer is arranged on the fourth strip electrode and the second internal electrode layer.

[0308] <5>

[0309] The feedthrough multilayer ceramic capacitor according to any one of <1> to <4>,

[0310] The first strip electrode, the second strip electrode, the third strip electrode, and the fourth strip electrode are respectively arranged to extend to a portion of the first main surface and a portion of the second main surface.

[0311] <6>

[0312] The feedthrough multilayer ceramic capacitor according to any one of <1> to <5>,

[0313] The first to fourth plating layers are Cu plating layers.

[0314] <7>

[0315] The feedthrough multilayer ceramic capacitor according to any one of <1> to <6>,

[0316] An upper plating layer is arranged on the first to fourth plating layers and on the first to fourth strip electrodes.

[0317] Description of Reference Numerals

[0318] 10, 110: Through-type multilayer ceramic capacitors;

[0319] 12: laminate;

[0320] 12a: 1st main side;

[0321] 12b: 2nd main side;

[0322] 12c: 1st side;

[0323] 12d: lateral side 2;

[0324] 12e: 1st end surface;

[0325] 12f: 2nd end surface;

[0326] 14: dielectric layer;

[0327] 16: internal electrode layer;

[0328] 16a: first internal electrode layer;

[0329] 16b: second internal electrode layer;

[0330] 18: inner layer;

[0331] 19: Opposing electrode portion;

[0332] 20a: first main surface side outer layer portion;

[0333] 20b: outer layer portion on the second main surface side;

[0334] 22a: first side outer layer portion;

[0335] 22b: 2nd side outer layer portion;

[0336] 24a: first end surface side outer layer portion;

[0337] 24b: second end surface side outer layer portion;

[0338] 26a: first opposing electrode portion;

[0339] 26b: second opposing electrode portion;

[0340] 28a: first lead electrode portion;

[0341] 28b: second lead electrode portion;

[0342] 28c: third lead electrode portion;

[0343] 28d: 4th lead electrode portion;

[0344] 30, 130: external electrodes;

[0345] 30a, 130a: first external electrode;

[0346] 30b, 130b: second external electrode;

[0347] 30c, 130c: third external electrode;

[0348] 30d, 130d: fourth external electrode;

[0349] 32: plating layer;

[0350] 32a: first plating layer;

[0351] 32b: second plating layer;

[0352] 32c: third plating layer;

[0353] 32d: 4th plating layer;

[0354] 34: with electrodes;

[0355] 34a: 1st band electrode;

[0356] 34b: 2nd band electrode;

[0357] 34c: 3rd band electrode;

[0358] 34d: 4th band electrode;

[0359] 36: upper plating layer;

[0360] 36a: first upper plating layer;

[0361] 36b: second upper plating layer;

[0362] 36c: 3rd upper plating layer;

[0363] 36d: 4th upper plating layer;

[0364] x: stacking direction;

[0365] y: width direction;

[0366] z: length direction.

Claims

1. A feedthrough multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction; a first internal electrode layer, which is led out to the first end surface and the second end surface among the plurality of internal electrode layers; a second internal electrode layer, which is led out to the first side surface and the second side surface among the plurality of internal electrode layers; a first external electrode disposed on the first end surface and connected to the first internal electrode layer; a second external electrode disposed on the second end surface and connected to the first internal electrode layer; a third external electrode disposed on the first side surface and connected to the second internal electrode layer; and a fourth external electrode disposed on the second side surface and connected to the second internal electrode layer; in, The first external electrode comprises: a first plating layer disposed on the first end surface; and a first strip electrode disposed on the first end surface and having a length shorter than a length of the first plating layer in the width direction. The second external electrode comprises: a second plating layer disposed on the second end surface; and a second strip electrode disposed on the second end surface and having a length shorter than a length of the second plating layer in the width direction. The third external electrode comprises: a third plating layer disposed on the first side surface; and a third strip electrode disposed on the first side surface and having a length shorter than a length of the third plating layer in the longitudinal direction. The fourth external electrode comprises: a fourth plating layer disposed on the second side surface; and a fourth strip electrode disposed on the second side surface and having a length shorter than a length of the fourth plating layer in the longitudinal direction.

2. The through-type multilayer ceramic capacitor according to claim 1, wherein: The lengths of the first plating layer and the second plating layer in the width direction are smaller than the length of the laminate in the width direction. The lengths of the first plating layer and the second plating layer in the stacking direction are smaller than the length of the stacked body in the stacking direction. The lengths of the third plating layer and the fourth plating layer in the longitudinal direction are smaller than the length of the laminate in the longitudinal direction. The lengths of the third plating layer and the fourth plating layer in the stacking direction are smaller than the length of the stacked body in the stacking direction.

3. The through-type multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The first plating layer and the second plating layer are arranged to cover the first internal electrode layer. The third plating layer and the fourth plating layer are arranged to cover the second internal electrode layer, The first strip electrode is arranged on the first plating layer and on the surface of the first end face, The second strip electrode is arranged on the second plating layer and on the surface of the second end face, The third strip electrode is arranged on the third plating layer and on the surface of the first side surface. The fourth belt electrode is arranged on the fourth plating layer and on the surface of the second side surface.

4. The through-type multilayer ceramic capacitor according to claim 1 or claim 2, wherein: The first strip electrode and the second strip electrode are arranged to cover the first internal electrode layer. The third strip electrode and the fourth strip electrode are arranged to cover the second internal electrode layer. The first plating layer is arranged on the first strip electrode and the first internal electrode layer. The second plating layer is arranged on the second strip electrode and the first internal electrode layer, The third plating layer is arranged on the third strip electrode and the second internal electrode layer. The fourth plating layer is arranged on the fourth strip electrode and the second internal electrode layer.

5. The through-type multilayer ceramic capacitor according to any one of claims 1 to 4, wherein: The first strip electrode, the second strip electrode, the third strip electrode, and the fourth strip electrode are respectively arranged to extend to a portion of the first main surface and a portion of the second main surface.

6. The through-type multilayer ceramic capacitor according to any one of claims 1 to 5, wherein: The first to fourth plating layers are Cu plating layers.

7. The through-type multilayer ceramic capacitor according to any one of claims 1 to 6, wherein: An upper plating layer is arranged on the first to fourth plating layers and on the first to fourth strip electrodes.

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