Integrated circuit with inductor in magnetic package

Abstract

In one example, an integrated circuit (200) includes: a substrate (206); a semiconductor die (104); a metal interconnect (130, 132, 134) coupled between the semiconductor die and the substrate; an insulating layer (2401, 2402, 2403, 2404) coupled between the semiconductor die and the substrate, the insulating layer surrounding the metal interconnect; an inductor (202) coupled to the substrate; and a magnetic material (208) encapsulating the semiconductor die, the inductor, the metal interconnect, and the insulating layer, the magnetic material having a different material than the insulating layer.

Description

Background Art

[0001] Inductors can store energy in a magnetic field when current flows through them, and can provide current by discharging the stored energy. Inductors can have many applications, such as proximity sensing, energy storage, actuation, power transmission, and filtering. Inductors can be coupled to or can be part of an integrated circuit, which can include circuitry that operates with the inductor to support those applications. In some examples, the inductor and circuitry can be enclosed in an integrated circuit package, which can reduce the footprint of the integrated circuit and shorten the interconnects between the inductor and the circuitry. Summary of the invention

[0002] An integrated circuit includes: a substrate, a semiconductor die, a metal interconnection, an insulating layer, an inductor, and a magnetic material. The metal interconnection is coupled between the semiconductor die and the substrate. The insulating layer is coupled between the semiconductor die and the substrate and surrounds the metal interconnection. The inductor is coupled to the substrate. The magnetic material encapsulates the semiconductor die, the inductor, the metal interconnection, and the insulating layer, and has a different material from the insulating layer.

[0003] A method includes forming an insulating layer on a wafer, patterning the insulating layer, and forming a first metal interconnect in the patterned insulating layer. The method further includes dicing the wafer to form semiconductor dies, the diced wafer also including the first metal interconnect and the patterned insulating layer. The method further includes mounting the semiconductor die to a substrate, mounting an inductor to the substrate, and depositing a magnetic material on the semiconductor die and the inductor to form an encapsulating package. The method further includes forming a second metal interconnect outside the encapsulating package, wherein the second metal interconnect is coupled to the first metal interconnect and the inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A and 1B is a schematic diagram of an example integrated circuit.

[0005] Figure 2A , Figure 2B , Figures 3A-3C and Figures 4A-4C A schematic diagram of an example of an integrated circuit.

[0006] Figure 5 A flow chart of an example method for fabricating an integrated circuit.

[0007] Figure 6A to 6V To show Figure 5 A diagram of the various operations of the instance method. DETAILED DESCRIPTION

[0008] Figure 1A and Figure 1Bis a schematic diagram illustrating an example integrated circuit 100 . Figure 1A and Figure 1B A perspective view and a side view of the integrated circuit 100 are shown, respectively. Figure 1A and Figure 1B , the integrated circuit 100 may include an inductor 102 and a semiconductor die 104 mounted to a packaging substrate 106 and encapsulated in an encapsulation package 108. The inductor 102 may include a metal coil surrounding a core. Examples of inductor cores may include air cores, ferrite cores, or iron powder cores. The inductor 102 may also be a molded inductor, wherein the coil and the core may be encapsulated in a package made of a molding compound, such as a magnetic molding compound (MMC) having metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. The encapsulation package 108 may shield the coil and the core and increase the magnetic field density, which may improve the efficiency of the inductor 102 in converting between electrical energy and magnetic energy. In addition, the encapsulation package 108 may include a molding compound, such as an epoxy molding compound (EMC), which may electrically insulate the inductor 102 and the semiconductor die 104 from external electrical signals such as noise signals and electrostatic signals.

[0009] Semiconductor die 104 and inductor 102 may form a system that supports specific applications such as proximity sensing, energy storage, actuation, power transmission, and filtering. For example, integrated circuit 100 may include a proximity sensor, wherein semiconductor die 104 may include an oscillator and a sensing circuit. The oscillator may drive inductor 102 with an oscillating current signal, and the sensing circuit may sense the frequency of the current signal. The proximity of a metal object to inductor 102 may change the inductance of inductor 102, which may change the frequency of the current signal. The sensing circuit may detect the metal object by detecting the change in frequency. As another example, integrated circuit 100 may include a switch-mode power converter for transmitting power from a power source to a load. In such an example, inductor 102 may provide energy storage, and semiconductor die 104 may include a switch to charge and discharge inductor 102 to set the voltage across the load.

[0010] In addition, the package substrate 106 can provide mechanical support to the inductor 102 and the semiconductor die 104, and provide electrical connections between the inductor and the semiconductor die, and between the integrated circuit 100 and external devices. For example, the package substrate 106 can include an electrically insulating material such as a polymer, an Ajinomoto Build-up Film (ABF), or a ceramic material. The package substrate 106 can also include metal pads 110, 112, 114, 116, and 118, which can be copper pads, located on a surface 120 where the inductor 102 and the semiconductor die 104 are mounted.

[0011] Furthermore, semiconductor die 104 may include a passivation layer 122, which may be coupled to metal pads 110, 112, 114, and 116 via respective metal interconnects 130, 132, 134, and 136. Each pad may be coupled to a respective metal interconnect via a solder layer. Passivation layer 122 may insulate circuitry in semiconductor die 104 from metal interconnects 130, 132, 134, and 136. Metal interconnects 130 to 136 may include, for example, copper pillars, solder bumps, and under-bump metallization (UBM) interconnects. Furthermore, inductor 102 may be coupled to metal pad 118 via a solder layer. Package substrate 106 may include metal interconnects on or below surface 120 to provide electrical connections between inductor 102 and semiconductor die 104, such as metal interconnects 140 between metal pads 116 and 118.

[0012] Package substrate 106 may also include metal pads on surface 150 opposite to surface 120, such as metal pads 160, 162, and 164, which may include copper pads or pads made of other metals (e.g., silver or palladium). Package substrate 106 may also include metal interconnects, such as copper interconnects, to provide electrical connections between pads on opposite surfaces. For example, package substrate 106 may include metal interconnect 170 between metal pads 110 and 160, metal interconnect 172 between metal pads 112 and 162, and metal interconnect 174 between metal pads 114 and 164. The metal pads and interconnects on surface 150 may provide electrical connections between external devices and integrated circuit 100. For example, metal pads 160, 162, and 164 may be coupled to a printed circuit board (PCB) 176 via respective solder balls 180, 182, and 184, which may provide electrical connections between integrated circuit 100 and external devices (e.g., a power source) on PCB 176. Package substrate 106 may also include a solder resist layer 190 on surface 150 to shield metal interconnects (e.g., metal interconnects 170, 172, and 174) in the package substrate from the solder balls.

[0013] Figure 2A Shown with Figure 1A and 1B An example of an integrated circuit 200 may have a reduced footprint compared to the integrated circuit 100 . Figure 2A A side view of integrated circuit 200 is shown. Figure 2A, the integrated circuit 200 may include an inductor 202 and a semiconductor die 104 mounted to a packaging substrate 206. The integrated circuit 200 may also include a magnetic material (e.g., MMC) on the packaging substrate 206. The magnetic material may serve as an encapsulation package 208 to encapsulate the inductor 202 and the semiconductor die 104. The inductor 202 may include: a coil portion 210, which may include various types of cores, such as a ferrite core and an iron powder core; and pillar portions 212a and 212b, which support the coil portion 210 above the packaging substrate 206. Also, the semiconductor die 104 may be positioned between the pillar portions 212a and 212b and below the coil portion 210, so that the coil portion 210 and the semiconductor die 104 may form a device stack. In some instances, the coil portion 210 may have an opening facing laterally (e.g., along the x / y axis), such as Figures 3A-3C In some examples, the coil portion 210 may have an opening facing upward / downward (eg, along the z-axis) on the semiconductor die 104, such as Figures 4A-4C as shown in .

[0014] The package substrate 206 may include metal pads 220, 222, 224, 226, 228, and 230, which may be copper pads, on a surface 232 to which the inductor 202 and the semiconductor die 104 are attached. The integrated circuit 200 may include metal interconnects 130, 132, 134, and 136 coupled between the semiconductor die 104 and the respective metal pads 222, 224, 226, and 228 via a solder layer. In addition, the pillar portions 212a and 212b of the inductor 202 may be coupled to the respective metal pads 220 and 230 via a solder layer.

[0015] The integrated circuit 200 may include an insulating layer 240 between the passivation layer 122 of the semiconductor die 104 and the surface 232 of the package substrate 206. The insulating layer 240 may surround the metal interconnects coupled between the semiconductor die 104 and the package substrate 206, and may include sublayers sandwiched between adjacent metal interconnects of the semiconductor die 104 and between the metal interconnects and the pillars of the inductor 202 to provide electrical insulation between the semiconductor die 104 and the metal interconnects of the inductor 202. For example, the insulating sublayer 240_1 may provide electrical insulation between the pillar portion 212a and the metal interconnect 130, the insulating sublayer 240_2 may provide electrical insulation between the metal interconnects 130 and 132, the insulating layer 240_3 may provide electrical insulation between the metal interconnects 132 and 134, the insulating layer 240_4 may provide electrical insulation between the metal interconnects 134 and 136, and the insulating layer 240_5 may provide electrical insulation between the metal interconnect 136 and the pillar portion 212b. In some examples, the insulating layer 240 may include a dielectric material having a high breakdown voltage, such as a polymer material (e.g., polyimide (PI), polybenzoxazole (PBO)), or an oxide material (e.g., silicon dioxide). The insulating layer 240 and the metal interconnects 130 to 136 are encapsulated in the encapsulation package 208.

[0016] The package substrate 206 may also include metal pads located on a surface 250 opposite to the surface 232, such as metal pads 252, 254, 256, and 258, which may include copper pads or pads made of other metals (e.g., silver and palladium). The metal pads 252, 254, 256, and 258 may be coupled to an external device, such as the PCB 176 and solder balls 180 to 184 of FIG. 1, via solder balls to provide electrical connections between the integrated circuit 200 and the external device. The package substrate 206 may also include metal interconnects, such as copper interconnects, connected between metal pads on the same or different surfaces. For example, the package substrate 206 may include a metal interconnect 260 coupled between metal pads 220 and 222 (on the surface 232) to provide electrical connections between the inductor 202 and the semiconductor die 104. The package substrate 206 may also include a metal interconnect 262 coupled between the metal pads 224 and 252, a metal interconnect 264 coupled between the metal pads 226 and 254, a metal interconnect 266 coupled between the metal pads 228 and 256, and a metal interconnect 268 coupled between the metal pads 230 and 258 to provide electrical connections between external devices and the inductor 202 and / or the semiconductor die 104. The package substrate 206 may include an electrically insulating layer 269, such as a polymer, ABF, or ceramic material, to provide electrical insulation between the metal interconnects and the metal pads. In addition, the package substrate 206 may include a solder resist layer 270 located below the surface 250 to shield the metal interconnects (e.g., metal interconnects 260, 262, 264, 266, and 268) in the package substrate from solder balls and external devices.

[0017] Also, as described above, the inductor 202 and the semiconductor die 104 may be encapsulated in an encapsulation package 208 on the package substrate 206, and the encapsulation package 208 may include a magnetic material such as MMC. The MMC may have metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. The encapsulation package 208 may shield the inductor 202 and increase the magnetic field density, which may improve the efficiency of the inductor 202 when converting between electrical energy and magnetic energy. The MMC material of the encapsulation package 208 may fill the space within the inductor 202, such as within the center of the coil portion 210 (e.g., if the inductor 202 has an air core) and between the individual coils of the coil portion 210. The MMC material may also fill the space between the coil portion 210 and the semiconductor die 104, except in the space filled by the insulating layer 240, and encapsulate the insulating layer 240 and the metal interconnects 130 to 136. The insulating layer 240 may have a higher breakdown voltage than the MMC material.

[0018] Figure 2B Another example of an integrated circuit 200 is shown. Figure 2B, the semiconductor die 104 can be positioned outside and adjacent to the inductor 202. The integrated circuit 200 can include another circuit component, such as a capacitor 280, positioned below the coil portion 210 and the pillar portions 212a and 212b, such that the coil portion 210 and the capacitor 280 can form a device stack. In some examples, the semiconductor die 104 and the capacitor 280 can be positioned below the coil portion 210 and the pillar portions 212a and 212b to form a device stack.

[0019] In addition to the metal pads 220-230 located on the surface 232 to which the semiconductor die 104 and the capacitor 280 are attached, the package substrate 206 may also include a metal pad 234 (e.g., a copper pad). The integrated circuit 200 may also include metal interconnects 130, 132, and 136 (e.g., copper pillars, solder bumps, or UBM interconnects) coupled between the semiconductor die 104 and the respective metal pads 222, 224, and 226 of the package substrate 206. The integrated circuit 200 may also include metal interconnects 282 and 284 (e.g., copper pillars, solder bumps, or UBM interconnects) coupled between the capacitor 280 and the respective metal pads 228 and 234. The package substrate 206 may also include metal interconnects coupled between the metal pads on the surface 232 and on the surface 250 to provide external access to the semiconductor die 104, the inductor 202, and the capacitor 280. For example, package substrate 206 may include metal interconnect 262 coupled between metal pads 222 and 252, metal interconnect 264 coupled between metal pads 224 and 254, metal interconnect 266 coupled between metal pads 234 and 256, and metal interconnect 268 coupled between metal pads 230 and 258. Package substrate 206 may also include metal interconnect 260 coupled between metal pads 220, 226, and 228 to provide internal electrical connections between semiconductor die 104, inductor 202, and capacitor 280.

[0020] Furthermore, the integrated circuit 200 may include an insulating layer 240 between the passivation layer 122 of the semiconductor die 104 and the surface 232 of the package substrate 206, and an insulating layer 290 between the capacitor 280 and the surface 232 of the package substrate 206. The insulating layers 240 and 290 may surround the metal interconnects of the respective semiconductor die 104 and the capacitor 280, and may include a sublayer sandwiched between adjacent metal interconnects to provide electrical insulation. For example, the insulating sublayer 240_1 may provide electrical insulation between the metal interconnect 130 and the outside of the encapsulation package 208, the insulating sublayer 240_2 may provide electrical insulation between the metal interconnects 130 and 132, the insulating layer 240_3 may provide electrical insulation between the metal interconnects 132 and 134, and the insulating layer 240_4 may provide electrical insulation between the metal interconnect 134 and the pillar portion 212a. Furthermore, the insulating sublayer 290_1 can provide electrical insulation between the pillar portion 212a and the metal interconnection 282, the insulating sublayer 290_2 can provide electrical insulation between the metal interconnections 282 and 284, and the insulating sublayer 290_3 can provide electrical insulation between the metal interconnection 290_3 and the pillar portion 212b. Both the insulating layers 240 and 290 can include a dielectric material having a higher breakdown voltage than the MMC material encapsulating the package 208, such as PI, PBO, or silicon dioxide.

[0021] By placing the semiconductor die 104 and / or the capacitor 280 below the coil portion 210 of the inductor 202, Figure 2A and Figure 2B The integrated circuit 200 may have a reduced footprint (eg, in the xy plane), which may also shorten the metal interconnects (eg, metal interconnects 260 ) between the semiconductor die 104 and the inductor 202 and reduce their parasitic capacitance. Figure 2A and Figure 2B The arrangement also allows the coil portion of the inductor to cover most of the footprint of the integrated circuit 200, and a larger inductor with increased inductance can be included in the integrated circuit 200. In addition, by encapsulating the inductor 202 in the MMC encapsulation package, the magnetic field density within the integrated circuit 200 can be increased, which can improve the efficiency of the inductor 202 in converting between electrical energy and magnetic energy. In addition, the metal interconnects (e.g., copper pillars and / or UBMs) of the semiconductor die 104 can be encapsulated (and insulated) with an insulating layer 240, which is made of a material with a higher breakdown voltage than the MMC, such as PI and PBO, which can reduce the risk of electrical shorts between adjacent interconnects and between the inductor 202 and the interconnects, thereby improving safety and reliability, while the coil portion 210 can be encapsulated in the MMC to improve the magnetic field density. All of this can improve the performance of the integrated circuit 200.

[0022] Figure 5 and Figure 6A to 6VAn example of a method of fabricating an integrated circuit having an inductor in a magnetic package, such as integrated circuit 200 of FIGS. 2 to 4C , is shown. Figure 5 A flowchart 500 is shown of an example method of manufacturing an integrated circuit, and Figure 6A to 6V It is shown Figure 5 A diagram of the various operations of the instance method.

[0023] See also Figure 5 and Fig. 6A In operation 502, a first insulating layer, such as insulating layer 602, may be formed on wafer 604. Wafer 604 may be coated with passivation layer 122 and may include vias 606 that penetrate passivation layer 122 to provide electrical connections to devices in wafer 604. Insulating layer 602 may include a dielectric material with a high breakdown voltage, such as a polymer material (e.g., PI and PBO), or an oxide material (e.g., silicon dioxide). Insulating layer 602 may be coated on wafer 604, or may be formed on wafer 604 by a chemical process (e.g., oxidation).

[0024] In operation 504, the insulating layer 602 may be patterned. Figure 6B , the insulating layer 602 may be patterned to create an opening 608 to expose the via 606. The patterning may be performed based on, for example, photolithography and a subsequent etching process and a plasma cleaning process.

[0025] In operation 506, metal interconnects, such as metal interconnect 610, may be formed in patterned insulating layer 602. For example, see Figure 6C , a metal interconnect 610, such as a UBM interconnect or a copper pillar, may be formed in the opening 608. In the case where the first metal interconnects (e.g., metal interconnect 610) include UBMs, they may be formed by a plating operation. After forming the UBM, solder balls 611 may be formed on the UBM by a reflow process. In some examples, operations 502, 504, and 506 may be part of a wafer-level chip scale packaging (CSP) operation.

[0026] In operation 508, wafer 604 may be singulated to form semiconductor dies, such as semiconductor die 104. Singulated wafer 604 also includes metal interconnects 610 and patterned insulating layer 602. Fig.6D , the insulating layer 602 may be represented by the insulating layer 240 , and the metal interconnect 610 and the via 606 may be represented by one of the metal interconnects 130 to 136 .

[0027] In operation 510, the semiconductor die 104 may be mounted to a substrate, which may be a carrier substrate, or a packaging substrate in which metal interconnects will be formed in subsequent operations. Fig. 6E, a plurality of semiconductor dies 104 may be mounted to a carrier substrate 612 via first metal interconnects 130 to 136 and an insulating layer 240. For example, semiconductor die 104a may be mounted to the carrier substrate 612 via metal interconnects 130a to 136a and an insulating layer 240a, and semiconductor die 104b may be mounted to the carrier substrate 612 via metal interconnects 130b to 136b and an insulating layer 240b. In some examples, the semiconductor dies 104a and 104b may be mounted to the carrier substrate 612 using a flip chip bonder, which may be preprogrammed to transfer the die to a specific location on the carrier substrate 612. The carrier substrate 612 may be made of various rigid materials, such as metal (e.g., iron), glass, or silicon. In some examples, the carrier substrate 612 may include a layer of adhesive carrier tape on a surface, and the flip chip bonder may apply a pressing force to adhere the semiconductor die to the carrier tape.

[0028] Reference again Figure 5 In operation 512, the inductor 202 may be mounted to the substrate. Fig. 6F , a plurality of inductors 202 may be mounted to a carrier substrate 612 and over respective semiconductor dies 104. For example, a leg portion of inductor 202a may be mounted to carrier substrate 612 (e.g., via a carrier tape) such that a coil portion is over semiconductor die 104a to form device stack 614a, and a leg portion of inductor 202b may be mounted to carrier substrate 612 such that a coil portion is over semiconductor die 104b to form device stack 614b. In some examples, inductors 202a and 202b may be mounted to carrier substrate 612 using a surface mounter that may be pre-programmed to transfer the inductors to specific locations on carrier substrate 612 and aligned with respective semiconductor dies. Thus, the carrier substrate 612 can maintain the relative positions of the inductors 202a and 202b and the semiconductor dies 104a and 104b within the respective device stacks 614a and 614b, as well as the relative positions of the device stacks 614a and 614b.

[0029] Reference again Figure 5 In operation 514, a magnetic material such as MMC may be deposited on the semiconductor die 104 and the inductor 202 to form the encapsulation package 208. The MMC may include metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. Figure 6G, encapsulation package 208 can be formed by depositing MMC over device stack 614a and over device stack 614b to encapsulate two device stacks. The MMC can then be molded to form encapsulation package 208. In some examples, molding can be performed in a compression molding machine, where the MMC and carrier substrate 612 with the device stacks can be placed in a hot mold. The mold can then be closed by a press (e.g., a hydraulic press). The pressure applied by the press on the mold can squeeze the MMC into the empty space between the inductor and the semiconductor die in each device stack (except for the space filled by the insulating layer 240), and mold the MMC into encapsulation package 208. After the MMC is cured and hardened, the mold can be opened to release the encapsulation package 208 and the carrier substrate 612.

[0030] Reference again Figure 5 In operation 516, a second metal interconnect may be formed outside of the encapsulation package 208, such as Figure 2A and 2B The metal interconnects 260 to 268 are connected to the inductor 202 and the metal interconnects 130 to 136.

[0031] Figure 6H to 6V An example of a sub-operation of operation 516 to form a second metal interconnect is shown. Figure 6H , in the case where the substrate of operation 512 is a carrier substrate 612, in a sub-operation 516a of operation 516, the carrier substrate 612 may be separated from the encapsulation package 208 and the device stacks 614a and 614b, and a partial package stack 618 including the encapsulation package 208 and the device stacks 614a and 614b may be formed. As described above, the encapsulation package 208 may be hardened from the curing of the MMC in operation 514, and the relative positions of the inductor 202 and the semiconductor die 104 may be maintained. Thus, the carrier substrate 612 may be separated from the encapsulation package 208 and the device stack. The separation of the carrier substrate 612 may be performed, for example, by heating a carrier tape or irradiating the carrier tape with ultraviolet light, and then removing the carrier tape. After carrier substrate 612 is separated from encapsulating package 208 and device stacks 614a and 614b, surface 620 of portion of package stack 618 including pillar portions of inductor 202, metal interconnects 130-136, and insulating layer 240 may be exposed.

[0032] See also Fig.6I, in sub-operation 516b, encapsulated package 208 and device stacks 614a and 614b may be flipped, and a second insulating layer, such as insulating layer 622, may be formed on surface 620. Insulating layer 622 may contact the pillar portion of inductor 202, metal interconnects 130 to 136 of semiconductor die 104, and insulating layer 240 that insulates the metal interconnects. Insulating layer 622 may include, for example, a polymer, ABF, or a ceramic material. In some examples, insulating layer 622 may be formed on surface 620 by a lamination process using, for example, a vacuum laminator.

[0033] See also Figure 6J , in sub-operation 516c, the insulating layer 622 may be patterned. As a result of the patterning, openings 630, 632, 634, 636, 638, and 640 may be generated to expose the pillar portions of the inductor 202 and the metal interconnects 130 to 136 of the semiconductor die 104. For example, openings 630a to 640a may be generated over the device stack 614a, and openings 630b to 640b may be generated over the device stack 614b. The patterning may be performed based on, for example, photolithography followed by etching and plasma cleaning. The patterned insulating layer 622 may become Figure 2A and Figure 2B The electrically insulating layer 269 of the package substrate 206 in FIG.

[0034] See also Figure 6K In sub-operation 516d, a metal layer 642 may be formed on the patterned insulating layer 622. The metal seed layer may cover the surface of the patterned insulating layer 622, the pillar portion of the inductor 202, and the metal interconnects 130 to 136 of the semiconductor die 104, and may become Figure 2A and Figure 2B The metal pads 220 to 230 of the patterned insulating layer 622 are formed on the metal pads 220 to 230. In some examples, the metal layer 642 may be a metal seed layer, such as a titanium seed layer, to provide a starting material for forming metal interconnects in the package substrate 206 in subsequent processing operations. The metal layer 642 may be formed on the patterned insulating layer 622 using various processes, such as an electroplating process or a sputtering process.

[0035] After sub-operation 516d, additional processing operations may be performed to form second metal interconnects in the package substrate 206. Examples of processing operations may include semi-additive processes and subtractive processes. Semi-additive processes may provide finer line and space patterning of metal interconnects than subtractive processes. Figures 6L to 6O Sub-operations 516e1 to 516h1 of a semi-additive process are shown, and Figures 6P to 6S Sub-operations 516e2 through 516h2 of the subtractive process are shown. Figures 6L to 6S The sub-operations in are used to manufacture a packaging substrate having multiple layers of metal interconnects.

[0036] See also Figure 6L , in sub-operation 516e1, a photoresist 650 may be formed on the metal layer 642. The photoresist 650 may be used to define the location of metal interconnects in the package substrate 206 in subsequent processing. In some examples, the photoresist 650 may include a dry film material that can be hardened by ultraviolet light. In some examples, the photoresist 650 may be formed on the metal layer 642 by a lamination process using, for example, a vacuum laminator.

[0037] See also Figure 6M In sub-operation 516f1, the photoresist 650 may be patterned into photoresist portions 650a to 650g. After patterning, openings 652a to 652f may be created to expose portions of the metal layer 642 and underlying openings of the insulating layer 622. The patterning may be performed based on, for example, photolithography and subsequent removal of the photoresist by a stripping liquid.

[0038] See also Figure 6N In sub-operation 516g1, a metal layer 670 may be formed in openings 652 (e.g., openings 652a to 652f) and on exposed portions of metal layer 642. Metal layer 670 may include a copper layer. Metal layer 670 may include a second metal interconnect in package substrate 206, such as Figure 2A and Figure 2B The metal interconnections 260 to 268 are formed by various processes, such as an electroplating process and a sputtering process.

[0039] See also Fig.6O In sub-operation 516h1, the photoresist portions 650a to 650g and the portions of the metal layer 642 below the photoresist portions 650a to 650g may be removed. The photoresist portions 650a to 650g may be removed by a stripping liquid. After removing the photoresist portions, the exposed underlying portions of the metal layer 642 may be removed by an etching process.

[0040] Figures 6P to 6S Sub-operations 516e2 to 516h2 of the subtractive process are shown. Figure 6P In sub-operation 516e2, a metal layer 670 (eg, a copper layer) may be formed on the metal layer 642. The metal layer 670 may be formed by various processes, such as an electroplating process or a sputtering process.

[0041] See also Figure 6Q In sub-operation 516f2, a photoresist 650 may be formed on the metal layer 670 and patterned into photoresist portions 650a to 650f. After patterning, openings 672a to 672g may be created to expose portions of the metal layer 670. The patterning may be performed based on, for example, photolithography and subsequent removal of the photoresist by a stripping liquid.

[0042] See also Figure 6R In sub-operation 516g2, the exposed portions of metal layer 670 in openings 672a to 672g may be removed by an etching process, and portions of metal layer 642 may be exposed. The remaining portions of metal layer 670 may become Figure 2A and Figure 2B Metal interconnects 260 to 268.

[0043] See also Figure 6S In sub-operation 516h2, the photoresist portions 650a to 650f and the portion of the metal layer 642 exposed by removing the metal layer 670 may be removed. The photoresist portions 650a to 650f may be removed by a stripping liquid. The exposed portion of the metal layer 642 may be removed by an etching process.

[0044] Figures 6T to 6U Examples of sub-operations 516i through 516k used to manufacture other components of the package substrate are shown. Figure 6T In sub-operation 516i, a solder resist layer 690 may be formed on portions of the metal layer 670 and the insulating layer 622 that are not covered by the metal layer 670. Examples of solder resist materials may include alkali-developable solder resists, UV-curable solder resists, and thermally curable solder resists. The solder resist layer 690 may be formed on portions of the metal layer 670 and the insulating layer 622 by various processes, such as a coating process or a lamination process using a vacuum laminator.

[0045] See also Figure 6U In sub-operation 516j, the solder resist layer 690 may be patterned into solder resist portions 690a to 690g. After patterning, openings 692a to 692f may be created to expose portions of the metal layer 670. The patterning of the solder resist layer 690 may be performed by a screen printing process. The patterned solder resist layer 690 may become Figure 2A and Figure 2B The solder resist layer 270 is provided.

[0046] See also Figure 6V In sub-operation 516k, metal pads 694a to 694f may be formed in corresponding openings 692a to 692f on the exposed portions of metal layer 670 to form package stack 696. Metal pads 694a to 694f may represent Figure 2A and Figure 2B The metal pads 252 to 258 are provided to improve the electrical connection between the metal layer 670 (and the metal interconnects) and the solder balls. The metal pads 694a to 694f may include silver (Au) or palladium (Pd) metal and may be formed on the exposed portions of the metal layer 670 by an electroplating process.

[0047] After sub-operation 516k, a plurality of integrated circuits 200 may be manufactured by slicing the package stack 696, such that each integrated circuit 200 may include the device stack of the inductor 202 and the semiconductor die 104, the insulating layer 240, and the metal interconnects 130-136, all of which may be mounted to the package substrate 206 including the insulating layer 622, the metal layer 670, the solder resist layer 690, and the metal pads 694. Each integrated circuit 200 may also include an MMC encapsulating the device stack and the insulating layer 240 as an encapsulation package 208.

[0048] In the case where the substrate of operation 512 is a packaging substrate, the packaging substrate may be prefabricated from the second insulating layer and may include a second metal interconnect. In such an example, sub-operation 516a may be skipped, and sub-operations 516b to 516k may be performed to form a packaging substrate, followed by operations 510 to 514 to mount the semiconductor die 104 and the inductor 202 to the packaging substrate, and deposit MMC on the semiconductor die 104 and the inductor 202 to form the encapsulation package 208.

[0049] Any method described herein can be performed in whole or in part using a computing system comprising one or more processors that can be configured to perform the steps. Therefore, an example can be directed to a computing system configured to perform the steps of any method described herein, which potentially performs corresponding steps or corresponding step groups with different components. Although presented in numbered steps, the steps of the method herein can be performed at the same time or in different orders. And, parts of these steps can be used together with parts of other steps from other methods. And, all or part of the steps can be optional. And, any step in the steps of any method can be performed using a module, unit, circuit or other component for performing these steps.

[0050] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first instance, device A is directly coupled to device B; or (b) in a second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, device A is indirectly coupled to device B through intermediate component C, so that device B is controlled by device A via the control signal provided by device A.

[0051] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0052] Circuits or devices described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described herein as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either at the time of manufacture or after manufacture, such as by an end user and / or a third party.

[0053] Certain components may be described herein as belonging to a particular process technology, but these components may be exchanged with components of other process technologies. The circuits described herein may be reconfigured to include replaced components to provide functionality at least partially similar to the functionality available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the displayed resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series or in parallel between the same two nodes as a single resistor or capacitor, respectively.

[0054] The use of the phrase "ground voltage potential" in this specification includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially" or "substantially" before a parameter means within + / -10% of the parameter.

[0055] Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Claims

1. An integrated circuit, comprising: substrate; Semiconductor die; a metal interconnect coupled between the semiconductor die and the substrate; an insulating layer coupled between the semiconductor die and the substrate, the insulating layer surrounding the metal interconnect; an inductor coupled to the substrate; as well as A magnetic material encapsulates the semiconductor die, the inductor, the metal interconnects, and the insulating layer, the magnetic material having a different material than the insulating layer.

2. The integrated circuit of claim 1, wherein the inductor comprises a coil portion and a pillar portion, the pillar portion coupled to the substrate.

3. The integrated circuit of claim 2, wherein the coil portion is on the semiconductor die.

4. The integrated circuit of claim 2, further comprising a capacitor encapsulated in the magnetic material and coupled to the substrate; The coil portion is located on the capacitor.

5. The integrated circuit of claim 1, wherein the magnetic material comprises metal particles and an epoxy resin in which the metal particles are suspended.

6. The integrated circuit of claim 1, wherein the insulating layer has a higher breakdown voltage than the magnetic material.

7. The integrated circuit of claim 6, wherein the insulating layer comprises a dielectric material.

8. The integrated circuit of claim 7, wherein the dielectric material comprises at least one of: a polyimide material, a polybenzoxazole material, or an oxide material.

9. The integrated circuit of claim 1, wherein the semiconductor die includes a passivation layer coupled to the metal interconnect.

10. The integrated circuit of claim 1, wherein the metal interconnect comprises at least one of: a pillar, or an under bump metallization (UBM) interconnect.

11. The integrated circuit of claim 1 , wherein the insulating layer is a first insulating layer, the metal interconnect is a first metal interconnect, and the substrate comprises: a first metal pad on a first side of the substrate, the first metal pad coupled to the first metal interconnect; a second metal pad on a second side of the substrate opposite the first side; a second insulating layer between the first side and the second side; as well as A second metal interconnect is in the second insulating layer and coupled between the first metal pad and the second metal pad.

12. The integrated circuit of claim 11, wherein: The first metal pad and the second metal interconnect comprise copper metal; The second metal pad comprises at least one of palladium metal or silver metal; and The second insulating layer includes at least one of the following: a polymer material, an Ajinomoto stacked film, or a ceramic material.

13. The integrated circuit of claim 11, further comprising a solder resist layer on the second side.

14. A method comprising: forming an insulating layer on the wafer; patterning the insulating layer; forming a first metal interconnect in the patterned insulating layer; dicing the wafer to form semiconductor dies, the diced wafer further comprising the first metal interconnect and the patterned insulating layer; mounting the semiconductor die to a substrate via the first metal interconnect and the patterned insulating layer; mounting an inductor to the substrate; depositing a magnetic material over the semiconductor die and the inductor to form an encapsulated package; as well as A second metal interconnect is formed outside the encapsulation package, wherein the second metal interconnect is coupled to the first metal interconnect and the inductor.

15. The method according to claim 14, wherein: The inductor has a leg portion and a coil portion; The pillar portion is coupled to the substrate; and The coil portion is on the semiconductor die.

16. The method of claim 14, wherein the insulating layer comprises a dielectric material comprising at least one of: a polyimide material, a polybenzoxazole material, or an oxide material; and The substrate comprises at least one of the following: a polymer material, an Ajinomoto stacked film, or a ceramic material.

17. The method of claim 14, further comprising: patterning the substrate; A metal layer is deposited on the portion of the patterned substrate to form the second metal interconnect.

18. The method according to claim 17, further comprising: forming a photoresist layer on the patterned substrate; patterning the photoresist layer to expose portions of the patterned substrate; as well as The metal layer is deposited on the exposed portion of the patterned substrate to form the second metal interconnect.

19. The method of claim 17, wherein the metal layer is a first metal layer, and the second metal interconnect is formed by: forming a photoresist layer on the metal layer; patterning the photoresist layer; as well as The portion of the metal layer exposed in the patterned photoresist layer is etched to form the second metal interconnect.

20. The method of claim 17, wherein the insulating layer is a first insulating layer, and the method further comprises: forming a second insulating layer on the second metal interconnect and the patterned substrate; patterning the second insulating layer to expose a portion of the second metal interconnect; as well as A metal pad is formed on the exposed portion of the second metal interconnection.

21. The method of claim 14, wherein: The substrate is a first substrate; The magnetic material is deposited on the semiconductor die, the inductor, and the first substrate; and The method further comprises: separating the first substrate from the magnetic material, the semiconductor die, and the inductor; mounting the magnetic material, the semiconductor die, and the inductor to a second substrate; and The second metal interconnection is formed in the second substrate.

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