High-speed sampler

Abstract

A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverter circuit, and a second transistor, a third transistor, and a fourth transistor coupled to an input of the first inverter circuit. A gate of the first transistor and a gate of the fourth transistor are coupled to a first input, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input. The regeneration circuit also includes a first switch and a second switch. The first switch and the third transistor are coupled in series between a first track and the first transistor, and the second switch and the fourth transistor are coupled in series between the first track and the second transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional patent application serial number 17 / 805,211 filed in the United States Patent and Trademark Office on June 2, 2022, the entire contents of which are incorporated herein as if fully set forth in their entirety below and for all applicable purposes. background Technical Field

[0004] Aspects of the present disclosure relate generally to samplers, and more particularly, to high speed samplers. Background Art

[0005] High-speed samplers can be used in high-speed serializer / deserializer (SerDes) applications. For example, a sampler can be used in a high-speed SerDes to sample a high-speed signal received by a receiver. The sampler can include a regeneration circuit that provides regeneration feedback to the sampler for quickly capturing data bits from the received signal. It is desirable to increase the speed at which the sampler samples signals at higher data rates and / or to increase the sensitivity of the sampler to capture data bits from small signals. Summary of the invention

[0006] The following content presents a brief summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is subsequently presented.

[0007] A first aspect relates to a regeneration circuit. The regeneration circuit includes: a first inverter circuit having an input and an output; and a second inverter circuit having an input and an output. The regeneration circuit also includes: a first transistor coupled to the input of the second inverter circuit, wherein the gate of the first transistor is coupled to the first input; and a second transistor coupled to the input of the first inverter circuit, wherein the gate of the second transistor is coupled to the second input. The regeneration circuit also includes: a third transistor, wherein the gate of the third transistor is coupled to the first input; and a fourth transistor, wherein the gate of the fourth transistor is coupled to the second input. The regeneration circuit also includes: a first switch, wherein the first switch and the third transistor are coupled in series between a first rail and the first transistor; and a second switch, wherein the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

[0008] The second aspect relates to a regeneration circuit. The regeneration circuit includes: a first inverter circuit having an input terminal and an output terminal; a second inverter circuit having an input terminal and an output terminal; a first transistor coupled to the input terminal of the second inverter circuit, wherein the gate of the first transistor is coupled to the first input terminal; and a second transistor coupled to the input terminal of the first inverter circuit, wherein the gate of the second transistor is coupled to the second input terminal. The regeneration circuit also includes: a pull-up circuit coupled to the input terminal of the first inverter circuit and the input terminal of the second inverter circuit; and a pull-down circuit coupled to the input terminal of the first inverter circuit and the input terminal of the second inverter circuit.

[0009] A third aspect relates to a method for operating a regenerative circuit of a sampler. The regenerative circuit includes: a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, a second transistor coupled to the input of the first inverting circuit, a third transistor, and a fourth transistor. The method includes: during a reset phase, disabling regenerative feedback of the first inverting circuit and the second inverting circuit. The method also includes: during a regenerative phase, enabling regenerative feedback of the first inverting circuit and the second inverting circuit; driving the gate of the first transistor and the gate of the third transistor with a first voltage; driving the gate of the second transistor and the gate of the fourth transistor with a second voltage; and coupling the third transistor to the output of the first inverting circuit or coupling the fourth transistor to the output of the second inverting circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a sampler including an input circuit and a regeneration circuit according to certain aspects of the present disclosure is shown.

[0011] Figure 2A An exemplary implementation of an input circuit according to certain aspects of the present disclosure is shown.

[0012] Figure 2B An exemplary implementation of a regeneration circuit according to certain aspects of the present disclosure is shown.

[0013] Figure 2C Another exemplary implementation of a regeneration circuit according to certain aspects of the present disclosure is shown.

[0014] Figure 3A is a timing diagram illustrating an example of voltage output by an input circuit to a regeneration circuit according to certain aspects of the present disclosure.

[0015] Figure 3Bis a timing diagram illustrating another example of voltage output by an input circuit to a regeneration circuit according to certain aspects of the present disclosure.

[0016] Figure 4 An example of a regeneration circuit including a pull-up circuit according to certain aspects of the present disclosure is shown.

[0017] Figure 5A An example of a regeneration circuit including a pull-down circuit in accordance with certain aspects of the present disclosure is shown.

[0018] Figure 5B Another example of a regeneration circuit including a pull-down circuit in accordance with certain aspects of the present disclosure is shown.

[0019] Figure 6 An example of a regenerative circuit including an input transistor providing a pull-up path in accordance with certain aspects of the present disclosure is shown.

[0020] Figure 7 An exemplary implementation of an input transistor according to certain aspects of the present disclosure is shown.

[0021] Figure 8 An exemplary implementation of a switch in a regeneration circuit according to certain aspects of the present disclosure is shown.

[0022] Fig. 9A An exemplary implementation of a first inverter circuit in a regeneration circuit according to certain aspects of the present disclosure is shown.

[0023] Fig. 9B An exemplary implementation of a second inverter circuit of a regeneration circuit according to certain aspects of the present disclosure is shown.

[0024] Fig.10 An exemplary implementation of a switch in an input circuit according to certain aspects of the present disclosure is shown.

[0025] Fig.11 Examples of systems in which aspects of the present disclosure may be used are shown in accordance with certain aspects of the present disclosure.

[0026] Fig.12 is a flow chart illustrating an exemplary method of operating a regeneration circuit according to certain aspects of the present disclosure. DETAILED DESCRIPTION

[0027] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0028] Figure 1 An example of a sampler 110 according to certain aspects of the present disclosure is shown. The sampler 110 may be used, for example, in a high-speed SerDes to sample an incoming data signal. The sampler 110 may also be referred to as a sense amplifier or another term. The sampler 110 includes an input circuit 120 and a regeneration circuit 150. The input circuit 120 may also be referred to as an input stage or another term, and the regeneration circuit 150 may also be referred to as a regeneration stage, a latch (e.g., a cross-coupled latch), or another term.

[0029] like Figure 1 As shown, the input circuit 120 has a first input terminal 130, a second input terminal 135, a first output terminal 140, and a second output terminal 145. The regeneration circuit 150 has a first input terminal 160, a second input terminal 165, a first output terminal 170, and a second output terminal 175. The first output terminal 160 of the regeneration circuit 150 is coupled to the first output terminal 140 of the input circuit 120, and the second input terminal 165 of the regeneration circuit 150 is coupled to the second output terminal 145 of the input circuit 120.

[0030] In this example, the input circuit 120 is configured to receive a differential input signal (e.g., a differential data signal) including a first input voltage INP and a second input voltage INN. The first input voltage INP is received at the first input terminal 130, and the second input voltage INN is received at the second input terminal 135. The differential input signal may have a small differential voltage (i.e., a small difference between the first input voltage INP and the second input voltage INN), where the polarity of the differential voltage represents a bit value. Taking SerDes as an example, the sampler 110 may be integrated on a first chip coupled to a second chip via a link, and the sampler may receive a differential input signal from a transmitter on the second chip via the link.

[0031] The input circuit 120 generates a first voltage DINT at a first output terminal 140 based on a first input voltage INP and a second input voltage INN and generates a second voltage NDINT at a second output terminal 145. As discussed further below, the input circuit 120 is configured to set the first voltage DINT and the second voltage NDINT to a reset voltage (e.g., a supply voltage) during a reset phase, and to change (e.g., discharge) the first voltage DINT and the second voltage NDINT at different rates based on the first input voltage INP and the second input voltage INN during a regeneration phase.

[0032] The regeneration circuit 150 is configured to receive a first voltage DINT at a first input terminal 160 and a second voltage NDINT at a second input terminal 165. As discussed further below, during the regeneration phase, the regeneration circuit 150 is configured to convert the first voltage DINT and the second voltage NDINT into a differential output voltage using regenerative feedback. The differential output signal includes a first output voltage OUTP at a first output terminal 170 and a second output voltage OUTN at a second output terminal 175, wherein the polarity of the differential output voltage represents the captured (i.e., resolved) bit value. It is desirable that the regeneration circuit 150 quickly converts the first voltage DINT and the second voltage NDINT into a large differential output voltage (i.e., a large difference between the first output voltage OUTP and the second output voltage OUTN) during the regeneration phase to quickly resolve the bit value for high-speed applications.

[0033] The first output 170 and the second output 175 of the regeneration circuit 150 may be coupled to a latch (not shown) configured to latch the captured bit value from the sampler 110. The latch may include a set-reset (SR) latch or another type of latch.

[0034] Figure 2A An exemplary implementation of an input circuit 120 according to certain aspects is shown. The input circuit 120 includes a first input transistor 210, a second input transistor 220, a first switch 230, a second switch 240, and a third switch 245. The second switch 240 is coupled between an upper rail 280 and the first input transistor 210, and the third switch 245 is coupled between the upper rail 280 and the second input transistor 220. The first input transistor 210 is coupled between the second switch 240 and a node 226, and the second input transistor 220 is coupled between the third switch 245 and the node 226. The first switch 230 is coupled between the node 226 and a lower rail 285. In an example, the upper rail 280 can provide a supply voltage VCC and the lower rail 285 can be coupled to ground. Generally speaking, the upper rail 280 is at a higher potential than the lower rail 285. The upper rail 280 can also be referred to as a supply rail or another term.

[0035] exist Figure 2A In the example shown, the first input transistor 210 is implemented with a first n-type field effect transistor (NFET), and the second input transistor 220 is implemented with a second NFET. It should be understood that the first input transistor 210 and the second input transistor 220 are not limited to NFETs and may be implemented with other types of transistors. In this example, the second switch 240 is coupled between the upper rail 280 and the drain of the first input transistor 210, and the first switch 230 is coupled between the source of the first input transistor 210 and the lower rail 285. The gate of the first input transistor 210 is coupled to the first input terminal 130 of the input circuit 120, and thus receives the first input voltage INP. Moreover, in this example, the third switch 245 is coupled between the upper rail 280 and the drain of the second input transistor 220, and the first switch 230 is coupled between the source of the second input transistor 220 and the lower rail 285. The gate of the second input transistor 220 is coupled to the second input terminal 135 of the input circuit 120, and thus receives the second input voltage INN.

[0036] The first switch 230 has a control input 235 driven by the timing signal, the second switch 240 has a control input 242 driven by the timing signal, and the third switch 245 has a control input 247 driven by the timing signal. In one example, the first switch 230 is configured to be turned on when the timing signal is high and turned off when the timing signal is low, and each of the second switch 240 and the third switch 245 is configured to be turned on when the timing signal is low and turned off when the timing signal is high. Figure 2A In the example shown, the timing signal is a clock signal CLK. As used herein, a "clock signal" is a periodic signal that oscillates between a high logic state and a low logic state. In some aspects, the high logic state (i.e., logic state one) may correspond to a voltage approximately equal to the supply voltage VCC, and the low logic state (i.e., logic state zero) may correspond to a voltage approximately equal to ground.

[0037] As used herein, a "control input" of a switch is an input that controls the on / off state of the switch based on a signal (e.g., a voltage signal) at the control input. For examples where the switch is implemented with a transistor, the control input is located at the gate of the transistor. In one example, the first switch 230 is implemented with an NFET, and each of the second switch 240 and the third switch 245 is implemented with a corresponding PFET. However, it should be understood that the present disclosure is not limited to this example.

[0038] In this example, the first output terminal 140 is coupled to the first node 222 between the second switch 240 and the first input transistor 210, and the second output terminal 145 is coupled to the second node 224 between the third switch 245 and the second input transistor 220. As discussed above, the input circuit 120 outputs the first voltage DINT at the first output terminal 140 and the second voltage NDINT at the second output terminal 145. Figure 1 In the example in , the first output terminal 140 is coupled to the drain of the first input transistor 210 , and the second output terminal 145 is coupled to the drain of the second input transistor 220 .

[0039] Figure 2B An exemplary implementation of a regeneration circuit 150 according to certain aspects is shown. In this example, the regeneration circuit 150 includes a first input transistor 250, a second input transistor 255, a first switch 290, a second switch 295, a first inverter circuit 260, and a second inverter circuit 270. As discussed further below, the first inverter circuit 260 and the second inverter circuit 270 are cross-coupled during the regeneration phase to provide regenerative feedback. As used herein, an "inversion circuit" is a circuit configured to invert a logic state (i.e., a logic level or logic value) at an input of the inversion circuit and output the inverted logic state at an output of the inversion circuit. The logic state can be represented by a voltage, where a low voltage (e.g., approximately) can represent a logic state zero, and a high voltage (e.g., approximately a supply voltage) can represent a logic state one. In some aspects, the inverting circuit has a threshold voltage, wherein when the voltage at the input of the inverting circuit drops below the threshold voltage, the output of the inverting circuit transitions from low to high, and when the voltage at the input of the inverting circuit rises above the threshold voltage, the output of the inverting circuit transitions from high to low. The inverting circuit may also be referred to as an inverter, an inverting circuit, or another term.

[0040] The first inverter circuit 260 has an input 262, an output 264, a first power supply terminal 266, and a second power supply terminal 268. The second inverter circuit 270 has an input 272, an output 274, a first power supply terminal 276, and a second power supply terminal 278. The first power supply terminal 266 of the first inverter circuit 260 and the first power supply terminal 276 of the second inverter circuit 270 are coupled to an upper rail 280. The second power supply terminal 268 of the first inverter circuit 260 and the second power supply terminal 278 of the second inverter circuit 270 are coupled to a lower rail 285 (e.g., ground).

[0041] The first switch 290 is coupled between the input terminal 272 of the second inverter circuit 270 and the output terminal 264 of the first inverter circuit 260, and the second switch 295 is coupled between the input terminal 262 of the first inverter circuit 260 and the output terminal 274 of the second inverter circuit 270. When the first switch 290 and the second switch 295 are turned on, the first inverter circuit 260 and the second inverter circuit 270 are cross-coupled, wherein the input terminal 272 of the second inverter circuit 270 is coupled to the output terminal 264 of the first inverter circuit 260 through the first switch 290, and the input terminal 262 of the first inverter circuit 260 is coupled to the output terminal 274 of the second inverter circuit 270 through the second switch 295. As discussed further below, the first switch 290 and the second switch 295 are turned on during the regeneration phase to enable regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270, and the first switch 290 and the second switch 295 are turned off during the reset phase to disable regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270. Each of the first switch 290 and the second switch 295 may be implemented with a respective transistor (e.g., a respective NFET), a respective transmission gate, or another type of switch.

[0042] The first input transistor 250 is coupled between the input terminal 272 of the second inverter circuit 270 and the lower rail 285. The gate of the first input transistor 250 is coupled to the first input terminal 160 of the regeneration circuit 150. Therefore, the gate of the first input transistor 250 is configured to receive the first voltage DINT (i.e., the first input signal to the regeneration circuit 150). In one example, the first input transistor 250 is configured to turn on when the voltage DINT is higher than the threshold voltage of the first input transistor 250 and to turn off when the voltage DINT is lower than the threshold voltage of the first input transistor 250. Figure 2B In the example shown, the first input transistor 250 is implemented as an NFET, wherein the drain of the first input transistor 250 is coupled to the input terminal 272 of the second inverter circuit 270, and the source of the first input transistor 250 is coupled to the lower rail 285. In addition, the first switch 290 is coupled between the output terminal 264 of the first inverter circuit 260 and the drain of the first input transistor 250. It should be understood that the first input transistor 250 can also be implemented with another type of transistor. In this example, the first output terminal 170 is coupled to the output terminal 264 of the first inverter circuit 260.

[0043] The second input transistor 255 is coupled between the input terminal 262 of the first inverter circuit 260 and the lower rail 285. The gate of the second input transistor 255 is coupled to the second input terminal 165 of the regeneration circuit 150. Therefore, the gate of the second input transistor 255 is configured to receive the second voltage NDINT (i.e., the second input signal to the regeneration circuit 150). In one example, the second input transistor 255 is configured to turn on when the voltage NDINT is higher than the threshold voltage of the second input transistor 255 and to turn off when the voltage NDINT is lower than the threshold voltage of the second input transistor 255. Figure 2B In the example shown, the second input transistor 255 is implemented as an NFET, wherein the drain of the second input transistor 255 is coupled to the input terminal 262 of the first inverter circuit 260, and the source of the second input transistor 255 is coupled to the lower rail 285. In addition, the second switch 295 is coupled between the output terminal 274 of the second inverter circuit 270 and the drain of the second input transistor 255. It should be understood that the second input transistor 255 can also be implemented with another type of transistor. In this example, the second output terminal 175 is coupled to the output terminal 274 of the second inverter circuit 270.

[0044] exist Figure 2B In the example of , the first switch 290 has a control input 292 driven by a timing signal, and the second switch 295 has a control input 297 driven by a timing signal (e.g., a clock signal CLK). In one example, the first switch 290 and the second switch 295 are configured to be turned on when the timing signal is high and turned off when the timing signal is low. Therefore, in this example, when the first switch 230 in the input circuit 120 is turned on, the first switch 290 and the second switch 295 are turned on, and when the second switch 240 and the third switch 245 in the input circuit 120 are turned on, the first switch 290 and the second switch 295 are turned off. For examples in which each of the first switch 290 and the second switch 295 is implemented with a corresponding transistor, the control inputs 292 and 297 of each of the first switch 290 and the second switch 295 are located at the gate of the corresponding transistor. In one example, each of the first switch 290 and the second switch 295 can be implemented with a corresponding NFET.

[0045]

[0029] Example operation of sampler 110 will now be discussed according to certain aspects.

[0046] When the timing signal (e.g., clock signal CLK) is low, the sampler 110 is in a reset phase. In the reset phase, the first switch 230 in the input circuit 120 is turned off. Therefore, the first switch 230 decouples the first input transistor 210 and the second input transistor 220 of the input circuit 120 from the lower rail 285 (e.g., ground). The second switch 240 and the third switch 245 are turned on. Therefore, the second switch 240 couples the first output terminal 140 to the upper rail 280, and the third switch 245 couples the second output terminal 145 to the upper rail 280. This causes the input circuit 120 to pull up the first output terminal 140 and the second output terminal 145 to the supply voltage VCC on the upper rail 280. Therefore, the first voltage DINT input to the gate of the first input transistor 250 of the regeneration circuit 150 and the second voltage NDINT input to the gate of the second input transistor 255 of the regeneration circuit 150 are both pulled up to VCC in the reset phase.

[0047] Moreover, in the reset phase, the first switch 290 and the second switch 295 in the regeneration circuit 150 are turned off. Therefore, the regeneration feedback in the regeneration circuit 150 is disabled (i.e., the cross-coupling of the inverter circuits 260 and 270 is cut off). In addition, the first input transistor 250 and the second input transistor 255 of the regeneration circuit 150 are both turned on because the voltage DINT and the voltage NDINT are both pulled up to the supply voltage VCC (assuming that VCC is greater than the threshold voltage of the first input transistor 250 and the threshold voltage of the second input transistor 255). Therefore, the input terminals 262 and 272 of the inverter circuits 260 and 270 are pulled low (e.g., ground). This causes the output terminals 264 and 274 of the inverter circuits 260 and 270 to be pulled high. In this example, the first output terminal 170 and the second output terminal 175 of the regeneration circuit 150 are also pulled high.

[0048] When a timing signal (eg, clock signal CLK) transitions from low to high, sampler 110 transitions to a regeneration phase during which input circuit 120 senses a differential input signal (eg, a differential data signal) at input terminals 130 and 135 of input circuit 120 . Figure 3A An example of voltages DINT and NDINT during the regeneration phase is shown when the input voltage INP is higher than the input voltage INN (which may represent a bit value of one). In this example, the timing signal (e.g., clock signal CLK) transitions from low to high at time T1. Also, in this example, the first input transistor 250 and the second input transistor 255 have the same threshold voltage 310, which is shown in FIG.

[0049] At time T1, the first switch 230 is turned on, and the second switch 240 and the third switch 245 are turned off. This allows the first input transistor 210 to pull down the voltage DINT based on the input voltage INP at the first input transistor 210, and allows the second input transistor 220 to pull down the voltage NDINT based on the input voltage INN at the second input transistor 220. In this example, the voltage DINT is pulled down (i.e., at a faster rate than the voltage NDINT. This is because the first input transistor 210 is driven by a higher voltage than the second input transistor 220 (i.e., INP>INN) in this example.

[0050] At time T2, the voltage DINT drops below the threshold voltage 310, which turns off the first input transistor 250 of the regeneration circuit 150. The second input transistor 255 of the regeneration circuit 150 is still turned on at time T2 because the voltage NDINT is still above the threshold voltage at time T2. Starting from time T2, the regeneration feedback of the regeneration circuit 150 pulls up the first output terminal 170 and pulls down the second output terminal 175 (e.g., pulls the first output terminal 170 to the supply voltage VCC and pulls the second output terminal 175 to ground). The pull-up of the first output terminal 170 and the pull-down of the second output terminal 175 produce a differential output voltage at the output terminals 170 and 175, where the output voltage OUTP is higher than the output voltage OUTN, which can represent a bit value of one.

[0051] Figure 3A The voltages DINT and NDINT are shown when the input voltage INP is higher than the input voltage INN. Figure 3B An example of voltages DINT and NDINT is shown where the input voltage INN is higher than the input voltage INP. In this case, during the regeneration phase, the voltage NDINT at the second output terminal 145 of the input circuit 120 drops at a faster rate than the voltage DINT at the first output terminal 140 of the input circuit 120. Therefore, the voltage NDINT drops below the threshold voltage 310 before the voltage DINT, causing the second input transistor 255 to turn off before the first input transistor 250. When this occurs, the regeneration feedback of the regeneration circuit 150 pulls up the second output terminal 175 and pulls down the first output terminal 170, thereby producing a large differential output voltage, where the output voltage OUTN is higher than the output voltage OUTP, which can represent a bit decision zero.

[0052] In both cases, it is desirable for the regeneration circuit 150 to quickly generate a large differential output voltage at the output terminals 170 and 175 during the regeneration phase to quickly resolve (i.e., capture) the bit value. A latch (e.g., an SR latch) coupled to the output terminals 170 and 175 of the regeneration circuit 150 can latch the resolved bit value, as discussed above. When the timing signal transitions from high back to low, the sampler 110 reenters the reset phase to reset the sampler 110 for the next bit value.

[0053] As discussed above, in Figure 2B In the example of , the first switch 290 and the second switch 295 are used to enable the regenerative feedback of the first inverting circuit 260 and the second inverting circuit 270 during the regeneration phase, and disable the regenerative feedback of the first inverting circuit 260 and the second inverting circuit 270 during the reset phase. The first switch 290 and the second switch 295 disable the regenerative feedback during the reset phase by cutting off the cross-coupling of the first inverting circuit 260 and the second inverting circuit 270 when the first switch 290 and the second switch 295 are turned off. However, it should be understood that the present disclosure is not limited to this example. In general, one or more switches placed at one or more locations in the regeneration circuit 150 can be used to enable or disable the regenerative feedback of the first inverting circuit 260 and the second inverting circuit 270, wherein the one or more switches are controlled by a timing signal (e.g., a clock signal CLK).

[0054] In this regard, Figure 2C An exemplary implementation is shown in which the regeneration circuit 150 includes a switch 296 coupled between the upper rail 280 and the supply terminals 266 and 276 of the inverter circuits 260 and 270. In this example, the Figure 2B A first switch 290 and a second switch 295 are shown, wherein the output 264 of the first inverter circuit 260 is coupled to the first input transistor 250, and the output 274 of the second inverter circuit 270 is coupled to the second input transistor 255. The switch 296 may be implemented with a PFET and has a control input 298 driven by the inversion of the timing signal (e.g., the inverted clock signal CLKb). In this example, the switch 296 is configured to be turned off during the reset phase and turned on during the regeneration phase. Turning off the switch 296 during the reset phase removes power from the upper rail 280 to the inverter circuits 260 and 270, which disables the regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270. It should be understood that the present disclosure is not limited to Figure 2B and Figure 2C Example shown.

[0055] Figure 4An example is shown in which the regeneration circuit 150 further includes a pull-up circuit 405 according to certain aspects. The pull-up circuit 405 is configured to provide an additional pull-up path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. According to certain aspects of the present disclosure, the pull-up circuit 405 includes a first pull-up transistor 410 and a second pull-up transistor 420.

[0056] exist Figure 4 In the example of FIG. 1 , the first pull-up transistor 410 is implemented with a first PFET and the second pull-up transistor 420 is implemented with a second PFET. The source of the first pull-up transistor 410 is coupled to the rail 280, the drain of the first pull-up transistor 410 is coupled to the input 262 of the first inverter circuit 260, and the gate of the first pull-up transistor 410 is coupled to the output 264 of the first inverter circuit 260. The source of the second pull-up transistor 420 is coupled to the rail 280, the drain of the second pull-up transistor 420 is coupled to the input 272 of the second inverter circuit 270, and the gate of the second pull-up transistor 420 is coupled to the output 274 of the second inverter circuit 270.

[0057]

[0046] Example operation of pull-up circuit 405 will now be discussed according to certain aspects.

[0058] When the voltage DINT drops faster than the voltage NDINT during the regeneration phase (e.g., INP>INN at the inputs 130 and 135 of the input circuit 120), the first input transistor 250 turns off before the second input transistor 255. This triggers the regenerative feedback of the regeneration circuit 150 to pull up the first output 170 and pull down the second output 175. Since the gate of the second pull-up transistor 420 is coupled to the second output 175, the pull-down of the second output 175 turns on the second pull-up transistor 420. This causes the second pull-up transistor 420 to pull up the input 272 of the second inverter circuit 270 toward the supply voltage VCC on the rail 280, which helps the second inverter circuit 270 drive the output 274 of the second inverter circuit 270 low. Since the output 274 of the second inverter circuit 270 is coupled to the second output 175, driving the output 274 of the second inverter circuit 270 low helps to further pull down the second output 175, thereby increasing the regeneration gain of the regeneration circuit 150. Therefore, in this case, the pull-up circuit 405 provides an additional pull-up path between the rail 280 and the input 272 of the second inverter circuit 270 during the regeneration phase, which increases the regeneration gain.

[0059] When the voltage NDINT drops faster than the voltage DINT during the regeneration phase (e.g., INN>INP at the inputs 130 and 135 of the input circuit 120), the second input transistor 255 turns off before the first input transistor 250. This triggers the regenerative feedback of the regeneration circuit 150 to pull up the second output 175 and pull down the first output 170. Since the gate of the first pull-up transistor 410 is coupled to the first output 170, the pull-down of the first output 170 turns on the first pull-up transistor 410. This causes the first pull-up transistor 410 to pull up the input 262 of the first inverter circuit 260 toward the supply voltage VCC on the rail 280, which helps the first inverter circuit 260 drive the output 264 of the first inverter circuit 260 low. Since the output 264 of the first inverter circuit 260 is coupled to the first output terminal 170, driving the output 264 of the first inverter circuit 260 lower helps to further pull down the first terminal 170, thereby increasing the regeneration gain of the regeneration circuit 150. Therefore, in this case, the pull-up circuit 405 provides an additional pull-up path between the rail 280 and the input terminal 262 of the first inverter circuit 260 during the regeneration phase, which increases the regeneration gain.

[0060] Therefore, the pull-up circuit 405 is configured to provide an additional pull-up path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. When the voltage DINT drops faster than the voltage NDINT (e.g., INP>INN), the pull-up path is located between the rail 280 and the input terminal 272 of the second inverter circuit 270, and when the voltage NDINT drops faster than the voltage DINT (e.g., INN>INP), the pull-up path is located between the rail 280 and the input terminal 262 of the first inverter circuit 260.

[0061] In order to further increase the regeneration gain of the regeneration circuit 150, a pull-down circuit may be added to the regeneration circuit 150. In this regard, Figure 5A An example is shown in which the regeneration circuit 150 further includes a pull-down circuit 505 according to certain aspects. The pull-down circuit 505 is configured to provide an additional pull-down path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150, which increases the signal strength at the output terminals 170 and 175 of the regeneration circuit 150. The pull-down circuit 505 can be used in combination with the pull-up circuit 405 to increase the regeneration gain, as discussed further below. According to certain aspects of the present disclosure, the pull-down circuit 505 includes a first pull-down transistor 510 and a second pull-down transistor 520.

[0062] exist Figure 5AIn the example of FIG. 1 , the first pull-down transistor 510 is implemented with a first NFET and the second pull-down transistor 520 is implemented with a second NFET. The drain of the first pull-down transistor 510 is coupled to the input 262 of the first inverter circuit 260, the source of the first pull-down transistor 510 is coupled to the lower rail 285 (e.g., ground), and the gate of the first pull-down transistor 510 is coupled to the input 272 of the second inverter circuit 270 and the first output 170. The drain of the second pull-down transistor 520 is coupled to the input 272 of the second inverter circuit 270, the source of the second pull-down transistor 520 is coupled to the lower rail 285, and the gate of the second pull-down transistor 520 is coupled to the input 262 of the first inverter circuit 260 and the second output 175. In other words, the first pull-down transistor 510 and the second pull-down transistor 520 are cross-coupled.

[0063]

[0046] Example operation of pull-down circuit 505 will now be discussed according to certain aspects.

[0064] When the voltage DINT drops faster than the voltage NDINT during the regeneration phase (e.g., INP>INN at the input terminals 130 and 135 of the input circuit 120), the first input transistor 250 turns off before the second input transistor 255. This triggers the regeneration feedback of the regeneration circuit 150 to pull up the first output terminal 170 and pull down the second output terminal 175. Since the gate of the first pull-down transistor 510 is coupled to the first output terminal 170, the pull-up of the first output terminal 170 turns on the first pull-down transistor 510. This causes the first pull-down transistor 510 to pull down the input terminal 262 of the first inverter circuit 260, which helps the first inverter circuit 260 drive the output terminal 264 high. Since the output terminal 264 of the first inverter circuit 260 is coupled to the first output terminal 170, driving the output terminal 264 of the first inverter circuit 260 high helps further pull up the first output terminal 170, thereby increasing the regeneration gain. Thus, in this case, the pull-down circuit 505 provides an additional pull-down path between the input 262 of the first inverter circuit 260 and the lower rail 285 (eg, ground) during the regeneration phase, which increases the regeneration gain.

[0065] When the voltage NDINT drops faster than the voltage DINT during the regeneration phase (e.g., INN>INP at the input terminals 130 and 135 of the input circuit 120), the second input transistor 255 turns off before the first input transistor 250. This triggers the regeneration feedback of the regeneration circuit 150 to pull up the second output terminal 175 and pull down the first output terminal 170. Since the gate of the second pull-down transistor 520 is coupled to the second output terminal 175, the pull-up of the second output terminal 175 turns on the second pull-down transistor 520. This causes the second pull-down transistor 520 to pull down the input terminal 272 of the second inverter circuit 270, which helps the second inverter circuit 270 drive the output terminal 274 high. Since the output terminal 274 of the second inverter circuit 270 is coupled to the second output terminal 175, driving the output terminal 274 of the second inverter circuit 270 high helps further pull up the second output terminal 175, thereby increasing the regeneration gain. Thus, in this case, the pull-down circuit 505 provides an additional pull-down path between the input 272 of the second inverter circuit 270 and the lower rail 285 (eg, ground) during the regeneration phase, which increases the regeneration gain.

[0066] Therefore, the pull-down circuit 505 is configured to provide an additional pull-down path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. When the voltage DINT drops faster than the voltage NDINT (e.g., INP>INN), the pull-down path is between the input terminal 262 of the first inverter circuit 260 and the lower rail 285 (e.g., ground), and when the voltage NDINT drops faster than the voltage DINT (e.g., INN>INP), the pull-down path is between the input terminal 272 of the second inverter circuit 270.

[0067] The pull-down circuit 505 can be used in combination with the pull-up circuit 405 to increase the regeneration gain of the regeneration circuit 150, which increases the signal strength at the output terminals 170 and 175 of the regeneration circuit 150. For example, when the voltage DINT drops faster than the voltage NDINT (e.g., INP>INN), the pull-up circuit 405 provides an additional pull-up path for pulling up the input terminal 272 of the second inverter circuit 270, while the pull-down circuit 505 provides an additional pull-down path for pulling down the input terminal 262 of the first inverter circuit 260. When the voltage NDINT drops faster than the voltage DINT (e.g., INN>INP), the pull-up circuit 405 provides an additional pull-up path for pulling up the input terminal 262 of the first inverter circuit 260, while the pull-down circuit 505 provides an additional pull-down path for pulling down the input terminal 272 of the second inverter circuit 270. Thus, in these aspects, pull-up circuit 405 pulls up the input of one of inverter circuits 260 and 270, and pull-down circuit 505 pulls down the input of the other of inverter circuits 260 and 270, depending on which of voltages DINT and NDINT drops faster, which in turn depends on input voltages INP and INN of input circuit 120.

[0068] Another advantage of the pull-up circuit 405 and the pull-down circuit 505 is that they continue to provide regeneration gain during the first portion of the reset phase before the input transistors 250 and 255 are turned on (i.e., before the input circuit 120 raises the voltages DINT and NDINT above the threshold voltages of the input transistors 250 and 255). This is because the pull-up circuit 405 and the pull-down circuit 505 continue to provide additional pull-up paths and additional pull-down paths even when the switches 290 and 295 are turned off by the timing signal (e.g., the clock signal CLK). The continued regeneration gain during the first portion of the reset phase allows the differential output voltage of the regeneration circuit 150 to continue to increase to better resolve the corresponding bit value.

[0069] It should be understood that the pull-down circuit 505 is not limited to Figure 5A In this regard, Figure 5B Another exemplary implementation is shown in which the gate of the first pull-down transistor 510 is coupled to the output 264 of the first inverter circuit 260 and the gate of the second pull-down transistor 520 is coupled to the output 274 of the second inverter circuit 270. Figure 5A In the exemplary implementation shown, pull-down transistors 510 and 520 in this example provide an additional pull-down path to increase regeneration gain.

[0070] As discussed above, the pull-up circuit 405 increases the regeneration gain of the regeneration circuit 150 by providing an additional pull-up path during the regeneration phase. The strength of the pull-up path can be increased by increasing the size (e.g., channel width) of the pull-up transistors 410 and 420 to further increase the regeneration gain of the regeneration circuit 150. However, increasing the size of the pull-up transistors 410 and 420 increases the reset time of the regeneration circuit 150, resulting in a tradeoff between regeneration and reset, as discussed further below.

[0071] At the beginning of the reset phase, the input circuit 120 raises the voltages DINT and NDINT, which are input to the input transistors 250 and 255 of the regeneration circuit 150. When the voltages DINT and NDINT rise to the threshold voltages of the input transistors 250 and 255, the input transistors 250 and 255 are turned on to pull both the input terminals 262 and 272 of the inverter circuits 260 and 270 low. However, one of the pull-up transistors 410 and 420 is initially turned on and resists the ability of the input transistors 250 and 255 to pull both the input terminals 262 and 272 of the inverter circuits 260 and 270 low, which increases the reset time. Increasing the size of the pull-up transistors 410 and 420 to further increase the regeneration gain exacerbates this problem by making it more difficult for the input transistors 250 and 255 to pull both the input terminals 262 and 272 of the inverter circuits 260 and 270 low to reset the regeneration circuit 150. Therefore, there is a tradeoff between regeneration and resetting associated with pull-up transistors 410 and 420 .

[0072] To solve the above problems, Figure 6 An example is shown where the regeneration circuit 150 also includes third and fourth input transistors 610 and 620 which ease the tradeoff between regeneration and reset and increase sensitivity as discussed further below. In this example, the regeneration circuit 150 also includes third and fourth switches 630 and 640.

[0073] The gate of the third input transistor 610 is coupled to the first input terminal 160 of the regeneration circuit 150 and thus receives the first voltage DINT. The third input transistor 610 and the third switch 630 are coupled in series between the rail 280 and the first output terminal 170 of the regeneration circuit 150. Figure 6In the example in which the third input transistor 610 is implemented with a corresponding PFET, wherein the source of the third input transistor 610 is coupled to the rail 280, and the third switch 630 is coupled between the drain of the third input transistor 610 and the first input transistor 250. For the example in which the third input transistor 610 is implemented with a corresponding PFET, the third input transistor 610 can be configured to turn on when the first voltage DINT drops below VCC-Vt3, where Vt3 is the threshold voltage of the third input transistor 610.

[0074] The third switch 630 has a control input 635 coupled to the input 262 of the first inverter circuit 260. In certain aspects, the third switch 630 is configured to turn on when the voltage at the control input 635 is below a threshold of the third switch 630, and to turn off when the voltage at the control input 635 is above a threshold of the third switch 630, as discussed further below. The third switch 630 may be implemented with a corresponding PFET or another type of switch.

[0075] The gate of the fourth input transistor 620 is coupled to the second input terminal 165 of the regeneration circuit 150 and thus receives the second voltage NDINT. The fourth input transistor 620 and the fourth switch 640 are coupled in series between the rail 280 and the second output terminal 175 of the regeneration circuit 150. Figure 6 , the fourth input transistor 620 is implemented with a corresponding PFET, wherein the source of the fourth input transistor 620 is coupled to the rail 280, and the fourth switch 640 is coupled between the drain of the fourth input transistor 620 and the second input transistor 255. For the example in which the fourth input transistor 620 is implemented with a corresponding PFET, the fourth input transistor 620 can be configured to turn on when the second voltage NDINT drops below VCC-Vt4, where Vt4 is the threshold voltage of the fourth input transistor 620. In some aspects, Vt3 and Vt4 can be approximately equal.

[0076] The fourth switch 640 has a control input 645 coupled to the input 272 of the second inverter circuit 270. In certain aspects, the fourth switch 640 is configured to turn on when the voltage at the control input 645 is below a threshold of the fourth switch 640, and to turn off when the voltage at the control input 645 is above a threshold of the fourth switch 640, as discussed further below. The fourth switch 640 can be implemented with a corresponding PFET or another type of switch.

[0077] Now we will discuss some aspects Figure 6 An exemplary operation of the exemplary regeneration circuit 150 is shown.

[0078] During the reset phase, the input circuit 120 pulls the voltages DINT and NDINT to the supply voltage VCC, as discussed above. This turns on the first input transistor 250 and the second input transistor 255 of the regeneration circuit 150, and pulls the input terminals 262 and 272 of the inverter circuits 260 and 270 low. This also turns off the third input transistor 610 and the fourth input transistor 620 of the regeneration circuit 150, because these transistors are implemented with PFETs in this example. Therefore, in this example, the input terminals 262 and 272 of the inverter circuits 260 and 270 are reset to low (e.g., approximately). In addition, both the third switch 630 and the fourth switch 640 are turned on. This is because the input transistors 610 and 620 pull the control input terminals 635 and 645 of the third switch 630 and the fourth switch 640 low during the reset phase.

[0079] When the sampler 110 transitions to the regeneration phase, a timing signal (e.g., a clock signal CLK) turns on the first switch 290 and the second switch 295, thereby enabling a regeneration feedback loop through the inverter circuits 260 and 270. At the beginning of the regeneration phase, both the first input transistor 250 and the second input transistor 255 are turned on, and both the third input transistor 610 and the fourth input transistor 620 are turned off. In addition, both the third switch 630 and the fourth switch 640 are turned on.

[0080] For the case where the input voltage INP is higher than the input voltage INN, the first voltage DINT drops (i.e., discharges) at a faster rate than the second voltage NDINT. This turns off the first input transistor 250 before the second input transistor 255, and turns on the third input transistor 610 before the fourth input transistor 620. The turning off of the first input transistor 250 triggers the regenerative feedback of the regeneration circuit 150 to pull up the first output terminal 170 and pull down the second output terminal 175 (e.g., pull the first output terminal 170 to the supply voltage VCC and pull the second output terminal 175 to the ground). The turning on of the third input transistor 610 causes the third input transistor 610 to pull up the first output terminal 170 through the third switch 630 (which is turned on). Therefore, in this case, the third input transistor 610 and the third switch 630 provide an additional pull-up path for pulling up the first output terminal 170, which increases the regeneration gain.

[0081] The pull-up of the first output terminal 170 turns off the fourth switch 640 because the control input terminal 645 of the fourth switch 640 is coupled to the first output terminal 170. This prevents the fourth input transistor 620 from pulling up the second output terminal 175 when the fourth input transistor 620 is eventually turned on (i.e., when NDINT drops below VCC-Vt4), thereby allowing the regeneration circuit 150 to regenerate to pull the second output terminal 175 low.

[0082] For the case where the input voltage INN is higher than the input voltage INP, the second voltage NDINT drops (i.e., discharges) at a faster rate than the first voltage DINT. This turns off the second input transistor 255 before the first input transistor 250, and turns on the fourth input transistor 620 before the third input transistor 610. The turning off of the second input transistor 255 triggers the regenerative feedback of the regeneration circuit 150 to pull up the second output terminal 175 and pull down the first output terminal 170 (e.g., pull the second output terminal 175 to the supply voltage VCC and pull the first output terminal 170 to the ground). The turning on of the fourth input transistor 620 causes the fourth input transistor 620 to pull up the second output terminal 175 through the fourth switch 640 (which is turned on). Therefore, in this case, the fourth input transistor 620 and the fourth switch 640 provide an additional pull-up path for pulling up the second output terminal 175, which increases the regeneration gain.

[0083] The pull-up of the second output terminal 175 turns off the third switch 630 because the control input terminal 635 of the third switch 630 is coupled to the second output terminal 175. This prevents the third input transistor 610 from pulling up the first output terminal 170 when the third input transistor 610 is eventually turned on (i.e., when DINT drops below VCC-Vt3), thereby allowing the regeneration circuit 150 to regenerate to pull the first output terminal 170 low.

[0084] Therefore, the third input transistor 610 and the fourth input transistor 620 provide an additional pull-up path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. For the case where the voltage DINT drops faster than the voltage NDINT (e.g., INP>INN), the third input transistor 610 provides an additional pull-up path between the first output terminal 170 and the rail 280 through the third switch 630. For the case where the voltage NDINT drops faster than the voltage DINT (e.g., INN>INP), the fourth input transistor 620 provides an additional pull-up path between the second output terminal 175 and the rail 280 through the fourth switch 640.

[0085] The third input transistor 610 and the fourth input transistor 620 allow the regeneration circuit 150 to achieve a higher regeneration gain without having to increase the size (e.g., channel width) of the first pull-up transistor 410 and the second pull-up transistor 420, which alleviates the trade-off between regeneration and reset associated with the pull-up transistors 410 and 420. This is because the third input transistor 610 and the fourth input transistor 620 provide an additional pull-up path during the regeneration phase in parallel with the additional pull-up path provided by the pull-up transistors 410 and 420. This increases the pull-up strength of the regeneration in the regeneration circuit 150 without having to increase the size of the first pull-up transistor 410 and the second pull-up transistor 420.

[0086] In addition, the input circuit 120 turns off both the third input transistor 610 and the fourth input transistor 620 during the reset phase, thereby allowing the first input transistor 250 and the second input transistor 255 to pull both the input terminals 262 and 272 of the inverter circuits 260 and 270 low during the reset phase to reset the regeneration circuit 150. This is because the input circuit 120 pulls the voltages DINT and NDINT to the supply voltage VCC during the reset phase, thereby turning off both the third input transistor 610 and the fourth input transistor 620. Once the input circuit 120 turns off the third input transistor 610 and the fourth input transistor 620 during the reset phase, these transistors no longer resist the ability of the first input transistor 250 and the second input transistor 255 to pull both the input terminals 262 and 272 of the inverter circuits 260 and 270 low during the reset phase. This further alleviates the tradeoff between regeneration and reset.

[0087] The third input transistor 610 and the fourth input transistor 620 also increase the sensitivity of the sampler 110. This is because the gates of the third input transistor 610 and the fourth input transistor 620 are driven by the voltages DINT and NDINT, respectively, generated based on the sensed input voltages INP and INN, respectively.

[0088] exist Figure 6 In the example shown, the third switch 630 is coupled between the third input transistor 610 and the first input transistor 250. However, it should be understood that the present disclosure is not limited to this example. For example, in some implementations, the third switch 630 may be coupled between the third input transistor 610 and the upper rail 280, wherein the third input transistor 610 is coupled between the third switch 630 and the first input transistor 250. Generally, the third input transistor 610 and the third switch 630 are coupled in series between the upper rail 280 and the first input transistor 250, wherein the third input transistor 610 or the third switch 630 is at the top. Also, in some implementations, the fourth switch 640 may be coupled between the fourth input transistor 620 and the upper rail 280, wherein the fourth input transistor 620 is coupled between the fourth switch 640 and the second input transistor 255. Generally, the fourth input transistor 620 and the fourth switch 640 are coupled in series between the upper rail 280 and the second input transistor 255, wherein the fourth input transistor 620 or the fourth switch 640 is at the top.

[0089] Figure 72 shows an exemplary implementation of the third switch 630 and the fourth switch 640. In this example, the third switch 630 is implemented with a first PFET 710 coupled between the drain of the third input transistor 610 and the first input transistor 250, wherein the gate of the first PFET 710 is coupled to the input terminal 262 of the first inverter circuit 260. Also, in this example, the fourth switch 640 includes a second PFET 720 coupled between the drain of the fourth input transistor 620 and the second input transistor 255, wherein the gate of the second PFET 720 is coupled to the input terminal 272 of the second inverter circuit 270. It should be understood that the third switch 630 and the fourth switch 640 are not limited to Figure 7 The exemplary implementation shown, and each of the third switch 630 and the fourth switch 640 may be implemented with another type of transistor, a transmission gate, or another type of switch.

[0090] Figure 8 An example is shown in which the first switch 290 is implemented with a first NFET 810 and the second switch 295 is implemented with a second NFET 820. In this example, one of the source and the drain of the first NFET 810 is coupled to the first input transistor 250 (e.g., the drain of the first input transistor 250), the other of the source and the drain of the first NFET 810 is coupled to the output terminal 264 of the first inverter circuit 260, and the gate of the first NFET 810 is coupled to the control input terminal 292 to receive a timing signal (e.g., the clock signal CLK). One of the source and the drain of the second NFET 820 is coupled to the second input transistor 255 (e.g., the drain of the second input transistor 255), the other of the source and the drain of the second NFET 820 is coupled to the output terminal 274 of the second inverter circuit 270, and the gate of the second NFET 820 is coupled to the control input terminal 297 to receive a timing signal (e.g., the clock signal CLK). In this example, the first switch 290 and the second switch 295 are turned on when the timing signal is high and turned off when the timing signal is low. It should be understood that the first switch 290 and the second switch 295 are not limited to Figure 8 The exemplary implementation shown, and each of the first switch 290 and the second switch 295 may be implemented with another type of transistor, a transmission gate, or another type of switch.

[0091] exist Figures 4 to 8 In the example shown, the regeneration circuit 150 includes a first switch 290 and a second switch 295 for enabling the regeneration feedback of the inverter circuits 260 and 270 during the regeneration phase and disabling the regeneration feedback of the inverter circuits 260 and 270 during the reset phase. However, it should be understood that the present disclosure is not limited to this example. For example, in other specific implementations, Figure 2CThe illustrated switch 296 may be used to enable or disable regenerative feedback of the inverter circuits 260 and 270, wherein the first switch 290 and the second switch 295 are omitted. In this example, the output 264 of the first inverter circuit 260 is coupled to the first input transistor 250, and the input 274 of the second inverter circuit 270 is coupled to the second input transistor 255. In general, one or more switches may be placed at one or more locations in the regeneration circuit 150 to enable or disable regenerative feedback of the inverter circuits 260 and 270.

[0092] Fig. 9A An exemplary implementation of a first inverter circuit 260 according to certain aspects is shown. In this example, the first inverter circuit 260 is a complementary inverter circuit including a PFET 910 and an NFET 920. The source of the PFET 910 is coupled to a first power supply terminal 266, the drain of the PFET 910 is coupled to an output terminal 264, and the gate of the PFET 910 is coupled to an input terminal 262. The drain of the NFET 920 is coupled to the output terminal 264, the gate of the NFET 920 is coupled to the input terminal 262, and the source of the NFET 920 is coupled to a second power supply terminal 268. It should be understood that the first inverter circuit 260 is not limited to Fig. 9A Example shown.

[0093] Fig. 9B 9 shows an exemplary implementation of a second inverter circuit 270 according to certain aspects. In this example, the second inverter circuit 270 is a complementary inverter circuit including a PFET 930 and an NFET 940. The source of the PFET 930 is coupled to the first power supply terminal 276, the drain of the PFET 930 is coupled to the output terminal 274, and the gate of the PFET 930 is coupled to the input terminal 272. The drain of the NFET 940 is coupled to the output terminal 274, the gate of the NFET 940 is coupled to the input terminal 272, and the source of the NFET 940 is coupled to the second power supply terminal 278. It should be understood that the second inverter circuit 270 is not limited to Fig. 9B Example shown.

[0094] Fig.10An exemplary implementation of a first switch 230, a second switch 240, and a third switch 245 in an input circuit 120 according to certain aspects is shown. In this example, the first switch 230 is implemented with an NFET 1010, wherein the drain of the NFET 1010 is coupled to the sources of the input transistors 210 and 220, the gate of the NFET 1010 is coupled to the control input 235, and the source of the NFET 1010 is coupled to a lower rail 285 (e.g., ground). The second switch 240 is implemented with a first PFET 1015, wherein the source of the first PFET 1015 is coupled to the upper rail 280, the gate of the first PFET 1015 is coupled to the control input 242, and the drain of the first PFET 1015 is coupled to the drain of the first input transistor 210. The third switch 245 is implemented with a second PFET 1020, wherein the source of the second PFET 1020 is coupled to the upper rail 280, the gate of the second PFET 1020 is coupled to the control input 247, and the drain of the second PFET 1020 is coupled to the drain of the second input transistor 220. In this example, the first switch 230 is turned on when the timing signal is high and is turned off when the timing signal is low. Also, in this example, the second switch 240 and the third switch 245 are turned on when the timing signal is low and are turned off when the timing signal is high. It should be understood that the first switch 230, the second switch 240, and the third switch 245 are not limited to Fig.10 An exemplary implementation is shown.

[0095] Fig.11 An example of a system 1105 in which aspects of the present disclosure may be used is shown. In this example, the system 1105 includes a first chip 1110 and a second chip 1115, wherein a SerDes may be used for communication between the first chip 1110 and the second chip 1115. The first chip 1110 includes a serializer 1120, a driver 1130, a first output pin 1140, and a second output pin 1142. The second chip 1115 includes a first receive pin 1150, a second receive pin 1152, a receiver 1160, a sampler 110, a latch 1170, and a deserializer 1180.

[0096] In this example, the first chip 1110 and the second chip 1115 are coupled via a differential serial link including a first line 1144 and a second line 1146. The first line 1144 is coupled between the first output pin 1140 and the first receive pin 1150, and the second line 1146 is coupled between the second output pin 1142 and the second receive pin 1152. The first line 1144 and the second line 1146 can each be implemented with metal lines, wires, etc. on a substrate (e.g., a printed circuit board).

[0097] On the first chip 1110, the serializer 1120 is configured to receive a parallel data stream (e.g., from a processor on the first chip 1110) and convert the parallel data stream into a serial data stream, which is output at an output terminal 1125 of the serializer 1120. The driver 1130 has an input terminal 1132 coupled to the output terminal 1125 of the serializer 1120, a first output terminal 1134 coupled to a first output pin 1140, and a second output terminal 1136 coupled to a second output pin 1142. The driver 1130 is configured to receive the serial data stream, convert the serial data stream into a differential signal, and drive a first line 1144 and a second line 1146 of a differential serial link with the differential data signal to send the differential signal to the second chip 1115. It should be understood that the first chip 1110 may include Fig.11 Additional components not shown in FIG. 11 (eg, an impedance matching network coupled to output pins 1140 and 1142, a pre-driver coupled between serializer 1120 and driver 1130, etc.).

[0098] On the second chip 1115, the receiver 1160 has a first input 1162 coupled to the first receive pin 1150, a second input 1164 coupled to the second receive pin 1152, a first output 1166 coupled to the first input 130 of the sampler 110, and a second output 1168 coupled to the second input 135 of the sampler 110. The receiver 1160 may include at least one of an amplifier and an equalizer (e.g., to compensate for frequency-dependent signal attenuation between the first chip 1110 and the second chip 1115). The sampler 110 receives the differential signal from the receiver 1160 and makes a bit decision based on the differential signal, as discussed above.

[0099] exist Fig.11 In the example of , the first output 170 of the sampler 110 is coupled to the first input 1172 of the latch 1170, and the second output 175 of the sampler 110 is coupled to the second input 1174 of the latch 1170. The latch 1170 has an output 1176 coupled to an input 1182 of the deserializer 1180. The latch 1170 is configured to latch the bit decisions from the sampler 110 and output the corresponding bits to the deserializer 1180. The deserializer 1180 is configured to convert the bits into parallel data streams, which can be output to one or more components (not shown) on the second chip 1115 for further processing. It should be understood that the second chip 1115 may include Fig.11 Additional components not shown (eg, impedance matching networks coupled to receive pins 1150 and 1152, clock recovery circuits, etc.) may be included.

[0100] exist Fig.11In the example in FIG. 1 , the second chip 1115 further includes a timing signal circuit 1190 configured to generate a timing signal (e.g., a clock signal CLK) for the sampler 110 and output the timing signal at an output terminal 1194. The output terminal 1194 can be coupled to the control input terminals of the switches 230, 240, and 245 in the input circuit 120 of the sampler 110 and the control input terminals of the switches 290 and 295 in the regeneration circuit 150.

[0101] In some aspects, the timing signal circuit 1190 may use clock data recovery to recover a timing signal (e.g., clock signal CLK) based on the bit decision of the sampler 110. The input terminal 1192 of the timing signal circuit 1190 may be coupled to the output terminal ( Fig.11 ), or may be coupled to one or both outputs 170 and 175 of sampler 110 to receive a bit decision.

[0102] In some aspects, the timing signal circuit 1190 may include a clock generator, which may include a phase-locked loop (PLL), a delay-locked loop (DLL), an oscillator, or any combination thereof to generate a timing signal (e.g., a clock signal CLK). It should be understood that the timing signal circuit 1190 may be implemented using various types of clock generators.

[0103] Fig.12 A method 1200 of operating a regeneration circuit of a sampler according to certain aspects is illustrated. The regeneration circuit (e.g., regeneration circuit 150) includes a first inverter circuit (e.g., first inverter circuit 260) having an input and an output, a second inverter circuit (e.g., second inverter circuit 270) having an input and an output, a first transistor (e.g., first input transistor 250) coupled to the input of the second inverter circuit, a second transistor (e.g., second input transistor 255) coupled to the input of the first inverter circuit, a third transistor (e.g., third input transistor 610), and a fourth transistor (e.g., fourth input transistor 620).

[0104] At block 1210, during the reset phase, regenerative feedback of the first inverter circuit and the second inverter circuit is disabled. For example, disabling regenerative feedback of the first inverter circuit and the second inverter circuit may include: decoupling the output of the first inverter circuit from the first transistor, and decoupling the output of the second inverter circuit from the second transistor. For example, the output of the first inverter circuit may be decoupled from the first transistor by turning off the first switch 290 (e.g., using a timing signal), and the output of the second inverter circuit may be decoupled from the second transistor by turning off the second switch 295 (e.g., using a timing signal). In another example, disabling regenerative feedback of the first inverter circuit and the second inverter circuit may include: turning off Figure 2CSwitch 296 is shown.

[0105] At block 1220, during the regeneration phase, regenerative feedback of the first inverter circuit and the second inverter circuit is enabled. For example, enabling regenerative feedback of the first inverter circuit and the second inverter circuit may include coupling an output of the first inverter circuit to the first transistor, and coupling an output of the second inverter circuit to the second transistor. For example, the output of the first inverter circuit may be coupled to the first transistor by turning on the first switch 290 (e.g., using a timing signal), and the output of the second inverter circuit may be coupled to the second transistor by turning on the second switch 295 (e.g., using a timing signal). In another example, enabling regenerative feedback of the first inverter circuit and the second inverter circuit may include turning on Figure 2C Switch 296 is shown.

[0106] At block 1230, during the regeneration phase, the gate of the first transistor and the gate of the third transistor are driven with the first voltage. For example, the input circuit 120 may drive the gate of the first transistor and the gate of the third transistor with the first voltage DINT.

[0107] At block 1240, during the regeneration phase, the gate of the second transistor and the gate of the fourth transistor are driven with the second voltage. For example, the input circuit 120 may drive the gate of the second transistor and the gate of the fourth transistor with the second voltage NDINT.

[0108] At block 1250, during the regeneration phase, a third transistor is coupled to the output of the first inverter circuit, or a fourth transistor is coupled to the output of the second inverter circuit. For example, the third switch 630 may couple the third transistor to the output of the first inverter circuit, or the fourth switch 640 may couple the fourth transistor to the output of the second inverter circuit.

[0109] In some aspects, during the regeneration phase, the first voltage decreases at a first rate, the second voltage decreases at a second rate, and the first rate is different from the second rate. For example, the first rate may be based on a first input signal (e.g., INP) to the sampler, and the second rate may be based on a second input signal (e.g., INN) to the sampler. In one example, the first input transistor 210 of the input circuit 120 may discharge the first node 222 based on the first input signal INP, thereby causing the first voltage DINT to decrease at a first rate, and the second input transistor 220 of the input circuit 120 may discharge the second node 224 based on the second input signal INN, thereby causing the second voltage NDINT to decrease at a second rate. In this example, the gate of the first input transistor 210 may be driven by the first input signal INP, and the gate of the second input transistor 220 may be driven by the second input signal INN.

[0110] In some aspects, if the first input signal is greater than the second input signal (e.g., INP>INN), the first rate is greater than the second rate, and if the second input signal is greater than the first input signal (e.g., INN>INP), the second rate is greater than the first rate.

[0111] In some aspects, coupling the third transistor to the output of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit includes: coupling the third transistor to the output of the first inverter circuit based on a voltage at the input of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit based on a voltage at the input of the second inverter circuit. For example, the control input 635 of the third switch 630 can be coupled to the input 262 of the first inverter circuit 260, and the control input 645 of the fourth switch 640 can be coupled to the input 272 of the second inverter circuit 270.

[0112] The method 1200 may further include: during the reset phase, pulling up the first voltage and the second voltage to the supply voltage. For example, during the reset phase, the first voltage DINT and the second voltage NDINT may be pulled up to the supply voltage VCC by turning on the second switch 240 and the third switch 245 of the input circuit 120.

[0113] Specific implementation examples are described in the following numbered clauses:

[0114] 1. A regeneration circuit, comprising:

[0115] A first inverting circuit, wherein the first inverting circuit has an input terminal and an output terminal;

[0116] a second inverting circuit, the second inverting circuit having an input terminal and an output terminal;

[0117] a first transistor coupled to the input terminal of the second inverter circuit, wherein a gate of the first transistor is coupled to a first input terminal;

[0118] a second transistor coupled to the input terminal of the first inverter circuit, wherein a gate of the second transistor is coupled to a second input terminal;

[0119] a third transistor, wherein a gate of the third transistor is coupled to the first input terminal;

[0120] a fourth transistor, wherein a gate of the fourth transistor is coupled to the second input terminal;

[0121] a first switch, wherein the first switch and the third transistor are coupled in series between a first rail and the first transistor; and

[0122] A second switch, wherein the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

[0123] 2. A regeneration circuit according to clause 1, wherein:

[0124] The first switch is coupled between a drain of the third transistor and a drain of the first transistor; and

[0125] The second switch is coupled between a drain of the fourth transistor and a drain of the second transistor.

[0126] 3. A regeneration circuit according to clause 2, wherein:

[0127] a source of the third transistor coupled to the first rail;

[0128] a source of the fourth transistor coupled to the first rail;

[0129] The source of the first transistor is coupled to a second rail; and

[0130] The source of the second transistor is coupled to the second rail.

[0131] 4. The regeneration circuit of clause 3, wherein the second rail is coupled to ground.

[0132] 5. A regeneration circuit according to any one of clauses 1 to 4, wherein:

[0133] The first transistor comprises a first n-type field effect transistor (NFET);

[0134] The second transistor comprises a second NFET;

[0135] The third transistor comprises a first p-type field effect transistor (PFET); and

[0136] The fourth transistor includes a second PFET.

[0137] 6. A regeneration circuit according to any one of clauses 1 to 5, wherein:

[0138] The first switch has a control input coupled to the input of the first inverter circuit; and

[0139] The second switch has a control input coupled to the input of the second inverter circuit.

[0140] 7. A regeneration circuit according to clause 6, wherein:

[0141] The first switch includes a first p-type field effect transistor (PFET) having a gate coupled to the input of the first inverter circuit; and

[0142] The second switch includes a second PFET having a gate coupled to the input of the second inverter circuit.

[0143] 8. The regeneration circuit according to any one of clauses 1 to 7, further comprising:

[0144] a third switch coupled between the first transistor and the output terminal of the first inverter circuit; and

[0145] A fourth switch is coupled between the second transistor and the output terminal of the second inverter circuit.

[0146] 9. A regeneration circuit according to clause 8, wherein:

[0147] The third switch has a control input configured to receive a timing signal; and

[0148] and

[0149] The fourth switch has a control input configured to receive the timing signal.

[0150] 10. The regeneration circuit of clause 9, wherein the timing signal comprises a clock signal.

[0151] 11. A regeneration circuit, comprising:

[0152] A first inverting circuit, wherein the first inverting circuit has an input terminal and an output terminal;

[0153] a second inverting circuit, the second inverting circuit having an input terminal and an output terminal;

[0154] a first transistor coupled to the input terminal of the second inverter circuit, wherein a gate of the first transistor is coupled to a first input terminal;

[0155] a second transistor coupled to the input terminal of the first inverter circuit, wherein a gate of the second transistor is coupled to a second input terminal;

[0156] a pull-up circuit coupled to the input terminal of the first inverter circuit and the input terminal of the second inverter circuit; and

[0157] A pull-down circuit is coupled to the input terminal of the first inverter circuit and the input terminal of the second inverter circuit.

[0158] 12. The regeneration circuit of clause 11, wherein the pull-up circuit comprises:

[0159] a third transistor coupled between the input of the first inverter circuit and a rail, wherein a gate of the third transistor is coupled to the output of the first inverter circuit; and

[0160] A fourth transistor is coupled between the input of the second inverter circuit and the rail, wherein a gate of the fourth transistor is coupled to the output of the second inverter circuit.

[0161] 13. A regeneration circuit according to clause 12, wherein:

[0162] The third transistor comprises a first p-type field effect transistor (PFET); and

[0163] The fourth transistor includes a second PFET.

[0164] 14. A regeneration circuit according to clause 13, wherein:

[0165] a source of the first PFET coupled to the rail and a drain of the first PFET coupled to the input of the first inverter circuit; and

[0166] The source of the second PFET is coupled to the rail, and the drain of the second PFET is coupled to the input of the second inverter circuit.

[0167] 15. The regeneration circuit of clause 11, wherein the pull-down circuit comprises:

[0168] a third transistor coupled between the input of the first inverter circuit and a rail, wherein a gate of the third transistor is coupled to the input of the second inverter circuit or the output of the first inverter circuit; and

[0169] a fourth transistor coupled between the input terminal of the second inverter circuit and the rail, wherein a gate of the fourth transistor is coupled to the

[0170] The input end of the first inverting circuit or the output end of the second inverting circuit.

[0171] 16. A regeneration circuit according to clause 15, wherein:

[0172] The third transistor comprises a first n-type field effect transistor (NFET); and

[0173] The fourth transistor includes a second NFET.

[0174] 17. A regeneration circuit according to clause 16, wherein:

[0175] The drain of the first NFET is coupled to the input of the first inverter circuit and the source of the first NFET is coupled to the rail; and

[0176] The drain of the second NFET is coupled to the input of the second inverter circuit, and the source of the second NFET is coupled to the rail.

[0177] 18. A regeneration circuit according to any of clauses 15 to 17, wherein the track is coupled to ground.

[0178] 19. The regeneration circuit of any one of clauses 11 to 18, further comprising:

[0179] a first switch coupled between the first transistor and the output terminal of the first inverter circuit; and

[0180] A second switch is coupled between the second transistor and the output terminal of the second inverter circuit.

[0181] 20. The regeneration circuit of clause 19, wherein:

[0182] The first switch has a control input configured to receive a timing signal; and

[0183] and

[0184] The second switch has a control input configured to receive the timing signal.

[0185] 21. A method of operating a regeneration circuit of a sampler, wherein the regeneration circuit comprises a first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, a second transistor coupled to the input of the first inverter circuit, a third transistor, and a fourth transistor, the method comprising:

[0186] During the reset phase,

[0187] disabling regenerative feedback of the first inverter circuit and the second inverter circuit;

[0188] During the regeneration phase,

[0189] enabling the regenerative feedback of the first inverter circuit and the second inverter circuit;

[0190] driving a gate of the first transistor and a gate of the third transistor with a first voltage;

[0191] driving a gate of the second transistor and a gate of the fourth transistor with a second voltage; and

[0192] The third transistor is coupled to the output terminal of the first inverter circuit or the fourth transistor is coupled to the output terminal of the second inverter circuit.

[0193] 22. The method of clause 21, wherein during the regeneration phase, the first voltage decreases at a first rate, the second voltage decreases at a second rate, and the first rate is different from the second rate.

[0194] 23. The method of clause 22, wherein the first rate is based on a first input signal to the sampler and the second rate is based on a second input signal to the sampler.

[0195] 24. The method of clause 23, wherein the first rate is greater than the second rate if the first input signal is greater than the second input signal, and the second rate is greater than the first rate if the second input signal is greater than the first input signal.

[0196] 25. The method of any of clauses 22 to 24, coupling the third transistor to the output of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit comprising:

[0197] If the first rate is greater than the second rate, coupling the third transistor to the output of the first inverter circuit; and

[0198] If the second rate is greater than the first rate, the fourth transistor is coupled to the output of the second inverter circuit.

[0199] 26. The method of any of clauses 22 to 25, coupling the third transistor to the output of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit comprising:

[0200] The third transistor is coupled to the output terminal of the first inverter circuit based on a voltage at the input terminal of the first inverter circuit or the fourth transistor is coupled to the output terminal of the second inverter circuit based on a voltage at the input terminal of the second inverter circuit.

[0201] 27. The method of any of clauses 21 to 26, further comprising: during the reset phase, pulling the first voltage and the second voltage up to a supply voltage.

[0202] 28. A method according to any one of clauses 21 to 27, wherein:

[0203] The first transistor comprises a first n-type field effect transistor (NFET);

[0204] The second transistor comprises a second NFET;

[0205] The third transistor comprises a first p-type field effect transistor (PFET); and

[0206] The fourth transistor includes a second PFET.

[0207] 29. A method according to any one of clauses 21 to 28, wherein:

[0208] Disabling the regenerative feedback of the first inverter circuit and the second inverter circuit includes:

[0209] decoupling the output of the first inverter circuit from the first transistor; and

[0210] decoupling the output of the second inverter circuit from the second transistor; and

[0211] Enabling the regenerative feedback of the first inverter circuit and the second inverter circuit includes:

[0212] coupling the output of the first inverter circuit to the first transistor; and

[0213] The output terminal of the second inverter circuit is coupled to the second transistor.

[0214] 30. A regeneration circuit according to any of clauses 12 to 14, wherein the pull-down circuit comprises:

[0215] a fifth transistor coupled between the input of the second inverter circuit and a second rail, wherein a gate of the fifth transistor is coupled to the input of the second inverter circuit or the output of the first inverter circuit; and

[0216] A sixth transistor is coupled between the input of the second inverter circuit and the second rail, wherein a gate of the sixth transistor is coupled to the input of the first inverter circuit or the output of the second inverter circuit.

[0217] 31. A regeneration circuit according to clause 30, wherein:

[0218] The fifth transistor comprises a first n-type field effect transistor (NFET); and

[0219] The sixth transistor includes a second NFET.

[0220] 32. A regeneration circuit according to clause 31, wherein:

[0221] The drain of the first NFET is coupled to the input of the first inverter circuit and the source of the first NFET is coupled to the rail; and

[0222] The drain of the second NFET is coupled to the input of the second inverter circuit, and the source of the second NFET is coupled to the rail.

[0223] 33. A regeneration circuit according to any of clauses 30 to 32, wherein the second rail is coupled to ground.

[0224] It should be understood that the present disclosure is not limited to the exemplary terms used above to describe aspects of the present disclosure.

[0225] Any reference to an element using designations such as "first", "second", etc. herein does not generally limit the number or order of those elements. Specifically, these designations are used herein as a convenient method to distinguish two or more elements or element instances. Thus, the reference to a first element and a second element does not mean that only two elements can be used, or that the first element must be located before the second element. In addition, it should be understood that the references "first", "second", etc. in the written description do not have to match the references "first", "second", etc. in the claims.

[0226] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "about," as used herein with respect to a specified value or property, is intended to indicate within 10% of the specified value or property.

[0227] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A regeneration circuit, comprising: A first inverter circuit, the first inverter circuit having an input terminal and an output terminal; a second inverting circuit, the second inverting circuit having an input terminal and an output terminal; a first transistor coupled to the input terminal of the second inverter circuit, wherein a gate of the first transistor is coupled to a first input terminal; a second transistor coupled to the input terminal of the first inverter circuit, wherein a gate of the second transistor is coupled to a second input terminal; a third transistor, wherein a gate of the third transistor is coupled to the first input terminal; a fourth transistor, wherein a gate of the fourth transistor is coupled to the second input terminal; a first switch, wherein the first switch and the third transistor are coupled in series between a first rail and the first transistor; and A second switch, wherein the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

2. The regeneration circuit according to claim 1, wherein: The first switch is coupled between a drain of the third transistor and a drain of the first transistor; and The second switch is coupled between a drain of the fourth transistor and a drain of the second transistor.

3. The regeneration circuit according to claim 2, wherein: a source of the third transistor coupled to the first rail; a source of the fourth transistor coupled to the first rail; The source of the first transistor is coupled to a second rail; and The source of the second transistor is coupled to the second rail.

4. The regeneration circuit of claim 3, wherein the second rail is coupled to ground.

5. The regeneration circuit according to claim 1, wherein: The first transistor comprises a first n-type field effect transistor (NFET); The second transistor comprises a second NFET; The third transistor comprises a first p-type field effect transistor (PFET); and The fourth transistor includes a second PFET.

6. The regeneration circuit according to claim 1, wherein: The first switch has a control input coupled to the input of the first inverter circuit; and The second switch has a control input coupled to the input of the second inverter circuit.

7. The regeneration circuit according to claim 6, wherein: The first switch includes a first p-type field effect transistor (PFET) having a gate coupled to the input of the first inverter circuit; and The second switch includes a second PFET having a gate coupled to the input of the second inverter circuit.

8. The regeneration circuit according to claim 1, further comprising: a third switch coupled between the first transistor and the output terminal of the first inverter circuit; and A fourth switch is coupled between the second transistor and the output terminal of the second inverter circuit.

9. The regeneration circuit according to claim 8, wherein: The third switch has a control input configured to receive a timing signal; and The fourth switch has a control input configured to receive the timing signal.

10. The regeneration circuit of claim 9, wherein the timing signal comprises a clock signal.

11. A regeneration circuit, comprising: A first inverter circuit, the first inverter circuit having an input terminal and an output terminal; a second inverting circuit, the second inverting circuit having an input terminal and an output terminal; a first transistor coupled to the input terminal of the second inverter circuit, wherein a gate of the first transistor is coupled to a first input terminal; a second transistor coupled to the input terminal of the first inverter circuit, wherein a gate of the second transistor is coupled to a second input terminal; a pull-up circuit coupled to the input terminal of the first inverter circuit and the input terminal of the second inverter circuit; and A pull-down circuit is coupled to the input terminal of the first inverter circuit and the input terminal of the second inverter circuit.

12. The regeneration circuit according to claim 11, wherein the pull-up circuit comprises: a third transistor coupled between the input of the first inverter circuit and a rail, wherein a gate of the third transistor is coupled to the output of the first inverter circuit; and A fourth transistor is coupled between the input of the second inverter circuit and the rail, wherein a gate of the fourth transistor is coupled to the output of the second inverter circuit.

13. The regeneration circuit according to claim 12, wherein: The third transistor comprises a first p-type field effect transistor (PFET); and The fourth transistor includes a second PFET.

14. The regeneration circuit according to claim 13, wherein: a source of the first PFET coupled to the rail and a drain of the first PFET coupled to the input of the first inverter circuit; and The source of the second PFET is coupled to the rail, and the drain of the second PFET is coupled to the input of the second inverter circuit.

15. The regeneration circuit of claim 11, wherein the pull-down circuit comprises: a third transistor coupled between the input of the first inverter circuit and a rail, wherein a gate of the third transistor is coupled to the input of the second inverter circuit or the output of the first inverter circuit; and A fourth transistor is coupled between the input of the second inverter circuit and the rail, wherein a gate of the fourth transistor is coupled to the input of the first inverter circuit or the output of the second inverter circuit.

16. The regeneration circuit of claim 15, wherein: The third transistor comprises a first n-type field effect transistor (NFET); and The fourth transistor includes a second NFET.

17. The regeneration circuit of claim 16, wherein: The drain of the first NFET is coupled to the input of the first inverter circuit and the source of the first NFET is coupled to the rail; and The drain of the second NFET is coupled to the input of the second inverter circuit, and the source of the second NFET is coupled to the rail.

18. The regeneration circuit of claim 15, wherein the rail is coupled to ground.

19. The regeneration circuit according to claim 11, further comprising: a first switch coupled between the first transistor and the output terminal of the first inverter circuit; and A second switch is coupled between the second transistor and the output terminal of the second inverter circuit.

20. The regeneration circuit of claim 19, wherein: The first switch has a control input configured to receive a timing signal; and The second switch has a control input configured to receive the timing signal.

21. A method of operating a regeneration circuit of a sampler, wherein the regeneration circuit comprises a first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, a second transistor coupled to the input of the first inverter circuit, a third transistor, and a fourth transistor, the method comprising: During the reset phase, disabling regenerative feedback of the first inverter circuit and the second inverter circuit; During the regeneration phase, enabling the regenerative feedback of the first inverter circuit and the second inverter circuit; driving a gate of the first transistor and a gate of the third transistor with a first voltage; driving a gate of the second transistor and a gate of the fourth transistor with a second voltage; as well as The third transistor is coupled to the output terminal of the first inverter circuit or the fourth transistor is coupled to the output terminal of the second inverter circuit.

22. The method of claim 21, wherein during the regeneration phase, the first voltage decreases at a first rate, the second voltage decreases at a second rate, and the first rate is different from the second rate.

23. The method of claim 22, wherein the first rate is based on a first input signal to the sampler and the second rate is based on a second input signal to the sampler.

24. The method of claim 23, wherein the first rate is greater than the second rate if the first input signal is greater than the second input signal, and the second rate is greater than the first rate if the second input signal is greater than the first input signal.

25. The method of claim 22, wherein coupling the third transistor to the output terminal of the first inverter circuit or coupling the fourth transistor to the output terminal of the second inverter circuit comprises: coupling the third transistor to the output of the first inverter circuit if the first rate is greater than the second rate; as well as If the second rate is greater than the first rate, coupling the fourth transistor to the output of the second inverter circuit.

26. The method of claim 22, wherein coupling the third transistor to the output terminal of the first inverter circuit or coupling the fourth transistor to the output terminal of the second inverter circuit comprises: The third transistor is coupled to the output terminal of the first inverter circuit based on a voltage at the input terminal of the first inverter circuit or the fourth transistor is coupled to the output terminal of the second inverter circuit based on a voltage at the input terminal of the second inverter circuit.

27. The method according to claim 21, further comprising: During the reset phase, the first voltage and the second voltage are pulled up to a supply voltage.

28. The method of claim 21, wherein: The first transistor comprises a first n-type field effect transistor (NFET); The second transistor comprises a second NFET; The third transistor comprises a first p-type field effect transistor (PFET); and The fourth transistor includes a second PFET.

29. The method of claim 21, wherein: Disabling the regenerative feedback of the first inverter circuit and the second inverter circuit includes: decoupling the output of the first inverter circuit from the first transistor; and decoupling the output of the second inverter circuit from the second transistor; and Enabling the regenerative feedback of the first inverter circuit and the second inverter circuit includes: coupling the output of the first inverter circuit to the first transistor; and The output terminal of the second inverter circuit is coupled to the second transistor.

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