Process method for improving cutting wide line trace of monocrystalline silicon wafer

By optimizing cutting process parameters like line speed, table speed, and acceleration/deceleration time, the process reduces wide groove marks on silicon wafers, enhancing quality and reliability.

CN119175803AActive Publication Date: 2024-12-24JINWAN GAOJING SOLAR ENERGY TECH CO LTD +1

Patent Information

Application Number
CN202411401979.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-10-09
Publication Date
2024-12-24
Estimated Expiration
2044-10-09

AI Technical Summary

Technical Problem

The existing cutting process for single crystal silicon wafers results in wide groove marks due to changes in mortar liquid concentration, affecting the lubrication and cooling performance of diamond wire, leading to increased damage and reduced quality and reliability of silicon wafers.

Method used

Optimizes cutting process parameters such as line speed, table speed, acceleration and deceleration time, and cutting cycle by analyzing key parameters using models and force analysis to reduce wide groove marks.

Benefits of technology

Improves cutting quality and yield of silicon wafers by effectively reducing wide groove marks, making the process more stable and cost-effective.

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Abstract

The invention discloses a process method for improving cutting wide line marks of a monocrystalline silicon wafer. The process method comprises the following steps that S1, the maximum linear speed V1 is obtained according to a cutting period linear speed model and the Newton second law; s2, obtaining F1y according to the silicon wafer cutting stress model; s3, through the steps S1 and S2, the acceleration and deceleration time t of the well-cut grain width is measured; s4, according to the cutting process parameter model, obtaining that the grain width = cutting depth / (period * period time); s5, measuring the period of cutting the width of the good lines through the step S4; s6, according to the step S4 and the cutting process parameter model, the line width = the average machine speed * (the average line supply amount + the average line return amount) / the average line speed is obtained; and S7, the machine speed and the linear speed of the well-cut lines are measured through the step S6, the technological parameters such as the linear speed, the machine speed, the acceleration and deceleration time and the cutting period are optimized by analyzing the key parameters influencing the line marks, and the line marks generated in the cutting process are reduced.
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Description

Technical Field

[0001] The invention belongs to the technical field of single crystal silicon wafer manufacturing in the solar photovoltaic industry, and particularly relates to a process method for improving wide grain marks in cutting single crystal silicon wafers. Background Art

[0002] As a key semiconductor material, the production process of single crystal silicon has undergone a transformation from polycrystalline silicon to single crystal silicon, which is mainly achieved through the crystal pulling process. During the crystal pulling process, the molten elemental silicon crystallizes into single crystal silicon under specific conditions to form a columnar silicon ingot. Subsequently, these silicon ingots need to be divided into smaller blocks for further processing into thin silicon wafers. This cutting process usually uses diamond wire cutting technology. The diamond wire makes reciprocating linear motion during the cutting process, and the silicon block slowly sinks and is cut into thin slices by the diamond wire. During the cutting process, in order to ensure the cutting effect, it is necessary to continuously spray cutting fluid to assist the cutting operation. However, there are some shortcomings in the existing cutting process. First, in terms of auxiliary materials, as the silicon rod is continuously cut, the diamond wire will be worn, and the concentration of the mortar liquid (mixed by cutting fluid, pure water and silicon powder) will gradually increase, resulting in a decrease in the lubrication and cooling performance of the cutting fluid and the ability of the diamond wire to carry the mortar liquid. Secondly, in terms of equipment, due to the change in the concentration of the mortar liquid, the position and flow of the mortar pipe will also change, which further affects the cutting effect. Finally, in terms of process parameters, factors such as line speed, table speed, process cycle, and acceleration and deceleration time will have a significant impact on the cutting quality. The combined effect of these factors makes it difficult for the cutting process to achieve an ideal cutting state, resulting in increased damage to the surface of the silicon wafer, which is manifested as an increase in the proportion of wide groove marks. The presence of wide groove marks not only reduces the aesthetics of the silicon wafer, but more importantly, it affects the functionality and reliability of the silicon wafer, and further affects the quality and performance of the final product. Therefore, it is particularly important to find a new process that can effectively reduce or eliminate wide groove marks. The present invention is proposed in this context, and aims to improve the cutting quality and yield of silicon wafers by optimizing the cutting process. Summary of the invention

[0003] In order to overcome the deficiencies of the prior art, the present invention aims to provide a process method for improving the cutting of wide grain lines in single crystal silicon wafers, thereby improving the cutting quality and yield of silicon wafers by optimizing the cutting process.

[0004] To solve the above problems, the technical solution adopted by the present invention is as follows: A process method for improving the wide groove marks of single crystal silicon wafer cutting, comprising the following steps:

[0005] S1: The maximum linear velocity V1 is obtained based on the cutting cycle linear velocity model and Newton's second law;

[0006] S2: According to the silicon wafer cutting force model, F 1y ;

[0007] S3: Through the above steps S1 and S2, the acceleration and deceleration time t for cutting a good grain width is measured;

[0008] S4: According to the cutting process parameter model, the line width = cutting depth / (cycle * cycle time);

[0009] S5: measuring the period of the width of the good cut lines through the above step S4;

[0010] S6: Through the above step S4 and the cutting process parameter model, it is obtained that the line width = average table speed * (average wire supply amount + average wire return amount) / average wire speed;

[0011] S7: Measure the table speed and line speed for cutting good lines through the above step S6.

[0012] Compared with the prior art, the beneficial effect of the present invention is that the present invention analyzes the key parameters that affect the grain lines and proposes to optimize the cutting process parameters such as line speed, table speed, acceleration and deceleration time and cutting cycle, thereby effectively reducing the grain lines generated during the cutting process, thereby improving the overall quality of silicon wafers and reducing production costs. At the same time, it also helps to expand the operating range of the cutting process, making the process more stable and reliable.

[0013] In the above process method, the silicon wafer cutting force model in step S2 is the force analysis of the diamond wire swinging moment;

[0014] In the above process method, the line width in step S4 = cutting depth / number of cycles.

[0015] In the above process method, the number of cycles = cycle time * [average line speed / (average supply line quantity + average return line quantity)].

[0016] In the above process method, the cycle time in step S4 is: cutting depth / average table speed.

[0017] In the above process method, the line width in step S6 = average table speed / cycle.

[0018] In the above process method, the line speed is 2100 m / min, the table speed range is 2300 um / min-2500 um / min, and the cycle range is 1.25 n / min-1.38 n / min.

[0019] In the above-mentioned process method, the cycle is 1.28n / min, the table speed range is 2300um / min-2500um / min, and the line speed setting range is 2100m / min-2300m / min.

[0020] In the above process method, the acceleration and deceleration time t is 5.5s-6.5s. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A process diagram of an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the acceleration and deceleration force of the diamond wire of the present invention;

[0023] Figure 3 It is a schematic diagram of the force applied to the diamond wire of the present invention when it swings;

[0024] Figure 4 It is a schematic diagram of the force analysis of the diamond wire at the moment of swinging of the present invention.

[0025] Explanation of the accompanying drawings: 100 diamond wire, 200 silicon wafer. DETAILED DESCRIPTION

[0026] The embodiments of the present invention are described in detail below. Figures 1 to 4 The embodiment of the present invention provides a process for improving the wide-groove line marks of a single-crystal silicon wafer 200, comprising the following steps:

[0027] S1: The maximum linear velocity V1 is obtained based on the cutting cycle linear velocity model and Newton's second law;

[0028] S2: According to the silicon wafer cutting force model, F 1y ;

[0029] S3: Through the above steps S1 and S2, the acceleration and deceleration time t for cutting a good grain width is measured;

[0030] S4: According to the cutting process parameter model, the line width = cutting depth / (cycle * cycle time);

[0031] S5: measuring the cycle of cutting good grain width through the above step S4;

[0032] S6: Through the above step S4 and the cutting process parameter model, it is obtained that the line width = average table speed * (average wire supply amount + average wire return amount) / average wire speed;

[0033] S7: Measure the table speed and line speed for cutting good lines through the above step S6.

[0034] The present invention analyzes the key parameters that affect the grain marks and proposes to optimize the cutting process parameters such as line speed, table speed, acceleration and deceleration time and cutting cycle, thereby effectively reducing the grain marks generated during the cutting process, thereby improving the overall quality of silicon wafers and reducing production costs. It also helps to expand the operating range of the cutting process and make the process more stable and reliable.

[0035] Further, refer to Figure 1 The cutting cycle of the single crystal silicon wafer 200 is shown in the figure. The cutting principle of the single crystal silicon is: a high-strength fine steel wire or resin wire coated with an abrasive (usually diamond powder, hereinafter referred to as diamond wire 100) is used as a cutting tool. The diamond wire 100 moves back and forth in a guide system. At the same time, the abrasive is transported to the cutting area by high-pressure water or other liquids. Under the action of mechanical force, the diamond wire 100 drives the abrasive to grind the single crystal silicon, thereby achieving cutting. According to the above cutting principle and the cutting of the single crystal silicon wafer 200 cycle, when the linear velocity accelerates from 0 to V1, v1=at, and F=ma, so v1=(F / m)*t can be obtained. Since the linear velocity change within a cycle is composed of uniform acceleration (deceleration), uniform speed and pause, in relatively ideal conditions, during the uniform speed process, the force F on the diamond wire 100 is the same as the dynamic friction resistance f it is subjected to, while during the uniform acceleration and deceleration process, the diamond wire 100 must not only overcome the dynamic friction resistance f it is subjected to, but also provide an additional force greater than f to enable it to achieve a uniform acceleration (deceleration) motion state. Therefore, the force F on the diamond wire 100 during the acceleration and deceleration process is much greater than that during the uniform speed state. Therefore, this application mainly analyzes the force F on the diamond wire 100 during acceleration and deceleration, with reference to Figure 2 and Figure 3 During the cutting process, the force F of the diamond wire 100 will fluctuate left and right due to the fluctuation of tension and the interference of the mortar liquid. Figure 2 Force diagram, force F is always along the direction of diamond wire 100, refer to Figure 3 , at the moment of swing, when the force F decreases, refer to Figure 4, the component force F1y acting on the surface of the silicon wafer 200 will also decrease accordingly, that is, the acceleration and deceleration time t will increase accordingly, the force acting on the surface of the silicon wafer 200 will decrease accordingly, and the effect on wide grain lines will be improved. Of course, the present invention is not limited to the specific value of the acceleration and deceleration time t. Preferably, when the acceleration and deceleration time t is 5.5s-6.5s, the grain line improvement effect is obvious. Furthermore, the force model of the silicon wafer 200 cutting in step S2 is the force analysis of the diamond wire 100 swinging at the moment. Therefore, when other conditions remain unchanged, the acceleration and deceleration time is increased, and the corresponding force F decreases, that is, the acceleration and deceleration time is appropriately increased, and the force acting on the surface of the silicon wafer 200 will decrease accordingly, which will improve the effect on wide grain lines. That is, through the above steps S1 and S2, the acceleration and deceleration time t for cutting a good grain width is measured.

[0036] Furthermore, according to the relationship between the line speed, table speed, grain width and cycle, a model of a slicer cutting a silicon wafer 200 is obtained. From the model of a slicer cutting a silicon wafer 200, it is concluded that: grain width = cutting depth / number of cycles, cycle = number of cycles / cycle time, and it can be concluded that: grain width = cutting depth / (cycle*cycle time). Further, the above formula is combined with the following two formulas: number of cycles = cycle time*[average line speed / (average supply line amount+average return line amount)] and cycle time = cutting depth / average table speed, and it can be concluded that: grain width = average table speed / Cycle and grain width = average table speed * (average wire supply + average wire return) / average line speed. Therefore, when the above formula: grain width = average table speed / cycle, under the condition that all conditions remain unchanged, appropriately reducing the table speed and increasing the cycle can reduce the grain width, that is, appropriate low table speed and high line speed have an improvement effect on wide grain lines. Preferably, the line speed is 2100m / min, the table speed range is 2300um / min-2500um / min, and the cycle range is 1.25n / min-1.38n / min, and the grain width improvement effect is more obvious. Furthermore, when all conditions in the formula: grain width = average table speed * (average wire supply amount + average wire return amount) / average wire speed remain unchanged, appropriately reducing the table speed and increasing the wire speed cycle can reduce the grain width, that is, appropriate low table speed and high wire speed have an improvement effect on wide grain lines. Preferably, when the cycle is 1.28n / min, the table speed range is 2300um / min-2500um / min, and the wire speed setting range is 2100m / min-2300m / min, the grain line mark improvement effect is more obvious.

[0037] It should be noted that in the description of the present invention, if there are any orientation descriptions, such as up, down, front, back, left, right, etc., the orientations or positional relationships indicated are all based on the orientations or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and cannot be understood as a limitation on the present invention.

[0038] In the description of the present invention, "several" means one or more, "more" means two or more, "greater than", "less than", "exceed" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used to distinguish the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0039] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0040] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A process for improving wide-groove line marks in cutting single-crystal silicon wafers, characterized in that: The following steps are involved: S1: The maximum linear velocity V1 is obtained based on the cutting cycle linear velocity model and Newton's second law; S2: According to the silicon wafer cutting force model, F 1y ; S3: Through the above steps S1 and S2, the acceleration and deceleration time t for cutting a good grain width is measured; S4: According to the cutting process parameter model, the line width = cutting depth / (cycle * cycle time); S5: measuring the period of the width of the good cut lines through the above step S4; S6: Through the above step S4 and the cutting process parameter model, it is obtained that the line width = average table speed * (average wire supply amount + average wire return amount) / average wire speed; S7: Measure the table speed and line speed for cutting good lines through the above step S6.

2. The process according to claim 1, characterized in that: The silicon wafer cutting force model in step S2 is the force analysis of the diamond wire at the moment of swinging.

3. The process according to claim 1, characterized in that: The line width in step S4 = cutting depth / number of cycles.

4. The process according to claim 3, characterized in that: The cycle=cycle number / cycle time.

5. The process according to claim 4, characterized in that: The number of cycles = cycle time * [average line speed / (average supply line quantity + average return line quantity)].

6. The process according to claim 4, characterized in that: The cycle time in step S4 = cutting depth / average table speed.

7. The process according to claim 6, characterized in that: In the step S6, the line width=average stage speed / cycle.

8. The process according to claim 7, characterized in that: The line speed is 2100 m / min, the stage speed range is 2300 um / min-2500 um / min, and the cycle range is 1.25 n / min-1.38 n / min.

9. The process according to claim 5, characterized in that: The cycle is 1.28n / min, the stage speed range is 2300um / min-2500um / min, and the line speed setting range is 2100m / min-2300m / min.

10. The process according to claim 1, characterized in that: The acceleration and deceleration time t is 5.5s-6.5s.

Citation Information

Patent Citations

  • Method for reducing silicon chip damaged layers during multi-wire cutting

    CN102700012A

  • Method for automatically adjusting technological parameters in monocrystalline silicon rod cutting

    CN112078040A

  • Rod lifting method for reducing scratches on surface of silicon wafer

    CN113071011A

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