Dynamic voltage frequency regulation controller, method of operating same, and integrated circuit

Abstract

A dynamic voltage frequency regulation controller, a method of operating the same, and an integrated circuit are provided. The integrated circuit includes: at least one sub-block circuit configured to process instructions; and a DVFS controller configured to control a power management unit (PMU) and a clock management unit (CMU) to control an operation voltage and an operation frequency, respectively, based on a resonant frequency calculated from a frequency response generated by dynamic characteristics of an entire power supply system including the PMU, a power transmission network (PDN), and a sub-block circuit.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0080680 filed on June 22, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0174932 filed on December 5, 2023, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to integrated circuits, and more particularly, to a dynamic voltage frequency scaling (or referred to as dynamic voltage frequency adjustment or dynamic voltage frequency scaling, DVFS) controller, an integrated circuit including the DVFS controller, and a method of operating the DVFS controller. Background Art

[0003] As computing systems such as mobile devices become miniaturized, power management becomes an important issue. Specifically, as the number of cores increases to improve the performance of mobile devices and the number of intellectual property (IP) devices included in mobile devices increases, the complexity of power management functions increases.

[0004] For example, the application processor of the mobile device may manage power by adjusting the frequency or voltage within the application processor via a dynamic frequency scaling (DFS) operation that adjusts the frequency within the application processor or a dynamic voltage scaling (DVS) operation that adjusts the voltage within the application processor. In addition, the application processor of the mobile device may manage power by adjusting the frequency or voltage within the application processor via a DVFS operation that adjusts the frequency and voltage within the application processor. Summary of the invention

[0005] Some example embodiments of the inventive concept provide a dynamic voltage frequency scaling (DVFS) controller, an integrated circuit including the DVFS, and a method of operating the DVFS controller, which performs a DVFS operation to optimize performance compared to an operating voltage and achieves a stable low-power operation even when a voltage sags.

[0006] According to some example embodiments of the inventive concept, an integrated circuit is provided, which may include: at least one sub-block circuit configured to: process an instruction; and a DVFS controller configured to: control a power management unit (PMU) and a clock management unit (CMU) to control an operating voltage and an operating frequency, respectively, based on a resonant frequency calculated from a frequency response generated by dynamic characteristics of an entire power system, the entire power system including the PMU, a power delivery network (PDN), and the at least one sub-block circuit.

[0007] According to some example embodiments of the inventive concept, there is provided a method of operating a DVFS controller for controlling an operating voltage and an operating frequency of an integrated circuit, the method comprising: receiving a resonant frequency calculated from a frequency response generated by dynamic characteristics of an entire power system, the entire power system comprising a PMU, a PDN, and sub-block circuits; receiving a feedback signal corresponding to an output of the entire power system to which the operating voltage and the operating frequency are applied; and controlling the PMU and the CMU to update the operating voltage and the operating frequency, respectively, based on the resonant frequency and the feedback signal.

[0008] According to some example embodiments of the inventive concept, a DVFS controller is provided, the DVFS controller including: a PMU driving circuit configured to: output a voltage control signal to the PMU; and a CMU driving circuit configured to: output a frequency control signal to the CMU, wherein the DVFS controller is configured to cause the PMU and the CMU to control an operating voltage and an operating frequency, respectively, based on a resonant frequency calculated from a frequency response generated by dynamic characteristics of an entire power system, the entire power system including the PMU, the PDN, and a sub-block circuit configured to process instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a system according to some example embodiments of the inventive concept;

[0011] Figure 2 is a block diagram of a computing system according to some example embodiments;

[0012] Figure 3 is a circuit diagram of a power supply system according to some example embodiments;

[0013] Figure 4 is a graph illustrating a frequency response of a power supply system according to some example embodiments;

[0014] Figure 5A and Figure 5B is a graph showing a time response of a power supply system for each frequency according to some example embodiments;

[0015] Figure 6 is a graph illustrating a time response of a power supply system according to frequency avoidance according to some example embodiments;

[0016] Figure 7 is a block diagram of a computing system according to some example embodiments;

[0017] Figure 8is a flow chart of a method of operating a dynamic voltage frequency scaling (DVFS) controller according to some example embodiments;

[0018] Fig. 9 is a block diagram of a system according to some example embodiments; and

[0019] Fig.10 is a block diagram of a communication device including an application processor (AP) according to some example embodiments. DETAILED DESCRIPTION

[0020] Some example embodiments will now be described more fully with reference to the accompanying drawings.In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions thereof are omitted.

[0021] Throughout the specification, when a component is “connected” to another component, it includes not only the case where the components are “directly connected” but also the case where the components are “indirectly connected” with another component in between. In addition, unless explicitly described to the contrary, the word “comprise” will be understood to indicate the inclusion of stated elements but not the exclusion of any other elements.

[0022] It will be understood that when an element (such as a layer, film, region, area, or substrate) is referred to as being "on" another element, the element may be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, in the specification, an element "on" another element may be above, below, or horizontally close to (e.g., horizontally adjacent to) the other element, and is not necessarily above the upper side of the other element based on the direction of gravity.

[0023] The use of the term "the" and similar referents may correspond to both the singular and the plural.The operations constituting the methods may be performed in any suitable order and are not necessarily limited to the order presented unless otherwise indicated herein or otherwise clearly contradicted by context.

[0024] All illustrations or illustrative terms are used in some example embodiments only to describe the technical concept in detail, and the scope of the inventive concept is not limited by these illustrations or illustrative terms unless these illustrations or illustrative terms are limited by the claims.

[0025] It will be understood that elements and / or their characteristics may be described herein as being "the same" or "equal" to other elements, and it will also be understood that elements and / or their characteristics described herein as being "equivalent", "identical" or "equal" to other elements may be "equivalent", "identical", "equal", "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or their characteristics. Elements and / or their characteristics that are "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or their characteristics will be understood to be equivalent, identical or equivalent to other elements and / or their characteristics within manufacturing tolerances and / or material tolerances. Elements and / or their characteristics that are equivalent or substantially equivalent and / or identical or substantially identical to other elements and / or their characteristics may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition. Although the terms "same", "equal" or "equivalent" may be used in the description of some example embodiments, it will be understood that some imprecision may exist. Thus, when one element is referred to as being the same as another element, it should be understood that the one element or value is the same as the other element within a desired manufacturing or operating tolerance range (eg, ±10%).

[0026] It will be understood that elements and / or characteristics thereof described herein as being "substantially" the same and / or equivalent encompass elements and / or characteristics thereof having relative differences in magnitude equal to or less than 10%. Furthermore, regardless of whether elements and / or characteristics thereof are modified to be "substantially," it will be understood that these elements and / or characteristics thereof should be interpreted as including manufacturing tolerances or operating tolerances (e.g., ±10%) around the stated elements and / or characteristics thereof.

[0027] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing tolerance or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but the tolerance of the shape is within the disclosed range. In addition, regardless of whether a numerical value or shape is modified to "approximately" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing tolerance or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween (such as, increments of 0.1%).

[0028] As described herein, when an operation is described as being performed “by” or “via” performing an additional operation, or an effect (such as a structure) is described as being established “by” or “via” performing an additional operation, it will be understood that the operation may be performed “based on” the additional operation and / or the effect / structure may be established “based on” the additional operation, which may include performing the additional operation alone or in combination with other further additional operations.

[0029] Figure 1 is a block diagram of system 10 according to some example embodiments.

[0030] Reference Figure 1 , the system 10 may include an intellectual property (IP) device 11 , a clock management unit (CMU) 12 , and a power management unit (PMU) 13 .

[0031] The system 10 may correspond to (e.g., may include) various types of data processing devices, and may correspond to a mobile device, for example. The system 10 may correspond to a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or an e-book.

[0032] The system 10 may include various types of memory devices. For example, the memory may correspond to various types of semiconductor memory devices. According to some example embodiments, the memory may be a dynamic random access memory (DRAM) (such as a double data rate synchronous DRAM (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, or a Rambus DRAM (RDRAM)). In addition, the memory may be any one of a flash memory, a phase change random access memory (RAM) (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FeRAM).

[0033] According to some example embodiments, system 10 can be implemented by using a system on chip (SoC). SoC may include a system bus to which a protocol with a specific bus standard is applied, and the components included in system 10 may be connected to the system bus. For example, the Advanced Microcontroller Bus Architecture (AMBA) protocol of an Advanced Reduced Instruction Set Computer (RISC) machine (ARM) may be applied as a standard for the system bus. Examples of bus types of the AMBA protocol may include an Advanced High Performance Bus (AHB), an Advanced Peripheral Bus (APB), an Advanced Extensible Interface (AXI), an AXI4, and an AXI Consistency Extension (ACE). In addition to them, other types of protocols (such as, SONICs' uNetwork, IBM's CoreConnect, and the Open Core Protocol (OpenCore Protocol) of OCP-IP) are also applicable.

[0034] The IP device 11 may include a plurality of (or at least one) sub-blocks 11_1 (also interchangeably referred to herein as sub-block circuits) and a dynamic voltage frequency adjustment (or referred to as dynamic voltage frequency adjustment or dynamic voltage frequency scaling, DVFS) controller 11_2. The IP device may be designed as an integrated circuit implemented with a plurality of transistors. The IP device 11 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or an image signal processor (ISP). Figure 1 One IP device 11 is shown, but the type and quantity (eg, number) of IP devices included in the system 10 are not limited thereto. Figure 1 , but the IP device 11 may additionally include a feedback block and a filter. According to some example embodiments, at least some of the feedback block, the filter, and the DVFS controller 11_2 may be disposed outside the IP device 11.

[0035] Each of the multiple sub-blocks 11_1 can process instructions independently. The sub-block can be a CPU core, a GPU core, an NPU core, or an ISP core. Because the IP device 11 includes multiple cores, the system 10 can also be called a multi-core processor. The sub-block can also be called a sub-functional block.

[0036] Each of the plurality of sub-blocks 11_1 may process instructions according to a clock signal CLK (e.g., a frequency of the clock signal CLK) and a power supply voltage VDD. The performance of the sub-block 11_1 may depend on the clock signal CLK and the power supply voltage VDD. As the magnitude of the power supply voltage VDD increases and the frequency of the clock signal CLK increases, the performance of the IP device 11 may be improved and the power consumption of the IP device 11 may be increased. In this specification, the frequency of the clock signal CLK is referred to as an operating frequency, and the magnitude of the power supply voltage VDD is referred to as an operating voltage.

[0037] The DVFS controller 11_2 may determine the corresponding operating states of various functional blocks in the system 10, and may provide control signals CTRL_CLK and CTRL_VDD “for adjusting the operating frequency and / or operating voltage of each functional block” to the CMU 12 and / or the PMU 13 according to the determination result. For example, the DVFS controller 11_2 may adjust the operating frequency and operating voltage provided to the plurality of sub-blocks 11_1.

[0038] In detail, the DVFS controller 11_2 may output (e.g., transmit) control signals CTRL_CLK and CTRL_VDD for controlling the operating conditions of the IP device 11 at a specific (or optionally, predetermined) sampling interval. In detail, the DVFS controller 11_2 may output a clock control signal CTRL_CLK for controlling the frequency of the clock signal CLK (e.g., controlling the CMU 12 to adjust the frequency of the clock signal CLK), and may output a voltage control signal CTRL_VDD for controlling the level (e.g., size) of the power supply voltage VDD (e.g., controlling the PMU 13 to adjust the size of the power supply voltage VDD).

[0039] The DVFS controller 11_2 may output control signals CTRL_CLK and CTRL_VDD for adjusting the operating frequency and / or operating voltage based on the resonant frequency calculated from the frequency response generated by the dynamic characteristics of the entire power system, which may result in an improvement in the performance and / or power consumption of the system 10. The entire power system may include a power management unit, a power delivery network (PDN), and one or more sub-blocks. This is described in detail below.

[0040] Environmental factors of the IP device 11, such as the temperature of the IP device 11 and the humidity of the IP device 11, may vary according to the operating time. Environmental factors not only affect the operation of the IP device 11, but may also affect the DVFS operation. For example, in the same workload, the target voltage and / or target frequency determined by the DVFS operation may vary according to the temperature or aging degree of the IP device 11. Therefore, according to some example embodiments, the DVFS controller 11_2 may perform the DVFS operation by considering the environmental factors, which may lead to an improvement in the performance and / or power consumption of the system 10.

[0041] The CMU 12 may generate a clock signal CLK based on the clock control signal CTRL_CLK and may adjust the frequency of the clock signal CLK. For example, the CMU 12 may include an oscillator that generates the clock signal CLK based on the clock control signal CTRL_CLK. The CMU 12 may include a clock generating device such as a phase-locked loop (PLL), a delay-locked loop (DLL), or a crystal. The CMU 12 may also be referred to as a clock generator or a clock generating circuit.

[0042] The PMU 13 may generate a power supply voltage VDD based on the voltage control signal CTRL_VDD and may adjust the magnitude of the power supply voltage VDD. For example, the PMU 13 may include a switching regulator that generates the power supply voltage VDD based on the voltage control signal CTRL_VDD. The PMU 13 may also be referred to as a power management integrated circuit (PMIC).

[0043] Although not in Figure 1 , but the system 10 may include other types of functional blocks that communicate with the IP device 11 (such as an input / output (IO) interface block, a universal serial bus (USB) host block, and a USB slave block (universal serial bus)).

[0044] Figure 2 is a block diagram of a computing system 200 according to some example embodiments.

[0045] Reference Figure 2 , computing system 200 may include a DVFS controller 210 , a CMU 220 , a PMU 230 , a PDN 240 , a sub-block 250 (also interchangeably referred to herein as a sub-block circuit), and a feedback block 260 . Figure 2 The DVFS controller 210, CMU 220, PMU 230 and sub-block 250 may be connected to Figure 1 The DVFS controller 11_2, the CMU 12, the PMU 13 and some of the plurality of sub-blocks 11_1 correspond to each other. At least one of the DVFS controller 210, the sub-block 250 and the feedback block 260 may be implemented using one integrated circuit (IC). Figure 1 describe Figure 2 ,and Figure 2 of Figure 1 The same or substantially the same description is omitted.

[0046] The DVFS controller 210 may receive a reference signal r(t) and a feedback signal f(t) from the feedback block 260. The reference signal r(t) may be received from an external source, a processing device, a memory, or other modules. The reference signal r(t) may be an input signal for pre-analyzing a frequency response generated by the dynamic characteristics of the entire power system, and for outputting optimal control signals CTRL_CLK and CTRL_VDD corresponding to an optimal operating voltage and an optimal operating frequency based on the analyzed frequency response. The reference signal r(t) may be compared with the output of the current sensor signal and used to generate an error signal. The feedback signal f(t) may be a signal generated by the feedback block 260 "by detecting the output voltage y(t) of the entire power system so as to reflect, for example, a change in the output voltage generated during the driving process of the sub-block 250". The feedback block 260 may be connected to the DVFS controller 210 to form a closed loop.

[0047] The DVFS controller 210 may include a CMU filter (or referred to as a CMU driving circuit) 211 and a PMU filter (or referred to as a PMU driving circuit) 212. The CMU filter 211 may generate an operating frequency control signal (or referred to as a frequency control signal) CTRL_CLK that enables the CMU 220 to control the operating frequency of the clock signal CLK, and the PMU filter 212 may generate an operating voltage control signal (or referred to as a voltage control signal) CTRL_VDD that enables the PMU 230 to control the operating voltage of the power supply voltage VDD. The CMU filter 211 and the PMU filter 212 may receive a reference signal r(t) and a feedback signal f(t), respectively.

[0048] The CMU filter 211 may receive a reference signal r(t) and a feedback signal f(t), and generate an operating frequency control signal CTRL_CLK for reducing the drooping of the output of the entire power system. The PMU filter 212 may receive a reference signal r(t) and a feedback signal f(t), and generate an operating voltage control signal CTRL_VDD for reducing the drooping of the output of the entire power system. The method of reducing the drooping of the output of the entire power system is described in detail below. The CMU filter 211 and the PMU filter 212 according to some example embodiments may calculate the difference between the reference signal r(t) and the feedback signal f(t), and may output control signals CTRL_CLK and CTRL_VDD reflecting the difference.

[0049] The DVFS controller 210 (e.g., the CMU filter 211 and the PMU filter 212 of the DVFS controller 210) may be implemented using an analog circuit composed of a combination of analog circuit elements. The CMU filter 211 and the PMU filter 212 according to some example embodiments may each be implemented using at least one circuit filter. The CMU filter 211 and the PMU filter 212 may each be implemented using an analog filter composed of RLC-based passive elements, and may also each be implemented using an analog filter including an active element such as an operational amplifier (Op-Amp). The CMU filter 211 and the PMU filter 212 may each be implemented only by hardware such as an analog circuit without software-based execution by a processor or the like, and thus may achieve low-power execution without the power required to perform software-based calculations.

[0050] The CMU 220 may receive the operating frequency control signal CTRL_CLK from the DVFS controller 210 and output the clock signal CLK having an operating frequency corresponding to the operating frequency control signal CTRL_CLK. The PMU 230 may receive the operating voltage control signal CTRL_VDD from the DVFS controller 210 and output the operating voltage VDD corresponding to the operating voltage control signal CTRL_VDD. Figure 1 Descriptions that are the same or substantially the same as those given about the CMU 220 and the PMU 230 are omitted.

[0051] The PDN 240 may be a general term for a transmission system including tracks, conductors, and the like for transmitting power to a unit such as a sub-block, and may constitute a power supply system including a PMU and a sub-block subjected to power transmission. The PDN 240 may receive an operating voltage VDD and a clock signal CLK having an operating frequency, and transmit an output voltage y(t) to the sub-block 250 based on the operating voltage VDD and the clock signal CLK having an operating frequency. The voltage value of the output voltage y(t) may vary depending on the operation of the sub-block, resulting in droop. As described below, in order to achieve a low power design by reducing the droop of the output voltage, the computing system 200 may analyze the frequency response and perform a DVFS operation based on the frequency response. The following refers to Figure 3 and Figure 4 A power system including the PDN 240 and a method for analyzing frequency response are described in detail.

[0052] The dynamic power consumption P of the sub-block 250 may be expressed as Equation 1.

[0053] Equation 1

[0054] P∝C·V 2 …f

[0055] Among them, C may indicate the capacitance of the sub-block, V may indicate the magnitude of the power supply voltage applied to the sub-block, and f may indicate the frequency of the clock signal applied to the sub-block. Therefore, for low-power design, both voltage and frequency need to be considered for appropriate design. Here, among the parameters related to the power supply, parameters other than the frequency f of the clock signal and the magnitude V of the power supply voltage may be a general term for the power supply coefficient. For example, the capacitance of the sub-block 250 in equation 1 may be referred to as the power supply coefficient.

[0056] The sub-block 250 may have a different circuit structure for each sub-block, and thus may have different performance for each sub-block. That is, the number of instructions that the sub-block 250 can process per unit time may be different for each sub-block. Due to different circuit structures, even when the magnitude of the power supply voltage and the frequency of the clock signal are the same, the power consumed by the sub-block 250 may be different. That is, the power supply coefficients of the sub-blocks may be different.

[0057] According to include Figure 2 Some example embodiments of the example embodiments shown in the can realize low power design by implementing the DVFS controller without software units. In addition, as described below, an effective low power design can be realized by reducing or minimizing the voltage droop of the output voltage through the DVFS operation based on the overall frequency response analysis.

[0058] Figure 3 is a circuit diagram of a power supply system 300 according to some example embodiments.

[0059] In detail, the power supply system 300 may be formed to include a PMU, a sub-block, and a PDN, and the PDN may be divided into a board and a package. The PMU, the sub-block, and the PDN may be the same as those described above. Figure 1 and Figure 2 Some example embodiments of PMUs, sub-blocks, and PDNs are described and are related to Figure 1 and Figure 2 Descriptions given of those that are the same or substantially the same are omitted.

[0060] The PMU may output an operating voltage VDD based on the received operating voltage control signal CTRL_VDD, and the operating voltage VDD may be transmitted to the sub-block through the PDN including the board and the package. The sub-block may receive a clock signal CLK having an operating frequency based on the operating frequency control signal CTRL_CLK from the CMU, and receive the operating voltage VDD through the PDN to process the instruction. The operating voltage VDD generated by the PMU may represent a voltage transmitted to the sub-block through the PDN as an output voltage y(t).

[0061] To analyze the power system 300, the response may be analyzed in the time domain. However, verifying interference and noise in all situations that may occur in the system may have a low probability and may take a long time to analyze. Figure 3 The components of the power system 300 are analyzed and based on Figure 3 When the circuit diagram of the components of the power supply system 300 is analyzed, the overall response may be modeled by analyzing the frequency response in the frequency domain based on the results of the analysis. Figure 3 The circuit diagram shown in is an equivalent circuit of the power supply system 300 and may include a plurality of resistors, a plurality of capacitors, and a plurality of inductors. As unknowns for analyzing the circuit, the current passing through the inductor or resistor and the voltage difference applied to the capacitor may be represented as a plurality of unknowns (represented by x (e.g., x 1 、x 2 、x 3 、x 4 、x 5 、x 6 、x 7 、x 8 、x 9 、x 11 、x 12 、x 15 and x 16) indicates). In order to determine the output voltage y(t) corresponding to the input of the operating voltage control signal CTRL_VDD and the operating frequency control signal CTRL_CLK (implemented in units of current), Kirchhoff's current law and Kirchhoff's voltage law (Kirchhoff's law) may be used. The circuit equation may be expressed as a differential equation in the time domain, which may be expressed as a set of multiple equations (such as, the following equation 2).

[0062] Equation 2

[0063]

[0064] x 1 =x 2 +x 3

[0065] x 9 =x 7 +x 8

[0066] x 9 =x 1 +2x 12 +x 16

[0067] In Equation 2, L 1 , L 3 , L 7 , L 8 , L 9 , L 10 , L 11 , L 13 and L 14 yes Figure 3 The inductances of the inductors L1, L3, L7, L8, L9, L10, L11, L13 and L14 of the power system 300 shown in FIG. 1 , R 2 , R 3 , R 7 , R 9 , R 10 , R 11 , R 12 , R 13 , R 14 , R 16 , R 17 and R 18 yes Figure 3 The resistances of resistors R1, R2, R3, R7, R9, R10, R11, R12, R13, R14, R16, R17, and R18 of the power system 300 shown in FIG. 1 and C 2 yes Figure 3The capacitances of capacitors C1 and C2 of the power supply system 300 shown in FIG. 6 to c 8 is a constant. For example, the power supply system 300 may further include a resistor R8 and a capacitor C7. In Equation 2, the current passing through the inductor or resistor and the voltage difference applied to the capacitor may be represented as a plurality of unknowns (indicated by x), and u 1 and u 2 Respectively represent the operating voltage control signal CTRL_VDD and the operating frequency control signal CTRL_CLK. It should be noted that Figure 3 The circuit diagram of and Equation 2 are a circuit diagram of the power supply system 300 and an equation corresponding to the circuit diagram of the power supply system 300 , and thus the embodiment is not limited to this type of circuit and equation.

[0068] Multiple equations, such as Equation 2 above, may be transformed to the frequency domain via Laplace transforms, and after the conversion, they may be combined as solving simultaneous equations to obtain the transfer function.

[0069] Respectively with u 1 and u 2 The corresponding transfer functions of the output y(t) can be expressed as H 1 and H 2 , and the frequency response can be represented using a Bode plot to represent the transfer function. Figure 4 The frequency response of the Bode plot of the transfer function through the power system 300 is detailed.

[0070] Figure 4 is a graph illustrating a frequency response of a power supply system according to some example embodiments.

[0071] Above Figure 3 The power system 300 can be calculated as a transfer function after circuit analysis to obtain the power supply system 300 by Figure 4 The frequency response can be analyzed using the Bode plot shown in Figure . Figure 4 The frequency response of φ is, for example, a graph, and example embodiments are not limited thereto.

[0072] Referring to the Bode plot, the size of the transfer function according to the frequency band can be seen. The main resonant frequency F1 as the frequency band with the largest size can be seen. In addition, the sub-resonant frequency F2 and the third resonant frequency F3 can be seen. Regarding the frequency control of the DVFS according to the comparative example, limited frequency adjustment in the frequency band of 100 MHz to several GHz can be achieved. In contrast, the frequency response according to some example embodiments can analyze the overall frequency response of the entire power supply system. Therefore, it can be used Figure 4 The frequency response in all frequency ranges including the range of 100MHz or less can be analyzed by using Bode plots, etc. Figure 4According to the frequency response shown in , the main resonant frequency F1 may be formed in an interval of about 40KHz to 50KHz, the sub-resonant frequency F2 may be formed in an interval of about 100MHz, and the third resonant frequency F3 may be formed in an interval of about 20MHz. Because the DVFS operation according to the comparative example mainly utilizes frequencies in a frequency band of 100MHz or higher, it may be difficult to perform an operation for identifying and avoiding the main resonant frequency F1 formed in the range of 40KHz to 50KHz (for example, such an operation may be referred to as frequency avoidance or resonant frequency avoidance). On the other hand, according to some example embodiments, since the entire frequency band is analyzed, the main resonant frequency F1 formed as an example in the range of about 40KHz to 50KHz below 100MHz may be identified. However, this is based on Figure 3 3 is an example of a frequency response Bode plot graph of the power supply system 300, and the frequencies of the main resonant frequency F1 and the sub-resonant frequency F2 may not be limited and may vary according to components (such as a PMU and a sub-block) constituting the power supply system.

[0073] Figure 5A and Figure 5B is a graph showing a time response of a power supply system for each frequency according to some example embodiments. Figure 6 is a graph illustrating a time response of a power supply system as a function of frequency avoidance according to some example embodiments.

[0074] In detail, Figure 5A is a graph showing the time response of the power supply system before resonant frequency avoidance is performed, Figure 6 is a graph showing the time response of the power supply system after performing resonant frequency avoidance, and Figure 5B It is shown Figure 5A An enlarged graph of portion "A" of the graph. Figures 1 to 4 describe Figure 5A , Figure 5B and Figure 6 , and redundant descriptions are omitted.

[0075] Reference Figure 5A and Figure 5B, showing the value of the output voltage (e.g., size, level, etc.) over time, wherein the graph GF1 represents the time response corresponding to the main resonant frequency F1, and the graph GF2 may take into account both the time responses corresponding to the main resonant frequency F1 and the sub-resonant frequency F2. In other words, the graph GF1 represents the output voltage of the sub-block that changes in response to the main resonance, and the graph GF2 represents the output voltage of the sub-block that changes by reflecting both the main resonance and the sub-resonance. Unlike the graph GF1, the graph GF2 also reflects the vibration of the sub-resonance. Therefore, it can be seen that the graph GF2 represents the aspect of oscillating up and down relative to the graph GF1. The graph GF2 is in accordance with Figure 4 The graph corresponding to the description that the sub-resonance frequency F2 is higher than the main resonance frequency F1 during the comparison between the main resonance frequency band and the sub-resonance frequency band shown in FIG.

[0076] Reference Figure 6 , graph G1 represents the time response corresponding to the main resonant frequency F1 and the sub-resonant frequency F2 before performing resonant frequency avoidance, and graph G2 represents the time response after performing avoidance of the main resonant frequency F1. The actual signal does not have a complete periodic characteristic and can be represented as the sum of multiple square waves by Fourier series. According to Figure 4 The frequency response of the square wave corresponding to each frequency may have a different waveform size. Among the square waves corresponding to each frequency, the time response considering the main resonant frequency F1 and the sub-resonant frequency F2 may be expressed as a graph G1. In order to reduce the influence of the vibration caused by resonance, a method of removing or avoiding the frequency of the main resonant frequency band or the sub-resonant frequency band may be performed. In this case, the magnitude of the amplitude appears larger in the main resonant frequency band than in the sub-resonant frequency band, so it may be important to remove or avoid the frequency in the main resonant frequency band. The time response in which the influence of the main resonant frequency F1 has been removed in the graph G1 may be expressed as a graph G2. It can be confirmed that the width of the vibration can be reduced by removing the component of the main resonant frequency F1, and the minimum value of the output voltage can be increased.

[0077] In power design, a condition that the output voltage value is equal to or greater than a minimum threshold value to achieve normal operation of the device may be required. When a device (such as a CPU) executes many instructions and the workload therefore consumes a large amount of current, voltage droop may occur, and as the voltage fluctuates, the entire voltage value (e.g., the magnitude of the output voltage y(t)) may be set high to ensure that the minimum output voltage value is equal to or greater than the minimum threshold value. Referring to equation 1 defined above, power consumption is proportional to the square of the voltage, so in the process of setting the voltage value for the process of performing the operation of the device, even under the influence of such voltage droop, a large amount of power may be consumed. Therefore, by reducing the oscillation amplitude of the output voltage and increasing the minimum value of the output voltage as described above, the voltage increase required to ensure that the minimum output voltage value is equal to or greater than the minimum threshold value may be required. In other words, by avoiding the frequency of the resonant frequency band, unnecessary voltage rise can be designed to be small, and stability can also be ensured, and effective low-power design can be achieved, thereby providing a device (e.g., an integrated circuit, a system, a device, etc.) that can have improved power consumption efficiency, reduced power consumption, etc. with reduced risk or prevention of an output voltage applied to at least one of its sub-blocks (sub-block circuits) from dropping below a threshold value to achieve normal operation of the device, thereby reducing or preventing system failures due to voltage sag. Therefore, the device can have improved operational reliability (e.g., reducing, minimizing, or preventing the possibility of the output voltage dropping below a threshold value to achieve normal operation of the device). As a result, the functions of such an apparatus (e.g., an integrated circuit, a system, a computing system, an equipment, etc.) may have improved functions based on the apparatus including a dynamic voltage frequency scaling (DVFS) controller (e.g., 210) configured to control a power management unit (PMU) and a clock management unit (CMU) to control an operating voltage (e.g., VDD applied to the PDN 240) and an operating frequency (e.g., a clock signal CLK applied to the PDN 240), respectively, based on a resonant frequency calculated from a frequency response generated by dynamic characteristics of an entire power system including the PMU (230), the PDN (240), and at least one sub-block (250). The value of the minimum threshold may be stored at a memory of the apparatus and may be received or accessed from the memory by the DVFS controller 210.

[0078] The DVFS operation may be implemented by considering both the main resonance frequency F1 and the sub resonance frequency F2. Since the vibration amplitude of the frequency band is large under both the main resonance and the sub resonance, the DVFS controller 210 may perform the DVFS operation by avoiding or responding to both the main resonance frequency band and the sub resonance frequency band.

[0079] In addition, the DVFS controller 210 may identify a resonant frequency band and perform frequency avoidance to handle the resonant frequency band, and may control the output voltage to be equal to or greater than a minimum threshold by finitely increasing the voltage in response to the resonant frequency band. The value of the minimum threshold may be stored at a memory of the device and may be received or accessed from the memory by the DVFS controller 210. For example, the CMU filter 211 in the DVFS controller 210 may be configured to control the operating frequency to avoid the resonant frequency. That is, the CMU filter 211 may output an operating frequency control signal CTRL_CLK for controlling the operating frequency to avoid the resonant frequency. The PMU filter 212 in the DVFS controller 210 may also be configured to control the operating voltage VDD in response to the resonant frequency. That is, when the operating frequency is close to the resonant frequency (e.g., within a 10% margin, within a 5% margin, within a 1% margin, etc.) (e.g., when the operating frequency is close to the resonant frequency (e.g., within a 10% margin, within a 5% margin, within a 1% margin, etc.) based on, for example, a determination at the DVFS controller 210 (e.g., the PMU filter 212) that the operating frequency is close to the resonant frequency (e.g., within a 10% margin, within a 5% margin, within a 1% margin, etc.)), the PMU filter 212 may output an operating voltage control signal CTRL_VDD for controlling the operating voltage VDD to increase.

[0080] According to some example embodiments including the above-described example embodiments, effective low-power design may be achieved by reducing or minimizing the voltage droop of the output voltage through the DVFS operation based on the overall frequency response analysis, thereby providing a device (e.g., an integrated circuit, a system, a device, etc.) that may have improved power consumption efficiency, reduced power consumption, etc. with a reduced risk or prevention of an output voltage applied to at least one sub-block (sub-block circuit) thereof from dropping below a threshold value to achieve normal operation of the device, thereby reducing or preventing system failure due to voltage droop. Therefore, the device may have improved operational reliability (e.g., the possibility of reducing, minimizing, or preventing the output voltage from dropping below a threshold value to achieve normal operation of the device). As a result, the functions of such an apparatus (e.g., an integrated circuit, a system, a computing system, an equipment, etc.) may have improved functions based on the apparatus including a dynamic voltage frequency scaling (DVFS) controller (e.g., 210) configured to control a power management unit (PMU) and a clock management unit (CMU) to control an operating voltage (e.g., VDD applied to the PDN 240) and an operating frequency (e.g., a clock signal CLK applied to the PDN 240), respectively, based on a resonant frequency calculated from a frequency response generated by dynamic characteristics of an entire power system including the PMU (230), the PDN (240), and at least one sub-block (250). In addition, a low power design may be achieved by implementing the DVFS controller without a software unit.

[0081] Figure 7 is a block diagram of a computing system 700 according to some example embodiments.

[0082] Reference Figure 7 , computing system 700 may include a DVFS controller 710 , a CMU 720 , a PMU 730 , a PDN 740 , a sub-block 750 (also interchangeably referred to herein as a sub-block circuit), a feedback block 760 , and Q filters 770 and 780 . Figure 7 The DVFS controller 710, CMU 720, PMU 730, PDN 740 and sub-block 750 can be connected with Figure 2 The DVFS controller 210, CMU 220, PMU 230, PDN 240, and sub-block 250 of the embodiment of the present invention correspond to each other. At least one of the DVFS controller 710, sub-block 750, feedback block 760, and Q filters 770 and 780 may be implemented using one IC. Figure 1 and Figure 2 describe Figure 7 , and redundant descriptions are omitted.

[0083] The computing system 700 includes Figure 2 Some example embodiments of the computing system 200 may also include in addition to Figure 2 The Q filters 770 and 780 outside the computing system 200 of the feedback block 760 may include a feedback sensor 761 and one or more refinement filters 762. The feedback sensor 761 may detect the output of the power system (e.g., the output voltage y(t)) to generate a sense signal. The feedback sensor 761 may be any of a variety of sensors (such as a voltage sensor, a current sensor, and a temperature sensor), and may include any sensor for converting the output into an appropriate signal. The feedback sensor according to some example embodiments may be configured as a voltage sensor, and may generate a sense signal by detecting the output voltage y(t). One or more refinement filters 762 are components for reprocessing and filtering the sense signal as needed. In some cases, one or more refinement filters 762 may be omitted. One or more refinement filters 762 may receive the sense signal, reprocess (refine) the sense signal, and generate a feedback signal. One or more refinement filters 762 may be configured as filters such as a low pass filter (LPF), a high pass filter (HPF), a band pass filter (BPF), an anti-aliasing filter, or may be configured as a combination of multiple filters. Finally, the feedback signal generated by the feedback block 760 may be transmitted to the DVFS controller 710 , and a closed loop may be formed.

[0084] The Q filters 770 and 780 may remove noise from the operating frequency control signal CTRL_CLK, which is the output of the CMU filter 711, and the operating voltage control signal CTRL_VDD, or may reprocess and filter the noise from the operating frequency control signal CTRL_CLK and the operating voltage control signal CTRL_VDD, which is the output of the PMU filter 712. For example, the Q filter 780 may process the noise of the operating voltage control signal CTRL_VDD, and the Q filter 770 may process the noise of the operating frequency control signal CTRL_CLK. Through filtering or reprocessing processes such as noise removal, unnecessary data may be removed, and a more efficient DVFS operation may be performed.

[0085] Figure 8 is a flow chart of a method of operating a DVFS controller according to some example embodiments. The DVFS controller may be any one of the DVFS controllers according to any one of the example embodiments.

[0086] Reference Figure 8 , the DVFS controller 210 may operate by performing a plurality of operations S810 to S830. Figure 8 , and are the same or substantially the same as the description of the above exemplary embodiments Figure 8 The description is omitted.

[0087] In operation S810, the DVFS controller 210 may receive a resonant frequency calculated from a frequency response generated by a dynamic characteristic of the power system (e.g., may determine the resonant frequency calculated from the frequency response generated by the dynamic characteristic of the power system, may receive a signal and / or data indicating the resonant frequency calculated from the frequency response generated by the dynamic characteristic of the power system, etc.). The power system may include a PMU, a PDN, and a sub-block. The DVFS controller 210 may receive the calculated resonant frequency from an external source, a processor, a memory, or any other unit. The received resonant frequency may include a primary resonant frequency and a secondary resonant frequency. The DVFS controller 210 may send a request for information indicating the resonant frequency to an external source (e.g., Fig. 9 ) such that an external source provides information to the DVFS controller 210 to receive the resonant frequency.

[0088] In operation S820, the DVFS controller 210 may receive a feedback signal (e.g., f(t)) corresponding to the output (e.g., output voltage y(t)) of the power system to which the operating voltage and the operating frequency are applied. For example, the DVFS controller 210 may receive the feedback signal f(t) from the feedback block 260 that has sensed the output voltage y(t). The feedback block may include only a feedback sensor, or may include an additional refinement filter. Figure 2 and Figure 7 The same description as given will not be repeated here.

[0089] In operation S830, the DVFS controller 210 may control the PMU and the CMU to update the operating voltage and the operating frequency, respectively, based on the resonant frequency and the feedback signal. In detail, the DVFS controller 210 may send the operating voltage control signal CTRL_VDD to the PMU so that the PMU updates the operating voltage VDD, and may send the operating frequency control signal CTRL_CLK to the CMU so that the CMU updates the operating frequency. The DVFS controller 210 according to some example embodiments may output (transmit) the operating voltage control signal CTRL_VDD through the PMU filter 212, and may output (transmit) the operating frequency control signal CTRL_CLK through the CMU filter 211.

[0090] According to some example embodiments including the above example embodiments, an effective low power design may be achieved by minimizing the voltage droop of the output voltage through the DVFS operation based on the overall frequency response analysis. Figure 8 The apparatus (e.g., an integrated circuit, a system, an apparatus, etc. according to any one of the example embodiments) of the method shown in the embodiment can have improved power consumption efficiency, reduced power consumption, etc., without compromising the output voltage applied to at least one sub-block (sub-block circuit) thereof to drop below a threshold value to achieve normal operation of the apparatus. As a result, the function of such an apparatus (e.g., an integrated circuit, a system, a computing system, an apparatus, etc.) can have improved functions based on an apparatus including a dynamic voltage frequency scaling (DVFS) controller (e.g., 210), which is configured to control a power management unit (PMU) and a clock management unit (CMU) to control an operating voltage (e.g., VDD applied to PDN 240) and an operating frequency (e.g., a clock signal CLK applied to PDN 240), respectively, based on a resonant frequency calculated from a frequency response generated by dynamic characteristics of an entire power system including a PMU (230), a PDN (240), and at least one sub-block (250). In addition, a low power design can be achieved by implementing the DVFS controller without a software unit.

[0091] Fig. 9 is a block diagram of a system 2000 according to some example embodiments.

[0092] Reference Fig. 9 , system 2000 may be implemented using a handheld device such as a mobile phone, a smart phone, a tablet computer, a PDA, an EDA, a digital still camera, a digital video camera, a PMP, a personal navigation device or PND, a handheld game console, or an e-book.

[0093] The system 2000 may include a SoC 2200 and a memory device 2300. The SoC 2200 may include a CPU 2210, a GPU 2220, an NPU 2230, an ISP 2240, a memory interface (MIF) 2250, a clock management unit (CMU) 2260, and a power management unit (PMU) 2270. The CPU 2210, the GPU 2220, the NPU 2230, and the ISP 2240 may be referred to as a master IP device, and the MIF 2250 may be referred to as a slave IP device. At least one of the CPU 2210, the GPU 2220, the NPU 2230, the ISP 2240, and the MIF 2250 may be a CPU 2210, a GPU 2220, a NPU 2230, a ISP 2240, and a MIF 2250 may be a CPU 2210, a GPU 2220, a NPU 2230, a ISP 2240, and a MIF 2250. Figures 1 to 8 An implementation example of an IP device described herein. Therefore, at least one of the CPU 2210, the GPU 2220, the NPU 2230, the ISP 2240, and the MIF 2250 may include a plurality of sub-blocks, and may include a DVFS controller that performs a DVFS operation based on power consumed by the plurality of sub-blocks. The DVFS controller included in the CPU 2210, the GPU 2220, the NPU 2230, the ISP 2240, and the MIF 2250 may control the CMU 2260 or the PMU 2270, and the CPU 2210, the GPU 2220, the NPU 2230, the ISP 2240, and the MIF 2250 may process instructions by receiving a clock signal CLK from the CMU 2260 and a power supply voltage from the PMU 2270.

[0094] The CPU 2210 may process or execute commands and / or data stored in the memory device 2300 in response to a clock signal generated by the CMU 2260 .

[0095] The GPU 2220 may obtain image data stored in the memory device 2300 in response to a clock signal generated by the CMU 2260. The GPU 2220 may generate data for outputting an image on a display (not shown) from the image data provided by the MIF 2250, and may encode the image data.

[0096] NPU 2230 may represent any device that executes a machine learning model. NPU 2230 may be a hardware block designed to execute a machine learning model. The machine learning model may be based on an artificial neural network, a decision tree, a support vector machine, a regression analysis, a Bayesian network, a genetic algorithm, etc. Non-limiting examples of artificial neural networks may include convolutional neural networks (CNNs), region-based convolutional neural networks (R-CNNs), region proposal networks (RPNs), recurrent neural networks (RNNs), stacked deep neural networks (S-DNNs), state-space dynamic neural networks (S-SDNNs), deconvolution networks, deep belief networks (DBNs), restricted Boltzmann machines (RBMs), fully convolutional networks, long short-term memory (LSTM) networks, and classification networks.

[0097] The ISP 2240 may perform a signal processing operation on raw data received from an image sensor (not shown) located outside the SoC 2200 , and may generate digital data with improved image quality.

[0098] The MIF 2250 may provide an interface to the memory device 2300 located outside the SoC 2200. The memory device 2300 may be a DRAM, a phase change random access memory (PRAM), a resistive random access memory (ReRAM), or a flash memory.

[0099] The CMU 2260 may generate a clock signal and provide the clock signal to the components of the SoC 2200. The CMU 2260 may include a clock generating device such as a PLL, a DLL, or a crystal. The PMU 2270 may convert external power into internal power and supply the internal power to the components of the SoC 2200.

[0100] Fig.10 is a block diagram of a communication device 3000 including an application processor (AP) 3010 according to some example embodiments.

[0101] Reference Fig.10 , the communication device 3000 may include an AP 3010, a memory device 3020, a display 3030, an input device 3040, and a radio transceiver 3050. The AP 3010 may be the above-referenced Figures 1 to 9 An implementation example of at least one of the IP devices is described.

[0102] The radio transceiver 3050 may transmit or receive a radio signal via the antenna 3060. For example, the radio transceiver 3050 may change a radio signal received through the antenna 3060 into a signal that can be processed by the AP 3010.

[0103] Therefore, the AP 3010 may process the signal output by the radio transceiver 3050 and transmit the processed signal to the display 3030. The radio transceiver 3050 may change the signal output by the AP 3010 into a radio signal and output the radio signal to the external device through the antenna 3060.

[0104] The input device 3040 is capable of inputting a control signal for controlling the operation of the AP 3010 or data to be processed by the AP 3010 , and may be implemented as a pointing device such as a touch pad and a computer mouse, a keypad, or a keyboard.

[0105] According to some example embodiments, the AP 3010 may include a plurality of sub-blocks and a DVFS controller for controlling operating conditions of the plurality of sub-blocks. Figures 1 to 9 As described above, the DVFS controller may reduce the voltage droop of the output voltage by performing the DVFS operation based on the overall frequency response analysis.

[0106] although Fig.10 Although not shown in the figure, the communication device 3000 may further include a clock management unit that provides a clock signal and a power management unit that provides a power supply voltage in addition to various components provided in the communication device 3000. The clock management unit may output a clock signal having a frequency adjusted under the control of the DVFS controller, and the power management unit may output a power supply voltage having a magnitude adjusted under the control of the DVFS controller.

[0107] As described herein, any device, system, module, portion, unit, controller, circuit and / or portion thereof according to any of the example embodiments, and / or any portion thereof (including but not limited to system 10, IP device 11, CMU 12, PMU 13, sub-block 11_1, DVFS controller 11_2, computing system 200, DVFS controller 210, CMU 220, PMU 230, PDN 240, sub-block 250, feedback block 260, CMU filter 211, PMU filter 212, computing system 700, DVFS controller 710, CMU 720, PMU 730, PDN 740, sub-block 750, feedback block 760, Q filter 770, Q filter 780, CMU filter 711, PMU filter 712, feedback sensor 761, one or more refinement filters 762, system 2000, Soc 2200, memory device 2300, CPU 2210, GPU 2220, NPU 2230, ISP 2240, memory interface (MIF) 2250, clock management unit (CMU) 2260, power management unit (PMU) 2270, communication device 3000, AP 3010, memory device 3020, display 3030, input device 3040, radio transceiver 3050, or any part thereof, etc.) may include one or more instances of a processing circuit (such as hardware including a logic circuit, a hardware / software combination (such as a processor that executes software), or a combination thereof), may be included in one or more instances of a processing circuit (such as hardware including a logic circuit, a hardware / software combination (such as a processor that executes software), or a combination thereof) and / or may be implemented by one or more instances of a processing circuit (such as hardware including a logic circuit, a hardware / software combination (such as a processor that executes software), or a combination thereof). For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) storing a program of instructions (e.g., a solid-state drive (SSD)) and a processor (e.g., a CPU), the processor (e.g., a CPU) being configured to execute the program of instructions to implement the functions and / or methods performed by some or all of any device, system, module, portion, unit, controller, circuit, and / or portions thereof according to any one of the example embodiments.

[0108] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: At least one sub-block circuit is configured to: process instructions; as well as A dynamic voltage-frequency regulation controller is configured to control a power management unit and a clock management unit to control an operating voltage and an operating frequency, respectively, based on a resonant frequency calculated from a frequency response generated by dynamic characteristics of an entire power system, wherein the entire power system includes a power management unit, a power delivery network, and at least one sub-block circuit.

2. The integrated circuit of claim 1 , further comprising: The feedback block circuit is configured to: detect the output of the entire power system to generate a feedback signal, and send the feedback signal to the dynamic voltage and frequency regulation controller.

3. The integrated circuit according to claim 2, wherein: The feedback block circuit includes: A feedback sensor configured to: detect an output of the entire power supply system and generate a first signal; and The refinement filter is configured to generate a second signal based on reprocessing the first signal, and send the second signal as a feedback signal to the dynamic voltage frequency regulation controller.

4. The integrated circuit according to claim 1, wherein: The dynamic voltage frequency scaling controller is configured to control the power management unit and the clock management unit to control the operating voltage and the operating frequency, respectively, based on the primary resonant frequency and the secondary resonant frequency both calculated from the frequency response.

5. The integrated circuit according to claim 1, wherein: The dynamic voltage frequency scaling controller includes: a power management unit driving circuit configured to: output a voltage control signal for adjusting an operating voltage to the power management unit; and The clock management unit driving circuit is configured to output a frequency control signal for adjusting the operating frequency to the clock management unit.

6. The integrated circuit according to claim 5, wherein: The clock management unit driving circuit is configured to send a frequency control signal that controls the operating frequency to avoid the resonant frequency.

7. The integrated circuit according to claim 5, wherein: The power management unit driving circuit is configured to send a voltage control signal that controls the operating voltage to increase based on determining that the operating frequency is adjacent to the resonant frequency.

8. The integrated circuit of claim 5, further comprising: A first Q filter is configured to: process noise of the voltage control signal; as well as The second Q filter is configured to process noise of the frequency control signal.

9. An integrated circuit according to any one of claims 1 to 8, wherein: The dynamic voltage frequency scaling controller is an analog circuit including a combination of analog circuit elements.

10. A method for operating a dynamic voltage and frequency scaling controller, the dynamic voltage and frequency scaling controller being used to control an operating voltage and an operating frequency of an integrated circuit, the method comprising: receiving a resonant frequency calculated from a frequency response resulting from a dynamic characteristic of an entire power system, the entire power system including a power management unit power management unit, a power delivery network, and a sub-block circuit; receiving a feedback signal corresponding to the output of the entire power system to which the operating voltage and the operating frequency are applied; as well as Based on the resonant frequency and the feedback signal, the power management unit and the clock management unit are controlled to update the operating voltage and the operating frequency respectively.

11. The method according to claim 10, wherein: The resonant frequency includes a primary resonant frequency and a secondary resonant frequency.

12. The method according to claim 10, wherein: The step of controlling includes outputting a frequency control signal for controlling the operating frequency to avoid the resonance frequency.

13. The method according to claim 10, wherein: The step of controlling includes outputting a voltage control signal for controlling the operating voltage based on determining that the operating frequency is adjacent to the resonant frequency.

14. The method according to any one of claims 10 to 13, wherein: The dynamic voltage frequency scaling controller is an analog circuit including a combination of analog circuit elements.

15. A dynamic voltage frequency regulation controller, comprising: The power management unit driving circuit is configured to: output a voltage control signal for adjusting the operating voltage to the power management unit; as well as The clock management unit driving circuit is configured to: output a frequency control signal for adjusting the operating frequency to the clock management unit, Among them, the power management unit and the clock management unit are respectively controlled to control the operating voltage and the operating frequency based on the resonant frequency calculated from the frequency response generated by the dynamic characteristics of the entire power system, and the entire power system includes the power management unit, the power delivery network and the sub-block circuit configured to process instructions.

16. The dynamic voltage frequency adjustment controller according to claim 15, wherein: The feedback signal is received from a feedback block circuit that detects the output of the entire power system.

17. The dynamic voltage frequency adjustment controller according to claim 15, wherein: The power management unit and the clock management unit are caused to control the operating voltage and the operating frequency, respectively, based on the primary resonant frequency and the secondary resonant frequency both calculated from the frequency response.

18. The dynamic voltage frequency adjustment controller according to claim 15, wherein: The clock management unit driving circuit is configured to send a frequency control signal that controls the operating frequency to avoid the resonant frequency.

19. The dynamic voltage frequency adjustment controller according to claim 15, wherein: The power management unit driving circuit is configured to send a voltage control signal that controls the operating voltage to increase based on determining that the operating frequency is adjacent to the resonant frequency.

20. The dynamic voltage frequency regulation controller according to any one of claims 15 to 19, wherein: The dynamic voltage frequency scaling controller is an analog circuit including a combination of analog circuit elements.

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