Current source circuit, ramp generator, analog-to-digital converter and chip

Abstract

The invention provides a current source circuit, a ramp generator, an analog-to-digital converter and a chip, the current source circuit is provided with a reference current generating circuit, a current mirror circuit and a clamping circuit, the current of a reference current source is mirrored through n mirror image branches, and the current generated by a current mirror is further clamped and shunted through the clamping circuit; the mirror image branch connected with the first input end or the second input end of the clamping circuit determines the magnitude of the output current of the current source circuit, the circuit is simple and easy to implement, the precision of the output current can be accurately controlled through gating of the mirror image branch, and the reliability of the current source circuit is improved. Meanwhile, the problem that in an existing scheme, when the adjustment digit of the needed output current is high, the number of transistors needing to be stacked is increased in an exponential mode can be solved, the balance between the current adjustment precision and the chip layout area can be achieved, and therefore the performance of the slope generator, the analog-digital converter and the chip designed based on the current source circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and in particular to a current source circuit, a ramp generator, an analog-to-digital converter and a chip. Background Art

[0002] In traditional functional chips such as optical fingerprint chips or image sensor chips, a single slope analog-to-digital converter (SS-ADC) is usually used to convert analog signals into digital signals.

[0003] A typical ADC is usually provided with a ramp generator, and the product of the output current Iramp of the current source circuit in the ramp generator and the corresponding clock cycle clk determines the accuracy of the ADC. In order to cope with the influence of components such as resistors and capacitors on the accuracy of the ADC due to the change of process corners, Iramp is usually required to be adjustable.

[0004] However, existing current source circuits generally have problems such as being unable to accurately control the Iramp reduction multiple and being unable to achieve a balance between current adjustment accuracy and chip layout area. Summary of the invention

[0005] The object of the present invention is to provide a current source circuit, a ramp generator, an analog-to-digital converter and a chip, which can reduce the number of MOS tubes while ensuring the current accuracy, so as to simplify the circuit and avoid the exponential expansion of the entire chip layout area.

[0006] To achieve the above object, the present invention provides a current source circuit, comprising:

[0007] A reference current generating circuit comprises a reference current source and a first transistor, wherein a gate and a drain of the first transistor are coupled to an output terminal of the reference current source;

[0008] A current mirror circuit, comprising a second transistor and n mirror branches, wherein the second transistor is communally connected with the first transistor and mirrors the current flowing through the first transistor, and input ends of the n mirror branches are all coupled to the drain of the second transistor for shunting the current flowing through the second transistor;

[0009] A clamping circuit, wherein a first input end is coupled to the m-way mirror branch among the n-way mirror branches and forms an output end of the current source circuit, and a second input end is coupled to the a-way mirror branch among the n-way mirror branches, and the clamping circuit is used to clamp the outputs of the m-way mirror branch and the a-way mirror branch so that the voltages of the first input end and the second input end are equal;

[0010] Among them, n, a, and m are all integers, 1≤m≤n, 0≤a≤n, and the output current provided by the current source circuit is related to the mirror branch connected to the first input terminal or the second input terminal.

[0011] Optionally, the reference current generating branch also includes a common-gate transistor, which is coupled between the drain of the first transistor and the output end of the reference current source, and the gate of the common-gate transistor is coupled to each of the mirror branches to provide a bias voltage to each of the mirror branches.

[0012] Optionally, a=nm, and the a-way mirror branch is the nm-way mirror branch remaining after removing the m-way mirror branch from the n-way mirror branch.

[0013] Optionally, the n mirror branches divide the current flowing through the second transistor into n equal parts, and when k of the m mirror branches are turned on and q of the a mirror branches are turned on, the calculation formula of the output current is: I ramp =b*I0*k / (k+q), where I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor, 1≤k≤m, 0≤q≤nm.

[0014] Optionally, it is characterized in that k=1, 1+q=2 j , and j is an integer ≥0.

[0015] Optionally, the structures of the n mirror branches are the same and all include the same number of shunt transistors, multiple shunt transistors in any one of the mirror branches are stacked in series, and the gates of all the shunt transistors are coupled together, and the source of the first shunt transistor in each of the mirror branches serves as the input end of the mirror branch and is coupled to the drain of the second transistor.

[0016] Optionally, the n mirror branches divide the current flowing through the second transistor into n parts, and at least two of the n parts have different magnitudes.

[0017] Optionally, the n currents are all different in magnitude and are in a first geometric progression with a common ratio of x.

[0018] Optionally, each of the mirror branches includes a corresponding number of shunt transistors; the multiple shunt transistors in each of the mirror branches are connected to the same gate and stacked in series, and the source of the first shunt transistor among the multiple shunt transistors serves as the input end of the mirror branch and is coupled to the drain of the second transistor; wherein the magnitude of the current shunted by each of the mirror branches depends on the number and width-to-length ratio of its shunt transistors.

[0019] Optionally, each of the mirror branches includes one shunt transistor, and the width-to-length ratios of the n shunt transistors are all different and are in a second geometric progression with a common ratio of x.

[0020] Optionally, among the n mirror branches, the output end of each mirror branch is coupled to the first input end and the second input end, and is disconnected from the second input end when being connected to the first input end. At this time, m=a=n, and the calculation formula of the output current is:

[0021]

[0022] Among them, I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor; S i has a one-to-one correspondence with the i-th mirror branch, and S i =1, it indicates that the i-th mirror branch is connected to the first input terminal, S i =0 indicates that the i-th mirror branch is disconnected from the first input terminal.

[0023] Optionally, all the shunt transistors in the n mirror branches have the same width-to-length ratio, and the number of the shunt transistors in each mirror branch is a third geometric progression with a common ratio of y, where y is the reciprocal of x.

[0024] Optionally, the clamping circuit includes a unit gain negative feedback amplifier, the non-inverting input terminal of the unit gain negative feedback amplifier is the first input terminal, the inverting input terminal of the unit gain negative feedback amplifier is the second input terminal and the output terminal of the unit gain negative feedback amplifier is coupled to the inverting input terminal of the unit gain negative feedback amplifier.

[0025] Optionally, the gating circuit is a multi-way gating device, or the gating circuit includes a plurality of gating switches; the multi-way gating device or each of the gating switches is coupled between the input end of the corresponding mirror branch and the drain of the second transistor, or is coupled between the output end of the corresponding mirror branch and the corresponding input end of the clamping circuit.

[0026] Based on the same inventive concept, the present invention also provides a ramp generator, which includes an operational amplifier, a charging capacitor and a current source circuit as described in the present invention, wherein the output end of the current source circuit is coupled to one end of the charging capacitor and the first input end of the operational amplifier, and the other end of the charging capacitor is coupled to the output end of the operational amplifier. The output current of the current source circuit flows through the charging capacitor to generate a ramp voltage.

[0027] Optionally, the ramp generator further includes a reference voltage circuit, an output end of the reference voltage circuit is coupled to the second input end of the operational amplifier, and is used to provide a corresponding reference voltage to the operational amplifier.

[0028] Based on the same inventive concept, the present invention also provides an analog-to-digital converter, which includes a comparator, a counter and a ramp generator as described in the present invention; the output end of the ramp generator is coupled to the first input end of the comparator, the second input end of the comparator is coupled to the corresponding analog input signal, and the output end of the comparator is coupled to the counter.

[0029] Based on the same inventive concept, the present invention further provides a chip, which includes the analog-to-digital converter as described in the present invention.

[0030] Optionally, the chip is used to convert the received optical signal into an electrical signal, such as an optical fingerprint chip or an image sensor chip.

[0031] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0032] 1. The current flowing through the first transistor is mirrored by the second transistor in the current mirror circuit, and the current flowing through the second transistor is further divided into n ways by n mirror branches in the current mirror circuit. The current output by the current mirror circuit is clamped by a clamp circuit. The mirror branch connected to the first input terminal or the second input terminal of the clamp circuit determines the size of the output current of the current source circuit (that is, determines the current adjustment accuracy of the output current of the current source circuit). The circuit is simple and easy to implement.

[0033] 2. By gating the mirror branch, the accuracy of the output current can be precisely controlled.

[0034] 3. The larger the number of n is, the higher the number of output current adjustment bits that can be achieved. When each mirror branch has only one shunt transistor, the number of stacked shunt transistors increases by 1 every time n increases by 1. This can solve the problem of the existing solution that the number of stacked transistors increases exponentially when the required number of output current adjustment bits is high, avoid the problem of exponential expansion of the entire chip layout area, and achieve a balance between current adjustment accuracy and chip layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0036] Figure 1 It is a structural schematic diagram of an existing current source circuit.

[0037] Figure 2 It is a structural schematic diagram of another existing current source circuit.

[0038] Figure 3 Schematic diagram of the structure of the current source circuit of the first embodiment of the present invention.

[0039] Figure 4 yes Figure 3 Schematic diagram of the equivalent structure when k=q=1 in the current source circuit shown.

[0040] Figure 5 yes Figure 3 Schematic diagram of the equivalent structure when k=m, q=nm in the current source circuit shown.

[0041] Figure 6 4 is a schematic structural diagram of a current source circuit according to a second embodiment of the present invention.

[0042] Figure 7 4 is a schematic structural diagram of a current source circuit according to a third embodiment of the present invention.

[0043] Figure 8 4 is a schematic diagram of the structure of a ramp generator according to a fourth embodiment of the present invention.

[0044] Fig. 9 4 is a schematic structural diagram of an analog-to-digital converter according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0045] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Figure 1 The invention discloses a current source circuit for a ramp generator of an ADC, and the output current Iramp can be adjusted by 8 bits. The current source circuit includes switches s0 to s8, a switch pd, and eight reference current sources with decreasing current multiples of I, I / 2, I / 4, I / 8, I / 16, I / 32, I / 64, and I / 128, and two reference current sources of I / 256. One end of the ten reference current sources is connected together, and the other end is connected to one end of switches s0 to s8 and switch pd in a one-to-one correspondence. The other ends of the ten switches are connected together to provide the output current Iramp. Thus, the magnitude of the output Iramp current can be controlled by turning on and off switches s0 to s8 and switch pd.

[0047] In this way, when the number of connected reference current sources increases, it is difficult to ensure the multiple relationship between the output current values ​​of each bit, that is, this solution cannot accurately control the multiple of Iramp decrease.

[0048] Figure 2This is another existing current source circuit used in a ramp generator for ADC, which adopts the method of superimposing n MOS tubes M1~Mn on the current source tube M0 to achieve a multiple reduction of the output current Iramp, wherein the types of the MOS tubes M0~Mn can be pmos or nmos. After M1~Mn are all turned on, the drain current of Mn is the output current Iramp provided by the current source circuit.

[0049] Taking pmos as an example, the specific principle of the current source circuit to achieve multiple reduction of the output current Iramp is as follows:

[0050] First, the formula between the drain current of any MOS tube and its width-to-length ratio (that is, the voltage-to-current formula of the MOS tube) is:

[0051]

[0052] Among them, Kn is the constant of the MOS tube, Vgs is the gate-source voltage of the MOS tube, Vth is the threshold voltage of the MOS tube, W / L is the width-to-length ratio of the MOS tube, and I is the drain current of the MOS tube after it is turned on.

[0053] It can be seen from the above current formula that the drain current (i.e., output current) of the MOS tube is proportional to the width-to-length ratio of the MOS tube. Changing the gate-source voltage Vgs of Mn can directly change the size of the output current Iramp provided by the current source circuit, and the gate-source voltage Vgs of Mn is equal to the difference between the gate voltage and the source voltage of Mn, and the gate voltage of Mn is determined by I0, and the source voltage of Mn is determined by the number n of MOS tubes superimposed on M0. The more the number n of MOS tubes superimposed on M0, the smaller the source voltage of Mn. Therefore, the number n determines the gate-source voltage Vgs of the MOS tube Mn, and then determines the size of the output current Iramp.

[0054] Combining the voltage-to-current formula of the above MOS tube, the formula for the output current Iramp provided by the current source circuit can be deduced as follows:

[0055]

[0056] Among them, I0 is the reference current, and n is the number of MOSFETs stacked on M0 (i.e., the number of M1 to Mn).

[0057] When n=1, the output current Iramp / I0=0.536, and so on. If Iramp / I0=0.25, then n=4, and if Iramp / I0=0.128, then n=10.

[0058] From the above formula of output current Iramp, it can be seen that the larger n is, the more MOS tubes will be stacked on M0, which will cause the entire chip layout area to expand. And because n can only be an integer, the ratio of Iramp / I0 cannot be an arbitrary fraction. In other words, the current source circuit cannot accurately control the accuracy of its output current Iramp, nor can it achieve a balance between the current adjustment accuracy and the chip layout area.

[0059] Based on this, the present invention provides a current source circuit, a current source, a ramp generator, an analog-to-digital converter and a chip, which adopt a new current shunt architecture, can accurately control the accuracy of the output current, and while achieving the required output current accuracy, can also reduce the number of superimposed MOS tubes, and is suitable for application scenarios of multi-bit current regulation, such as a successive approximation analog-to-digital converter under multi-bit current regulation.

[0060] The following is combined with Figure 3 To Attachment Fig. 9 The technical solution proposed by the present invention is further described in detail with specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0061] First embodiment

[0062] Please refer to Figure 3 , this embodiment provides a current source circuit 101, which includes a reference current generating circuit 101a, a current mirror circuit 101b, a gating circuit 101c and a clamping circuit 101d.

[0063] The reference current generating circuit 101a comprises a reference current source I0, a first transistor Mp0 and a common-gate transistor MP1, and the reference current source I0 is used to provide a reference current I0. The current mirror circuit 101b comprises a second transistor M0 and n shunt transistors M1 to Mn. The gating circuit 101c comprises n gating switches S <1> ~S <n>The clamping circuit 101d includes a unity gain negative feedback amplifier amp.

[0064] The first transistor Mp0, the common-gate transistor Mp1, the second transistor M0 and n shunt transistors M1-Mn form a cascade current mirror structure, which, on the one hand, increases the output impedance, thereby increasing the intrinsic gain by times and making the output current Iramp more stable; on the other hand, makes the current mirror copy current more accurately.

[0065] Exemplarily, the source of the first transistor Mp0 and the source of the second transistor M0 are coupled to the power supply voltage VDD, and the gate of the first transistor Mp0 is coupled to the gate of the second transistor M0 and the output end of the reference current source I0, so that the first transistor Mp0 and the second transistor M0 are connected in common gate and source. The other end of the reference current source I0 is grounded. The drain of the first transistor Mp0 is coupled to the source of the common-gate transistor Mp1.

[0066] The sizes of the common-gate transistor Mp1 and the first transistor Mp0 are different. The first transistor Mp0 is responsible for controlling the reference current I0 output by the reference current generating circuit 101a, and converting the reference current I0 into a bias voltage Vbp2, and providing it to the second transistor M0. Further considering the mismatch requirement, the size of the first transistor Mp0 is relatively large.

[0067] The common-gate transistor Mp1 can play the following roles: (1) It is responsible for providing small signal gain to increase the output impedance, and considering the transconductance requirements, the width-to-length ratio of the common-gate transistor Mp1 is relatively high; (2) It plays the role of a shunt resistor.

[0068] The sources of the n shunt transistors M1 to Mn are all coupled to the drain of the second transistor M0, and the gates of the n shunt transistors M1 to Mn are all coupled to the gate of the common-gate transistor Mp1, so that the n shunt transistors M1 to Mn are connected in common source and common gate to form n mirror branches. <1> ~S <n>The input terminals of the shunt transistor M1 are connected one by one. For example, the drain of the shunt transistor M1 is connected to the gate switch S <1> The input terminal of the shunt transistor M2 is connected to the drain of the gate switch S <2> The input terminal of the shunt transistor Mm is connected to the input terminal of the gate switch S. <m>The input terminal of the shunt transistor Mm+1 is connected to the drain of the gate switch S<m+1> The input terminal of the shunt transistor Mn-1 is connected to the drain of the gate switch S <n-1>The input terminal of the shunt transistor Mn is connected to the drain of the gate switch S <n>The input terminal connection of

[0069] In this embodiment, the current mirror circuit adopts a common source and common gate structure, which can effectively reduce the channel modulation effect, thereby reducing the change of the output current with the change of the power supply voltage VDD and improving the power supply rejection ratio. At the same time, the bias voltage is provided to the current mirror circuit through the first transistor Mp0 and the common gate transistor Mp1, eliminating the additional bias circuit and simplifying the circuit structure.

[0070] Strobe switch S <1> ~Switch S <n>They are all controlled independently of each other. <1> ~Switch S <m>The output terminals of the m selection switches are all coupled to the non-inverting input terminal of the unity gain negative feedback amplifier amp to form the output terminal A of the current source circuit. <1> ~Switch S <m>The conduction or shutoff of the gate switch S controls the conduction and shutoff of the circuit between the m mirror branches where the shunt transistors M1 to Mm are located and the non-inverting input terminal of the unit gain negative feedback amplifier amp, thereby controlling the output current Iramp provided by the output terminal A of the current source circuit.<m+1> ~Switch S <n>The output ends of the nm gate switches are coupled to the inverting input and output ends of the unity gain negative feedback amplifier amp to form a node B.<m+1> ~Switch S <n>The conduction or shutoff of the circuit between the nm-way mirror branch where the shunt transistors Mm+1 to Mn are located and the inverting input terminal of the unity gain negative feedback amplifier amp is controlled to control the conduction and shutoff of the circuit, thereby controlling the voltage of the node B.

[0071] In this embodiment, the output of the unit gain negative feedback amplifier amp is always equal to the input, and the unit gain negative feedback amplifier amp clamps the voltage of the output terminal A and the node B so that the voltage of the output terminal A (i.e., the non-inverting input terminal of amp) and the voltage of the node B (i.e., the inverting input terminal of amp) are equal, that is, the k-path mirror branch that is turned on in the m-path mirror branch where the shunt transistors M1 to Mm are located is clamped, and the q-path mirror branch that is turned on in the nm-path mirror branch where the shunt transistors Mm+1 to Mn are located is clamped so that the drain voltages of the shunt transistors in these turned-on mirror branches are the same, which is equivalent to shunting the current flowing through the second transistor M0 through these turned-on mirror branches.

[0072] The maximum adjustable bit number of the output current Iramp provided by the current source circuit 101 is n bits. When the width-to-length ratios of the n shunt transistors M1 to Mn are the same, the gate switch S <1> ~Switch S <m>Control the conduction of k-way in the m-way mirror branch and select the switch S<m+1> ~Switch S <n>Control the q path of the remaining nm path mirror branches to be turned on, M0 mirrors the reference current I0 flowing through Mp0 according to the mirror ratio of b:1, then the current flowing through M0 is b*I0, after the k path and q path are turned on, the current flowing through M0 is divided into k+q parts, so the output current Iramp=b*I0*k / (k+q). Wherein, I0 is the reference current output by the reference current source I0, b is the mirror ratio between the second transistor M0 and the first transistor Mp0, and 1≤k≤m, 0≤q≤nm, k, q, n are all integers. And at this time, k and q can be adaptively adjusted according to S <1> ~S <n>changes with the changes of.

[0073] Therefore, when n is determined, the switch control signal S <n:1>The output current Iramp can be adjusted by n bits. <n:1>The difference in k and q can be precisely controlled, and the value of k / (k+q) can be precisely controlled, so that the output current Iramp is not limited to being adjusted in a 2-fold decreasing manner, but can be adjusted by any desired multiple k / (k+q). In addition, while achieving the adjustment of multi-bit output current, it will not cause an exponential increase in transistors, so the area of ​​the current source circuit for achieving multi-bit output current adjustment can be reduced, avoiding an exponential increase in the chip layout area.

[0074] As an example, n≥2, among the m mirror branches coupled to the output terminal A, only the mirror branch where M1 is located is conductive with the output terminal A, and among the nm mirror branches coupled to the node B, only the mirror branch where M2 is located is conductive with the node B. At this time, k=1, q=1, and the equivalent circuit of the current source circuit of this embodiment is as follows: Figure 4 As shown. In the unit gain negative feedback amplifier amp, M0 is divided into two shunt transistors M1 and M2 of the same size, and the currents flowing through M1 and M2 are equal. Assuming that M0 mirrors the reference current I0 flowing through Mp0 at a mirror ratio of 1:1, the currents flowing through M1 and M2 are both equal to I0 / 2, and the output current Iramp = I0 / 2.

[0075] As another example, n≥2, all m mirror branches coupled to the output terminal A are connected to the output terminal A, and all nm mirror branches coupled to the node B are connected to the node B. At this time, k=m, q=nm, and the equivalent circuit of the current source circuit of this embodiment is as follows: Figure 5 As shown. In the unit gain negative feedback amplifier amp, M0 is divided into n shunt transistors M1 to Mn of the same size, and the currents flowing through M1 to Mn are equal. Assuming that M0 mirrors the reference current I0 flowing through Mp0 at a mirror ratio of 1:1, the currents flowing through M1 to Mn are all equal to I0 / n, and the output current Iramp = I0*m / n.

[0076] As another example, see Figure 3 and Figures 8 to 9 The current source circuit is applied to the slope generator of a single slope ADC (SS-ADC, single slope analog-to-digital converter), wherein the width-to-length ratios of the n shunt transistors M1-Mn are the same, and only one of the m mirror branches coupled to the output terminal A is conductive with the output terminal A (i.e., k=1), and q of the nm mirror branches coupled to the node B are conductive with the node B, and 1+q=2 j , j is an integer and j ≥ 0, for example 2 j =1, 2, 4…, in this case, the output current Iramp can be reduced by 2 times.

[0077] It should be understood that the gating circuit 101c in this embodiment is composed of n gating switches S <1> ~Switch S <m>and are respectively coupled between the shunt transistor and the output terminal A. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, n gate switches S <1> ~Switch S <m>They can be coupled between the source of the shunt transistor and the drain of M0, and can also control the on-off between the mirror branch and the unit gain negative feedback amplifier. <1> ~Switch S <m>It can also be replaced by a multiplexer, that is, the gating circuit 101c can also be a multiplexer, and the multiplexer can be an integrated device or a dedicated circuit. In other embodiments of the present invention, when a constant current source with an unadjustable output current is required, the values ​​of n, k or m, q or nm can be designed according to the performance requirements of the constant current source, and the gating switch S can be omitted. <0> ~Switch S <m-1>, the drains of k shunt transistors among the m shunt transistors are directly connected to the output terminal A, and the drains of q shunt transistors among the nm shunt transistors are directly connected to the node B, thereby outputting an output current Iramp=I0*k / (k+q) of a fixed proportion, where k and q are both fixed values.

[0078] In summary, the current source circuit of this embodiment mirrors the current of the reference current source through n mirror branches with shunt transistors, and further clamps and shunts the current generated by the current mirror through a clamping circuit. The mirror branch connected to the first input terminal or the second input terminal of the clamping circuit determines the size of the output current of the current source circuit (that is, determines the current adjustment accuracy of the output current of the current source circuit). The circuit is simple and easy to implement. Moreover, by gating the mirror branch, the accuracy of the output current can be accurately controlled. Among them, the larger the n, the higher the number of adjustable bits (bits) of the output current that can be achieved. For every increase of n by 1, the number of superimposed shunt transistors increases by 1. This can solve the problem of the exponential increase of transistors required to be superimposed when the required number of adjustable bits (bits) of the output current is high in the existing solution, avoid the problem of exponential expansion of the entire chip layout area, and achieve a balance between the current adjustment accuracy and the chip layout area.

[0079] It is worth noting that in this embodiment, the example is taken that each of the n mirror branches is composed of a shunt transistor, and the width-to-length ratios of the n shunt transistors M1 to Mn are the same, but the technical solution of the present invention is not limited thereto.

[0080] For example, in another embodiment of the present invention, in the n mirror branches, each mirror branch is composed of c shunt transistors stacked in series, and the width-to-length ratios of the c shunt transistors may be the same or different, but the n mirror branches can still shunt the current flowing through the second transistor into n equal parts. At this time, the m mirror branches are still coupled to the output terminal A, and the remaining nm mirror branches are coupled to the output terminal B. By controlling the on and off of each mirror branch, k of the m mirror branches are turned on, and q of the remaining nm mirror branches are turned on, thereby achieving the effect of controlling the output current Iramp=I0*k / (k+q) of the current source circuit.

[0081] For another example, in another embodiment of the present invention, the current source circuit can still be used Figure 3 The circuit structure shown in FIG. 1 is shown in FIG. 1 , but the width-to-length ratios of the n shunt transistors M1 to Mn may not be completely the same or may be different from each other. The n-bit switch control signal S <n:1>The n-bit adjustment of the output current Iramp can be achieved, but the magnitude of the output current in this case will be different from the output current Iramp in this embodiment due to the different width-to-length ratios of the n shunt transistors M1 to Mn, and the calculation formula of the output current is relatively complicated.

[0082] Second embodiment

[0083] Please refer to Figure 6 This embodiment provides a current source circuit 101, which consists of Figure 3 The circuit shown is further modified to achieve multi-bit output current regulation when the width-to-length ratios of the n shunt transistors M1 to Mn are different from each other.

[0084] The current source circuit 101 also includes a reference current generating circuit 101a, a current mirror circuit 101b, a gating circuit 101c and a clamping circuit 101d.

[0085] The current source circuit 101 provided in this embodiment differs from the current source circuit 101 in the first embodiment in the following two aspects: (1) the gating circuit 101c includes a gating switch S <1> ~Switch S <n>and the strobe switch S_ <1> ~Select switch S_ <n>, a total of 2n gate switches. Among them, the drain of each shunt transistor Mi is coupled to the gate switch S arranged in pairs. ~ and the selection switch S_ , and the switch S The output terminal of is coupled to the output terminal A, and the gate switch S_ The output terminals of the switches S and S_ When one of them is turned on, the other is turned off, i=1-n. (2) The width-to-length ratios of the n shunt transistors are all different and the width-to-length ratios of the n shunt transistors are a geometric progression, and the common ratio of the geometric progression is x.

[0086] For example, the gate switch S <1> and the strobe switch S_ <1> Set in pairs, select switch S <1> and the strobe switch S_ <1> The input terminals of the shunt transistor M1 are coupled to the drain of the shunt transistor M1, and the gate switch S <1> The output terminal of is coupled to the output terminal A, and the gate switch S_ <1> The output terminal is coupled to node B, and the switch S <1> When turned on, the gate switch S_ <1> Turn off (i.e. cut off, disconnect). <2> and the strobe switch S_ <2> Set in pairs, select switch S <2> and the strobe switch S_ <2> The input terminals of the shunt transistor M2 are coupled to the drain of the shunt transistor M2, and the switch S <2> The output terminal of is coupled to the output terminal A, and the gate switch S_ <2> The output terminal is coupled to node B, and the switch S <2> When turned on, the gate switch S_ <2> Shut down. By analogy, the gate switch S <n>and the strobe switch S_ <n>Set in pairs, select switch S <n>and the strobe switch S_ <n>The input terminals of the shunt transistor Mn are coupled to the drain of the shunt transistor Mn, and the gate switch S <n>The output terminal of is coupled to the output terminal A, and the gate switch S_ <n>The output terminal is coupled to node B, and the switch S <n>When turned on, the gate switch S_ <n>Turn off (i.e. cut off, disconnect).

[0087] That is, among the n shunt transistors M1 to Mn, the drain of each shunt transistor is simultaneously coupled to the output terminal A and the node B through two gate switches arranged in pairs, and the drain of any shunt transistor is disconnected from the node B when it is connected to the output terminal A. At this time, the number a of mirror branches coupled to the output terminal A and the number a of mirror branches coupled to the node B are both n, that is, m=a=n.

[0088] In this embodiment, the width-to-length ratio of M2 is x times that of M1, the width-to-length ratio of M3 is x times that of M2, and so on, the width-to-length ratio of Mn is x times that of Mn-1.

[0089] According to the above formula between the drain current of the MOS tube and the width-to-length ratio of the MOS tube, it can be obtained that the drain current (i.e., the output current) of the MOS tube is proportional to its width-to-length ratio. If the width-to-length ratio of M1 is normalized to 1, and the current flowing through M1 is I1, then the width-to-length ratio of Mn is x n-1 , the current flowing through Mn is x n-1 *I1, the total current flowing through M1~Mn is equal to the current flowing through M0. Further, M0 mirrors the reference current I0 flowing through Mp0 according to the mirror ratio of b:1, and the current flowing through M0 is b*I0, and for the i-th shunt transistor in M1~Mn, when the switch S is turned on Turn on and enable switch S_ When turned off, the i-th shunt transistor is connected to the output terminal A (i.e., the first input terminal of the unit gain negative feedback amplifier amp), and the current of the mirror branch where the i-th shunt transistor is located flows to the output terminal A; the gate switch S Turn off and enable switch S_ When turned on, the i-th shunt transistor is disconnected from the output terminal A, and the current of the mirror branch where the i-th shunt transistor is located flows to the node B. Therefore, the total output current Iramp at the output terminal A of the current source circuit 101 is the sum of the currents of the mirror branches that are turned on to the output terminal A, that is, the total output current Iramp at the output terminal A of the current source circuit 101 is:

[0090]

[0091] Among them, I ramp is the output current, I0 is the reference current output by the reference current source I0, b is the mirror ratio between the second transistor M0 and the first transistor Mp0, and x is the common ratio of the geometric progression. i corresponds to the i-th shunt transistor, and S i =1, indicating the gate switch S Turn on and enable switch S_ The i-th shunt transistor is turned off, and the current between the i-th shunt transistor and the output terminal A (i.e., the first input terminal of the unity gain negative feedback amplifier amp) is turned on, and the current of the mirror branch where the i-th shunt transistor is located flows to the output terminal A; S i = 0, indicating the gate switch S Turn off and enable switch S_ The i-th shunt transistor is turned on, and the current in the mirror branch where the i-th shunt transistor is located flows to node B. The total output current Iramp is the sum of all S i =The sum of the output currents of the mirror branches with 1.

[0092] Therefore, when n is determined, the switch control signal S <n:1>The output current Iramp can be adjusted by n bits. <n:1>The S corresponding to the corresponding mirror branch can be accurately controlled. i The value of is 0 or 1, so that the output current Iramp is not limited to being adjusted in a 2-fold decreasing manner, but can be adjusted by any desired multiple. In addition, while achieving the adjustment of the multi-bit output current, it will not cause an exponential increase in transistors, so the area of ​​the current source circuit for achieving multi-bit output current adjustment can be reduced, avoiding an exponential increase in the chip layout area.

[0093] It should be understood that, in this embodiment, when the number of mirror branches conducting with the output terminal A is k, the number of mirror branches conducting with the node B is nk.

[0094] In addition, the current mirror circuit in this embodiment still adopts a common source and common gate structure, so that the channel modulation effect can be effectively reduced, which also reduces the change of the output current with the change of the power supply voltage VDD and improves the power supply rejection ratio. At the same time, the bias voltage is provided to the current mirror circuit through the first transistor Mp0 and the common gate transistor Mp1, eliminating the additional bias circuit and simplifying the circuit structure.

[0095] As an example, when x=2, the width-to-length ratio of M2 is twice that of M1, the width-to-length ratio of M3 is twice that of M2, and so on, the width-to-length ratio of Mn is twice that of Mn-1, and M0 mirrors the reference current I0 flowing through Mp0 at a mirror ratio of 1:1 (i.e., b=1). At this time, the total output current at the output terminal A is:

[0096]

[0097] In summary, the current source circuit of this embodiment also mirrors the current of the reference current source through the n-way mirror branch with shunt transistors of the current mirror, and further clamps and shunts the current generated by the current mirror through the clamping circuit. The mirror branch connected to the first input end of the clamping circuit determines the size of the output current of the current source circuit (that is, determines the current adjustment accuracy of the output current of the current source circuit). The circuit is simple and easy to implement. Moreover, by gating the mirror branch, the accuracy of the output current can be accurately controlled. Among them, the larger the n, the higher the number of adjustable bits (bits) of the output current that can be achieved. For every increase of n by 1, the number of superimposed shunt transistors increases by 1. This can solve the problem of the exponential increase of the number of superimposed transistors required when the required output current adjustment bit (bit) is high in the existing solution, avoid the problem of exponential expansion of the entire chip layout area, and achieve a balance between the current adjustment accuracy and the chip layout area.

[0098] Third embodiment

[0099] Please refer to Figure 7 This embodiment provides a current source circuit 101, which differs from the first embodiment and the second embodiment in that the number of shunt transistors in each of the n mirror branches can be different from each other, and it can also achieve the required output current accuracy by controlling the on-off of the n mirror branches.

[0100] As an example, see Figure 7 In this current source circuit, each mirror branch is composed of a shunt transistor, and the width-to-length ratio of all shunt transistors is the same, but the number of shunt transistors is a geometric progression with a common ratio of 2, so that the shunt of the current flowing through the second transistor by the n mirror branches is a geometric progression with a common ratio of 1 / 2. Among them, the first mirror branch is composed of a shunt transistor M1, the second mirror branch is composed of two shunt transistors M2_1 and M2_2 connected in series, and so on. The mth mirror branch is composed of 2 m-1 Shunt transistors Mm_1, Mm_2~Mm_2 m-1 The m+1th mirror branch is composed of 2 m Shunt transistors Mm+1_1, Mm+1_2~Mm+1_2 m The nth mirror branch is composed of 2 n Shunt transistors Mn_1, Mn_2~Mn_2 n-1 When the connection method between the output end of the n mirror branches in this example and the clamp circuit adopts the connection method in the second embodiment, that is, in the n mirror branches, the output end of each mirror branch is coupled to the first input end (i.e., output end A) and the second input end (i.e., node B) of the clamp circuit, and is disconnected from the second input end when it is connected to the first input end of the clamp circuit, and is connected to the second input end when it is disconnected from the first input end of the clamp circuit. At this time, m=a=n, and the calculation formula of the output current of the current source circuit is still:

[0101]

[0102] Among them, I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor; S i has a one-to-one correspondence with the i-th mirror branch, and S i =1, it indicates that the i-th mirror branch is connected to the first input terminal, S i =0 means that the i-th mirror branch is disconnected from the first input terminal, and x=1 / 2. That is, the output current is:

[0103]

[0104] When the connection method between the output ends of the n mirror branches in this example and the clamp circuit adopts the connection method in the first embodiment, that is, among the n mirror branches, the output ends of m mirror branches are coupled to the first input end of the clamp circuit (that is, the output end A), and the output ends of the remaining nm mirror branches are coupled to the second input end of the clamp circuit (that is, node B), and the k-way mirror branch among the m mirror branches coupled to the output end A is further controlled to be turned on, and the q-way mirror branch of the nm mirror branches coupled to the node B is controlled to be turned on, then the output current of the current source circuit is equal to the sum of the shunted currents of the turned-on k-way mirror branches, and the sum of the shunted currents of the turned-on k-way mirror branches and the turned-on q-way mirror branches is equal to the current flowing through the second transistor. It should be understood that in other embodiments of the present invention, as long as the number of shunt transistors and the width-to-length ratio of each mirror branch in the n-mirror branches can be matched with each other to achieve the shunt size required by the mirror branch, the current flowing through the second transistor is divided into n parts through the n-mirror branches, and the n parts of current can be equally divided or unequally divided. And the coupling method of the output end of the n-mirror branch and the two input ends of the clamping circuit can adopt the method of the first embodiment or the method of the second embodiment as needed, both of which can achieve the accuracy of accurately controlling the output current and achieve a balance between the current adjustment accuracy and the chip layout area to a certain extent.

[0105] Fourth embodiment

[0106] Please refer to Figure 8 The present embodiment further provides a ramp generator 10, which includes an operational amplifier vramp_op, a charging capacitor C1, and a current source circuit 101 as described in the present invention. The output end of the current source circuit 101 is coupled to the charging capacitor S i and a first input terminal (such as an inverting input terminal) of the operational amplifier vramp_op, and the other end of the charging capacitor C1 is coupled to the output terminal of the operational amplifier vramp_op. The output current Iramp of the current source circuit 101 flows through the charging capacitor C1 to generate a ramp voltage vramp that changes linearly with time.

[0107] Optionally, the ramp generator further includes a reference voltage circuit, an output end of which is coupled to a second input end (eg, a non-inverting input end) of the operational amplifier vramp_op, for providing a corresponding reference voltage to the operational amplifier vramp_op.

[0108] The reference voltage circuit may be implemented by any suitable circuit design, and may provide one reference voltage or a plurality of different reference voltages for selection, which is not specifically limited in the present invention.

[0109] As an example, the reference voltage circuit includes a voltage divider circuit 102 and selection switches vr1_sw, vr1_sw, vr2_sw, and vr3_sw. The voltage divider circuit 102 can generate three reference voltages vr1, vr2, and vr3 of different sizes based on the bias current Ib1 and the reference voltage vcm_res. When the selection switch vr1_sw is turned on, it can provide the reference voltage vr1 to the second input terminal of the operational amplifier vramp_op. When the selection switch vr2_sw is turned on, it can provide the reference voltage vr2 to the second input terminal of the operational amplifier vramp_op. When the selection switch vr3_sw is turned on, it can provide the reference voltage vr3 to the second input terminal of the operational amplifier vramp_op.

[0110] In this example, the ramp transmitter also includes a charge-discharge switch vr_sw, a charging capacitor C2, and a reset switch ramp_rst. When one of the selection switches vr1_sw, vr1_sw, vr2_sw, and vr3_sw is turned on, the voltage provided will charge the charging capacitor C2 after the charge-discharge switch vr_sw is turned on. After the charge-discharge switch vr_sw is turned off, the charging capacitor C2 stabilizes the voltage of the second input terminal of the operational amplifier vramp_op. One end of the reset switch ramp_rst is coupled to the first input terminal of the operational amplifier vramp_op, and the other end is coupled to the output terminal of the operational amplifier vramp_op. After the reset switch ramp_rst is turned on, it discharges the charging capacitor C1, thereby resetting the ramp voltage vramp.

[0111] Based on the same invention concept, please refer to Fig. 9 This embodiment also provides an analog-to-digital converter (ADC), which includes a comparator 11, a counter 12 and a ramp generator 10 as described in the present invention; the output end of the ramp generator 10 is coupled to the first input end of the comparator 11 (such as the in-phase input end "+"), the second input end of the comparator 11 (such as the inverting input end "-") is coupled to the corresponding analog input signal Vin, and the output end of the comparator 11 is coupled to the counter 12.

[0112] The product of the ramp voltage vramp output by the ramp generator 10 and the clock period clk of the counter 12 can determine the accuracy of the ADC. For example, the least significant bit (LSB) of the ADC is: LSB=Iramp*clk / C1.

[0113] Among them, since the ramp generator 10 is the ramp generator of the present invention, the output current Iramp provided by the current source circuit therein is adjustable, and the accuracy of the output current Iramp determines the accuracy of the ADC, and can cope with the influence of resistance and capacitance changing with the process corner on the ADC accuracy.

[0114] Based on the same inventive concept, this embodiment further provides a chip, which includes the analog-to-digital converter described in this embodiment. The analog-to-digital converter is used to convert an analog input signal Vin into a corresponding digital signal.

[0115] The chip may be a chip for converting a received optical signal into an electrical signal. For example, the chip may be an optical fingerprint chip or an image sensor chip, or any other functional chip that needs to convert an analog input signal into a digital signal.

[0116] The ramp generator, analog-to-digital converter and chip of this embodiment, due to the adoption of the current source circuit of the present invention, can provide multi-precision current regulation and reduce the chip area under multi-precision regulation, and can meet the needs of higher-precision products.

[0117] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / m> < / n> < / n> < / m> < / n> < / n>

Claims

1. A current source circuit, characterized in that: include: A reference current generating circuit comprises a reference current source and a first transistor, wherein a gate and a drain of the first transistor are coupled to an output terminal of the reference current source; A current mirror circuit, comprising a second transistor and n mirror branches, wherein the second transistor is communally connected with the first transistor and mirrors the current flowing through the first transistor, and input ends of the n mirror branches are all coupled to the drain of the second transistor for shunting the current flowing through the second transistor; A clamping circuit, wherein a first input end is coupled to the m-way mirror branch among the n-way mirror branches and forms an output end of the current source circuit, and a second input end is coupled to the a-way mirror branch among the n-way mirror branches, and the clamping circuit is used to clamp the outputs of the m-way mirror branch and the a-way mirror branch so that the voltages of the first input end and the second input end are equal; Among them, n, a, and m are all integers, 1≤m≤n, 0≤a≤n, and the output current provided by the current source circuit is related to the mirror branch connected to the first input terminal or the second input terminal.

2. The current source circuit according to claim 1, characterized in that: The reference current generating branch also includes a common-gate transistor, which is coupled between the drain of the first transistor and the output end of the reference current source, and the gate of the common-gate transistor is coupled to each of the mirror branches to provide a bias voltage to each of the mirror branches.

3. The current source circuit according to claim 1, characterized in that: a=nm, and the a-way mirror branch is the nm-way mirror branch remaining after removing the m-way mirror branch from the n-way mirror branch.

4. The current source circuit according to claim 3, characterized in that: The n mirror branches divide the current flowing through the second transistor into n equal parts, and when k of the m mirror branches are turned on and q of the a mirror branches are turned on, the calculation formula of the output current is: I ramp =b*I0*k / (k+q), where I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor, 1≤k≤m, 0≤q≤nm.

5. The current source circuit according to claim 4, characterized in that: k=1,1+q=2 j , and j is an integer ≥0.

6. The current source circuit according to claim 4, characterized in that: The structures of the n mirror branches are the same and all include the same number of shunt transistors. Multiple shunt transistors in any one of the mirror branches are stacked in series, and the gates of all the shunt transistors are coupled together. The source of the first shunt transistor in each of the mirror branches serves as the input end of the mirror branch and is coupled to the drain of the second transistor.

7. The current source circuit according to claim 1 or 3, characterized in that: The n mirror branches divide the current flowing through the second transistor into n parts, and at least two of the n parts have different magnitudes.

8. The current source circuit according to claim 7, characterized in that: The n currents are all different in magnitude and present a first geometric progression with a common ratio of x.

9. The current source circuit according to claim 8, characterized in that: Each of the mirror branches includes a corresponding number of shunt transistors; the multiple shunt transistors in each of the mirror branches are connected with a common gate and stacked in series, and the source of the first shunt transistor among the multiple shunt transistors serves as the input end of the mirror branch and is coupled to the drain of the second transistor; wherein the magnitude of the current shunted by each of the mirror branches depends on the number and width-to-length ratio of its shunt transistors.

10. The current source circuit according to claim 9, characterized in that: Each of the mirror branches includes a shunt transistor, and the width-to-length ratios of the n shunt transistors are all different and are in a second geometric progression with a common ratio of x.

11. The current source circuit according to claim 10, characterized in that: In the n mirror branches, the output end of each mirror branch is coupled to the first input end and the second input end, and is disconnected from the second input end when being connected to the first input end. At this time, m=a=n, and the calculation formula of the output current is: Among them, I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor; S i has a one-to-one correspondence with the i-th mirror branch, and S i =1, it indicates that the i-th mirror branch is connected to the first input terminal, S i =0 indicates that the i-th mirror branch is disconnected from the first input terminal.

12. The current source circuit according to claim 9, characterized in that: All the shunt transistors in the n mirror branches have the same width-to-length ratio, and the number of the shunt transistors in each mirror branch is a third geometric progression with a common ratio of y, where y is the reciprocal of x.

13. The current source circuit according to claim 1, characterized in that: The clamp circuit includes a unit gain negative feedback amplifier, the non-inverting input terminal of the unit gain negative feedback amplifier is the first input terminal, the inverting input terminal of the unit gain negative feedback amplifier is the second input terminal, and the output terminal of the unit gain negative feedback amplifier is coupled to the inverting input terminal of the unit gain negative feedback amplifier.

14. The current source circuit according to claim 1, characterized in that: The gating circuit is a multi-way gating device, or the gating circuit includes a plurality of gating switches; the multi-way gating device or each of the gating switches is coupled between the input end of the corresponding mirror branch and the drain of the second transistor, or is coupled between the output end of the corresponding mirror branch and the corresponding input end of the clamping circuit.

15. A ramp generator, characterized in that: It includes an operational amplifier, a charging capacitor and a current source circuit as described in any one of claims 1-14, wherein the output end of the current source circuit is coupled to one end of the charging capacitor and the first input end of the operational amplifier, the other end of the charging capacitor is coupled to the output end of the operational amplifier, and the output current of the current source circuit flows through the charging capacitor to generate a ramp voltage.

16. The ramp generator according to claim 15, characterized in that It also includes a reference voltage circuit, the output end of which is coupled to the second input end of the operational amplifier for providing a corresponding reference voltage to the operational amplifier.

17. An analog-to-digital converter, characterized in that: It comprises a comparator, a counter and a ramp generator as claimed in claim 15 or 16; the output end of the ramp generator is coupled to the first input end of the comparator, the second input end of the comparator is coupled to the corresponding analog input signal, and the output end of the comparator is coupled to the counter.

18. A chip, characterized in that: Comprising the analog-to-digital converter of claim 17.

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