Current source circuit, slope generator, analog-to-digital converter and chip

Abstract

The application provides a current source circuit, a slope generator, an analog-to-digital converter and a chip, the current source circuit has a reference current generation circuit, a current mirror circuit and a clamping circuit, the current of the reference current source is mirrored through n mirror branches, and the current generated by the current mirror is further shunted through the clamping circuit, the mirror branch connected to the first input end or the second input end of the clamping circuit determines the size of the output current of the current source circuit, the circuit is simple and easy to realize, the precision of the output current can be accurately controlled through the gating of the mirror branch, meanwhile, the problem that the number of transistors required to be stacked increases exponentially when the adjustment bit number of the required output current is high in the prior art scheme can be solved, and the balance between the current adjustment precision and the chip layout area can be achieved, and thus the performance of the slope generator, the analog-to-digital converter and the chip designed based on the current source circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital conversion, in particular to a current source circuit, a slope generator, an analog-to-digital converter and a chip. BACKGROUND

[0002] In a conventional functional chip such as an optical fingerprint chip or an image sensor chip, a single slope analog-to-digital converter (SS-ADC) is usually used to realize the conversion from an analog signal to a digital signal.

[0003] A typical ADC usually has a slope generator, and the product of the output current Iramp of the current source circuit in the slope generator and the corresponding clock period clk determines the accuracy of the ADC. In order to cope with the influence of the variation of elements such as resistors and capacitors with process corners on the accuracy of the ADC, it is usually required that Iramp is adjustable.

[0004] However, the existing current source circuit generally has problems such as being unable to accurately control the decrement multiple of Iramp and being unable to balance the current adjustment accuracy and the chip layout area. SUMMARY

[0005] The present application relates to the technical field of analog-to-digital conversion, in particular to a current source circuit, a slope generator, an analog-to-digital converter and a chip.

[0006] To achieve the above-mentioned purpose, the present application provides a current source circuit, which comprises:

[0007] a reference current generation circuit having a reference current source and a first transistor, the gate and the drain of the first transistor being coupled to the output end of the reference current source;

[0008] a current mirror circuit having a second transistor and n-way mirror branches, the second transistor being connected in common source and common gate with the first transistor and mirroring the current flowing through the first transistor, the input ends of the n-way mirror branches being coupled to the drain of the second transistor for shunting the current flowing through the second transistor;

[0009] a clamping circuit, a first input end of which is coupled to an m-way mirror branch of the n-way mirror branches and forms an output end of the current source circuit, and a second input end of which is coupled to an a-way mirror branch of the n-way mirror branches, the clamping circuit being used for clamping the outputs of the m-way mirror branch and the a-way mirror branch so that the voltages of the first input end and the second input end are equal;

[0010] wherein n, a, m are integers, 1≤m≤n, 0≤a≤n, and the output current provided by the current source circuit is related to the mirror branch connected to the first input terminal or the second input terminal.

[0011] Optionally, the reference current generating circuit further comprises a common-gate transistor, which is coupled between the drain of the first transistor and the output terminal of the reference current source, and the gate of the common-gate transistor is coupled to each of the mirror branches for providing a bias voltage to each of the mirror branches.

[0012] Optionally, a=n-m, and the a mirror branches are n-m mirror branches remaining after removing the m mirror branches from the n mirror branches.

[0013] Optionally, the n mirror branches split the current flowing through the second transistor into n equal parts, and when k mirror branches in the m mirror branches are turned on and q mirror branches in the a mirror branches are turned on, the calculation formula of the output current is: I ramp =b*I0*k / (k+q), wherein I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor, 1≤k≤m, and 0≤q≤n-m.

[0014] Optionally, k=1, 1+q=2 j , and j is an integer greater than or equal to 0.

[0015] Optionally, the n mirror branches have the same structure and comprise the same number of shunt transistors, the plurality of shunt transistors in any of the mirror branches are connected in series, and the gates of all the shunt transistors are coupled together, the source of the first shunt transistor in each of the mirror branches is the input terminal of the mirror branch and is coupled to the drain of the second transistor.

[0016] Optionally, the n mirror branches split the current flowing through the second transistor into n parts, and at least two of the n parts of current have different sizes.

[0017] Optionally, the n parts of current all have different sizes and form a first geometric progression with a common ratio x.

[0018] Optionally, each of the mirror branches comprises a corresponding number of shunt transistors; the shunt transistors in each of the mirror branches are connected in common and are connected in series; a source of a first shunt transistor in the shunt transistors is coupled to the drain of the second transistor and serves as an input terminal of the mirror branch; wherein the current shunted by each of the mirror branches depends on the number and width-length ratio of the shunt transistors thereof.

[0019] Optionally, each of the mirror branches comprises one shunt transistor, and the width-length ratios of the n shunt transistors are different and form a second geometric progression with a common ratio x.

[0020] Optionally, the output terminal of each of the n mirror branches is coupled to the first input terminal and the second input terminal, and is disconnected from the second input terminal when conducting between the first input terminal; at this time, m = a = n, and the calculation formula of the output current is:

[0021]

[0022] wherein I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor; S i corresponds to the i-th mirror branch, and S i = 1 indicates that the i-th mirror branch is connected to the first input terminal, and S i = 0 indicates that the i-th mirror branch is disconnected from the first input terminal.

[0023] Optionally, the width-length ratios of all the shunt transistors in the n mirror branches are the same, and the number of the shunt transistors in each of the mirror branches forms a third geometric progression with a common ratio y, wherein y is the reciprocal of x.

[0024] Optionally, the clamping circuit comprises a unit gain negative feedback amplifier, the non-inverting input terminal of the unit gain negative feedback amplifier is the first input terminal, the inverting input terminal of the unit gain negative feedback amplifier is the second input terminal, and the output terminal of the unit gain negative feedback amplifier is coupled to the inverting input terminal of the unit gain negative feedback amplifier.

[0025] Optionally, the current source circuit further comprises a gating circuit, the gating circuit is a multi-channel gate or comprises a plurality of gating switches; the multi-channel gate or each of the gating switches is coupled between the input terminal of the corresponding mirror branch and the drain of the second transistor, or is coupled between the output terminal of the corresponding mirror branch and the corresponding input terminal of the clamping circuit.

[0026] ​Based on the same inventive concept, the application further provides a slope generator, which comprises an operational amplifier, a charging capacitor and a current source circuit as described in the application, the output end of the current source circuit is coupled to one end of the charging capacitor and the first input end of the operational amplifier, the other end of the charging capacitor is coupled to the output end of the operational amplifier, and the output current of the current source circuit flows through the charging capacitor to generate a slope voltage.

[0027] Optionally, the slope generator further comprises a reference voltage circuit, the output end of the reference voltage circuit is coupled to the second input end of the operational amplifier, for providing a corresponding reference voltage to the operational amplifier.

[0028] Based on the same inventive concept, the application further provides an analog-to-digital converter, which comprises a comparator, a counter and a slope generator as described in the application; the output end of the slope generator is coupled to the first input end of the comparator, the second input end of the comparator is coupled to a corresponding analog input signal, and the output end of the comparator is coupled to the counter.

[0029] Based on the same inventive concept, the application further provides a chip, which comprises an analog-to-digital converter as described in the application.

[0030] Optionally, the chip is used for converting a received optical signal into an electrical signal, such as an optical fingerprint chip or an image sensor chip.

[0031] Compared with the prior art, the technical scheme of the application has at least the following beneficial effects:

[0032] 1. The second transistor in the current mirror circuit mirrors the current flowing through the first transistor, and the current flowing through the second transistor is further divided into n paths through the n mirror branches in the current mirror circuit, and the current output by the current mirror circuit is clamped by the clamping circuit, and the mirror branch connected to the first input end or the second input end of the clamping circuit determines the size of the output current of the current source circuit (i.e. determines the current adjustment precision of the output current of the current source circuit), and the circuit is simple and easy to implement.

[0033] 2. The precision of the output current can be accurately controlled through the gating of the mirror branches.

[0034] 3. The larger the n is, the higher the number of bits of the output current that can be adjusted is, when each mirror branch only has one shunt transistor, the number of shunt transistors stacked increases by 1 with each increase of 1 in n, thereby solving the problem that the number of transistors that need to be stacked increases exponentially when the number of bits of the output current that needs to be adjusted is high in the prior art, avoiding the problem of exponential expansion of the entire layout area of the chip, and achieving a balance between the current adjustment precision and the layout area of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0035] Those skilled in the art will understand that the drawings provided herein are included for illustrative purposes and represent the general nature of the invention without any limitation to the scope of the invention. In the drawings:

[0036] Figure 1 is a structural schematic diagram of a current source circuit of the prior art.

[0037] Figure 2 is a structural schematic diagram of another current source circuit of the prior art.

[0038] Figure 3 is a structural schematic diagram of a current source circuit of the first embodiment of the present application.

[0039] Figure 4 is a structural schematic diagram of a current source circuit of the first embodiment of the present application. Figure 3 is an equivalent structural schematic diagram of the current source circuit shown in

[0040] Figure 5 is an equivalent structural schematic diagram of the current source circuit shown in Figure 3

[0041] is a structural schematic diagram of a current source circuit of the second embodiment of the present application. Figure 6

[0042] is a structural schematic diagram of a current source circuit of the third embodiment of the present application. Figure 7

[0043] is a structural schematic diagram of a ramp generator of the fourth embodiment of the present application. Figure 8

[0044] is a structural schematic diagram of an analog-to-digital converter of the fourth embodiment of the present application. Figure 9 DETAILED DESCRIPTION

[0045] ​In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon reading this disclosure that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application. It should be understood that the present application can be practiced with departure from these specific details, and that specific details can be implemented only in some embodiments. There are many

[0046] Figure 1 For the existing current source circuit in the slope generator of ADC, the output current Iramp can be regulated by 8 bits (i.e. 8 bits). Wherein, the current source circuit includes switches s0-s8, switch pd, and 8 reference current sources with current multiples of I, I / 2, I / 4, I / 8, I / 16, I / 32, I / 64, I / 128 and 2 reference current sources with current multiple of I / 256, one end of the 10 reference current sources is connected together, the other end is connected to one end of switches s0-s8 and switch pd one by one, the other end of the 10 switches is connected together to provide output current Iramp. Thus, by turning on and off of switches s0-s8 and switch pd, the size of output current Iramp can be controlled.

[0047] In this way, when the number of accessed reference current sources increases, it is difficult to ensure the multiple relationship between the output current values of each bit, i.e. the scheme cannot achieve accurate control of the multiple of Iramp decrease.

[0048] Figure 2For another current source circuit in the existing slope generator for ADC, it adopts the way of superimposing n mos tubes M1~Mn on the current source tube M0 to realize the multiple decrease of output current Iramp, wherein the types of the mos tubes M0~Mn are selectable pmos or nmos, and the drain current of Mn is the output current Iramp provided by the current source circuit after M1~Mn are all turned on.

[0049] Taking pmos as an example, the specific principle of realizing the multiple decrease of output current Iramp by the current source circuit is as follows:

[0050] Firstly, the formula between the drain current of any mos tube and its width-length ratio (i.e. the voltage-to-current formula of the mos tube) is as follows:

[0051] .

[0052] Wherein, Kn is the constant of the mos tube, Vgs is the gate-source voltage of the mos tube, Vth is the threshold voltage of the mos tube, W / L is the width-length ratio of the mos tube, and I is the drain current of the mos tube after being turned on.

[0053] From the above current formula, it can be known that the drain current (i.e. output current) of the mos tube is proportional to the width-length ratio of the mos tube, and the size of the output current Iramp provided by the current source circuit can be directly changed by changing the gate-source voltage Vgs of Mn, wherein the gate-source voltage Vgs of Mn is equal to the difference between the gate voltage and the source voltage of Mn, the gate voltage of Mn is determined by I0, the source voltage of Mn is determined by the number n of the superimposed mos tubes on M0, and the source voltage of Mn is smaller when the number n of the superimposed mos tubes on M0 is larger, so the number n determines the gate-source voltage Vgs of the mos tube Mn, and then determines the size of the output current Iramp.

[0054] The voltage-to-current formula of the mos tube can be combined to derive the formula of the output current Iramp provided by the current source circuit as follows:

[0055] .

[0056] Wherein, I0 is the reference current, and n is the number of the superimposed mos tubes on M0 (i.e. the number of M1~Mn).

[0057] When n=1, the output current Iramp / I0=0.536, and so on. If Iramp / I0=0.25, then n=4, and if Iramp / I0=0.128, then n=10.

[0058] From the above formula of the output current Iramp, the more n is, that is, the more mos transistors superimposed on M0, which will lead to the expansion of the whole layout area of the chip, and because n can only be an integer, the ratio of Iramp / I0 cannot be an arbitrary fraction. That is, the current source circuit cannot accurately control the accuracy of its output current Iramp, and cannot achieve the balance between the current adjustment accuracy and the chip layout area.

[0059] Based on this, the application provides a current source circuit, a current source, a slope generator, an analog-to-digital converter and a chip, which adopts a new current shunt architecture, can accurately control the accuracy of the output current, and can reduce the number of superimposed mos transistors while achieving the required output current accuracy, and is suitable for application scenarios of multi-bit current regulation, such as successive approximation type analog-to-digital converters under multi-bit current regulation.

[0060] The technical solutions of the application will be further described in detail below in combination with the accompanying drawings. Figure 3 to the accompanying drawings Figure 9 The technical solutions of the application will be further described in detail below in combination with the accompanying drawings.

[0061] First embodiment

[0062] Please refer to Figure 3 The embodiment provides a current source circuit 101, which comprises a reference current generating circuit 101a, a current mirror circuit 101b, a gating circuit 101c and a clamping circuit 101d.

[0063] The reference current generating circuit 101a has a reference current source I0, a first transistor Mp0 and a common gate transistor MP1, and the reference current source I0 is used to provide a reference current I0. The current mirror circuit 101b has a second transistor M0 and n shunt transistors M1-Mn. The gating circuit 101c has n gating switches S <n>The clamp circuit 101d comprises a unit-gain negative feedback amplifier amp.

[0064] The first transistor Mp0, the common-gate transistor Mp1, the second transistor M0 and the n shunt transistors M1-Mn form a cascade current mirror structure, which on one hand makes the output impedance large, thereby increasing the intrinsic gain times, making the output current Iramp more stable, and on the other hand makes the current mirror replication current more accurate.

[0065] Exemplarily, the source of the first transistor Mp0 and the source of the second transistor M0 are coupled to a power supply voltage VDD, the gate of the first transistor Mp0 is coupled to the gate of the second transistor M0 and the output terminal of the reference current source I0, whereby the first transistor Mp0 and the second transistor M0 are connected in common-gate common-source. The other end of the reference current source I0 is grounded. The drain of the first transistor Mp0 is coupled to the source of the common-gate transistor Mp1.

[0066] The common-gate transistor Mp1 is not the same size as the first transistor Mp0, the first transistor Mp0 is responsible for controlling the size of the reference current I0 output by the reference current generation circuit 101a, and converts the reference current I0 into a bias voltage Vbp2 and provides it to the second transistor M0. Further considering the requirement of mismatch, the size of the first transistor Mp0 is relatively large.

[0067] The common-gate transistor Mp1 can perform the following functions: (1) responsible for providing small signal gain to increase the output impedance, and considering the requirement of transconductance, the width-length ratio of the common-gate transistor Mp1 is relatively high; (2) acts as a shunt resistor.

[0068] The sources of the n shunt transistors M1-Mn are all coupled to the drain of the second transistor M0, the gates of the n shunt transistors M1-Mn are all coupled to the gate of the common-gate transistor Mp1, whereby the n shunt transistors M1-Mn are connected in common-source common-gate, forming n mirror branches. The drains of the n shunt transistors M1-Mn are coupled to the n selection switches S <n>The drain of the shunt transistor M1 is connected to the input end of the gating switch S<1>, the drain of the shunt transistor M2 is connected to the input end of the gating switch S<2>, and so on, the drain of the shunt transistor Mm is connected to the input end of the gating switch S <m>the drain of the shunt transistor Mm+1 is connected to the input of the gate switch S <n-1>The input terminal is connected, and the drain of the shunt transistor Mn is connected to the gating switch S. <n>The input end of the current mirror circuit is connected to the output end of the first transistor Mp0.

[0069] In this embodiment, the current mirror circuit adopts a common-source and common-gate structure, which can effectively reduce the channel modulation effect, thereby reducing the variation of the output current with the variation of the power supply voltage VDD and improving the power supply rejection ratio. Meanwhile, the first transistor Mp0 and the common-gate transistor Mp1 provide a bias voltage for the current mirror circuit, thereby eliminating an additional bias circuit and simplifying the circuit structure.

[0070] The gating switch S<1> to the gating switch S <n>Each of the switches S<1> to S<4> is independently controlled. The switches S<1> to S<4> are controlled by the control unit 20. <m>The output terminals of the m gating switches are coupled to the non-inverting input terminals of the unity-gain negative feedback amplifiers amp, forming the output terminal A of the current source circuit, through the gating switches S <m>The control signal is used to control the on or off of the m-way mirror branch in which the shunt transistors M1~Mm are located and the circuit between the non-inverting input terminal of the unit gain negative feedback amplifier amp, so as to control the size of the output current Iramp provided by the output terminal A of the current source circuit. The gating switches S <n>The output terminals of the n-m gating switches are coupled to the inverting input terminal and the output terminal of the unity-gain negative feedback amplifier amp, forming a node B, through the gating switch S <n>The on or off of the shunt transistor Mm+1~Mn controls the on or off of the circuit between the n-m way mirror branch and the inverting input terminal of the unit gain negative feedback amplifier amp, thereby controlling the voltage of node B.

[0071] In this embodiment, the output of the unit gain negative feedback amplifier amp is always equal to the input, and the unit gain negative feedback amplifier amp clamps the voltage of the output terminal A and node B, so that the voltages of the output terminal A (i.e. the non-inverting input terminal of amp) and node B (i.e. the inverting input terminal of amp) are equal, i.e. the k way mirror branch in the m way mirror branch in which the shunt transistor M1~Mm is turned on is clamped, and the q way mirror branch in the n-m way mirror branch in which the shunt transistor Mm+1~Mn is turned on is clamped, so that the drain voltages of the shunt transistors in these turned on mirror branches are the same, thereby equivalent to shunting the current flowing through the second transistor M0 through these turned on mirror branches.

[0072] wherein the maximum adjustment bit number of the output current Iramp provided by the current source circuit 101 is n bit. And when the width-length ratios of the n shunt transistors M1~Mn are the same, the on-off of the gating switch S <m>The kth branch in the mth mirror branch is controlled to be conductive, and the gating switch S <n>The remaining n-m mirror branches are controlled to conduct q paths, and the reference current I0 flowing through Mp0 is mirrored by M0 according to a mirror ratio of b:1, so the current flowing through M0 is b*I0. After k and q paths are conducted, the current flowing through M0 is divided into k+q parts, so the output current Iramp is b*I0*k / (k+q). Wherein, I0 is the reference current output by the reference current source I0, b is the mirror ratio between the second transistor M0 and the first transistor Mp0, and 1≤k≤m, 0≤q≤n-m, k, q, n are all integers. And at this time, k, q can be adaptively adjusted according to S <n>varies in accordance with the change of the voltage V.

[0073] Thus, in the case where n is determined, the n-bit switch control signal S <n:1>An n-bit regulation of the output current Iramp can be implemented. And the switch control signal S <n:1>The sizes of k and q can be accurately controlled, and the value of k / (k+q) can be accurately controlled, so that the output current Iramp is not limited to being adjusted in a 2-fold decreasing manner, and adjustment of any required multiple k / (k+q) can be achieved. In addition, while achieving adjustment of the output current of multiple bits, the number of transistors does not increase exponentially, so that the area of the current source circuit for achieving adjustment of the output current of multiple bits can be reduced, and the chip layout area does not increase exponentially.

[0074] As an example, n≥2, only the mirror branch in which M1 is located among the m mirror branches coupled to the output end A is conductive between the output end A, and only the mirror branch in which M2 is located among the n-m mirror branches coupled to the node B is conductive between the node B, at this time k=1, q=1, and the equivalent circuit of the current source circuit of the embodiment is as shown in Figure 4 Under the action of the unit gain negative feedback amplifier amp, M0 is divided into two split transistors M1 and M2 of the same size, and the currents flowing through M1 and M2 are equal. Assuming that M0 mirrors the reference current I0 flowing through Mp0 according to a 1:1 mirror ratio, the currents flowing through M1 and M2 are each equal to I0 / 2, and the output current Iramp at this time is I0 / 2.

[0075] As another example, n≥2, all the m mirror branches coupled to the output end A are conductive between the output end A, and all the n-m mirror branches coupled to the node B are conductive between the node B, at this time k=m, q=n-m, and the equivalent circuit of the current source circuit of the embodiment is as shown in Figure 5 Under the action of the unit gain negative feedback amplifier amp, M0 is divided into n split transistors M1-Mn of the same size, and the currents flowing through M1-Mn are equal. Assuming that M0 mirrors the reference current I0 flowing through Mp0 according to a 1:1 mirror ratio, the currents flowing through M1-Mn are each equal to I0 / n, and the output current Iramp at this time is I0*m / n.

[0076] As another example, please refer to Figure 3 and Figure 8 to Figure 9 The current source circuit is applied to a slope generator of a single slope ADC (SS-ADC, single slope analog-to-digital converter), the width-length ratios of the n split transistors M1-Mn are the same, only one of the m mirror branches coupled to the output end A is conductive between the output end A (i.e., k=1), and q of the n-m mirror branches coupled to the node B are conductive between the node B, and 1+q=2 j , j is an integer and j≥0, for example, 2 j =1, 2, 4, …, in which case 2-fold decreasing of the output current Iramp can be achieved.

[0077] It should be understood that the gating circuit 101c in this embodiment is composed of n gating switches S <m>The n gating switches S<1>~S<n> are connected in series and coupled between the shunt transistor and the output terminal A, but the technical solution of the present application is not limited to this. In other embodiments of the present application, the n gating switches S<1>~S<n> are connected in parallel and coupled between the shunt transistor and the output terminal A. <m>The source of the shunt transistor and the drain of the M0 can be coupled to each other, and the same can control the on-off of the mirror branch to the unit gain negative feedback amplifier. In other embodiments of the application, n gating switches S <m>The multiplexer 101c can also be replaced by a multiplexer, i.e., the multiplexer 101c is also a multiplexer, which can be an integrated device or a special-purpose circuit, etc. In other embodiments of the present application, when a constant current source with an unadjustable output current is needed, the values of n, k or m, q or n-m can be designed according to the performance requirements of the constant current source, and the gating switches S <m-1>The drains of k shunt transistors out of m shunt transistors are directly connected to the output terminal A, and the drains of q shunt transistors out of nm shunt transistors are directly connected to node B, thereby outputting a fixed-proportion output current Iramp = I0 * k / (k + q), where k and q are fixed values.

[0078] In summary, the current source circuit of this embodiment mirrors the current from the reference current source through n mirror branches with shunt transistors, and further clamps and shunts the current generated by the current mirror through a clamping circuit. The mirror branch connected to the first or second input terminal of the clamping circuit determines the magnitude of the output current of the current source circuit (i.e., the current adjustment accuracy of the output current of the current source circuit). The circuit is simple and easy to implement. Moreover, the accuracy of the output current can be precisely controlled by selecting the mirror branches. The larger n is, the higher the number of bits that can be adjusted for the output current. For every 1 increase in n, the number of stacked shunt transistors increases by 1. This solves the problem of the exponential increase in the number of stacked transistors required by existing solutions when the required number of bits for output current adjustment is high, avoiding the problem of exponential expansion of the entire chip layout area, and achieving a balance between current adjustment accuracy and chip layout area.

[0079] It is worth noting that in this embodiment, each of the n mirror branches is composed of a shunt transistor, and the width-to-length ratio of the n shunt transistors M1 to Mn is the same. However, the technical solution of the present invention is not limited to this.

[0080] For example, in another embodiment of the present invention, each of the n mirror branches is composed of c shunt transistors connected in series. The aspect ratios of these c shunt transistors can be the same or different. However, the n mirror branches can still divide the current flowing through the second transistor into n equal parts. At this time, the m mirror branches are still coupled to the output terminal A, and the remaining nm mirror branches are coupled to the output terminal B. By controlling the on and off of each mirror branch, k of the m mirror branches are turned on, and q of the remaining nm mirror branches are turned on. This can also achieve the effect of controlling the output current of the current source circuit Iramp = I0 * k / (k + q).

[0081] For example, in another embodiment of the present invention, the current source circuit can still be used. Figure 3 The circuit structure shown can be used, but the aspect ratios of the n shunt transistors M1~Mn can be different or not identical. It can still be controlled by an n-bit switching signal S. <n:1>The n-bit regulation of the output current Iramp can be realized, but the size of the output current in this case is different from the output current Iramp in the embodiment, due to the different width-length ratios of the n shunt transistors M1-Mn, and the calculation formula of the output current is relatively more complex.

[0082] Second Embodiment

[0083] Please refer to Figure 6 The current source circuit 101 provided by the embodiment is obtained by further transforming the circuit shown in Figure 3 The current source circuit 101 provided by the embodiment is obtained by further transforming the circuit shown in

[0084] The current source circuit 101 also includes a reference current generating circuit 101a, a current mirror circuit 101b, a gating circuit 101c, and a clamping circuit 101d.

[0085] The difference between the current source circuit 101 provided by the embodiment and the current source circuit 101 of the first embodiment includes the following two points: (1) the gating circuit 101c includes gating switches S <n>and the strobe switch S_ <1> ~Selection switch S_ <n>, and 2n total gating switches. Among them, the drain of each shunt transistor Mi is coupled to a pair of gating switches S and a gate switch S , and a gating switch S the output terminal of the first comparator is coupled to the output terminal A, and the output terminal of the second comparator is coupled to the output terminal B. The output ends of the first and second amplifiers are coupled to the node B, and the gating switch S and S one of the n shunt transistors is turned on while the other is turned off, i=1~n. (2) The width-length ratios of the n shunt transistors are different and the width-length ratios of the n shunt transistors are an equal ratio series, and the common ratio of the equal ratio series is x.

[0086] Exemplarily, the gating switch S<1> and the gating switch S_<1> are arranged in pairs, the input ends of the gating switch S<1> and the gating switch S_<1> are coupled to the drain of the shunt transistor M1, the output end of the gating switch S<1> is coupled to the output end A, and the output end of the gating switch S_<1> is coupled to the node B. When the gating switch S<1> is turned on, the gating switch S_<1> is turned off (i.e. cut off, disconnected). The gating switch S<2> and the gating switch S_<2> are arranged in pairs, the input ends of the gating switch S<2> and the gating switch S_<2> are coupled to the drain of the shunt transistor M2, the output end of the gating switch S<2> is coupled to the output end A, and the output end of the gating switch S_<2> is coupled to the node B. When the gating switch S<2> is turned on, the gating switch S_<2> is turned off. By analogy, the gating switch S <n>and a gate switch S <n>Pairs of sets, strobe switch S <n>and a gate switch S <n>The input terminals are all coupled to the drain of the shunt transistor Mn, and the selector switch S <n>the output terminal of the first comparator is coupled to the output terminal A, and the output terminal of the second comparator is coupled to the output terminal B. <n>The output end of the first amplifier is coupled to a node B, a gating switch S <n>When turned on, the gate switch S <n>Turn off (i.e. cut off, disconnect).

[0087] That is, the drain of each of the n shunt transistors M1~Mn is coupled to the output terminal A and the node B through the two selection switches arranged in pairs, and the drain of any shunt transistor is disconnected from the node B when it is turned on between the output terminal A. At this time, the number of mirror branches coupled to the output terminal A and the number of mirror branches coupled to the node B are both n, i.e. m=a=n.

[0088] In this embodiment, the width-length ratio of M2 is x times that of M1, the width-length ratio of M3 is x times that of M2, and so on, and the width-length ratio of Mn is x times that of Mn-1.

[0089] According to the formula between the drain current of the mos transistor and the width-length ratio of the mos transistor, the drain current (i.e. output current) of the mos transistor is proportional to its width-length ratio. If the width-length ratio of M1 is normalized to 1, the current flowing through M1 is I1, and the width-length ratio of Mn is x n-1 , the current flowing through Mn is x n-1 *I1, and the total current flowing through M1~Mn is equal to the current flowing through M0. Further, M0 mirrors the reference current I0 flowing through Mp0 according to the mirror ratio of b:1, the current flowing through M0 is b*I0, and for the i-th shunt transistor in M1~Mn, when the selection switch S Conducting and gating switch S When the switch is off, the i-th shunt transistor is turned on between the output terminal A (i.e. the first input terminal of the unity-gain negative feedback amplifier amp) and the current of the mirror branch in which the i-th shunt transistor is located flows to the output terminal A; the gating switch S Shut-off and gating switch S When conducting, the i-th shunt transistor is disconnected with the output end A, and the current of the mirror branch where the i-th shunt transistor is located flows to the node B. Therefore, the total output current Iramp at the output end A of the current source circuit 101 is the sum of the currents of the mirror branches conducting with the output end A, and the formula of the total output current Iramp at the output end A of the current source circuit 101 is:

[0090] .

[0091] wherein, I ramp is the output current, I0 is the reference current output by the reference current source I0, b is the mirror ratio between the second transistor M0 and the first transistor Mp0, and x is the common ratio of the geometric progression. i Corresponding to the i-th shunt transistor, and S i =1 indicates that the gating switch S Conducting and gating switch S When the switch S is turned off, the i-th shunt transistor is turned on between the output terminal A (i.e. the first input terminal of the unity-gain negative feedback amplifier amp), and the current of the mirror branch in which the i-th shunt transistor is located flows to the output terminal A; S i = 0, indicating that the gating switch S Shut-off and gating switch S When the switch control signal S is turned on, the i-th shunt transistor is disconnected from the output terminal A, and the current of the mirror branch in which the i-th shunt transistor is located flows to the node B, and the total output current Iramp is the sum of the output currents of all the mirror branches with n = 1. i

[0092] Thus, in the case where n is determined, the switch control signal S <n:1>An n-bit regulation of the output current Iramp can be implemented. And the switch control signal S <n:1>The difference allows for precise control of the corresponding S-band of the mirror branch. i The value of Iramp can be either 0 or 1, thus allowing the output current Iramp to be adjusted not only in a 2-fold decrease manner, but also to achieve any desired multiple adjustment. Furthermore, while achieving multi-bit output current adjustment, it does not cause an exponential increase in the number of transistors, thereby reducing the area of ​​the current source circuit for multi-bit output current adjustment and avoiding an exponential increase in chip layout area.

[0093] It should be understood that in this embodiment, when the number of mirror branches connected to output terminal A is k, the number of mirror branches connected to node B is nk.

[0094] Furthermore, the current mirror circuit in this embodiment still adopts a common-source, common-gate structure, which can effectively reduce the channel modulation effect, thereby reducing the change in output current with the power supply voltage VDD and improving the power supply rejection ratio. At the same time, the first transistor Mp0 and the common-gate transistor Mp1 provide bias voltage to the current mirror circuit, eliminating the need for an additional bias circuit and simplifying the circuit structure.

[0095] As an example, when x=2, the width-to-length ratio of M2 is twice that of M1, the width-to-length ratio of M3 is twice that of M2, and so on, the width-to-length ratio of Mn is twice that of Mn-1, and M0 mirrors the reference current I0 of Mp0 in a 1:1 mirror ratio (i.e., b=1). At this time, the total output current at output terminal A is:

[0096] .

[0097] In summary, the current source circuit of this embodiment also mirrors the current of the reference current source through n mirror branches with shunt transistors in the current mirror, and further clamps and shunts the current generated by the current mirror through a clamping circuit. The mirror branch connected to the first input terminal of the clamping circuit determines the magnitude of the output current of the current source circuit (i.e., the current adjustment accuracy of the output current of the current source circuit). The circuit is simple and easy to implement. Moreover, the accuracy of the output current can be precisely controlled by selecting the mirror branch. The larger n is, the higher the number of bits that can be adjusted for the output current. For every 1 increase in n, the number of stacked shunt transistors increases by 1. This solves the problem of the exponential increase in the number of stacked transistors required by existing solutions when the required number of bits for adjusting the output current is high, avoiding the problem of exponential expansion of the entire chip layout area, and achieving a balance between current adjustment accuracy and chip layout area.

[0098] Third Embodiment

[0099] Please refer to Figure 7 The third embodiment provides a current source circuit 101, which is different from the first and second embodiments in that the number of shunt transistors in each of the n mirror branches can be different from each other, and the required output current accuracy can also be achieved by controlling the on-off of the n mirror branches.

[0100] As an example, refer to Figure 7 The current source circuit is composed of shunt transistors in each mirror branch, and the width-length ratios of all shunt transistors are the same, but the number of shunt transistors forms a geometric progression with a common ratio of 2, so that the shunt of the n mirror branches to the current flowing through the second transistor forms a geometric progression with a common ratio of 1 / 2. Among them, the first mirror branch is composed of one shunt transistor M1, the second mirror branch is composed of two shunt transistors M2_1 and M2_2 connected in series, and so on. The mth mirror branch is composed of two shunt transistors Mm_1 and Mm_2~Mm_2 connected in series, and the (m+1)th mirror branch is composed of two shunt transistors Mm+1_1 and Mm+1_2~Mm+1_2 connected in series, and the nth mirror branch is composed of two shunt transistors Mn_1 and Mn_2~Mn_2 connected in series. m-1 m-1 m m n n-1 When the connection mode of the output end of the n mirror branches in this example to the clamping circuit adopts the connection mode in the second embodiment, that is, in the n mirror branches, the output end of each mirror branch is coupled to the first input end (i.e. output end A) and the second input end (i.e. node B) of the clamping circuit, and is turned on between the first input end and the second input end, and is turned off between the first input end and the second input end. When the first input end is turned off between the first input end and the second input end, the output end of each mirror branch is turned on between the first input end and the second input end, and m=a=n at this time. The calculation formula of the output current of the current source circuit is still:

[0101] .

[0102] Where I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor; S i corresponds to the ith mirror branch, and S i =1 indicates that the ith mirror branch is turned on between the first input end and the second input end, and S i =0 indicates that the ith mirror branch is turned off between the first input end and the second input end, and x=1 / 2. That is, the output current is:

[0103] . ​​​​​

[0104] When the connection mode of the output ends of the n-way mirror branches in this example to the clamping circuit adopts the connection mode in the first embodiment, that is, among the n-way mirror branches, the output ends of m-way mirror branches are all coupled to the first input end (that is, the output end A) of the clamping circuit, and the output ends of the remaining n-m-way mirror branches are all coupled to the second input end (that is, the node B) of the clamping circuit, further controlling k-way mirror branches among the m-way mirror branches coupled to the output end A to be turned on, and controlling q-way mirror branches among the n-m-way mirror branches coupled to the node B to be turned on, then the output current of the current source circuit is equal to the sum of the partial currents of the k-way mirror branches turned on, and the sum of the partial currents of the k-way mirror branches turned on and the q-way mirror branches turned on is equal to the current flowing through the second transistor. It should be understood that in other embodiments of the present application, as long as the number and width-length ratio of the partial current transistors of each mirror branch in the n-way mirror branches can cooperate with each other to achieve the required partial current of the mirror branch, the current flowing through the second transistor can be divided into n parts by the n-way mirror branches, and the n parts of current can be equal or unequal. And the coupling mode of the output ends of the n-way mirror branches to the two input ends of the clamping circuit can adopt the mode of the first embodiment or the mode of the second embodiment as needed, which can achieve the accuracy of accurately controlling the output current to a certain extent and balance the current adjustment accuracy and the chip layout area.

[0105] Fourth embodiment

[0106] Please refer to Figure 8 The present embodiment also provides a slope generator 10, which comprises an operational amplifier vramp_op, a charging capacitor C1 and a current source circuit 101 as described in the present application. Wherein, the output end of the current source circuit 101 is coupled to one end of the charging capacitor C1 and the first input end (for example, the inverting input end) of the operational amplifier vramp_op, the other end of the charging capacitor C1 is coupled to the output end of the operational amplifier vramp_op, and the output current Iramp of the current source circuit 101 flows through the charging capacitor C1 to generate a slope voltage vramp that changes linearly with time. i

[0107] Optionally, the slope generator further comprises a reference voltage circuit, the output end of the reference voltage circuit is coupled to the second input end (for example, the non-inverting input end) of the operational amplifier vramp_op, for providing a corresponding reference voltage to the operational amplifier vramp_op.

[0108] Wherein, the reference voltage circuit can be implemented by any suitable circuit design, which can provide a reference voltage or multiple selectable different reference voltages, and the present application does not make specific limitations thereto.

[0109] ​As an example, the reference voltage circuit includes a voltage divider circuit 102 and selection switches vr1_sw, vr1_sw, vr2_sw, vr3_sw, the voltage divider circuit 102 is capable of generating three different sizes of reference voltages vr1, vr2, vr3 based on a bias current Ib1 and a reference voltage vcm_res, the selection switch vr1_sw is capable of providing the reference voltage vr1 to the second input terminal of the operational amplifier vramp_op when turned on, the selection switch vr2_sw is capable of providing the reference voltage vr2 to the second input terminal of the operational amplifier vramp_op when turned on, and the selection switch vr3_sw is capable of providing the reference voltage vr3 to the second input terminal of the operational amplifier vramp_op when turned on.

[0110] In this example, the ramp transmitter further includes a charge-discharge switch vr_sw, a charging capacitor C2, and a reset switch ramp_rst. The voltage provided by one of the selection switches vr1_sw, vr1_sw, vr2_sw, vr3_sw when turned on will charge the charging capacitor C2 after the charge-discharge switch vr_sw is turned on, and the charging capacitor C2 will stabilize the voltage at the second input terminal of the operational amplifier vramp_op after the charge-discharge switch vr_sw is turned off. One end of the reset switch ramp_rst is coupled to the first input terminal of the operational amplifier vramp_op, and the other end is coupled to the output terminal of the operational amplifier vramp_op. The reset switch ramp_rst discharges the charging capacitor C1 after being turned on, thereby achieving the reset of the ramp voltage vramp.

[0111] Based on the same inventive concept, please refer to Figure 9 The embodiment also provides an analog-to-digital converter (ADC) including a comparator 11, a counter 12, and a ramp generator 10 as described in the present application; the output terminal of the ramp generator 10 is coupled to the first input terminal (such as the non-inverting input terminal "+") of the comparator 11, the second input terminal (such as the inverting input terminal "-") of the comparator 11 is coupled to a corresponding analog input signal Vin, and the output terminal of the comparator 11 is coupled to the counter 12.

[0112] The product of the ramp voltage vramp output by the ramp generator 10 and the clock period clk of the counter 12 can determine the accuracy of the ADC. As an example, the least significant bit (LSB) of the ADC is: LSB = Iramp*clk / C1.

[0113] In the slope generator 10, the output current Iramp provided by the current source circuit is adjustable, and the precision of the output current Iramp determines the precision of the ADC, and the influence of the resistance and the capacitance changing with the process corner on the precision of the ADC can be coped with.

[0114] Based on the same inventive concept, the embodiment further provides a chip comprising the ADC as described in the embodiment. The ADC is used to convert an analog input signal Vin into a corresponding digital signal.

[0115] The chip can be a chip used to convert a received optical signal into an electrical signal. For example, the chip can be an optical fingerprint chip or an image sensor chip, or any functional chip that needs to convert an analog input signal into a digital signal.

[0116] The slope generator, the ADC and the chip of the embodiment can provide multi-precision current regulation and reduce the chip area under multi-precision regulation, and can be applied to the demand of higher-precision products, due to the use of the current source circuit of the application.

[0117] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application in any way. Any modification or change made by a person skilled in the art based on the above disclosure is within the protection scope of the technical solution of the application. ​ < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / m> < / n> < / n> < / m> < / n> < / n>

Claims

1. A current source circuit, characterized by, The application relates to a reference current generating circuit. The reference current generating circuit comprises a reference current source and a first transistor, the gate and the drain of the first transistor are coupled to the output of the reference current source; The current mirror circuit comprises a second transistor and n mirror branches, the second transistor is connected in common source and common gate with the first transistor and mirrors the current flowing through the first transistor, the drains of the second transistor are coupled to the input of the n mirror branches, and the n mirror branches are used for shunting the current flowing through the second transistor; The clamping circuit has a first input coupled to the mth mirror branch of the n mirror branches and forms the output of the current source circuit, and has a second input coupled to the ath mirror branch of the n mirror branches, and the clamping circuit is used for clamping the outputs of the mth mirror branch and the ath mirror branch, so that the voltages of the first input and the second input are equal; Wherein, n, a, and m are integers, 1<=m<=n, 0<=a<=n, and the output current provided by the current source circuit is related to the mirror branch connected to the first input or the second input.

2. The current source circuit of claim 1, wherein, The reference current generating circuit further comprises a common-gate transistor, the common-gate transistor is coupled between the drain of the first transistor and the output of the reference current source, and the gate of the common-gate transistor is coupled to each of the mirror branches, and the common-gate transistor is used for providing a bias voltage for each of the mirror branches.

3. The current source circuit of claim 1, wherein, a=n-m, and the ath mirror branch is the n-m mirror branches remaining after removing the mth mirror branch from the n mirror branches.

4. The current source circuit of claim 3, wherein, The n-way mirror branch divides the current flowing through the second transistor into n equal parts, and when k paths in the m-way mirror branch are turned on and q paths in the a-way mirror branch are turned on, the calculation formula of the output current is: I ramp =b*I0*k / (k+q), wherein I ramp is the output current, I0 is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor, 1≤k≤m, and 0≤q≤n-m.

5. The current source circuit of claim 4, wherein, k = 1, 1 + q = 2 j and j is an integer ≥ 0.

6. The current source circuit of claim 4, wherein, The n mirror branches have the same structure and comprise the same number of shunt transistors, the shunt transistors in any of the mirror branches are connected in series, and the gates of all the shunt transistors are coupled together, the source of the first shunt transistor in each of the mirror branches is used as the input of the mirror branch and is coupled to the drain of the second transistor.

7. The current source circuit of claim 1 or 3, wherein, The n mirror branches shunt the current flowing through the second transistor into n parts, and at least two of the n parts of current have different sizes.

8. The current source circuit of claim 7, wherein, The n parts of current have different sizes and form a first equal ratio series with a common ratio x.

9. The current source circuit of claim 8, wherein, Each of the mirror branches comprises a corresponding number of shunt transistors, the shunt transistors in each of the mirror branches are connected in common gate and connected in series, the source of the first shunt transistor in each of the mirror branches is used as the input of the mirror branch and is coupled to the drain of the second transistor, and the size of the current shunted by each of the mirror branches depends on the number and width-length ratio of the shunt transistors.

10. The current source circuit of claim 9, wherein, Each of the mirror branches comprises one shunt transistor, the width-length ratios of the n shunt transistors are different and form a second equal ratio series with a common ratio x.

11. The current source circuit of claim 10, wherein, In the n mirror branches, the output of each of the mirror branches is coupled to the first input and the second input, and is disconnected from the second input when conducting between the first input, at this time, m=a=n, and the calculation formula of the output current is: ， wherein I ramp is the output current, I0is the reference current output by the reference current source, b is the mirror ratio between the second transistor and the first transistor; S i corresponds to the ith mirror branch, and S i = 1 indicates that the ith mirror branch is connected to the first input, and S i = 0 indicates that the ith mirror branch is disconnected from the first input.

12. The current source circuit of claim 9, wherein, The width-length ratios of all the current divider transistors in the n mirror branches are the same, and the number of the current divider transistors in each of the n mirror branches forms a third equal ratio series with a common ratio y, wherein y is the reciprocal of x.

13. The current source circuit of claim 1, wherein, The clamping circuit comprises a unit-gain negative feedback amplifier, the non-inverting input terminal of the unit-gain negative feedback amplifier is the first input terminal, the inverting input terminal of the unit-gain negative feedback amplifier is the second input terminal, and the output terminal of the unit-gain negative feedback amplifier is coupled to the inverting input terminal of the unit-gain negative feedback amplifier.

14. The current source circuit of claim 1, wherein, The current source circuit further comprises a gating circuit, which is a multiplexer or comprises a plurality of gating switches; the multiplexer or each of the gating switches is coupled between the input terminal of the corresponding mirror branch and the drain of the second transistor, or coupled between the output terminal of the corresponding mirror branch and the corresponding input terminal of the clamping circuit.

15. A ramp generator characterized by The current source circuit of any one of claims 1-14, an operational amplifier, a charging capacitor, and the current source circuit, the output terminal of the current source circuit being coupled to one end of the charging capacitor and a first input terminal of the operational amplifier, the other end of the charging capacitor being coupled to an output terminal of the operational amplifier, and the output current of the current source circuit flowing through the charging capacitor to generate a ramp voltage.

16. The ramp generator of claim 15, wherein, The current source circuit of any one of claims 1-14, further comprising a reference voltage circuit, the output terminal of the reference voltage circuit being coupled to a second input terminal of the operational amplifier, for providing a corresponding reference voltage to the operational amplifier.

17. An analog-to-digital converter, characterized by The current source circuit of any one of claims 1-14, further comprising a comparator, a counter, and the ramp generator, the output terminal of the ramp generator being coupled to a first input terminal of the comparator, a second input terminal of the comparator being coupled to a corresponding analog input signal, and an output terminal of the comparator being coupled to the counter.

18. A chip, characterized by The current source circuit of any one of claims 1-14, further comprising an analog-to-digital converter. The current source circuit of any one of claims 1-14, further comprising an analog-to-digital converter.

Images