Manufacturing method of semiconductor structure

Abstract

The invention relates to a manufacturing method of a semiconductor structure, and the method comprises the steps: providing a substrate, and forming a first electrode on the substrate; forming a grid electrode on the first electrode, wherein the top surface of the grid electrode is covered by the isolation layer; forming a channel hole penetrating through the isolation layer and the grid electrode, wherein the channel hole exposes a part of the top surface of the first electrode; forming a gate dielectric layer, wherein the gate dielectric layer covers the side wall of the channel hole; forming a channel layer, wherein the channel layer covers the gate dielectric layer and the top surface of the first electrode exposed by the channel hole; filling a heat conduction material in the channel hole to form a heat conduction layer; performing thermal annealing treatment on the channel layer and the heat-conducting layer together, and then removing the heat-conducting layer; forming an insulating layer in the channel hole, wherein the insulating layer covers part of the inner side wall of the channel layer; and forming a second electrode on the insulating layer, wherein the second electrode is in contact connection with the top of the channel layer. The resistance of the channel layer is reduced, the conductivity of the channel layer is improved, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] With the continuous innovation of semiconductor technology, the characteristic size of semiconductor components is continuously reduced in order to improve the integration density of integrated circuits.

[0003] The reduction in the characteristic size of semiconductor components has greatly increased the difficulty of their production. There are still some technical problems that need to be further improved in the production of semiconductor components with smaller size nodes. Summary of the invention

[0004] Based on this, it is necessary to provide a method for manufacturing a semiconductor structure to address the problems in the prior art.

[0005] In a first aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0006] providing a substrate, and forming a first electrode on the substrate;

[0007] forming a gate on the first electrode, wherein a top surface of the gate is covered by an isolation layer;

[0008] forming a channel hole penetrating the isolation layer and the gate, wherein the channel hole exposes a portion of the top surface of the first electrode;

[0009] forming a gate dielectric layer, wherein the gate dielectric layer covers the sidewalls of the channel hole;

[0010] forming a channel layer, wherein the channel layer covers the gate dielectric layer and a top surface of the first electrode exposed by the channel hole;

[0011] Filling the channel hole with a heat-conducting material to form a heat-conducting layer;

[0012] After thermal annealing is performed on the channel layer and the heat-conducting layer, the heat-conducting layer is removed;

[0013] forming an insulating layer in the channel hole, wherein the insulating layer covers a portion of an inner sidewall of the channel layer;

[0014] A second electrode is formed on the insulating layer, wherein the second electrode is contact-connected with a top portion of the channel layer.

[0015] In one embodiment, after the channel layer and the heat conducting layer are subjected to a thermal annealing treatment together, the channel layer is formed into a polycrystalline semiconductor layer that conformally covers the sidewalls and the bottom surface of the channel hole.

[0016] In one embodiment, the heat conducting layer includes a barrier layer and a metal layer formed in sequence, and the barrier layer is disposed between the metal layer and the channel layer.

[0017] In one embodiment, forming an insulating layer in the channel hole comprises:

[0018] Depositing an insulating material to fill the channel hole, wherein the insulating material covers the channel layer and at least fills a portion of the channel hole;

[0019] The insulating material is etched back into the channel hole.

[0020] In one embodiment, a top surface of the insulating layer is higher than a top surface of the gate and lower than a top surface of the channel hole, and the insulating layer exposes a portion of an inner sidewall of the channel layer.

[0021] In one embodiment, forming the second electrode comprises:

[0022] forming a contact layer, wherein the contact layer covers the exposed inner sidewall of the channel layer and fills the unfilled area of ​​the channel hole;

[0023] A metal conductive layer is formed, wherein the metal conductive layer covers a top surface of the contact layer, a top surface of the channel layer, and a top surface of the isolation layer.

[0024] In one embodiment, the forming of the metal conductive layer includes: sequentially forming a metal barrier layer and a metal conductive layer, wherein the metal barrier layer is disposed between the metal conductive layer and the contact layer.

[0025] In one embodiment, the contact layer also covers the top surface of the isolation layer, and the contact layer is disposed between the metal conductive layer and the isolation layer.

[0026] In one embodiment, forming the second electrode comprises:

[0027] forming a metal barrier layer, wherein the metal barrier layer covers the inner sidewall of the top of the channel layer, the top surface of the channel layer, and the top surface of the isolation layer;

[0028] A metal conductive layer is formed, wherein the metal conductive layer covers the metal barrier layer and fills an unfilled area of ​​the channel hole.

[0029] In one embodiment, before forming the second electrode on the insulating layer, the method further includes:

[0030] The channel layer on the top surface of the isolation layer is removed by etching to expose the top surface of the isolation layer, and the channel layer in each of the channel holes is disconnected.

[0031] The manufacturing method of the semiconductor structure disclosed in the present invention forms a heat-conducting layer to cover the channel layer after the channel layer is deposited, and the heat-conducting layer and the channel layer are thermally annealed together. The good heat-conducting effect of the heat-conducting layer is utilized, and during the thermal annealing process, the heat-conducting layer conducts heat to heat the channel layer, so that the channel layer is heated uniformly. The channel layer forms a polycrystalline semiconductor layer that conformally covers the channel hole, reduces the resistance of the channel layer, improves the conductivity of the channel layer, and is beneficial to improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a process flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0034] Figure 2 is a schematic diagram of a structure after a first electrode, a gate and an isolation layer are formed on a substrate provided in an embodiment;

[0035] Figure 3 A schematic diagram of a structure after an initial channel hole is formed provided in an embodiment;

[0036] Figure 4 is a schematic diagram of a structure after a channel hole and a gate dielectric layer are formed in one embodiment;

[0037] Figure 5 is a schematic diagram of a structure after a channel layer is formed in one embodiment;

[0038] Figure 6 A schematic diagram of a structure after a heat-conducting layer and a channel layer are heat-treated together in one embodiment;

[0039] Figure 7 It is a schematic diagram of the structure after the heat-conducting layer and the channel layer are heat-treated together in another embodiment;

[0040] Figure 8 It is a schematic diagram of a structure after the heat-conducting layer is removed and an insulating layer is formed in the channel hole in one embodiment;

[0041] Fig. 9 is a schematic diagram of a structure after a contact layer is formed in one embodiment;

[0042] Fig.10 A schematic diagram of a semiconductor structure formed in accordance with an embodiment;

[0043] Fig.11 A semiconductor structure formed in one embodiment Fig.10 Cross-section along line AA;

[0044] Fig.12 A schematic structural diagram of a semiconductor structure formed in another embodiment;

[0045] Fig.13 A semiconductor structure formed for another embodiment is along Fig.12 Cross-section along line BB.

[0046] Description of reference numerals:

[0047] 11. substrate; 21. first electrode; 211. first conductive layer; 212. first contact layer; 2111. first barrier metal layer; 2112. first conductive metal layer; 2113. second barrier metal layer; 23. gate; 24. isolation layer; 25. gate dielectric layer; 26. channel layer; 27. insulating layer; 28. isolation sidewall; 29. ​​second electrode; 291. contact layer; 292. metal conductive layer; 2921. metal barrier layer; 2922. metal conductive layer; 293. nitride layer; 30. thermal conductive layer; 31. barrier layer; 32. metal layer; 40. channel hole; 40a. initial channel hole; 41. first dielectric layer; 42. second dielectric layer;

[0048] D1, first direction; D2, second direction. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0051] As described in the background art, the characteristic size of semiconductor devices is reduced, which greatly increases the difficulty of manufacturing them. There are still some technical problems that need to be further improved in manufacturing semiconductor devices with smaller size nodes.

[0052] For example, in the manufacturing process of semiconductor components, it is necessary to form a uniform polycrystalline semiconductor layer, but the crystal orientation uniformity and distribution uniformity of the polycrystalline semiconductor layer are difficult to ensure. In particular, when a polycrystalline semiconductor layer is formed on the surface of a previous layer device, it is affected by the morphology of the previous layer device and it is difficult to ensure the continuity of the polycrystalline semiconductor layer.

[0053] According to an exemplary embodiment, this exemplary embodiment provides a method for manufacturing a semiconductor structure. Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figure 1 As shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0054] Step S10: providing a substrate 11, and forming a first electrode 21 on the substrate 11;

[0055] Step S20: forming a gate 23 on the first electrode 21, wherein the top surface of the gate 23 is covered by an isolation layer 24;

[0056] Step S30: forming a channel hole 40 penetrating the isolation layer 24 and the gate 23 , wherein the channel hole 40 exposes a portion of the top surface of the first electrode 21 ;

[0057] Step S40: forming a gate dielectric layer 25, wherein the gate dielectric layer 25 covers the sidewalls of the channel hole 40;

[0058] Step S50: forming a channel layer 26, wherein the channel layer 26 covers the gate dielectric layer 25 and the top surface of the first electrode 21 exposed by the channel hole 40;

[0059] Step S60: filling the channel hole 40 with a heat-conducting material to form a heat-conducting layer 30;

[0060] Step S70: After thermal annealing is performed on the channel layer 26 and the heat-conducting layer 30, the heat-conducting layer 30 is removed;

[0061] Step S80: forming an insulating layer 27 in the channel hole 40 , wherein the insulating layer 27 covers a portion of the inner sidewall of the channel layer 26 ;

[0062] Step S90 : forming a second electrode 29 on the insulating layer 27 , wherein the second electrode 29 is in contact with the top of the channel layer 26 .

[0063] In the method for manufacturing the semiconductor structure of the present embodiment, after the channel layer 26 is deposited, a heat-conducting layer 30 is formed to cover the channel layer 26. The heat-conducting layer 30 and the channel layer 26 are thermally annealed together. By utilizing the good thermal conductivity of the heat-conducting layer 30, the heat-conducting layer 30 conducts heat to heat the channel layer 26 during the thermal annealing process, so that the channel layer 26 is heated uniformly. The channel layer 26 forms a polycrystalline semiconductor layer that conformally covers the channel hole 40, thereby reducing the resistance of the channel layer 26 and improving the conductivity of the channel layer 26, which is beneficial to improving the electrical performance of the semiconductor structure.

[0064] Figure 2-Figure 13 The cross-sectional diagram of the corresponding steps of the method for manufacturing the semiconductor structure provided in this embodiment. Figure 2-Figure 13 The method for manufacturing the semiconductor structure provided in this embodiment is described in detail.

[0065] In step S10, referring to Figure 2 The substrate 11 may be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited thereto.

[0066] A first electrode 21 is formed on the substrate 11, and the first electrode 21 may be a source electrode or a drain electrode. A first conductive layer 211 may be formed on the substrate 11 by a physical vapor deposition process (PVD), and a first contact layer 212 may be deposited on the first conductive layer 211 by a chemical vapor deposition process (CVD) or an atomic layer deposition process (ALD). Then, the first contact layer 212 and the first conductive layer 211 are patterned to form the first electrode 21. The first electrode 21 extends along a first direction D1 and is spaced apart along a second direction D2, and the first direction D1 is different from the second direction D2.

[0067] In one example, referring to Figure 2 The first conductive layer 211 includes a first barrier metal layer 2111, a first conductive metal layer 2112 and a second barrier metal layer 2113 stacked in sequence.

[0068] For example, the materials of the first barrier metal layer 2111 and the second barrier metal layer 2113 may include titanium nitride, the material of the first conductive metal layer 2112 may include metal tungsten, and the material of the first contact layer 212 may include doped polysilicon.

[0069] In this embodiment, after the first electrode 21 is formed, the first dielectric layer 41 can be deposited by CVD, and the first dielectric layer 41 covers the first electrode 21 and fills the area between the first electrodes 21. After the first dielectric layer 41 is formed, the top surface of the first dielectric layer 41 is ground into a plane to facilitate the execution of subsequent processes.

[0070] For example, the material of the first dielectric layer 41 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0071] In step S20, referring to Figure 2 PVD deposition can be used to form a gate conductive layer, which covers the first dielectric layer 41. The gate conductive layer is etched to form a gate 23, which extends along the second direction D2 and is spaced apart along the first direction D1.

[0072] For example, the gate 23 may include a gate barrier layer and a gate metal layer stacked in sequence from bottom to top, or the gate 23 may also include a gate semiconductor layer and / or a gate metal silicide layer, the gate semiconductor layer may be located on the gate metal layer, and the gate metal silicide layer may be located on the gate semiconductor layer or the gate metal layer.

[0073] Then, a second dielectric layer 42 may be formed by CVD deposition. The second dielectric layer 42 covers the sidewalls of the gate 23 and fills and covers the gate 23 .

[0074] For example, the material of the second dielectric layer 42 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0075] Next, an isolation layer 24 may be formed by CVD deposition. The isolation layer 24 covers the top surface of the gate 23 and the top surface of the second dielectric layer 42 .

[0076] For example, the material of the isolation layer 24 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0077] In step S30 and step S40, first, refer to Figure 3 , patterning the isolation layer 24 and the gate 23 to form an initial channel hole 40a penetrating the isolation layer 24 and the gate 23, the bottom wall of the initial channel hole 40a exposes a portion of the top surface of the first dielectric layer 41 below, and the sidewall of the initial channel hole 40a exposes a portion of the gate 23.

[0078] Then, refer to Figure 4 A gate dielectric layer 25 may be formed on the surface of the gate 23 exposed by the initial channel hole 40a by ALD deposition or thermal oxidation process. The material of the gate dielectric layer 25 includes oxide, such as silicon oxide or aluminum oxide.

[0079] Next, continue to refer to Figure 4 , the gate dielectric layer 25 on the bottom wall of the initial channel hole 40 a and the first dielectric layer 41 thereunder are removed by etching until a portion of the top surface of the first electrode 21 is exposed, thereby forming the channel hole 40 .

[0080] For example, the gate dielectric layer 25 and the first dielectric layer 41 at the bottom wall of the initial channel hole 40 a are etched using an anisotropic etching process, and the etching rate of the etching process in a direction perpendicular to the substrate 11 is much greater than the etching rate in a direction parallel to the substrate 11 .

[0081] In step S50, referring to Figure 5 The channel layer 26 is formed by CVD deposition, and the channel layer 26 covers the bottom wall and sidewall of the channel hole 40 and the top surface of the isolation layer 24. The material of the channel layer 26 includes an amorphous semiconductor material. For example, the material of the channel layer 26 includes amorphous silicon.

[0082] In step S60, referring to Figure 6 A thermal conductive material is deposited by PVD to form a thermal conductive layer 30 , and the thermal conductive layer 30 covers the channel layer 26 and fills the unfilled area of ​​the channel hole 40 .

[0083] In one example, the heat conducting layer 30 completely fills the unfilled area of ​​the channel hole 40 ; in another example, the heat conducting layer 30 partially fills the unfilled area of ​​the channel hole 40 .

[0084] In this embodiment, the heat conducting layer 30 fills the unfilled area of ​​the channel hole 40 to increase the volume of the conductive layer 30 , which is beneficial to increase the thermal conductivity uniformity of the heat conducting layer 30 , so that during the thermal annealing process, the conductive layer 30 conducts heat uniformly to heat the channel layer 26 .

[0085] The thermal conductivity of the heat-conducting layer 30 is greater than the thermal conductivity of the channel layer 26 , so that the channel layer 26 is heated by transferring heat from the heat-conducting layer 30 to the channel layer 26 .

[0086] According to actual process requirements, the material of the thermal conductive layer 30 may include cobalt, copper, tungsten, aluminum or oxides or nitrides of the above metals; the material of the thermal conductive layer 30 may also include a carbon material with good thermal conductivity, such as silicon carbide or amorphous carbon.

[0087] In one embodiment, referring to Figure 7 As shown, the heat conducting layer 30 includes a barrier layer 31 and a metal layer 32 formed in sequence, and the barrier layer 31 is disposed between the metal layer 32 and the channel layer 26. The barrier layer 31 is used to prevent the metal material of the metal layer 32 from diffusing into other devices or film layers, thereby preventing the diffusion of the metal material from causing a short circuit in the device and improving the reliability of the semiconductor structure.

[0088] The material of the barrier layer 31 includes at least one of cobalt oxide, cobalt nitride, copper oxide, copper nitride, tungsten oxide, tungsten nitride, titanium nitride, titanium oxide, aluminum oxide or aluminum nitride; the material of the metal layer 32 includes at least one of cobalt, copper, tungsten or aluminum.

[0089] In one example, the material of the barrier layer 31 includes cobalt oxide, and the material of the metal layer 32 includes cobalt; in another example, the material of the barrier layer 31 includes titanium nitride, and the material of the metal layer 32 includes tungsten.

[0090] In step S70, refer to Figure 6 or Figure 7 , thermal annealing is performed on the channel layer 26 and the heat conducting layer 30. For example, furnace annealing or rapid thermal annealing may be used.

[0091] During the thermal annealing process, the thermal conductivity of the heat-conducting layer 30 is high and the temperature rises quickly. The temperature of the heat-conducting layer 30 rises quickly, and the overall temperature of the heat-conducting layer 30 is uniform. The heat-conducting layer 30 conducts heat to the channel layer 26, so that the channel layer 26 is heated uniformly. The crystal orientation of the channel layer 26 is rearranged to form a polycrystalline semiconductor layer that conformally covers the channel hole 40.

[0092] In one embodiment, after the channel layer 26 and the heat conductive layer 30 are thermally annealed together, the channel layer 26 is formed into a polysilicon layer that conformally covers the sidewalls and bottom surface of the channel hole 40 .

[0093] It can be understood that in the semiconductor field, the ALD process can only deposit a conformal covering film layer through atomic layer epitaxy, but the ALD process cannot deposit a polycrystalline semiconductor layer. The polycrystalline semiconductor layer needs to be annealed after CVD deposition. The polycrystalline semiconductor layer covers the previous layer device. Affected by the morphology of the previous layer device, the polycrystalline semiconductor layer may be heated unevenly during the thermal annealing process, affecting the continuity of the polycrystalline semiconductor layer. In this embodiment, by forming a thermal conductive layer 30 and performing thermal annealing together with the channel layer 26, the thermal conductive layer 30 has high thermal conductivity and fast temperature rise. After the temperature of the thermal conductive layer 30 rises, the channel layer 26 is uniformly heated, so that the channel layer 26 forms a polycrystalline silicon layer that conformally covers the channel hole 40, thereby improving the conductivity of the channel layer 26, which is beneficial to improving the electrical performance of the semiconductor structure.

[0094] After the thermal annealing treatment, the heat conducting layer 30 is removed by etching to expose the channel layer 26. For example, the heat conducting layer 30 may be removed by a wet process, and the etching solution has a high etching ratio to the material of the channel layer 26.

[0095] In one embodiment, step S80 of forming an insulating layer 27 in the channel hole 40 includes:

[0096] Step S81: depositing an insulating material to fill the channel hole 40 , wherein the insulating material covers the channel layer 26 and at least fills a portion of the channel hole 40 ;

[0097] Reference Figure 8 CVD or ALD may be used to deposit an insulating material, which covers the channel layer 26 and fills the unfilled region of the channel hole 40 .

[0098] Step S82 : etching back the insulating material into the channel hole 40 .

[0099] Reference Figure 8 , the insulating material is etched back until its top surface is lower than the top surface of the channel hole 40 , and the insulating material etched and retained in the channel hole 40 forms an insulating layer 27 .

[0100] For example, the material of the insulating layer 27 may include a low-k dielectric material or silicon oxide, and the low-k dielectric material may be a material having a lower dielectric constant than silicon oxide. The low-k dielectric material may include one or more of flowable oxide (FOX), torn silazene (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), or flowable CVD (FCVD) oxide.

[0101] In one embodiment, referring to Figure 8 The top surface of the insulating layer 27 is higher than the top surface of the gate 23 and lower than the top surface of the channel hole 70 , and the insulating layer 27 exposes a portion of the inner sidewall of the channel layer 26 .

[0102] In one embodiment, before forming the second electrode 29 on the insulating layer 27 in step S90 , the method further includes: step S81 : etching and removing the channel layer 26 on the top surface of the isolation layer 24 , exposing the top surface of the isolation layer 24 , and disconnecting the channel layer 26 in each channel hole 40 .

[0103] Reference Fig. 9 After forming the insulating layer 27 , the channel layer 26 on the top surface of the isolation layer 24 is removed by etching to disconnect the channel layer 26 in each channel hole 40 .

[0104] For example, the channel layer 26 on the top surface of the isolation layer 24 may be removed by etching using a dry process.

[0105] In step S90, referring to Figure 9-13 , forming a second electrode 29, the second electrode 29 contacts the top of the channel layer 26, the second electrode 29 extends along the first direction D1, and is arranged at intervals along the second direction D2. The second electrode 29 is a drain or a source. Among them, one of the first electrode 21 and the second electrode 29 is a source, and the other is a drain.

[0106] In one embodiment, step S90 of forming the second electrode 29 includes the following steps:

[0107] Step S91a: forming a contact layer 291, wherein the contact layer 291 covers the exposed inner sidewalls of the channel layer 26 and fills the unfilled area of ​​the channel hole 40;

[0108] Reference Fig. 9 CVD deposition may be used to form a contact layer 291 , which covers the exposed inner sidewalls of the channel layer 26 and fills the unfilled region of the channel hole 40 .

[0109] The material of the contact layer 291 may include a semiconductor material. For example, the material of the contact layer 291 includes polysilicon.

[0110] Step S92 a : forming a metal conductive layer 292 , wherein the metal conductive layer 292 covers the top surface of the contact layer 291 , the top surface of the channel layer 26 , and the top surface of the isolation layer 24 .

[0111] Reference Fig.10 , Fig.11 , PVD deposition is used to form a metal conductive layer 292. The metal conductive layer 292 may include a single layer structure or a multi-layer structure.

[0112] Then, the patterned metal conductive layer 292 and the contact layer 291 form discrete second electrodes 29 , which extend along the first direction D1 and are spaced apart along the second direction D2 .

[0113] In one embodiment, referring to Fig.10 , Fig.11 , forming a metal conductive layer 292, including: sequentially forming a metal barrier layer 2921 and a metal conductive layer 2922, wherein the metal barrier layer 2921 is disposed between the metal conductive layer 2922 and the contact layer 291. The metal barrier layer 2921 is used to prevent the metal material in the metal conductive layer 2922 from diffusing into other devices or film layers, thereby preventing the metal material from inducing a short circuit in adjacent devices, and improving the reliability of the semiconductor structure.

[0114] For example, the material of the metal barrier layer 2921 may include at least one of tantalum, tantalum nitride, and titanium nitride; and the material of the metal conductive layer 2922 may include tungsten.

[0115] The second electrode 29 manufactured in this embodiment has a metal conductive layer 292 that is in contact with the inner side wall of the top of the channel layer 26 through the contact layer 291, thereby reducing the contact resistance between the second electrode 29 and the channel layer 26 and reducing the overall resistance of the semiconductor structure, which is beneficial to improving the electrical performance and read-write performance of the semiconductor structure and improving the response rate of the semiconductor structure.

[0116] In one embodiment, the contact layer 291 also covers the top surface of the isolation layer 24, and the contact layer 291 is disposed between the metal conductive layer 292 and the isolation layer 24. In this way, the contact area between the contact layer 291 and the metal conductive layer 292 is further increased, the contact resistance between the contact layer 291 and the metal conductive layer 292 is reduced, the electrical performance and read / write performance of the semiconductor structure are further improved, and the response rate of the semiconductor structure is improved.

[0117] In one embodiment, step S90 of forming the second electrode 29 includes the following steps:

[0118] Step S91b: forming a metal barrier layer 2921, wherein the metal barrier layer 2921 covers the inner sidewall of the top of the channel layer 26, the top surface of the channel layer 26 and the top surface of the isolation layer 24;

[0119] Step S92 b : forming a metal conductive layer 2922 , wherein the metal conductive layer 2922 covers the metal barrier layer 291 and fills the unfilled area of ​​the channel hole 40 .

[0120] Reference Fig.12 , Fig.13 The second electrode 29 manufactured by the manufacturing method of the semiconductor structure of this embodiment only includes two layers: a metal barrier layer 291 and a metal conductive layer 2922, which saves the process steps of forming the contact layer 291, saves the manufacturing cost and manufacturing time, and is beneficial to improving the product yield.

[0121] In some embodiments, reference Fig.10 or Fig.13 After forming the second electrode 29, the exposed sidewalls of the metal conductive layer 292 of the second electrode 29 can be nitrided to form a nitride layer 293. The metal nitride layer 293 is used to prevent the metal material in the second electrode 29 from diffusing into other devices or film layers, thereby avoiding the diffusion of metal materials and further reducing the risk of short circuits between devices.

[0122] Then, an insulating material is deposited by CVD or ALD to cover the nitride layer 293 and fill between the second electrodes 29 to form an isolation sidewall 28 for isolating the second electrodes 29 .

[0123] In some embodiments, the nitride layer 293 can be formed into silicon nitride by direct deposition. In this case, the non-metallic nitride layer 293 is located between the metal conductive layer 292 and the isolation sidewall 28, which is used to enhance the isolation effect and strengthen the surface adhesion between the metal conductive layer 292 and the isolation sidewall 28, thereby enhancing the connection strength between the second electrode 29 and the isolation sidewall 28, increasing the stability of the semiconductor structure, and reducing the risks of damage, delamination, and falling off of the semiconductor structure.

[0124] By way of example, the material of the isolation sidewall 28 may include at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide.

[0125] According to an exemplary embodiment, this embodiment provides a semiconductor structure, and the semiconductor structure of this embodiment is manufactured by the manufacturing method of the above embodiment. The semiconductor structure can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory (flash EPROM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), or other types of memory.

[0126] Reference Fig.10 , Fig.11 , Fig.12 , Fig.13 As shown, the semiconductor structure includes a substrate 11 and a first electrode 21, a gate 23 and a second electrode 29 stacked in sequence on the substrate 11; a first dielectric layer 41 is arranged between the gate 23 and the first electrode 21, and the gate 23 and the first electrode 21 are separated by the first dielectric layer 41, and an isolation layer 24 is arranged between the gate 23 and the second electrode 29, and the isolation layer 24 covers the top surface of the gate 23.

[0127] A channel hole 40 is provided between the first electrode 21 and the second electrode 29 . The channel hole 40 penetrates the isolation layer 24 , the gate 23 and the first dielectric layer 41 . The channel layer 26 is provided in the channel hole 40 . The channel layer 26 is a polycrystalline semiconductor layer that conformally covers the bottom wall and side walls of the channel hole 40 . The bottom wall of the channel layer 26 is in contact with the top surface of the first electrode 21 .

[0128] A gate dielectric layer 25 is disposed between the gate 23 and the outer sidewall of the channel layer 26. An insulating layer 27 is disposed inside the channel layer 26, and the insulating layer 27 covers the bottom wall and at least a portion of the inner sidewall of the channel layer 26. A second electrode 29 is disposed above the insulating layer 27, and the second electrode 29 covers the top surface of the insulating layer 27 and is in contact with the top of the channel layer 26.

[0129] In some embodiments, the channel layer 26 is a polysilicon layer conformally covering the bottom wall and sidewalls of the channel hole 40 .

[0130] In the semiconductor structure of this embodiment, the channel layer 26 is a polycrystalline semiconductor layer conformally covering the channel hole 40 , which reduces the resistance of the channel layer 26 and improves the conductivity of the channel layer 26 , which is beneficial to improving the electrical performance of the semiconductor structure.

[0131] According to an exemplary embodiment, this embodiment provides an electronic device, including the semiconductor structure in the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0132] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate, and forming a first electrode on the substrate; forming a gate on the first electrode, wherein a top surface of the gate is covered by an isolation layer; forming a channel hole penetrating the isolation layer and the gate, wherein the channel hole exposes a portion of the top surface of the first electrode; forming a gate dielectric layer, wherein the gate dielectric layer covers the sidewalls of the channel hole; forming a channel layer, wherein the channel layer covers the gate dielectric layer and a top surface of the first electrode exposed by the channel hole; Filling the channel hole with a heat-conducting material to form a heat-conducting layer; After thermal annealing is performed on the channel layer and the heat-conducting layer, the heat-conducting layer is removed; forming an insulating layer in the channel hole, wherein the insulating layer covers a portion of an inner sidewall of the channel layer; A second electrode is formed on the insulating layer, wherein the second electrode is contact-connected with a top portion of the channel layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After the channel layer and the heat conducting layer are subjected to a thermal annealing treatment together, the channel layer is formed into a polycrystalline semiconductor layer that conformally covers the sidewalls and the bottom surface of the channel hole.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The heat conduction layer includes a barrier layer and a metal layer which are formed in sequence, and the barrier layer is arranged between the metal layer and the channel layer.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of forming an insulating layer in the channel hole comprises: Depositing an insulating material to fill the channel hole, wherein the insulating material covers the channel layer and at least fills a portion of the channel hole; The insulating material is etched back into the channel hole.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The top surface of the insulating layer is higher than the top surface of the gate and lower than the top surface of the channel hole, and the insulating layer exposes a portion of the inner sidewall of the channel layer.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The forming of the second electrode comprises: forming a contact layer, wherein the contact layer covers the exposed inner sidewall of the channel layer and fills the unfilled area of ​​the channel hole; A metal conductive layer is formed, wherein the metal conductive layer covers a top surface of the contact layer, a top surface of the channel layer, and a top surface of the isolation layer.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The forming of the metal conductive layer comprises: forming a metal barrier layer and a metal conductive layer in sequence, wherein the metal barrier layer is arranged between the metal conductive layer and the contact layer.

8. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The contact layer also covers the top surface of the isolation layer, and the contact layer is arranged between the metal conductive layer and the isolation layer.

9. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The forming of the second electrode comprises: forming a metal barrier layer, wherein the metal barrier layer covers the inner sidewall of the top of the channel layer, the top surface of the channel layer, and the top surface of the isolation layer; A metal conductive layer is formed, wherein the metal conductive layer covers the metal barrier layer and fills an unfilled area of ​​the channel hole.

10. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: Before forming the second electrode on the insulating layer, the method further includes: The channel layer on the top surface of the isolation layer is removed by etching to expose the top surface of the isolation layer, and the channel layer in each of the channel holes is disconnected.

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