Electronic device

Abstract

The present disclosure provides an electronic device including an electronic component, an encapsulation layer surrounding the electronic component, a circuit structure electrically connected to the electronic component, the circuit structure having a connection portion, a bonding component overlapping the connection portion and electrically connected to the electronic component, and a first auxiliary pad electrically connected to the bonding component. The first auxiliary pad is disposed in the circuit structure. Besides, the connecting part is arranged between the first auxiliary pad and the joint assembly, the connecting part is overlapped with the first auxiliary pad, and the intrinsic stress of the first auxiliary pad is between + 800 MPa and-1000 MPa.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and in particular to an electronic device having a packaging structure. Background Art

[0002] The packaging method includes fan-in packaging or fan-out packaging, wherein fan-out packaging is for example fan-out panel level package (FOPLP) or fan-out wafer level package (FOWLP) technology. The packaging method can improve the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) in a given area, and has been widely used in the production and manufacturing of electronic devices in recent years.

[0003] However, the packaging structure has many structures integrating heterogeneous material interfaces (for example, the interface between the redistribution layer (RDL) and the conductive pad, the under bump metallurgy (UBM) area, etc.), and the interfaces of heterogeneous materials are often prone to delamination or peeling due to the presence of large stress.

[0004] As mentioned above, developing a method for improving the reliability of the packaging structure of an electronic device (eg, improving the strength of the connection structure between interfaces) is still one of the research topics that the industry is currently working hard on. Summary of the invention

[0005] According to some embodiments of the present disclosure, an electronic device is provided, comprising an electronic component, a packaging layer, a circuit structure, a bonding component, and a first auxiliary pad, wherein the packaging layer surrounds the electronic component, the circuit structure is electrically connected to the electronic component, the circuit structure has a connecting portion, the bonding component overlaps with the connecting portion and is electrically connected to the electronic component, and the first auxiliary pad is disposed in the circuit structure. In addition, the connecting portion is disposed between the first auxiliary pad and the bonding component, the connecting portion overlaps with the first auxiliary pad, and the intrinsic stress of the first auxiliary pad is between +800MPa and -1000MPa.

[0006] In order to make the features and advantages of the present disclosure more obvious and understandable, some embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram showing a cross-sectional structure of an electronic device according to some embodiments of the present disclosure;

[0008] FIG. 2A to FIG. 2F A schematic diagram showing a cross-sectional structure of an electronic device at different process stages according to some embodiments of the present disclosure;

[0009] Figure 3 A schematic diagram showing a cross-sectional structure of an electronic device according to some embodiments of the present disclosure;

[0010] Figure 4 A schematic diagram showing a cross-sectional structure of an electronic device according to some embodiments of the present disclosure;

[0011] Figure 5 A schematic diagram showing a cross-sectional structure of an electronic device according to some embodiments of the present disclosure;

[0012] Figure 6 A schematic diagram of the top structure of an electronic device according to some embodiments of the present disclosure is shown.

[0013]

Explanation of symbols

[0014] 10A, 10B, 10C, 10D, 10E: Electronic devices

[0015] 20: External electronic components

[0016] 100:Substrate

[0017] 102: Peeling layer

[0018] 200: Chip

[0019] 200R: Accommodation space

[0020] 200U, 200U': Electronic components

[0021] 201: Conductive pad

[0022] 202: passivation layer

[0023] 202v: Through hole

[0024] 204: Insulation layer

[0025] 204v:Through hole

[0026] 300: Encapsulation layer

[0027] 400-1, 400-1', 400-2, 400-3: patterned conductive layer

[0028] 400R: Circuit Structure

[0029] 402-1, 402-2: Insulation layer

[0030] 402v:Through hole

[0031] 410, 410-1, 410-2, 410-3: Auxiliary pads

[0032] 420:Joint assembly

[0033] CP:Connection

[0034] O1: Intersection

[0035] T202, T204, T402-1, T402-2, T410, T410-2, Tcp: thickness

[0036] W400-2, W410, Wcp: Width

[0037] Wa, Wb: distance

[0038] R1: First Area

[0039] R2: Second Area DETAILED DESCRIPTION

[0040] The following is a detailed description of the electronic device and its manufacturing method according to the embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not limitations of the present disclosure. In addition, similar and / or corresponding numbers may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding numbers is only for the purpose of simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0041] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in the embodiments to describe the relative relationship of one component to another component in the drawings. It is understood that if the device in the drawings is turned upside down, the component described on the "lower" side will become the component on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1 It is also understood that the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not drawn to scale, and in fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0042] Furthermore, when a first material layer is mentioned as being located on or above a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0043] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify components, do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. For example, the first component in the specification may be the second component in the claims.

[0044] In some embodiments of the present disclosure, terms such as "connection", "interconnection", etc., related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein another structure is disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "coupled" include any direct and indirect electrical connection means.

[0045] In the text, the terms "about", "substantially", and "approximately" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The term "range between a first value and a second value" means that the range includes the first value, the second value, and other values ​​therebetween. Furthermore, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0046] According to the embodiments of the present disclosure, a scanning electron microscope (SEM), an optical microscope (OM), an α-step, an ellipsometer, or other suitable methods may be used to measure the width, thickness, or height of each component, and the spacing or distance between components. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image of a component to be measured, and the width, thickness, or height of each component, and the spacing or distance between components may be measured.

[0047] It should be understood that the following embodiments may replace, reorganize, or combine features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0049] According to an embodiment of the present disclosure, an electronic device is provided, comprising an auxiliary pad arranged in a circuit structure, which can improve the overall stress balance of the connection structure (for example, the connection part and the bonding component of the circuit structure), reduce the vertical stress when the connection structure is bonded, and thereby improve the packaging reliability of the electronic device.

[0050] According to the embodiments of the present disclosure, the electronic device can be applied to a power module, a semiconductor packaging device, a display device, a light-emitting device, a backlight device, an antenna device, a touch device, a sensing device, a wearable device, a vehicle device, a battery device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, but is not limited thereto. Furthermore, the electronic device may, for example, include liquid crystal, quantum dots (QD), fluorescence, phosphorescence, other suitable materials or a combination of the foregoing. The electronic device may include electronic components, and the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED or a quantum dot light emitting diode (quantum dotLED), but is not limited thereto. According to some embodiments, the electronic device may include a panel and / or a backlight module, and the panel may include, for example, a liquid crystal panel or other self-luminous panels, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be understood that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto.

[0051] According to an embodiment of the present disclosure, the manufacturing method of the provided electronic device can be applied, for example, to a wafer-level package (WLP) process or a panel-level package (PLP) process, and can adopt a chip first process or a chip last / RDL first process, which will be further described in detail below. According to an embodiment of the present disclosure, the packaging structure of the electronic device can include a system on package (SoC), a system in package (SiP), an antenna in package (AiP), or a combination thereof, but is not limited thereto.

[0052] Please refer to Figure 1 , Figure 1 A schematic cross-sectional structure diagram of an electronic device 10A is shown according to some embodiments of the present disclosure. It should be understood that for the sake of clarity, some components of the electronic device 10A may be omitted in the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 10A described below. According to other embodiments, some features of the electronic device 10A described below may be replaced or omitted.

[0053] like Figure 1 As shown, the electronic device 10A may include an electronic component 200U, a packaging layer 300 , a circuit structure 400R, a bonding component 420 and an auxiliary pad 410 .

[0054] According to some embodiments, the electronic component 200U may include a chip 200 , a passivation layer 202 , and an insulating layer 204 . The passivation layer 202 may be disposed between the chip 200 and the insulating layer 204 .

[0055] According to some embodiments, the chip 200 may include, for example, a known-good die (KGD), an integrated circuit chip (IC), a surface mount device (SMD), a diode chip, a filter, a sensor, a micro-electromechanical system component (MEMS), a liquid crystal chip, a structure of a semiconductor-related process, or a structure of a semiconductor-related process disposed on a substrate (e.g., polyimide, glass, silicon substrate or other suitable substrate materials) or other suitable electronic components, wherein the surface mount components include capacitors, resistors, inductors, etc., but are not limited thereto.

[0056] According to some embodiments, the passivation layer 202 may be disposed on the surface of the chip 200 and in contact with the chip 200. According to some embodiments, the passivation layer 202 may have a through hole 202v and the conductive material may be disposed in the through hole 202v. For example, the electronic component 200U may further include a conductive pad 201, and the passivation layer 202 may surround the conductive pad 201. The through hole 202v may expose at least a portion of the conductive pad 201, and the conductive material may be electrically connected to the conductive pad 201 through the through hole 202v. The conductive pad 201 may be, for example, one end of a transistor (e.g., source, gate, and drain). According to some embodiments, the conductive material disposed in the through hole 202v may be a part of the patterned conductive layer 400-1 of the circuit structure 400R, and the circuit structure 400R may be electrically connected to the chip 200 through the through hole 202v of the passivation layer 202. The passivation layer 202 may have a single layer or a multi-layer structure. Furthermore, the passivation layer 202 has a thickness T202. According to some embodiments, the thickness T202 may range from 0.3 micrometers (μm) to 1.2 micrometers (0.3 μm ≤ thickness T202 ≤ 1.2 μm), for example, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, or 1.1 μm, but not limited thereto. According to some embodiments, the thermal expansion coefficient (CTE) of the passivation layer 202 may range from 0.1 ppm / K to 10 ppm / K (0.1 ppm / K ≤ thermal expansion coefficient of the passivation layer 202 ≤ 10 ppm / K), or from 1 ppm / K to 9 ppm / K, for example, 2 ppm / K, 3 ppm / K, 4 ppm / K, 5 ppm / K, 6 ppm / K, 7 ppm / K, or 8 ppm / K, but not limited thereto. The thickness described in the present disclosure may be the maximum thickness of the component along the Z direction in the cross-sectional view.

[0057] The insulating layer 204 may be disposed between the passivation layer 202 and the circuit structure 400R. According to some embodiments, the insulating layer 204 may be disposed on the surface of the passivation layer 202 and in contact with the passivation layer 202. The insulating layer 204 may have a through hole 204v and a conductive material may be disposed in the through hole 204v, the conductive material disposed in the through hole 204v may serve as a part of the patterned conductive layer 400-1, and the circuit structure 400R may be electrically connected to the chip 200 via the through hole 204v of the insulating layer 204. The insulating layer 204 may have a single-layer or multi-layer structure. Furthermore, the insulating layer 204 has a thickness T204. According to some embodiments, the thickness T204 may range from 5 μm to 25 μm (5 μm ≤ thickness T204 ≤ 25 μm), or from 10 μm to 20 μm, for example, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, or 19 μm, but not limited thereto. According to some embodiments, the thermal expansion coefficient of the insulating layer 204 may range from 10 ppm / K to 50 ppm / K (10 ppm / K ≤ thermal expansion coefficient of the insulating layer 204 ≤ 50 ppm / K), or from 15 ppm / K to 45 ppm / K, or from 20 ppm / K to 40 ppm / K, for example, 25 ppm / K, 30 ppm / K, or 35 ppm / K, but not limited thereto. The thermal expansion coefficient referred to in the present disclosure can be measured by a thermomechanical analyzer. For example, a 1 cm*1 cm (1 cm long and 1 cm wide) sample can be made for testing, or a sample of a suitable size can be made according to the limitation of the instrument, but the present invention is not limited thereto.

[0058] It is worth noting that the thickness T204 of the insulating layer 204 is greater than the thickness T202 of the passivation layer 202. With this configuration, the insulating layer 204 can provide a buffering effect to reduce the risk of the electronic component 200U being broken during the wafer cutting process (e.g., cutting to form chips). Furthermore, the aforementioned thickness T202 refers to the maximum thickness of the passivation layer 202 in the normal direction of the chip 200 (e.g., the Z direction in the drawings); the aforementioned thickness T204 refers to the maximum thickness of the insulating layer 204 in the normal direction of the chip 200 (e.g., the Z direction in the drawings). According to some embodiments, the thermal expansion coefficient of the insulating layer 204 is greater than the thermal expansion coefficient of the passivation layer 202.

[0059] According to some embodiments, the material of the passivation layer 202 may include an inorganic material, an organic material, or a combination thereof, but is not limited thereto. For example, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or a combination thereof, but is not limited thereto. For example, the organic material may include polyethylene terephthalate (PET), polyethylene (PE), polyethersulfone (PES), polycarbonate (PC), polymethylmethacrylate (PMMA), polyimide (PI), photosensitive polyimide (PSPI), other suitable passivation materials, or a combination thereof, but is not limited thereto.

[0060] According to some embodiments, the insulating layer 204 may include a polymer insulating material, such as an ABF build-up film (Ajinomoto Build-up Film), a polyphenylene phthalate (PBPA) or a polyphenylene phthalate (PBPA) layer. Polyimide (PBO), polyimide, photosensitive polyimide, benzocyclobutene (BCB), other suitable insulating materials or combinations thereof, but are not limited thereto.

[0061] like Figure 1 As shown, the encapsulation layer 300 may surround the electronic component 200U. In detail, the encapsulation layer 300 surrounds the electronic component 200U means that the encapsulation layer 300 at least contacts two side surfaces of the electronic component 200U from a cross-sectional perspective. According to some embodiments, the encapsulation layer 300 may contact the side surface and the top surface of the electronic component 200U. According to some embodiments, the encapsulation layer 300 may also contact a portion of the circuit structure 400R, for example, contact the patterned conductive layer 400-1 and the insulating layer 402-1, but is not limited thereto.

[0062] The encapsulation layer 300 can reduce the influence of water and oxygen in the external environment on the electronic component 200U (especially the chip 200), but it is not limited thereto. According to some embodiments, the encapsulation layer 300 may include a molding compound, an epoxy resin, other suitable encapsulation materials or a combination thereof, but it is not limited thereto. According to some embodiments, the encapsulation layer 300 may include filling particles, and the filling particles enable the encapsulation layer 300 to have excellent rigidity, reduce scratches on the electronic device, or further reduce the influence of water and oxygen in the external environment on the electronic component 200U, but it is not limited thereto. According to some embodiments, the filling particles of the encapsulation layer 300 may include silicon oxide, aluminum oxide, titanium oxide, a combination thereof or other suitable materials, but it is not limited thereto, wherein the particle size of the filling particles may be between 0.1 μm and 50 μm.

[0063] like Figure 1 As shown, the circuit structure 400R is adjacent to the electronic component 200U and the packaging layer 300, and the circuit structure 400R is electrically connected to the electronic component 200U. According to some embodiments, the circuit structure 400R can be used as a redistribution layer (RDL), which can redistribute the circuits of the electronic device and / or further increase the circuit fan-out area, or different electronic components can be electrically connected to each other through the circuit structure 400R. For example, the spacing between two adjacent contact pads of the circuit structure 400R at one end of the contact chip 200 can be less than or equal to the spacing between two adjacent contact pads of the circuit structure 400R away from the end of the chip 200, so that the circuit structure 400R can adjust the circuit fan-out condition, but it is not limited thereto. Further, the circuit structure 400R can be applied to wafer level chip scale package (WLCSP), wafer level package (WLP), panel level package (PLP) or other packaging methods, but it is not limited thereto.

[0064] The circuit structure 400R as a rewiring structure may have one or more insulating layers and a patterned conductive layer. Figure 1 As shown, according to some embodiments, the circuit structure 400R may include an insulating layer 402-1, an insulating layer 402-2, a patterned conductive layer 400-1, a patterned conductive layer 400-2 and a patterned conductive layer 400-3 (as a connecting portion CP), and the circuit structure 400R may include an insulating layer 402-1, an insulating layer 402-2, a patterned conductive layer 400-1, a patterned conductive layer 400-2 and a patterned conductive layer 400-3 which may be disposed between the electronic component 200U and the bonding component 420.

[0065] In detail, according to some embodiments, the patterned conductive layer 400-1 can be disposed in the through hole 202v of the passivation layer 202 and the through hole 204v of the insulating layer 204 to be electrically connected to the chip 200, and a portion of the patterned conductive layer 400-1 can be disposed on the surface of the electronic component 200U and the packaging layer 300.

[0066] According to some embodiments, the insulating layer 402-1 may cover the patterned conductive layer 400-1 and the packaging layer 300, and the insulating layer 402-1 may have a through hole 402v, and the through hole 402v may overlap with the through hole 202v of the passivation layer 202 and / or the through hole 204v of the insulating layer 204. In detail, according to some embodiments, in the normal direction of the chip 200 (e.g., the Z direction in the drawings), the through hole 402v of the insulating layer 402-1 may at least partially overlap with the through hole 202v of the passivation layer 202 and / or the through hole 204v of the insulating layer 204. However, according to other embodiments, in the normal direction of the chip 200 (e.g., the Z direction in the drawings), the through hole 402v of the insulating layer 402-1 and the through hole 202v of the passivation layer 202 and / or the through hole 204v of the insulating layer 204 may not overlap or be staggered. According to an embodiment of the present disclosure, the "component A overlaps with component B" means that the projections of component A and component B on the same plane in the Z direction at least partially overlap. Furthermore, the insulating layer 402-1 may have a single-layer or multi-layer structure. The insulating layer 402-1 has a thickness T402-1. According to some embodiments, the thickness T402-1 may range from 3 μm to 25 μm (3 μm ≤ thickness T402-1 ≤ 25 μm), or from 5 μm to 15 μm, for example, 7 μm, 10 μm or 12 μm, but not limited thereto. According to some embodiments, the thermal expansion coefficient of the insulating layer 402-1 may range from 10 ppm / K to 50 ppm / K (10 ppm / K ≤ thermal expansion coefficient of the insulating layer 402-1 ≤ 50 ppm / K), or from 15 ppm / K to 45 ppm / K, for example, 16 ppm / K, 22 ppm / K or 35 ppm / K, but not limited thereto.

[0067] According to some embodiments, the patterned conductive layer 400-2 may be disposed in the through hole 402v of the insulating layer 402-1 to be electrically connected to the patterned conductive layer 400-1, and a portion of the patterned conductive layer 400-2 may be disposed on the surface of the insulating layer 402-1. According to some embodiments, in the normal direction of the chip 200 (e.g., the Z direction in the drawings), the patterned conductive layer 400-2 at least partially overlaps with the patterned conductive layer 400-1.

[0068] The patterned conductive layer 400-3 may serve as a connection portion CP, as a portion for connecting the circuit structure 400R with the bonding element 420. According to some embodiments, the patterned conductive layer 400-3 may be, for example, an under-bump metallization (UBM). According to some embodiments, the connection portion CP may be disposed on the surface of the patterned conductive layer 400-2, and the connection portion CP may be disposed between the patterned conductive layer 400-2 and the bonding element 420. According to some embodiments, in the normal direction of the chip 200 (e.g., the Z direction in the drawings), the connection portion CP at least partially overlaps with the patterned conductive layer 400-2 and the patterned conductive layer 400-1. Furthermore, according to some embodiments, the connection portion CP has a width Wcp, the patterned conductive layer 400-2 has a width W400-2, and the width Wcp of the connection portion CP may be greater than or equal to 0.3 times the width W400-2 of the patterned conductive layer 400-2, and less than or equal to 1.5 times the width W400-2 of the patterned conductive layer 400-2 (that is, 0.3x width W400-2≤width Wcp≤1.5xwidth W400-2). According to some embodiments, the width Wcp may be greater than or equal to 0.5 times the width W400-2 and less than or equal to 1.2 times the width W400-2, but is not limited thereto.

[0069] It is worth noting that when the width of the connection portion CP and the patterned conductive layer 400-2 conform to the aforementioned configuration, the stress during bonding can be alleviated from being excessively concentrated on the bonding surface, thereby causing the bonding component 420 and the connection portion CP to peel off or break, and other problems, thereby improving the structural strength or reliability of the electronic device. Furthermore, the aforementioned width Wcp refers to the maximum width of the connection portion CP in the direction perpendicular to the normal direction of the chip 200 (for example, the X direction in the drawings); the aforementioned width W400-2 refers to the maximum width of the patterned conductive layer 400-2 in the direction perpendicular to the normal direction of the chip 200 (for example, the X direction in the drawings).

[0070] According to some embodiments, the insulating layer 402-2 may cover the patterned conductive layer 400-2 and the insulating layer 402-1, and the connection portion CP may be disposed in the insulating layer 402-2. Furthermore, the insulating layer 402-2 may have a single-layer or multi-layer structure. Alternatively, the insulating layer 402-2 may be the same as or different from the insulating layer 402-1. For example, according to some embodiments, the thickness of the insulating layer 402-2 may be greater than the thickness of the insulating layer 402-1, or, according to some embodiments, the thermal expansion coefficient of the insulating layer 402-2 may be less than the thermal expansion coefficient of the insulating layer 402-1, but the present invention is not limited thereto.

[0071] According to some embodiments, the patterned conductive layer 400-1, the patterned conductive layer 400-2, and the patterned conductive layer 400-3 include conductive materials, such as copper (Cu), titanium (Ti), aluminum (Al), tantalum (Ta), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but are not limited thereto. Furthermore, the materials of the patterned conductive layer 400-1, the patterned conductive layer 400-2, and the patterned conductive layer 400-3 may be the same or different from each other.

[0072] According to some embodiments, the material of the insulating layer 402-1 may include a polymer insulating material, for example, polyphenylene bis(phenylene)bis(thiophene). The insulating layer 402-1 may include polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), resin, polymer, other suitable polymer insulating materials or combinations thereof, but not limited thereto. According to other embodiments, the insulating layer 402-1 may include silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), other suitable insulating materials or combinations thereof, but not limited thereto.

[0073] According to some embodiments, the insulating layer 402-2 may include insulating materials, such as solder mask, epoxy resin, inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or a combination thereof), organic polymer materials (e.g., polyimide resin, benzocyclobutene, polyparaxylene, naphthalene polymer, fluorocarbon, or acrylate), other suitable insulating materials, or a combination thereof, but not limited thereto. According to some embodiments, the insulating layer 402-2 may be formed of a solder resist material, but not limited thereto.

[0074] It should be understood that, according to different embodiments, the circuit structure 400R may include any appropriate number of insulating layers and patterned conductive layers, and the present disclosure is not limited to the embodiments shown in the embodiments.

[0075] like Figure 1As shown, the bonding component 420 may overlap with the connection portion CP and be electrically connected to the electronic component 200U. In detail, the bonding component 420 may be electrically connected to the chip 200 of the electronic component 200U by the connection portion CP of the circuit structure 400R, the patterned conductive layer 400-2 and the patterned conductive layer 400-1. According to some embodiments, the bonding component 420 may be disposed on the surface of the connection portion CP and in contact with the connection portion CP. According to some embodiments, one end of the bonding component 420 is electrically connected to the connection portion CP, and the other end may be electrically connected to a printed circuit board (PCB) (not shown) or other external components, but the present disclosure is not limited thereto. According to some embodiments, the bonding component 420 reacts with the connection portion CP to form an intermediate layer (not shown), and at least a portion of the intermediate layer is disposed between the connection portion CP and the bonding component 420.

[0076] According to some embodiments, the material of the bonding element 420 may include tin, silver, lead-free tin, copper, nickel, gold, gallium, other suitable materials, or combinations thereof, but is not limited thereto.

[0077] like Figure 1 As shown, the auxiliary pad 410 can be arranged in the circuit structure 400R. In other words, the auxiliary pad 410 can be in the same layer as at least one insulating layer in the circuit structure 400R, and the auxiliary pad 410 can be surrounded by at least one insulating layer in the circuit structure 400R. Specifically, the auxiliary pad 410 can be arranged between the connection part CP and the chip 200, and the connection part CP can be arranged between the auxiliary pad 410 and the bonding component 420. In the normal direction of the chip 200 (for example, the Z direction in the accompanying drawings), the connection part CP overlaps with the auxiliary pad 410. For example, in the Z direction, the geometric center of the auxiliary pad 410 overlaps with the connection part CP, or, in a cross-sectional structural schematic diagram, the intersection point O1 of the diagonal line of the auxiliary pad 410 overlaps with the connection part CP (as shown in FIG. 2 ). Figure 1 ). According to some embodiments, the auxiliary pad 410 may contact the insulating layer 402-1, but is not limited thereto. According to some embodiments, the auxiliary pad 410 may contact the patterned conductive layer 400-1 and / or the patterned conductive layer 400-2, but is not limited thereto. According to some embodiments, the auxiliary pad 410 may be disposed at a position adjacent to the through hole 402v and contact the patterned conductive layer 400-2 in the through hole 402v, but is not limited thereto.

[0078] It is worth noting that when the connecting portion CP is arranged between the auxiliary pad 410 and the bonding component 420 and the connecting portion CP overlaps with the auxiliary pad 410, the auxiliary pad 410 can improve the stress balance of the electronic device, reduce the vertical stress when the bonding component 420 and the connecting portion CP are bonded, and reduce the risk of the bonding component 420 or the connecting portion CP breaking or peeling off from each other, thereby improving the reliability of the electronic device.

[0079] According to some embodiments, the thermal expansion coefficient of the auxiliary pad 410 is smaller than the thermal expansion coefficient of the insulating layer (insulating layer 402-1 and / or insulating layer 402-2) of the circuit structure 400R. Specifically, according to some embodiments, the thermal expansion coefficient of the auxiliary pad 410 may be between 0.1ppm / K and 12ppm / K (0.1ppm / K≤thermal expansion coefficient of the auxiliary pad 410≤12ppm / K), or between 1ppm / K and 11ppm / K, for example, 2ppm / K, 3ppm / K, 4ppm / K, 5ppm / K, 6ppm / K, 7ppm / K, 8ppm / K, 9ppm / K or 10ppm / K, but not limited thereto.

[0080] According to some embodiments, the Young's modulus of the auxiliary pad 410 is greater than the Young's modulus of the insulating layer (insulating layer 402-1 and / or insulating layer 402-2) of the circuit structure 400R. Specifically, according to some embodiments, the Young's modulus of the auxiliary pad 410 may be between 220 GPa and 270 GPa (220 GPa≤Young's modulus of the auxiliary pad 410≤270 GPa), for example, 230 GPa, 240 GPa, 250 GPa, or 260 GPa, but not limited thereto. The Young's modulus referred to in the present disclosure may be obtained by measuring the stress and strain curve of the sample using a universal testing machine, for example, it may be measured with reference to ASTM-D638, ASTM-D882, ASTM-D3039 or other suitable standard methods, but not limited thereto.

[0081] It is worth noting that when the Young's modulus of the auxiliary pad 410 is greater than the Young's modulus of the insulating layer of the circuit structure 400R, the stress transfer between the bonding component 420 and the circuit structure 400R can be reduced or prevented, or the vertical stress can be supported or reduced, thereby improving the reliability of the electronic device.

[0082] In addition, according to some embodiments, the intrinsic stress of the auxiliary pad 410 may be between +800 MPa and -1000 MPa (-1000 MPa≤intrinsic stress of the auxiliary pad 410≤+800 MPa), or between +600 MPa and -800 MPa, or between +400 MPa and -600 MPa, for example, +300 MPa, +200 MPa, +100 MPa, 0 MPa, -100 MPa, -200 MPa, -300 MPa, -400 MPa or -500 MPa, but is not limited thereto.

[0083] It is worth noting that when the auxiliary pad 410 has the aforementioned specific intrinsic stress, it can compensate for the mechanical characteristics of the circuit structure 400R, improve stress balance, and thereby improve the reliability of the electronic device. Furthermore, according to some embodiments, a spectral reflection ellipsometer can be used to measure the thickness and refractive index of the auxiliary pad 410, and the intrinsic stress of the auxiliary pad 410 can be determined by the difference in refractive index.

[0084] In addition, if Figure 1 As shown, the auxiliary pad 410 may have a width W410, and according to some embodiments, the width W410 of the auxiliary pad 410 may be smaller than the width W400-2 of the patterned conductive layer 400-2. In other words, the width W410 of the auxiliary pad 410 may be smaller than the width of the patterned conductive layer in contact with the connection portion CP. According to some embodiments, the width W410 of the auxiliary pad 410 is greater than or equal to 0.3 times the width W400-2 of the patterned conductive layer 400-2, and less than or equal to 0.6 times the width W400-2 of the patterned conductive layer 400-2 (that is, 0.3x width W400-2≤width W410≤0.6xwidth W400-2). According to some embodiments, the width W410 may be greater than or equal to 0.4 times the width W400-2 and less than or equal to 0.5 times the width W400-2, but is not limited thereto.

[0085] It is worth noting that when the width of the auxiliary pad 410 and the patterned conductive layer 400-2 conforms to the aforementioned configuration, it can alleviate the problem that the stress is excessively concentrated on the bonding surface during bonding, thereby causing the bonding component 420 and the connection portion CP to peel off or break, thereby improving the structural strength or reliability of the electronic device. Furthermore, the aforementioned width W410 refers to the maximum width of the auxiliary pad 410 in the direction perpendicular to the normal direction of the chip 200 (for example, the X direction in the figure); the definition of the width W400-2 is as described above, and will not be repeated here.

[0086] Furthermore, the auxiliary pad 410 may have a thickness T410. According to some embodiments, the ratio of the thickness T410 of the auxiliary pad 410 to the thickness (thickness T402-1 or thickness T402-2) of the insulating layer (insulating layer 402-1 or insulating layer 402-2) of the circuit structure 400R may be between 0.5 and 1 (that is, 0.5≤thickness T410 / thickness T402-1≤1, 0.5≤thickness T410 / thickness T402-2≤1), for example, the ratio may be 0.6, 0.7, 0.8 or 0.9, but not limited thereto. Specifically, according to some embodiments, the thickness T410 of the auxiliary pad 410 may be between 1 μm and 30 μm (1 μm≤thickness T410≤30 μm), or between 5 μm and 25 μm, for example, 10 μm, 15 or 20 μm, but not limited thereto.

[0087] It is worth noting that when the thickness T410 of the auxiliary pad 410 and the thickness of the insulating layer of the circuit structure 400R meet the aforementioned configuration, the stress during bonding can be relieved from excessive concentration on the bonding surface, thereby causing the bonding component 420 and the connection portion CP to peel off or break, and other problems, thereby improving the structural strength or reliability of the electronic device. Furthermore, the aforementioned thickness T410 refers to the maximum thickness of the auxiliary pad 410 in the normal direction of the chip 200 (for example, the Z direction in the figure); the definition of the thickness T402-1 or the thickness T402-2 is as described above, and will not be repeated here.

[0088] According to some embodiments, the material of the auxiliary pad 410 may include silicon oxide (SiOx), silicon nitride (SiNx), titanium dioxide (TiO2), other suitable materials or combinations thereof, but is not limited thereto. It should be understood that the material of the auxiliary pad 410 is not limited to the aforementioned ones, and according to other embodiments, materials having the aforementioned specific thermal expansion coefficient, Young's modulus or intrinsic stress properties may also be used to form the auxiliary pad 410.

[0089] In addition, if Figure 1 As shown, according to some embodiments, the side surface of a portion of the auxiliary pad 410 may be flush or coplanar with the side surface of the patterned conductive layer 400-1, but the present disclosure is not limited thereto. According to other embodiments, the side surface of a portion of the auxiliary pad 410 may protrude from the side surface of the patterned conductive layer 400-1, or the side surface of a portion of the patterned conductive layer 400-1 may protrude from the side surface of the auxiliary pad 410, but is not limited thereto. Furthermore, according to some embodiments, the auxiliary pad 410 may have an inclined side surface, for example, the auxiliary pad 410 may have a trapezoidal shape, but is not limited thereto. According to different embodiments, the auxiliary pad 410 may have any suitable shape, for example, a rectangular, triangular or irregular shape, but is not limited thereto. According to some embodiments, the auxiliary pad 410 may have an arc-shaped top angle or bottom angle.

[0090] Next, please refer to Figure 2A , FIG. 2A to FIG. 2F The cross-sectional structure diagram of the electronic device in different process stages according to some embodiments of the present disclosure is shown. FIG. 2A to FIG. 2F The manufacturing method of the electronic device according to the embodiment of the present disclosure is further described.

[0091] It should be understood that, according to some embodiments, additional operating steps may be provided before, during and / or after the method for making the electronic device 10A is performed. According to some embodiments, some of the operating steps described may be replaced or omitted. According to some embodiments, the order of some of the operating steps described is interchangeable. In addition, it should be understood that the components or components that are the same or similar to the above will be represented by the same or similar reference numerals in the following text, and their materials and functions are the same or similar to those described in the above text, so this part will not be repeated in the following text.

[0092] First, please refer to Figure 2A , providing a substrate 100. The substrate 100 may be a carrier substrate. According to some embodiments, the substrate 100 may include a glass carrier substrate, a ceramic carrier substrate or other suitable carrier substrates, but is not limited thereto. According to some embodiments, the substrate 100 may be a chip or a wafer, but is not limited thereto.

[0093] A release layer 102 may be formed on the substrate 100. The release layer 102 may be removed from a subsequently formed overlying structure (e.g., the electronic component 200U) together with the substrate 100. The release layer 102 may include a polymer-based material, but is not limited thereto. According to some embodiments, the release layer 102 may include a heat-insulating material based on epoxy resin, which loses its adhesiveness when heated, such as a thermal release tape (HRT) or a light-to-heat-conversion (LTHC) release coating. According to other embodiments, the release layer 102 may include an ultraviolet (UV) glue that loses its adhesiveness when exposed to ultraviolet light. According to yet other embodiments, the release layer 102 may lose its adhesiveness by a laser lift-off process. According to some embodiments, the release layer 102 may be formed by a coating and curing process, a lamination process, other suitable processes, or a combination of the foregoing. According to some embodiments, the step of forming the lift-off layer 102 may be omitted. In other words, a subsequent film layer may be formed on the substrate 100 .

[0094] Next, an electronic component 200U may be formed on the substrate 100, and the electronic component 200U may be located on the peeling layer 102. According to some embodiments, a chip 200, a conductive pad 201, a passivation layer 202, and an insulating layer 204 may be sequentially formed on the substrate 100. In detail, according to some embodiments, a wafer (not shown) may be first disposed on the substrate 100 and the peeling layer 102, the wafer having the passivation layer 202, and an insulating layer 204 may be formed on the wafer and the peeling layer 102, and then a dicing process is performed to dicing the wafer into chips 200. According to some embodiments, the diced chips 200 and the passivation layer 202 and the insulating layer 204 thereon may be further transferred to another substrate 100 and the peeling layer 102 for subsequent processes.

[0095] According to some embodiments, the polymer insulating material may be formed on the substrate 100 and the release layer 102 by a coating process, a printing process, a chemical vapor deposition process, other suitable methods or a combination thereof to obtain the insulating layer 204 .

[0096] According to some embodiments, the cutting process may include a laser cutting process, but is not limited thereto. Furthermore, as mentioned above, the thickness T204 of the insulating layer 204 is greater than the thickness T202 of the passivation layer 202. With this configuration, the insulating layer 204 can provide a buffering effect to reduce the risk of the electronic component 200U being broken by the cutting process.

[0097] Please refer to Figure 2B , a packaging layer 300 may be formed to surround the electronic component 200U. Specifically, according to some embodiments, the electronic component 200U may be first transferred and inverted onto another carrier substrate, and then a packaging layer 300 may be formed on the carrier substrate. The carrier substrate may then be removed by, for example, a laser lift-off process to obtain a Figure 2B The structure shown.

[0098] According to some embodiments, a molding compound, epoxy resin, other suitable packaging materials, or a combination thereof may be formed around the electronic component 200U by compression molding, transfer molding, or other suitable methods to obtain the packaging layer 300. According to some embodiments, the material of the packaging layer 300 may be molded in a liquid or semi-liquid state and then cured.

[0099] Please refer to Figure 2C, a portion of the passivation layer 202 and the insulating layer 204 may be removed to form a through hole 202v and a through hole 204v, and the through hole 202v may expose a portion of the conductive pad 201. According to some embodiments, the passivation layer 202 and the insulating layer 204 may be patterned by one or more photolithography processes and / or etching processes to form the through hole 202v and the through hole 204v. According to some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying, etc., but is not limited thereto. The etching process may include a dry etching process or a wet etching process, but is not limited thereto.

[0100] Next, a patterned conductive layer 400-1 may be formed on the electronic component 200U and in the through hole 202v and the through hole 204v. According to some embodiments, the conductive material may be formed on the electronic component 200U and in the through hole 202v and the through hole 204v by a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. Furthermore, the conductive material may be patterned by one or more photolithography processes and / or etching processes to form the patterned conductive layer 400-1.

[0101] Please refer to Figure 2D , an auxiliary pad 410 may be formed on the patterned conductive layer 400-1. According to some embodiments, the auxiliary pad 410 may be in contact with the patterned conductive layer 400-1. According to some embodiments, the material of the auxiliary pad 410 may be formed on the patterned conductive layer 400-1 by a coating process, a printing process, a lamination process, a chemical vapor deposition process, other suitable methods or a combination of the foregoing.

[0102] Next, an insulating layer 402-1 may be formed on the patterned conductive layer 400-1 and the packaging layer 300. According to some embodiments, the insulating layer 402-1 may also cover the auxiliary pad 410, and then a planarization process may be performed to make the top surface of the insulating layer 402-1 substantially flush with the top surface of the auxiliary pad 410, so as to obtain Figure 2D According to some embodiments, an insulating material may be formed on the patterned conductive layer 400 - 1 and the packaging layer 300 by a coating process, a printing process, a chemical vapor deposition process, other suitable methods or a combination thereof to obtain an insulating layer 402 - 1 .

[0103] Please refer to Figure 2E , a portion of the insulating layer 402 - 1 is removed to form a through hole 402 v. According to some embodiments, the insulating layer 402 - 1 may be patterned by one or more photolithography processes and / or etching processes to form the through hole 402 v.

[0104] Next, a patterned conductive layer 400-2 may be formed on the insulating layer 402-1 and in the through hole 402v. According to some embodiments, the patterned conductive layer 400-2 may contact the auxiliary pad 410. According to some embodiments, the conductive material may be formed on the insulating layer 402-1 and in the through hole 402v by a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. Furthermore, the conductive material may be patterned by one or more photolithography processes and / or etching processes to form the patterned conductive layer 400-2.

[0105] Next, a patterned conductive layer 400-3 (connecting portion CP) may be formed on the patterned conductive layer 400-2, and the patterned conductive layer 400-3 may overlap with the auxiliary pad 410. According to some embodiments, a conductive material may be formed on the patterned conductive layer 400-2 by a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. Furthermore, the conductive material may be patterned by one or more photolithography processes and / or etching processes to form the patterned conductive layer 400-3.

[0106] Next, an insulating layer 402-2 may be formed on the patterned conductive layer 400-2 and the insulating layer 402-1. According to some embodiments, the insulating layer 402-2 may also cover the patterned conductive layer 400-3, and then a planarization process may be performed to make the top surface of the insulating layer 402-2 substantially flush with the top surface of the patterned conductive layer 400-3, so as to obtain Figure 2E According to some embodiments, an insulating material may be formed on the patterned conductive layer 400-2 and the insulating layer 402-1 by a coating process, a printing process, a chemical vapor deposition process, other suitable methods or a combination thereof to obtain an insulating layer 402-2.

[0107] Please refer to Figure 2F , a bonding component 420 can be formed on the patterned conductive layer 400-3 (connecting portion CP). The bonding component 420 can be arranged corresponding to the connecting portion CP, that is, in the normal direction of the chip 200 (the Z direction in the figure), the bonding component 420 overlaps with the connecting portion CP. According to some embodiments, the bonding component 420 can be bonded to the connecting portion CP by a reflow process, a fusion bonding process, a hybrid bonding process, a metal-to-metal bonding process, other suitable methods or a combination of the foregoing. At this point, the production of the electronic device 10A is substantially completed, and the electronic device 10A can be inverted to obtain Figure 1 The structure shown.

[0108] As mentioned above, in the embodiment of the manufacturing method of the electronic device 10A, a chip first process is adopted, but the present disclosure is not limited thereto. According to other embodiments, the manufacturing method of the electronic device may also adopt a chip last (chip last / RDL first) process, that is, the circuit structure 400R is formed first.

[0109] Please refer to Figure 3 , Figure 3 A schematic cross-sectional structure diagram of an electronic device 10B according to some other embodiments of the present disclosure is shown. It should be understood that for the sake of clarity, some components of the electronic device 10B may be omitted in the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 10B described below. According to other embodiments, some features of the electronic device 10B described below may be replaced or omitted.

[0110] The electronic device 10B is substantially similar to the aforementioned electronic device 10A. Compared with the electronic device 10A, the electronic device 10B includes a plurality of auxiliary pads 410. Specifically, the electronic device 10B may include an auxiliary pad 410-1 and an auxiliary pad 410-2, wherein the auxiliary pad 410-2 is adjacent to at least one side of the connection portion CP. The auxiliary pad 410-2 is also disposed in the circuit structure 400R, and the auxiliary pad 410-2 may be disposed between the bonding component 420 and the patterned conductive layer 400-2, and the auxiliary pad 410-2 may contact the connection portion CP. In the normal direction of the chip 200 (e.g., the Z direction in the drawings), the auxiliary pad 410-2 may overlap with the patterned conductive layer 400-2.

[0111] The thermal expansion coefficient of the auxiliary pad 410-2 is smaller than the thermal expansion coefficient of the insulating layer (insulating layer 402-1 and / or insulating layer 402-2) of the circuit structure 400R. Specifically, according to some embodiments, the thermal expansion coefficient of the auxiliary pad 410-2 may be between 0.1ppm / K and 12ppm / K (0.1ppm / K≤thermal expansion coefficient of auxiliary pad 410-2≤12ppm / K), or between 1ppm / K and 11ppm / K, for example, 2ppm / K, 3ppm / K, 4ppm / K, 5ppm / K, 6ppm / K, 7ppm / K, 8ppm / K, 9ppm / K or 10ppm / K, but not limited thereto.

[0112] According to some embodiments, the Young's modulus of the auxiliary pad 410-2 is greater than the Young's modulus of the insulating layer (insulating layer 402-1 and / or insulating layer 402-2) of the circuit structure 400R. Specifically, according to some embodiments, the Young's modulus of the auxiliary pad 410-2 may be between 220 GPa and 270 GPa (220 GPa≤Young's modulus of the auxiliary pad 410-2≤270 GPa), for example, 230 GPa, 240 GPa, 250 GPa, or 260 GPa, but not limited thereto.

[0113] According to some embodiments, the intrinsic stress of the auxiliary pad 410-2 may be between -100 MPa and -1000 MPa (-1000 MPa≤intrinsic stress of the auxiliary pad 410-2≤-100 MPa), for example, -200 MPa, -300 MPa, -400 MPa, -500 MPa, -600 MPa, -700 MPa, -800 MPa or -900 MPa, but is not limited thereto.

[0114] It is worth noting that when the auxiliary pad 410 - 2 has the aforementioned specific intrinsic stress, it can further compensate for the mechanical characteristics of the circuit structure 400R, improve stress balance, and thereby improve the reliability of the electronic device.

[0115] Furthermore, the auxiliary pad 410-2 has a thickness T410-2, and the connecting portion CP has a thickness Tcp, and the ratio of the thickness T410-2 of the auxiliary pad 410-2 to the thickness Tcp of the connecting portion CP may be between 0.8 and 1 (that is, 0.8≤thickness T410-2 / thickness Tcp≤1), for example, the ratio may be 0.85, 0.9 or 0.95, but is not limited thereto. Specifically, according to some embodiments, the thickness T410-2 of the auxiliary pad 410-2 may be between 1μm and 30μm (1μm≤thickness T410-2≤30μm), or between 5μm and 25μm, for example, 10μm, 15 or 20μm, but is not limited thereto. Furthermore, the thickness T410-2 of the auxiliary pad 410-2 may be the same as or different from the thickness T410-1 of the auxiliary pad 410-1. According to some embodiments, the thickness T410-2 of the auxiliary pad 410-2 is smaller than the thickness T410-1 of the auxiliary pad 410-1, thereby reducing the vertical stress when the connection structure is bonded, thereby improving the packaging reliability of the electronic device.

[0116] It is worth noting that when the thickness T410-2 of the auxiliary pad 410-2 and the thickness Tcp of the connecting part CP meet the above configuration, the stress during bonding can be alleviated from being excessively concentrated on the bonding surface, thereby causing problems such as peeling or breaking of the bonding component 420 and the connecting part CP, thereby improving the structural strength or reliability of the electronic device.

[0117] In addition, if Figure 3As shown, the side surface of the auxiliary pad 410-2 is not flush with the side surface of the patterned conductive layer 400-2, and the side surface of the patterned conductive layer 400-2 may protrude from the side surface of the auxiliary pad 410-2. Specifically, there is a distance Wa between the side surface of the auxiliary pad 410-2 and the side surface of the patterned conductive layer 400-2, and the distance Wa may be between 0.125 μm and 0.2 μm (that is, 0.125 μm ≤ distance Wa ≤ 0.2 μm), for example, 0.13 μm, 0.14 μm, 0.15 μm, 0.16 μm, 0.17 μm, 0.18 μm or 0.19 μm, but is not limited thereto.

[0118] It is worth noting that when the side surface of the auxiliary pad 410-2 and the side surface of the patterned conductive layer 400-2 meet the above configuration, the stress during bonding can be relieved from excessive concentration on the bonding surface, thereby causing the bonding component 420 and the connection portion CP to peel off or break, etc., thereby improving the structural strength or reliability of the electronic device. Furthermore, the above distance Wa refers to the minimum distance between the side surface of the auxiliary pad 410-2 and the side surface of the patterned conductive layer 400-2 in the direction perpendicular to the normal direction of the chip 200 (for example, the X direction in the figure).

[0119] Please refer to Figure 4 , Figure 4 A schematic cross-sectional structure diagram of an electronic device 10C according to some other embodiments of the present disclosure is shown. It should be understood that for the sake of clarity, some components of the electronic device 10C may be omitted in the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 10C described below. According to other embodiments, some features of the electronic device 10C described below may be replaced or omitted.

[0120] The electronic device 10C is substantially similar to the aforementioned electronic device 10B. Compared with the electronic device 10B, the electronic device 10C may further include an auxiliary pad 410-3. In this embodiment, the auxiliary pad 410-2 is adjacent to one side of the connection portion CP, and the auxiliary pad 410-3 is adjacent to the other side of the connection portion CP. The auxiliary pad 410-3 is also disposed in the circuit structure 400R, and the auxiliary pad 410-3 may be disposed between the bonding component 420 and the patterned conductive layer 400-2, and the auxiliary pad 410-3 may contact the connection portion CP. In the normal direction of the chip 200 (for example, the Z direction in the accompanying drawings), the auxiliary pad 410-3 may overlap with the patterned conductive layer 400-2. The auxiliary pad 410-3 may have a similar or identical thermal expansion coefficient, Young's modulus, intrinsic stress and thickness range as the auxiliary pad 410-2, which will not be repeated here.

[0121] like Figure 4As shown, the side surface of the auxiliary pad 410-3 may be flush with the side surface of the patterned conductive layer 400-2, the side surface of the auxiliary pad 410-3 may protrude from the side surface of the auxiliary pad 410-1, and there is a distance Wb between the side surface of the auxiliary pad 410-3 and the side surface of the auxiliary pad 410-1, and the distance Wb may be between 0.125μm and 0.2μm (that is, 0.125μm≤distance Wb≤0.2μm), for example, 0.13μm, 0.14μm, 0.15μm, 0.16μm, 0.17μm, 0.18μm or 0.19μm, but not limited thereto. According to some embodiments, the distance Wa between the side surface of the auxiliary pad 410-2 and the side surface of the patterned conductive layer 400-2 is equal to the distance Wb between the side surface of the auxiliary pad 410-3 and the side surface of the auxiliary pad 410-1.

[0122] It is worth noting that when the side surfaces of the auxiliary pad 410-1, the auxiliary pad 410-2, and the auxiliary pad 410-3 and the side surface of the patterned conductive layer 400-2 conform to the aforementioned configuration, the stress during bonding can be relieved from excessive concentration on the bonding surface, thereby causing the bonding component 420 and the connection portion CP to peel off or break, and other problems, thereby improving the structural strength or reliability of the electronic device. Furthermore, the aforementioned distance Wb refers to the minimum distance between the side surface of the auxiliary pad 410-3 and the side surface of the auxiliary pad 410-1 in the direction perpendicular to the normal direction of the chip 200 (for example, the X direction in the figure).

[0123] Next, please refer to Figure 5 , Figure 5 A schematic cross-sectional structure diagram of an electronic device 10D is shown according to some other embodiments of the present disclosure. It should be understood that for the sake of clarity, some components of the electronic device 10D may be omitted in the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 10D described below. According to other embodiments, some features of the electronic device 10D described below may be replaced or omitted.

[0124] The electronic device 10D may further include an electronic component 200U', and the electronic component 200U' may be integrated and packaged in the electronic device 10D together with the electronic component 200U. According to some embodiments, the electronic component 400 may include components such as resistors, capacitors, inductors, transistors, etc., but is not limited thereto. Furthermore, the circuit structure 400R of the electronic device 10D may further include a patterned conductive layer 400-1', and the patterned conductive layer 400-1' may be disposed between the chip 200 and the patterned conductive layer 400-1. In addition, the electronic device 10D may be joined to the external electronic component 20 via a joining component 420, one end of the joining component 420 being electrically connected to the connecting portion CP, and the other end being electrically connected to the external electronic component 20. The external electronic component 20 may, for example, include a printed circuit board (PCB), but the present disclosure is not limited thereto.

[0125] like Figure 5 As shown, in this embodiment, the chip 200 has a receiving space 200R, and a portion of the packaging layer 300 can be disposed in the receiving space 200R. Specifically, the receiving space 200R can be a recessed structure, the receiving space 200R can be located on the side of the chip 200 where the circuit structure 400R is not disposed, and the receiving space 200R can be disposed at the corner of the chip 200. The receiving space 200R can accommodate the packaging layer 300, thereby reducing the stress concentration at the corner of the chip 200. Furthermore, the receiving space 200R can also be used as a positioning mark,

[0126] Next, please refer to Figure 6 , Figure 6 FIG. 1 is a schematic diagram showing a top view of an electronic device 10E according to some embodiments of the present disclosure. It should be understood that for the sake of clarity, Figure 6 Only the bonding component 420 and the edges of the chip 200 and the encapsulation layer 300 are schematically shown.

[0127] Figure 6 As shown, the electronic device 10E may have a first region R1 and a second region R2, the region where the chip 300 overlaps with the circuit structure 400R is defined as the first region R1, and the second region R2 surrounds the first region R1. The electronic device 10E includes a plurality of bonding components 420, and the bonding components 420 may be disposed in the first region R1 and the second region R2. According to some embodiments, the auxiliary pad 410 may be correspondingly disposed at the bonding components 420 around the junction of the first region R1 and the second region R2 (for clear display, the bonding components 420 located around the junction of the first region R1 and the second region R2 are represented by dots in the accompanying drawings). Since there is usually a relatively large stress at the junction of the first region R1 and the second region R2, the auxiliary pad 410 is selectively disposed at this junction, which can improve the stress balance of the electronic device while reducing the manufacturing cost, thereby improving the reliability of the electronic device.

[0128] In summary, according to an embodiment of the present disclosure, the electronic device includes an auxiliary pad arranged in the circuit structure, which can improve the overall stress balance of the connection structure (for example, the connection part and the bonding component of the circuit structure), reduce the vertical stress when the connection structure is bonded, and thereby improve the packaging reliability of the electronic device.

[0129] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. The features between the embodiments of the present disclosure can be mixed and matched as needed as long as they do not violate the spirit of the invention or conflict with each other. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. The scope of protection of the present disclosure shall be subject to the scope of the appended claims. Any embodiment or claim of the present disclosure does not need to achieve all the purposes, advantages and features disclosed in this disclosure.

Claims

1. An electronic device, characterized in that: include: an electronic component; an encapsulation layer surrounding the electronic component; a circuit structure electrically connected to the electronic component, the circuit structure having a connecting portion; a bonding component overlapping the connecting portion and electrically connected to the electronic component; and a first auxiliary pad, disposed in the circuit structure, The connecting portion is disposed between the first auxiliary pad and the bonding component, the connecting portion overlaps with the first auxiliary pad, and the intrinsic stress of the first auxiliary pad is between +800 MPa and -1000 MPa.

2. The electronic device according to claim 1, wherein: The electronic components include: One chip; a passivation layer; and A first insulating layer, wherein the passivation layer is disposed between the chip and the first insulating layer, and the thickness of the first insulating layer is greater than the thickness of the passivation layer.

3. The electronic device according to claim 2, wherein: The circuit structure is electrically connected to the chip via a first through hole of the first insulating layer.

4. The electronic device as claimed in claim 2, characterized in that: The chip has a containing space, and a part of the packaging layer is arranged in the containing space.

5. The electronic device according to claim 1, wherein: The circuit structure further includes: A patterned conductive layer, wherein the connecting portion is disposed between the patterned conductive layer and the bonding component.

6. The electronic device as claimed in claim 5, characterized in that: The width of the first auxiliary pad is smaller than the width of the patterned conductive layer.

7. The electronic device according to claim 6, wherein: The width of the first auxiliary pad is greater than or equal to 0.3 times the width of the patterned conductive layer, and less than or equal to 0.6 times the width of the patterned conductive layer.

8. The electronic device as claimed in claim 5, characterized in that: The width of the connecting portion is greater than or equal to 0.3 times the width of the patterned conductive layer, and less than or equal to 1.5 times the width of the patterned conductive layer.

9. The electronic device as claimed in claim 1, wherein: The circuit structure further includes: A second insulating layer is disposed between the electronic component and the bonding component, wherein the thermal expansion coefficient of the first auxiliary pad is smaller than the thermal expansion coefficient of the second insulating layer.

10. The electronic device according to claim 1, wherein: The circuit structure further includes: A second insulating layer is disposed between the electronic component and the bonding component, wherein the Young's modulus of the first auxiliary pad is greater than the Young's modulus of the second insulating layer.

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