Electrostatic discharge protection circuit for die-to-die input / output signals

Abstract

An integrated circuit device includes an electrostatic discharge (ESD) protection circuit including a plurality of P + / N-well diodes (P-diodes) and a plurality of N + / P-wells (N-diodes) arranged in a stripe geometry, a p-tapped anode stripe of the ESD protection circuit being shared between a first P-diode and a second P-diode of the ESD protection circuit, and an n-tapped cathode strip of the ESD protection circuit is shared between a first N-diode and a second N-diode of the ESD protection circuit. Other examples are disclosed and claimed.

Description

Background Art

[0001] Electrostatic discharge (ESD) can be harmful to electronic devices. During an ESD event, charge is transferred from one object to another (e.g., from a person to an integrated circuit (IC)). The transferred charge can result in a high current through the IC in a short period of time, potentially damaging the device. Such ESD events can affect the IC throughout its lifetime, including during manufacturing and assembly. Electrostatic discharge (ESD) events that can damage integrated circuits can occur during the manufacture and assembly of semiconductor devices. ICs can incorporate on-chip ESD protection structures to protect the input, output, and power pins of the IC.

[0002] There is a continuing need for improved computing devices to enable the growing demand for modeling complex systems, providing reduced computational time, and other considerations. In some cases, the scaling characteristics of ICs have been a driving force for such improvements. Other advances have been made in materials, device structures, circuit layouts, and the like. In particular, there is a continuing desire to improve ESD protection circuits used for, used in, or otherwise supporting the operation of ICs. In view of these and other aspects, the present improvements are needed. As the desire to increase computing efficiency becomes more prevalent, such improvements may become critical. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The materials described herein are illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, where considered appropriate, reference numerals are repeated between the drawings to indicate corresponding or similar elements, e.g., having the same or similar functions. The present disclosure will be described with additional specificity and detail through the use of the accompanying drawings:

[0004] Figure 1 A block diagram of an example integrated circuit (IC) device including one or more shared stripe electrostatic discharge (SS ESD) protection circuits for die-to-die (D2D) input / output (IO) is shown;

[0005] Figure 2 A schematic diagram showing an example of an ESD protection circuit in which various strips may be shared;

[0006] Figure 3 A block diagram illustrating an example physical layout of an example SS ESD protection circuit;

[0007] Figure 4 A block diagram illustrating an example physical layout of an example SS ESD protection circuit having multi-finger diodes;

[0008] Figure 5 shows a layout diagram of an IC device including an example SS ESD protection circuit;

[0009] Figure 6 yes Figure 5 An enlarged view of region A of the IC device;

[0010] Figure 7 A block diagram of a system including an example stacked IC device having a SS ESD protection circuit for D2D IO is shown;

[0011] Figure 8 shows a diagram of an example data server machine employing an IC device having a SS ESD protection circuit for D2DIO; and

[0012] Fig. 9 is a block diagram of an example computing device, all in accordance with at least some implementations of the present disclosure. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which illustrate, by way of illustration, specific examples in which the claimed subject matter may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the subject matter. The various examples, while different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in conjunction with one example may be implemented in other examples without departing from the spirit and scope of the claimed subject matter.

[0014] References in this specification to "one example" or "an example" mean that a particular feature, structure, or characteristic described in conjunction with that example is included in at least one embodiment contained in the description. Therefore, the use of the phrase "one example" or "in an example" does not necessarily refer to the same example. In addition, the position or arrangement of the various elements within each disclosed example may be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the subject matter is limited only by the appended claims, properly interpreted, and the full scope of equivalents to which the appended claims are entitled.

[0015] As used herein, the terms "over", "to", "between", and "on" may refer to the relative position of one layer with respect to other layers. A layer "over" or "on" another layer or joined "to" another layer may be directly in contact with the other layer, or may have one or more intervening layers. A layer "between" layers may be directly in contact with the layers, or may have one or more intervening layers.

[0016] The terms "coupled" and "connected" and their derivatives may be used herein to describe the structural relationship between components. These terms are not intended to be synonymous with each other. On the contrary, in a specific example, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediate elements between them), and / or that two or more elements cooperate or interact with each other (e.g., such as in a causal relationship, an electrical relationship, a functional relationship, etc.).

[0017] The term "circuit" or "module" may refer to one or more passive and / or active components that are arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on".

[0018] The vertical orientation is in the z-direction, and the statements "top", "bottom", "above", and "below" refer to relative positions in the z-dimension with the usual meaning. However, the examples are not necessarily limited to the orientations or configurations shown in the figures. The term "aligned" (i.e., vertically or laterally) indicates that at least a portion of a component is aligned in the relevant direction, while "fully aligned" indicates that the entirety of the component is aligned in the relevant direction.

[0019] The terms "substantially," "close," "approximately," "near," and "about" generally mean within + / - 10% of a target value (unless otherwise indicated). The term "predominantly" means more than 50% or more than half, unless otherwise indicated in the specific context of use. For example, a composition that is primarily a first component means that more than half of the composition is the first component. The term "primarily" means the most or largest portion. For example, a composition that is primarily a first component means that the composition has more of the first component than any other component. A composition that is primarily a first and a second component means that the composition has more of the first and second components than any other components.

[0020] Unless otherwise stated, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates different instances of the similar objects being referred to and is not intended to imply that the objects so described must be in a given order temporally, spatially, sequentially, or in any other manner.

[0021] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0022] The views labeled "Section," "Profile," and "Plan" correspond to orthogonal planes within a Cartesian coordinate system. Thus, section and profile views are taken in the xz and yz planes, and plan views are taken in the xy plane. Typically, a profile view in the xz plane is a section view. The figures are labeled with axes to indicate the orientation of the figure where appropriate.

[0023] Some integrated circuits (ICs) can utilize diode-based electrostatic discharge (ESD) protection at pads (e.g., metallization structures associated with signals). A pad macro can consist of a separate instance of a metallized N+ / P-well diode (N-diode) and a metallized P+ / N-well diode (P-diode) coupled in series between a positive voltage source (e.g., VDD) and a reference voltage (e.g., VSS or ground), wherein the anode of the N-diode is at VSS, the cathode of the P-diode is at VDD, and the pad is located at the junction of the cathode of the N-diode and the anode of the P-diode. Two signal pads can be arranged as two instances of such a pad macro placed adjacent to each other. The problem with the macro approach is that each diode consists of a separate anode and cathode layout, and a separate diode strap is used to implement a human body model (HBM) type of ESD stress. Under HBM, current can be forced between two adjacent pads. The current capabilities of the diodes at the two pads must be the same. The problem is that such a pad macro that supports HBM-based ESD protection consumes a large amount of circuit area.

[0024] Another approach to ESD protection of signals involves arranging the ESD diodes in a ring geometry where the diffusion at the pad is surrounded by a diode strip diffusion ring. One problem is that the ring diode strip layout results in even more area overhead because it provides two strips, one at the top of the diode and one at the bottom of the diode, which must be placed spaced apart from other diffusions according to design rules.

[0025] Typically, the circuit area on an IC is space-constrained. For stacked ICs, metallization structures (e.g., microbumps) can be used to interconnect the ICs in the stack. Examples of microbumps include small copper bumps that are formed on the die and then connected and assembled into a package to provide a suitable electrical connection between two or more IC dies. Microbumps are typically made with a specified minimum spacing or interval between adjacent bumps on the die (e.g., a 25 μm bump size on a minimum 40 μm spacing). Other problems may occur when the bump size or spacing is scaled down.

[0026] For ICs utilized in a stacked arrangement, the area and spacing of die-to-die (D2D) input / output (IO) signals are arranged to be compatible with a specified micro-bump spacing. In the floor plan of a specific IC, micro-bumps can be organized as bump bundles for various D2D connections (e.g., power, IO signals, other signals, etc.), including one or more bundles for D2D IO signals. The vertical and horizontal dimensions of the bundle are specified constraints that must be matched with the required number of micro-bumps connected to the available pads on both sides of the IC. For some ICs, the area of ​​a single D2D IO can play an important role in the floor plan and the overall chip area. One problem is that some on-chip ESD diode layouts may cause significant area consumption of the ESD diodes in a single D2D IO. Another problem is that if the vertical dimension of the D2D-IO bundle is too large (e.g., due to excessive circuit area requirements), there may be more micro-bumps than required on both sides for IO signals (e.g., additional floating micro-bumps may not be effectively utilized). The D2D-IO bundle layout is also constrained in the horizontal direction due to the power bus routing and adjacent circuit blocks.

[0027] Some examples can overcome one or more of the aforementioned problems. Some examples can provide techniques for improving or optimizing the layout of ESD diodes for D2D IO signals. In some examples, the D2D IO signal may be exposed only to charge device model (CDM) stress (e.g., eliminating the need to provide HBM-based ESD protection between two adjacent pads). Typically, there is no HBM stress in the actual application of the D2D IO signal, and HBM stress is not utilized during D2D IO circuit verification. In addition, because the D2D IO signal is not exposed to latch-up risk, the ESD diode used in the D2D IO signal does not require a ring-type diode strip layout (e.g., a cathode of a P-diode or an anode of an N-diode) (e.g., a latch protection ring is not required in most practical D2D IO applications). Advantageously, the amount of circuit area utilized by the ESD protection circuit can be reduced (e.g., thereby supporting a finer pitch microbump with fewer floating microbumps and a smaller D2D-IO beam size).

[0028] Some examples may provide techniques for area-optimized placement of ESD diodes in a bundle of many D2D IOs (e.g., tens, hundreds, thousands, etc.). In some examples, the ESD diodes are placed in a stripe geometry where two ESDP-diodes (e.g., see Figure 2-3 The p-tap anode strips of the P-diode 1 and P-diode 2 in FIG. 1 are connected to two pads (see, for example, Figure 2-3 The two ESD P-diodes (for example, see Figure 2-3 The n-tap cathode strips of N-diode 1 and N-diode 2 in FIG. 1 are connected to two pads (see, for example, Figure 2-3 The ESD diode is shared between two ESD N-diodes (pad 1 and pad 2).

[0029] Advantageously, some examples can utilize shared anodes and cathodes to reduce layout area compared to a macro pad approach or an annular approach. For example, a macro pad approach can involve four strips, while some examples can utilize three strips (e.g., approximately 25% area savings). For example, the layout area can be reduced by up to 50% compared to annular geometry. Another advantage is that, in some examples, the area reduction of ESD in D2D IO can lead to compatibility of D2D IO with finer micro bump pitches.

[0030] Figure 1 An illustrative block diagram of an example IC device 100 including an ESD protection circuit 110 is shown, the ESD protection circuit 110 including a plurality of P-diodes (not shown) and a plurality of N-diodes (not shown) arranged in a strip geometry 120. A p-tapped anode strip 130 of the ESD protection circuit 110 is shared between a first P-diode and a second P-diode of the ESD protection circuit 110, and an n-tapped cathode strip 140 of the ESD protection circuit 110 is shared between a first N-diode and a second N-diode of the ESD protection circuit 110. In some examples, the ESD protection circuit 110 provides protection for signals from electrostatic charge stored in the IC itself (e.g., providing adequate protection for CDM). For example, the ESD protection circuit 110 provides protection for signals from discharge voltages between five volts and thirty-five volts. In some examples, the signals include D2D IO signals.

[0031] In some examples, the anode of the first P-diode and the cathode of the first N-diode can be coupled to the first pad (eg, see Figure 2-3 ), and the anode of the second P-diode and the cathode of the second N-diode can be coupled to the second pad (eg, see Figure 2-3 2), and the IC device 100 may further include a first band diffusion at the first pad for the first P-diode and the first N-diode, the first band diffusion being shared with a second band diffusion at the second pad for the second P-diode and the second N-diode. In some examples, the shared first band diffusion and the second band diffusion may be arranged in a single-finger layout. In some examples, the shared first band diffusion and the second band diffusion may be arranged in a multi-finger layout.

[0032] Figure 2A schematic diagram of an example of an ESD protection circuit 200 is shown in which various strips may be shared. The ESD protection circuit 200 includes P-diodes (P-diode 1 and P-diode 2) and N-diodes (N-diode 1 and N-diode 2). The cathode C-P1 of P-diode 1 is coupled to VDD (e.g., a positive power supply voltage), and the anode A-P1 of P-diode 1 is coupled to pad 1. The cathode C-P2 of P-diode 2 is coupled to VDD, and the anode A-P2 of P-diode 2 is coupled to pad 2. The cathode C-N1 of N-diode 1 is coupled to pad 1, and the anode A-N1 of N-diode 1 is coupled to VSS (e.g., a reference voltage or ground). The cathode C-N2 of N-diode 2 is coupled to pad 2, and the anode A-N2 of N-diode 2 is coupled to VSS.

[0033] In some examples, the ESD protection circuit 200 can be used for a bundle of many D2D IOs with an area optimized layout of the ESD diodes. For example, the layout of the ESD diodes can be arranged in a stripe geometry, where the p-tap anode stripe of N-Diode 1 and N-Diode 2 is shared between two diodes N-Diode 1 and N-Diode 2 connected to Pad 1 and Pad 2, respectively (see, for example, Figure 3 ), and wherein the n-tapped cathode strips of P-diode 1 and P-diode 2 are shared between two diodes P-diode 1 and P-diode 2 connected to pad 1 and pad 2, respectively (see Figure 3 ). In some examples, the band diffusion of the ESD diodes at pad 1 and pad 2 can be shared (see, for example, Figure 3 ), since D2D IO does not require HBM testing. The example of a shared-band diode layout style can be applied to single-finger diodes (see, for example, Figure 3 ) or multi-finger diodes (see, for example, Figure 4 ).

[0034] like Figure 2 As noted in , cathode C-P1 of P-diode 1 and cathode C-P2 of P-diode 2 may be coupled to VDD. Anode A-P1 of P-diode 1 may be coupled to pad 1. Anode A-P2 of P-diode 2 may be coupled to pad 2. Cathode C-N1 of N-diode 1 may be coupled to pad 1. Cathode C-N2 of N-diode 2 may be coupled to pad 2. Anode A-N1 of N-diode 1 and anode A-N2 of N-diode 2 may be coupled to VSS.

[0035] Figure 3 1 is a block diagram showing an example physical layout of an ESD protection circuit 300. The ESD protection circuit 300 includes a plurality of ESD diodes (not shown), which include at least a first P-diode (e.g., Figure 2P-diode 1), a first N-diode (eg, Figure 2 N-diode 1), a second P-diode (eg, Figure 2 P-diode 2), and a second N-diode (eg, Figure 2 For example, the first P-diode and the second P-diode and the first N-diode and the second N-diode are arranged in a strip geometry. The ESD diodes can be fabricated on one or more internal layers of the IC using any suitable technology. The ESD protection circuit also includes: a first pad (e.g., Figure 2 The first metallization structure 310 for the pad 1 in the embodiment of the present invention has a connection portion to the anode of the first P-diode and the cathode of the first N-diode below the first metallization structure 310 on another layer (e.g., an inner layer); a second metallization structure 320 for the second pad on the first layer, the second metallization structure 320 having a connection portion to the anode of the second P-diode and the cathode of the second N-diode on another layer below the second metallization structure 320; a third metallization structure 330 for a positive voltage source on the first layer, the third metallization structure 330 being between the first metallization structure 310 and the second metallization structure 320 and adjacent to the first metallization structure 310 a first metallization structure 310 and a second metallization structure 320, and having connections to respective cathodes of the first P-diode and the second P-diode on another layer below the third metallization structure 330; and a fourth metallization structure 340 for a reference voltage source on the first layer, the fourth metallization structure 340 being aligned with the third metallization structure 330 (e.g., in the same stripe) and being between and adjacent to the first metallization structure 310 and the second metallization structure 320, and having connections to respective anodes of the first N-diode and the second N-diode on another layer below the fourth metallization structure 340.

[0036] In some examples, the first layer can correspond to an outer layer of the IC device, and / or the first P-diode and the second P-diode and the first N-diode and the second N-diode can provide ESD protection for the D2D IO signal. In some examples, the ESD protection circuit 300 can also include a multi-finger diode arrangement structure, which includes: a fifth metallization structure for a first pad on the first layer, the fifth metallization structure is adjacent to the second metallization structure 320 and is on the opposite side of the second metallization structure 320 relative to the third metallization structure 330; a sixth metallization structure for a second pad on the first layer; and a seventh metallization structure for a positive voltage source on the first layer, the seventh metallization structure is between the fifth metallization structure and the sixth metallization structure and is adjacent to the fifth metallization structure and the sixth metallization structure (for example, see Figure 4 ).

[0037] Figure 4 An example layout of an ESD protection circuit 400 with a pad 1 and pad 2 bundle for a multi-finger ESD diode is shown. The layout can support a shared n-diffusion strip for P-diode 1 and P-diode 2. A first metallization structure 410 is used for pad 1, a second metallization structure 420 is used for pad 2, and a third metallization structure 430 is used for VDD. A fourth metallization structure for VSS is not shown. The multi-finger layout also includes: a fifth metallization structure 440 for pad 1, which is adjacent to the second metallization structure 420 and on the opposite side of the second metallization structure 420 relative to the third metallization structure 430; a sixth metallization structure 450 for pad 2; and a seventh metallization structure 460 for VDD, which is between and adjacent to the fifth metallization structure 440 and the sixth metallization structure 450.

[0038] Figure 5 is an illustrative view of a portion of an IC device 500 having an ESD protection circuit with shared straps as described herein. Figure 6 is an enlarged view of region A of IC device 500. In an IC device using a 35 μm micro-bump pitch (e.g., or less), thousands of D2D IOs can be placed. As packaging technology continues to shrink, the micro-bump pitch can be further reduced and hundreds of thousands of D2D IOs can be provided on a single die. Figure 5, circles represent microbumps and squares represent metallization areas for power connections (e.g., VDD, VSS, etc.). The dashed box B represents a D2D IO bundle in which the IOs are stacked vertically. As the vertical dimension of the D2D IO bundle increases, the area of ​​the microbumps increases (e.g., the "Y" dimension of the ESD protection circuit increases as the vertical dimension of the D2D bundle increases). The horizontal dimension of the ESD protection can be fixed based on the spacing of the microbumps or the spacing between the metallization structures for power connections (e.g., a fixed "X" dimension). Preferably, the ESD protection circuit does not increase the area of ​​the D2D IO bundle by more than the number of required D2D IO connections (e.g., without increasing the number of floating microbumps).

[0039] Some examples provide techniques for area-optimized ESD protection of D2D IO with receiver / transmitter (RX / TX) implemented within sensitive IC devices. D2D IO signals are exposed to charge device model (CDM) type stress during assembly. CDM stress is evaluated as a discharge voltage of 5-35V. The CDM voltage depends on the quality of the equipment in the assembly line and the electrostatic protection level of the air ionizer. The CDM voltage can correspond to a CDM discharge current of 40mA-300mA, depending on the voltage level and die size.

[0040] Some examples of IC device 500 may utilize an area efficient layout of ESD diodes, as described herein, for CDM protection in D2D IO. The area efficient layout style may be applied to, but is not limited to, diodes connected to at least two pads (e.g., such as pad 1 and pad 2 as mentioned elsewhere herein). The ESD diodes in the D2D IO may be arranged in a strip geometry because there is no latch-up requirement. The strip diffusion of the diodes at pad 1 and pad 2 may be shared because HBM testing is not required for the D2D IO. The shared strip diode layout style may be applied to single finger diodes, or multi-finger diodes (e.g., Figure 4 shows the layout of a two-finger stripe diode).

[0041] Figure 7 A block diagram of an example of a system 700 including two IC devices 710, 720 having a D2D IO signal therebetween is shown, although other examples of the system 700 may include more than two IC devices. One or more of the IC devices (e.g., at least the IC device 710) include respective shared-stripe ESD (SSESD) protection circuits 730 for two or more of the D2D IO signals as described herein.

[0042] In some examples, the ESD protection circuit 730 can include a plurality of P-diodes and a plurality of N-diodes arranged in a stripe geometry, with a p-tap anode stripe of the SS ESD protection circuit 730 shared between a first P-diode and a second P-diode of the SS ESD protection circuit 730, and an n-tap cathode stripe of the SS ESD protection circuit 730 shared between a first N-diode and a second N-diode of the SS ESD protection circuit 730. In some examples, the SS ESD protection circuit 730 can provide protection for signals from electrostatic charge (e.g., CDM) stored in the IC device 710 itself. For example, the SS ESD protection circuit 730 can provide protection for signals from discharge voltages between five volts and thirty-five volts.

[0043] In some examples, an anode of the first P-diode and a cathode of the first N-diode are coupled to the first pad, and an anode of the second P-diode and a cathode of the second N-diode are coupled to the second pad, and the SS ESD protection circuit may further include a first band diffusion of the first P-diode and the first N-diode at the first pad, the first band diffusion being shared with a second band diffusion of the second P-diode and the second N-diode at the second pad. In some examples, the shared first band diffusion and the second band diffusion are arranged in a single-finger layout. In some examples, the shared first band diffusion and the second band diffusion are arranged in a multi-finger layout.

[0044] In some examples, the physical layout of the SS ESD protection circuit may include: a first metallization structure for a first pad on a first layer, the first metallization structure having connections to an anode of a first P-diode and a cathode of a first N-diode on another layer below the first metallization structure; a second metallization structure for a second pad on the first layer, the second metallization structure having connections to an anode of a second P-diode and a cathode of a second N-diode on another layer below the second metallization structure; a third metallization structure for a positive voltage source on the first layer, the third metallization structure being between and adjacent to the first and second metallization structures, and having connections to respective cathodes of the first and second P-diodes on another layer below the third metallization structure; and a fourth metallization structure for a reference voltage source on the first layer, the fourth metallization structure being aligned with the third metallization structure, and being between and adjacent to the first and second metallization structures, and having connections to respective anodes of the first and second N-diodes on another layer below the fourth metallization structure. For example, the first layer corresponds to an outer layer of one of the one or more IC devices. In some examples, the physical layout of the SS ESD protection circuit may also include a multi-finger diode arrangement structure, the multi-finger diode arrangement structure including: a fifth metallization structure for a first pad on the first layer, the fifth metallization structure being adjacent to the second metallization structure and on an opposite side of the second metallization structure relative to the third metallization structure; a sixth metallization structure for a second pad on the first layer; and a seventh metallization structure for a positive voltage source on the first layer, the seventh metallization structure being between and adjacent to the fifth and sixth metallization structures.

[0045] Figure 8 A diagram of an example data server machine 1006 employing an IC device 1050 having an SS ESD protection circuit for D2D IO as described herein is shown according to some examples. The server machine 1006 can be any commercial server (e.g., including any number of high performance computing platforms arranged in a rack and networked together for electronic data processing) that includes one or more devices 1050 having one or more SS ESD protection circuits for D2D IO in the illustrative example.

[0046] As also shown, server machine 1006 includes a battery and / or power supply 1015 to provide power to device 1050, and in some examples provide power delivery functions, such as power regulation. Device 1050 can be deployed as part of package-level integrated system 1010. Integrated system 1010 is further shown in expanded view 1020. In an exemplary example, device 1050 (labeled as "memory / processor") includes at least one memory chip (e.g., RAM) and / or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or a graphics processor, etc.) having the characteristics discussed herein. In an example, device 1050 is a microprocessor including a cache memory. As shown, device 1050 can be a multi-chip module using one or more IC devices with one or more SS ESD protection circuits for D2D IO, as discussed herein. The device 1050 may be further coupled (e.g., communicatively coupled) to a board, interposer, or substrate 1060 along with one or more of a power management IC (PMIC) 1030, an RF (wireless) IC (RFIC) 1025 (including a broadband RF (wireless) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband and analog front end module further including a power amplifier on a transmit path and a low noise amplifier on a receive path)), and a controller 1035 thereof. In some examples, the RFIC 1025, the PMIC 1030, the controller 1035, and the device 1050 include an IC device with SS ESD protection circuitry for D2D IOs on a substrate 1060 in a multi-chip module.

[0047] Fig. 9 is a block diagram of an example computing device 1100 according to some examples. For example, one or more components of the computing device 1100 may include any of the devices or structures discussed herein. Fig. 9 1100, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some examples, some or all of the components included in computing device 1100 may be attached to one or more printed circuit boards (e.g., motherboards). In some examples, various of these components may be fabricated onto a single system-on-chip (SoC) die. Additionally, in various examples, computing device 1100 may not include Fig. 9, but the computing device 1100 may include an interface circuit system for coupling to one or more components. For example, the computing device 1100 may not include the display device 1103, but may include a display device interface circuit system (e.g., a connector and a driver circuit system) to which the display device 1103 can be coupled. In another set of examples, the computing device 1100 may not include an audio output device 1104, other output devices 1105, a global positioning system (GPS) device 1109, an audio input device 1110, or other input devices 1111, but may include an audio output device interface circuit system, other output device interface circuit system, GPS device interface circuit system, audio input device interface circuit system, and audio input device interface circuit system to which the audio output device 1104, other output devices 1105, GPS device 1109, audio input device 1110, or other input devices 1111 can be coupled.

[0048] The computing device 1100 may include a processing device 1101 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" indicates a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1101 may include a memory 1121, a communication device 1122, a cooling device 1123, a battery / power regulation device 1124, a logic 1325, an interconnect 1126 (i.e., optionally including a redistribution layer (RDL), or a metal-insulator-metal (MIM) device), a thermal regulation device 1127, and a hardware security device 1128.

[0049] Processing device 1101 may include one or more digital signal processors (DSPs), application specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute encryption algorithms in hardware), server processors, or any other suitable processing devices.

[0050] Computing device 1100 may include memory 1102, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some examples, memory 1102 includes memory that shares a die with processing device 1101. The memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0051] The computing device 1100 may include a thermal conditioning / cooling device 1106. The thermal conditioning / cooling device 1106 may maintain the processing device 1101 (and / or other components of the computing device 1100) at a predetermined low temperature during operation. The predetermined low temperature may be any temperature discussed herein.

[0052] In some examples, computing device 1100 may include a communication chip 1107 (e.g., one or more communication chips). For example, communication chip 1107 may be configured to manage wireless communications for transmitting data to and from computing device 1100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some examples they may not.

[0053] The communication chip 1107 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates and / or modifications (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 1107 can operate according to the Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE network. The communication chip 1107 can operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1107 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. In other examples, the communication chip 1107 can operate according to other wireless protocols. The computing device 1100 may include an antenna 1113 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0054] In some examples, the communication chip 1107 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1107 can include multiple communication chips. For example, the first communication chip 1107 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 1107 can be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, the first communication chip 1107 can be dedicated to wireless communications, and the second communication chip 1107 can be dedicated to wired communications.

[0055] Computing device 1100 may include battery / power circuitry 1108. Battery / power circuitry 1108 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 1100 to an energy source separate from computing device 1100 (e.g., AC line power).

[0056] Computing device 1100 may include a display device 1103 (or corresponding interface circuitry, as discussed above). Display device 1103 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0057] Computing device 1100 may include audio output device 1104 (or corresponding interface circuitry, as discussed above). Audio output device 1104 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0058] Computing device 1100 may include audio input device 1110 (or corresponding interface circuitry, as discussed above). Audio input device 1110 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0059] Computing device 1100 may include GPS device 1109 (or corresponding interface circuitry, as discussed above). GPS device 1109 may communicate with a satellite-based system and may receive the location of computing device 1100, as is known in the art.

[0060] Computing device 1100 may include other output devices 1105 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1105 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0061] The computing device 1100 may include other input devices 1111 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1111 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0062] The computing device 1100 may include a security interface device 1112. The security interface device 1112 may include any device that provides security measures for the computing device 1100, such as intrusion detection, biometric authentication, security encoding or decoding, access list management, malware detection, or spyware detection.

[0063] Computing device 1100 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular telephone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0064] The subject matter of this description is not necessarily limited to Figure 1-9 The present subject matter can be applied to other transistor applications, as well as any suitable manufacturing application, as will be appreciated by those skilled in the art.

[0065] The following examples refer to further examples, and details in the examples may be used anywhere in one or more examples.

[0066] Example 1 includes an integrated circuit (IC) device, including an electrostatic discharge (ESD) protection circuit, wherein the electrostatic discharge (ESD) protection circuit includes a plurality of P+ / N-well diodes (P-diodes) and a plurality of N+ / P-well (N-diodes) arranged in a strip geometry, a p-tap anode strip of the ESD protection circuit shared between a first P-diode and a second P-diode of the ESD protection circuit, and an n-tap cathode strip of the ESD protection circuit shared between a first N-diode and a second N-diode of the ESD protection circuit.

[0067] Example 2 includes the IC device of Example 1, wherein the ESD protection circuit provides protection for signals from electrostatic charge stored in the IC itself.

[0068] Example 3 includes the IC device of Example 2, wherein the ESD protection circuit provides protection for signals from discharge voltages between five volts and thirty-five volts.

[0069] Example 4 includes the IC device of any of Examples 2-3, wherein the signal comprises a die-to-die input / output signal.

[0070] Example 5 includes the IC device of any one of Examples 1 to 4, wherein the anode of the first P-diode and the cathode of the first N-diode are coupled to a first pad, and wherein the anode of the second P-diode and the cathode of the second N-diode are coupled to a second pad, the IC device also including a first band diffusion of the first P-diode and the first N-diode at the first pad, the first band diffusion being shared with a second band diffusion of the second P-diode and the second N-diode at the second pad.

[0071] Example 6 includes the IC device of Example 5, wherein the shared first strap diffusion and the second strap diffusion are arranged in a single-finger layout.

[0072] Example 7 includes the IC device of Example 5, wherein the shared first strap diffusion and the second strap diffusion are arranged in a multi-finger layout.

[0073] Example 8 includes a device including: a first P+ / N-well diode (P-diode), a first N+ / P-well diode (N-diode), a second P-diode, and a second N-diode; a first metallization structure for a first pad on a first layer, the first metallization structure having connections to an anode of the first P-diode and a cathode of the first N-diode on another layer below the first metallization structure; a second metallization structure for a second pad on the first layer, the second metallization structure having connections to an anode of the second P-diode and a cathode of the second N-diode on another layer below the second metallization structure; a third metallization structure for a positive voltage source on the first layer, The third metallization structure is between and adjacent to the first and second metallization structures and has connections to the respective cathodes of the first and second P-diodes on another layer below the third metallization structure; and a fourth metallization structure for a reference voltage source on the first layer, the fourth metallization structure being aligned with the third metallization structure and between and adjacent to the first and second metallization structures and having connections to the respective anodes of the first and second N-diodes on another layer below the fourth metallization structure.

[0074] Example 9 includes the apparatus of Example 8, wherein the first P-diode and the second P-diode and the first N-diode and the second N-diode are arranged in a stripe geometry.

[0075] Example 10 includes the apparatus of any of Examples 8 to 9, wherein the first layer corresponds to an outer layer of an integrated circuit (IC) device.

[0076] Example 11 includes the apparatus of any of Examples 8 to 10, wherein the first P-diode and the second P-diode and the first N-diode and the second N-diode are used to provide electrostatic discharge protection for die-to-die input / output signals.

[0077] Example 12 includes the device of any one of Examples 8 to 11, further including a multi-finger diode arrangement structure, the multi-finger diode arrangement structure including: a fifth metallization structure for a first pad on a first layer, the fifth metallization structure being adjacent to the second metallization structure and on an opposite side of the second metallization structure relative to the third metallization structure; a sixth metallization structure for a second pad on the first layer; and a seventh metallization structure for a positive voltage source on the first layer, the seventh metallization structure being between and adjacent to the fifth metallization structure and the sixth metallization structure.

[0078] Example 13 includes a system comprising two or more integrated circuit (IC) devices having a die-to-die (D2D) input / output (IO) signal therebetween, one or more of the IC devices including corresponding electrostatic discharge (ESD) protection circuits for two or more of the D2D IO signals, the ESD protection circuits comprising a plurality of P+ / N-well diodes (P-diodes) and a plurality of N+ / P-wells (N-diodes) arranged in a strip geometry, a p-tapped anode strip of the ESD protection circuit shared between a first P-diode and a second P-diode of the ESD protection circuit, and an n-tapped cathode strip of the ESD protection circuit shared between a first N-diode and a second N-diode of the ESD protection circuit.

[0079] Example 14 includes the system of Example 13, wherein the ESD protection circuit provides protection for the signal from electrostatic charge stored in the IC itself.

[0080] Example 15 includes the system of Example 14, wherein the ESD protection circuit provides protection for signals from discharge voltages between five volts and thirty-five volts.

[0081] Example 16 includes the system of any of Examples 14 to 15, wherein the signal comprises a die-to-die input / output signal.

[0082] Example 17 includes the system of any of Examples 13 to 16, wherein the anode of the first P-diode and the cathode of the first N-diode are coupled to a first pad, and wherein the anode of the second P-diode and the cathode of the second N-diode are coupled to a second pad, the IC device further comprising a first band diffusion of the first P-diode and the first N-diode at the first pad, the first band diffusion being shared with a second band diffusion of the second P-diode and the second N-diode at the second pad.

[0083] Example 18 includes the system of Example 17, wherein the shared first band diffusion and the second band diffusion are arranged in a single-finger layout.

[0084] Example 19 includes the system of Example 17, wherein the shared first band diffusion and the second band diffusion are arranged in a multi-finger layout.

[0085] Example 20 includes the system of any of Examples 13 to 19, wherein the physical layout of the ESD protection circuit includes: a first metallization structure for a first pad on a first layer, the first metallization structure having connections to an anode of a first P-diode and a cathode of a first N-diode on another layer below the first metallization structure; a second metallization structure for a second pad on the first layer, the second metallization structure having connections to an anode of a second P-diode and a cathode of a second N-diode on another layer below the second metallization structure; a third metallization structure for a positive voltage source on the first layer, the third metallization structure being connected between the first metallization structure and the cathode of the second P-diode; and a fourth metallization structure for a reference voltage source on the first layer, the fourth metallization structure being aligned with the third metallization structure and being between and adjacent to the first and second metallization structures, and having connections to respective cathodes of the first and second P-diodes on another layer below the third metallization structure; and a fourth metallization structure for a reference voltage source on the first layer, the fourth metallization structure being aligned with the third metallization structure and being between and adjacent to the first and second metallization structures, and having connections to respective anodes of the first and second N-diodes on another layer below the fourth metallization structure.

[0086] Example 21 includes the system of Example 20, wherein the first layer corresponds to an outer layer of an IC device of the one or more IC devices.

[0087] Example 22 includes the system of any of Examples 20 to 21, further including a multi-finger diode arrangement structure, the multi-finger diode arrangement structure including: a fifth metallization structure for a first pad on a first layer, the fifth metallization structure being adjacent to the second metallization structure and on an opposite side of the second metallization structure relative to the third metallization structure; a sixth metallization structure for a second pad on the first layer; and a seventh metallization structure for a positive voltage source on the first layer, the seventh metallization structure being between and adjacent to the fifth metallization structure and the sixth metallization structure.

[0088] Example 23 includes a method, comprising forming a first P+ / N-well diode (P-diode), a first N+ / P-well diode (N-diode), a second P-diode, and a second N-diode on a substrate; forming a first metallization structure for a first pad on a first layer of the substrate, the first metallization structure having connections to an anode of the first P-diode and a cathode of the first N-diode on another layer of the substrate below the first metallization structure; forming a second metallization structure for a second pad on the first layer of the substrate, the second metallization structure having connections to an anode of the second P-diode and a cathode of the second N-diode on another layer of the substrate below the second metallization structure; forming a first ... first pad on a first layer of the substrate, the first metallization structure having connections to an anode of the second P-diode and a cathode of the second N-diode on another layer of the substrate below the second metallization structure; forming a second metallization structure for a second pad on the first layer of the substrate a third metallization structure for a positive voltage source, the third metallization structure being between and immediately adjacent to the first and second metallization structures and having connections to respective cathodes of the first and second P-diodes on another layer of the substrate below the third metallization structure; and a fourth metallization structure forming a reference voltage source on the first layer of the substrate, the fourth metallization structure being aligned with the third metallization structure and being between and immediately adjacent to the first and second metallization structures and having connections to respective anodes of the first and second N-diodes on another layer below the fourth metallization structure.

[0089] Example 24 includes the method of Example 23, wherein the first P-diode and the second P-diode and the first N-diode and the second N-diode are arranged in a stripe geometry.

[0090] Example 25 includes the method of any of Examples 23 to 24, wherein the first layer of the substrate corresponds to an outer layer of an integrated circuit (IC) device.

[0091] Example 26 includes the method of any of Examples 23 to 25, wherein the first P-diode and the second P-diode and the first N-diode and the second N-diode are used to provide electrostatic discharge protection for die-to-die input / output signals.

[0092] Example 27 includes the method of any one of Examples 23 to 26, further including forming a multi-finger diode arrangement structure, wherein the forming of the multi-finger diode arrangement structure includes: forming a fifth metallization structure for the first pad on the first layer of the substrate, the fifth metallization structure being adjacent to the second metallization structure and on the opposite side of the second metallization structure relative to the third metallization structure; forming a sixth metallization structure for the second pad on the first layer of the substrate; and forming a seventh metallization structure for a positive voltage source on the first layer of the substrate, the seventh metallization structure being between the fifth metallization structure and the sixth metallization structure and being adjacent to the fifth metallization structure and the sixth metallization structure.

[0093] Example 28 includes an apparatus comprising: a module for forming a first P+ / N-well diode (P-diode), a first N+ / P-well diode (N-diode), a second P-diode, and a second N-diode on a substrate; a module for forming a first metallization structure for a first pad on a first layer of the substrate, the first metallization structure having a connection to an anode of the first P-diode and a cathode of the first N-diode on another layer of the substrate below the first metallization structure; a module for forming a second metallization structure for a second pad on the first layer of the substrate, the second metallization structure having a connection to an anode of the second P-diode and a cathode of the second N-diode on another layer of the substrate below the second metallization structure; a module for forming the a module for forming a third metallization structure for a positive voltage source on the first layer of the substrate, the third metallization structure being between and immediately adjacent to the first and second metallization structures and having connections to respective cathodes of the first and second P-diodes below the third metallization structure on another layer of the substrate; and a module for forming a fourth metallization structure for a reference voltage source on the first layer of the substrate, the fourth metallization structure being aligned with the third metallization structure and being between and immediately adjacent to the first and second metallization structures and having connections to respective anodes of the first and second N-diodes below the fourth metallization structure on another layer.

[0094] Example 29 includes the apparatus of Example 28, wherein the first P-diode and the second P-diode and the first N-diode and the second N-diode are arranged in a stripe geometry.

[0095] Example 30 includes the apparatus of any of Examples 28 to 29, wherein the first layer of the substrate corresponds to an outer layer of an integrated circuit (IC) device.

[0096] Example 31 includes the apparatus of any of Examples 28 to 30, wherein the first P-diode and the second P-diode and the first N-diode and the second N-diode are used to provide electrostatic discharge protection for die-to-die input / output signals.

[0097] Example 32 includes the apparatus of any one of Examples 28 to 31, further comprising a module for forming a multi-finger diode arrangement structure, the module comprising: a module for forming a fifth metallization structure for the first pad on the first layer of the substrate, the fifth metallization structure being adjacent to the second metallization structure and on the opposite side of the second metallization structure relative to the third metallization structure; a module for forming a sixth metallization structure for the second pad on the first layer of the substrate; and a module for forming a seventh metallization structure for a positive voltage source on the first layer of the substrate, the seventh metallization structure being between the fifth metallization structure and the sixth metallization structure and being adjacent to the fifth metallization structure and the sixth metallization structure.

[0098] The present disclosure may be practiced through modification and alteration, and the scope of the appended claims is not limited to the examples described so far. For example, the above examples may include a specific combination of features. However, the above examples are not restrictive in this regard, and in various embodiments, the above examples may include taking only a subset of these features, taking a different order of these features, taking a different combination of these features, and / or taking additional features in addition to those features explicitly listed. Therefore, the scope of the patent right should be determined by reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. An integrated circuit (IC) device, comprising: an electrostatic discharge (ESD) protection circuit comprising a plurality of P+ / N-well diodes (P-diodes) and a plurality of N+ / P-wells (N-diodes) arranged in a stripe geometry; a p-tap anode strip of the ESD protection circuit, the p-tap anode strip shared between a first P-diode and a second P-diode of the ESD protection circuit; as well as An n-tap cathode stripe of the ESD protection circuit, the n-tap cathode stripe being shared between a first N-diode and a second N-diode of the ESD protection circuit.

2. The IC device according to claim 1, wherein: The ESD protection circuit provides protection for signals from static charges stored in the IC itself.

3. The IC device according to claim 2, wherein: The ESD protection circuit provides protection for the signal from discharge voltages between five volts and thirty-five volts.

4. The IC device according to claim 2, wherein: The signals include die-to-die input / output signals.

5. The IC device according to any one of claims 1 to 4, wherein: An anode of the first P-diode and a cathode of the first N-diode are coupled to a first pad, and wherein an anode of the second P-diode and a cathode of the second N-diode are coupled to a second pad, the IC device further comprising: The first P-diode and the first N-diode have a first strap diffusion at the first pad, the first strap diffusion being shared with a second strap diffusion of the second P-diode and the second N-diode at the second pad.

6. The IC device according to claim 5, wherein: The shared first band diffusion and the second band diffusion are arranged in a single-finger layout.

7. The IC device according to claim 5, wherein: The shared first band diffusion and the second band diffusion are arranged in a multi-finger layout.

8. An apparatus comprising: a first P+ / N-well diode (P-diode), a first N+ / P-well diode (N-diode), a second P-diode, and a second N-diode; a first metallization structure for a first pad on a first layer, the first metallization structure having connections to an anode of the first P-diode and a cathode of the first N-diode on another layer below the first metallization structure; a second metallization structure for a second pad on the first layer, the second metallization structure having connections to an anode of the second P-diode and a cathode of the second N-diode on another layer below the second metallization structure; a third metallization structure for a positive voltage supply on the first layer, the third metallization structure being between and immediately adjacent to the first and second metallization structures and having connections to respective cathodes of the first and second P-diodes on another layer below the third metallization structure; as well as a fourth metallization structure for a reference voltage source on the first layer, the fourth metallization structure aligned with the third metallization structure and between and immediately adjacent to the first and second metallization structures and having connections to respective anodes of the first and second N-diodes on another layer below the fourth metallization structure.

9. The device according to claim 8, wherein: The first and second P-diodes and the first and second N-diodes are arranged in a stripe geometry.

10. The device according to claim 8, wherein: The first layer corresponds to an outer layer of an integrated circuit (IC) device.

11. The device according to any one of claims 8 to 10, wherein: The first and second P-diodes and the first and second N-diodes are used to provide electrostatic discharge protection for die-to-die input / output signals.

12. The apparatus according to any one of claims 8 to 10, further comprising a multi-finger diode arrangement, the multi-finger diode arrangement comprising: a fifth metallization structure for the first pad on the first layer, the fifth metallization structure being immediately adjacent to the second metallization structure and on an opposite side of the second metallization structure relative to the third metallization structure; a sixth metallization structure for the second pad on the first layer; as well as A seventh metallization structure for the positive voltage source on the first layer, the seventh metallization structure being between and adjacent to the fifth and sixth metallization structures.

13. A system comprising two or more integrated circuit (IC) devices having die-to-die (D2D) input / output (IO) signals therebetween, one or more of the IC devices comprising respective electrostatic discharge (ESD) protection circuits for two or more of the D2D IO signals, the ESD protection circuits comprising: a plurality of P+ / N-well diodes (P-diodes) and a plurality of N+ / P-well (N-diodes) arranged in a stripe geometry; a p-tap anode strip of the ESD protection circuit, the p-tap anode strip shared between a first P-diode and a second P-diode of the ESD protection circuit; as well as An n-tap cathode stripe of the ESD protection circuit, the n-tap cathode stripe being shared between a first N-diode and a second N-diode of the ESD protection circuit.

14. The system according to claim 13, wherein: The ESD protection circuit provides protection for signals from static charges stored in the IC itself.

15. The system of claim 14, wherein: The ESD protection circuit provides protection for the signal from discharge voltages between five volts and thirty-five volts.

16. The system of claim 14, wherein: The signals include die-to-die input / output signals.

17. A system according to any one of claims 13 to 16, wherein: An anode of the first P-diode and a cathode of the first N-diode are coupled to a first pad, and wherein an anode of the second P-diode and a cathode of the second N-diode are coupled to a second pad, the IC device further comprising: The first P-diode and the first N-diode have a first strap diffusion at the first pad, the first strap diffusion being shared with a second strap diffusion of the second P-diode and the second N-diode at the second pad.

18. The system of claim 17, wherein: The shared first band diffusion and the second band diffusion are arranged in a single-finger layout.

19. The system of claim 17, wherein: The shared first band diffusion and the second band diffusion are arranged in a multi-finger layout.

20. The system according to any one of claims 13 to 16, wherein: The physical layout of the ESD protection circuit includes: a first metallization structure for a first pad on a first layer, the first metallization structure having connections to an anode of a first P-diode and a cathode of a first N-diode on another layer below the first metallization structure; a second metallization structure for a second pad on the first layer, the second metallization structure having connections to an anode of a second P-diode and a cathode of a second N-diode on another layer below the second metallization structure; a third metallization structure for a positive voltage supply on the first layer, the third metallization structure being between and immediately adjacent to the first and second metallization structures and having connections to respective cathodes of the first and second P-diodes on another layer below the third metallization structure; and a fourth metallization structure for a reference voltage source on the first layer, the fourth metallization structure aligned with the third metallization structure and between and immediately adjacent to the first and second metallization structures and having connections to respective anodes of the first and second N-diodes on another layer below the fourth metallization structure.

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