Universal serial bus voltage discharge

Abstract

Techniques for discharging a universal serial bus voltage are provided. It is determined that the universal serial bus voltage has exceeded a threshold. Accordingly, a start-up discharge operation is triggered to discharge the universal serial bus voltage. The discharge operation includes applying an incrementally increasing voltage reference value to the amplifier according to a periodic interval until a discharge trigger point is reached. The amplifier outputs a voltage signal to a gate driver that controls a gate of a transistor that provides a discharge path for universal serial bus voltage discharge. In response to reaching the discharge trigger point, the incremental increase in the voltage reference value applied to the amplifier is stopped.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit (IC) that controls universal serial bus (USB) power delivery to an electronic device. Background Art

[0002] According to the Universal Serial Bus (USB) Power Delivery (USB-PD) protocol, the power application will meet certain timing specifications regarding the movement of the Universal Serial Bus voltage (VBUS). For example, during a Programmable Power Supply (PPS) transition in about 275 milliseconds (ms), VBUS will change from a maximum voltage of about 21.5 volts (V) (or 28V for an extended power range (EPR)) to a minimum voltage of about 3.3V. Therefore, the voltage converter must discharge the VBUS output capacitor so as not to exceed a certain VBUS because the USB sink voltage requirement is reduced. For a 1 millifarad (mF) VBUS capacitor, a discharge of 24.5V in 275ms corresponds to an average current of about 90 milliamperes (mA). However, an average current of 90mA will result in a peak power dissipation of 2.5 watts (W) at 28V.

[0003] Typically, on-die VBUS discharge is resistive and uses higher current at higher VBUS voltages, resulting in even higher power dissipation. For higher thermal resistance packages, such as small outline integrated circuits (SOICs), thin shrink small outline packages (TSSOPs), which may be used instead of quad flat no-leads (QFNs) due to assembly cost, higher thermal resistance (or θ-Ja) of 50-90°C / W results in a sudden increase in die temperature, resulting in reliability risks due to temperatures reaching above 150°C (e.g., 225°C or higher). As a result, in some USB Type-C interfaces, external power transistors are used and controlled by the USB controller using general purpose input / output (GPIO) signals, which increases the die area and cost of the USB device in order to handle such high temperature increases to protect the die where the voltage converter controller(s) are located. Summary of the invention

[0004] This summary is provided to introduce some concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0005] In an embodiment of the technology presented herein, a method for discharging a universal serial bus voltage is provided. The method includes determining that the universal serial bus voltage exceeds a threshold value. In response to determining that the universal serial bus voltage exceeds the threshold value, a discharge operation is triggered by a universal serial bus power delivery (USB-PD) controller to discharge the universal serial bus voltage. The USB-PD controller performs the discharge operation by applying an incrementally increasing voltage reference value to an amplifier according to periodic intervals until a discharge trigger point is reached. The amplifier outputs a voltage signal to a gate driver, which controls the gate of a transistor to provide a discharge path for discharging the universal serial bus voltage. In response to reaching the discharge trigger point, the incremental increase of the voltage reference value applied to the amplifier is stopped.

[0006] In an embodiment of the technology presented herein, a device is provided. The device includes a module for triggering the initiation of a discharge operation to discharge the universal serial bus voltage in response to determining that the universal serial bus voltage exceeds a threshold. The device includes a module for performing the discharge operation by applying an incrementally increasing voltage reference value to an amplifier according to periodic intervals until a discharge trigger point is reached, wherein the amplifier outputs a voltage signal to a gate driver, and the gate driver controls the gate of a transistor to provide a discharge path for the discharge of the universal serial bus voltage. The device includes a module for stopping the incremental increase of the voltage reference value applied to the amplifier in response to reaching the discharge trigger point.

[0007] In an embodiment of the technology presented herein, a device is provided. The device includes a transistor configuration configured to provide a discharge path for a universal serial bus voltage based on a voltage applied to a gate of the transistor. The device includes a universal serial bus power delivery (USB-PD) controller, which is instantiated as an integrated circuit configured to provide universal serial bus power delivery control. The USB-PD controller includes a gate driver configured to control the voltage applied to the gate of the transistor to control the transistor configuration to provide a discharge path for the discharge of the universal serial bus voltage. The integrated circuit includes an amplifier configured to output a voltage signal to the gate driver to control the gate driver. The voltage signal is based on an incrementally increased voltage value applied to the amplifier. The incrementally increased voltage value increases according to a periodic interval until a discharge trigger point is detected.

[0008] In an embodiment of the technology presented herein, a device is provided. The device includes a transistor configuration configured to provide a discharge path for a universal serial bus voltage based on a voltage applied to the gate of the transistor. The device includes a universal serial bus power delivery (USB-PD) controller, which is instantiated as an integrated circuit configured to provide universal serial bus power delivery control. The USB-PD controller includes a gate driver, which is configured to control the voltage applied to the gate of the transistor to control the transistor configuration to provide a discharge path for the discharge of the universal serial bus voltage. The device includes an amplifier, which is configured to output a voltage signal to the gate driver to control the gate driver, wherein the voltage signal is based on an incrementally increasing voltage value applied to the amplifier, wherein the incrementally increasing voltage value increases according to a periodic interval until a discharge trigger point is detected. The device includes a pull-down device, which is configured to pull down the voltage applied to the gate of the transistor in response to the drain voltage of the transistor crossing the universal serial bus voltage to close the discharge path.

[0009] To achieve the aforementioned and related purposes, the following description and accompanying drawings set forth certain illustrative aspects and embodiments. These only indicate some of the various ways in which one or more aspects may be employed. When considered in conjunction with the accompanying drawings, other aspects, advantages, and novel features of the present disclosure will become apparent from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a component block diagram illustrating a device that implements discharge of a universal serial bus voltage in accordance with at least some techniques presented herein.

[0011] Figure 2 is an illustration of an example method for discharging a universal serial bus voltage in accordance with at least some techniques presented herein.

[0012] Figure 3A is a component block diagram illustrating a device that implements discharge of a universal serial bus voltage in accordance with at least some techniques presented herein.

[0013] Figure 3B is a component block diagram illustrating a device that implements discharge of a universal serial bus voltage in accordance with at least some techniques presented herein.

[0014] Figure 4 is an illustration of an example timing diagram according to some embodiments.

[0015] Figure 5 An exemplary embodiment of a system for a USB device in accordance with some embodiments is shown. DETAILED DESCRIPTION

[0016] The claimed subject matter is now described with reference to the accompanying drawings, wherein the same reference numerals are generally used to refer to the same elements throughout. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it is apparent that the claimed subject matter can be practiced without these specific details. In other examples, well-known structures and devices are shown in block diagram form to facilitate description of the claimed subject matter.

[0017] A system and method for discharging a universal serial bus voltage is provided, which can be implemented for a USB-PD controller that can be configured to operate in a variety of electronic devices. Embodiments of such electronic devices include, but are not limited to, personal computers (e.g., laptop computers, notebook computers, etc.), mobile computing devices (e.g., tablet computers, tablet computers, e-reader devices, etc.), mobile communication devices (e.g., smart phones, cellular phones, personal digital assistants, messaging devices, pocket PCs, etc.), connection and charging devices (e.g., cables, hubs, docking stations, adapters, chargers, etc.), audio / video / data recording and / or playback devices (e.g., cameras, recorders, handheld scanners, monitors, etc.), and other similar electronic devices that can use a USB interface for communication, battery charging, and / or power delivery.

[0018] USB Type-C TM(also referred to herein as "USB-C") is a type of technology for USB connectors. USB Type-C is defined in various releases and / or versions of the USB Type-C specification. The USB Type-C specification defines a Type-C receptacle, a Type-C plug, and a Type-C cable that can support USB communications and power delivery via the USB power delivery protocol defined in various revisions / versions of the USB-PD specification. Examples of USB Type-C features and requirements may include, but are not limited to: data and other communications according to USB 2.0 and USB 3.0 / 3.1, electromechanical definitions and performance requirements for Type-C cables, electromechanical definitions and performance requirements for Type-C receptacles, electromechanical definitions and performance requirements for Type-C plugs, requirements for Type-C to legacy cable assemblies and adapters, requirements for Type-C-based device detection and interface configuration, requirements for optimized power delivery of Type-C connectors, and the like. Some electronic devices may comply with specific revisions and / or versions of the USB-PD specification (e.g., revision 1.0, revision 2.0, revision 3.0, etc., or subsequent revisions / versions). The USB-PD specification defines a standard protocol designed to be used over USB Type-C. TM The port provides more flexible power delivery as well as data communication over a single USB-C cable to achieve maximum functionality of USB-enabled devices. The USB-PD specification also describes the architecture, protocols, power behaviors, parameters, and cabling required to manage power delivery over USB-C cables at up to 100W (or even higher in the case of EPR). According to the USB-PD specification, USB Type-C TM Devices at the port (e.g., USB-enabled devices) can negotiate more current and / or higher or lower voltages on a USB-C cable than allowed in older USB specifications (e.g., USB 2.0 specification, USB 3.1 specification, USB Battery Charging Specification Revision 1.1 / 1.2, etc.). For example, the USB-PD specification defines the requirements for a PD contract that can be negotiated between a pair of USB-enabled devices. The PD contract can specify the power levels and direction of power transfer that the two devices can accommodate, and can be dynamically renegotiated (e.g., without the need for the device to be unplugged) upon request by either device and / or in response to various events and conditions (e.g., power role swap, data role swap, hard reset, power failure, etc.). According to the USB-PD specification, an electronic device is typically configured to deliver power to another device through a power path configured on a USB VBUS line.

[0019] In some embodiments, a discharge operation is implemented to discharge a universal serial bus voltage (e.g., VBUS) of an integrated circuit for USB power delivery, which may include a USB-PD AC-DC converter. The discharge operation may be implemented for a primary-side controlled or secondary-side controlled USB-PD converter. In some embodiments, the discharge operation is implemented as an analog discharge operation. The discharge operation is performed to address thermal issues associated with discharging the VBUS voltage. When the VBUS voltage exceeds a threshold (e.g., greater than a PD contract negotiated between a power consuming device such as a phone and a power delivery device such as a USB-PD converter connected to a wall plug), the discharge is performed, which may be detected by the firmware. Thus, the discharge operation is triggered to start.

[0020] As part of implementing the discharge operation, a transistor configuration (e.g., a synchronous rectifier field effect transistor circuit (SR_FET), a single transistor, a transistor with a parallel diode, a transistor with a parallel buffer circuit, wherein the buffer circuit may have a series capacitor and a resistor, etc.) is controlled to provide a discharge path (e.g., a leakage path) for discharging the VBUS voltage. The transistor configuration is not fully turned on, as this would cause a large current to flow, which would result in a large amount of uncontrolled energy. Instead, the transistor configuration is turned on in an analog manner so as to limit the current and perform the discharge in a controlled manner. This is achieved by applying an incrementally increasing voltage reference value (e.g., an increment of 10mV or any other adjustable value) to the amplifier according to periodic intervals (e.g., every 0.5ms or any other adjustable value increment) until a discharge trigger point is reached. The incrementally increasing voltage reference value causes the amplifier to output a voltage signal (e.g., a voltage signal that is 4 times the voltage reference value applied to the amplifier, such as a 40mV voltage signal for a 10mV voltage reference value). The voltage signal causes the gate driver to control the gate of the transistor of the transistor configuration to provide a discharge path for the VBUS voltage until a trigger point is reached (e.g., a trigger point where the VBUS voltage decreases by 100 mV at a periodic interval of 0.5 ms, or any other adjustable trigger point). Once the VBUS voltage reaches the target discharge voltage, the discharge operation is stopped.

[0021] In some embodiments where a discharge operation is performed, a 1mF VBUS voltage cap corresponds to a 200mA current flowing through the transistor configuration. Thus, the VBUS voltage can discharge 25V in 125ms, which meets any USB specification, such as the USB Type-C and / or USB-PD specification, without causing undesirable heat within the integrated circuit. This is because the transistor configuration and the discharge path are external to the integrated circuit. For a primary-side controlled USB-PD AC-DC converter, the discharge operation can react to a situation where the primary side turns on the primary transistor configuration, which would cause the drain voltage to increase. Because the current in the transistor configuration is limited to 200mA, a pull-down device is provided for disabling the voltage signal to the transistor configuration in order to stop the discharge so that the transistor configuration is not damaged by a current exceeding 200mA.

[0022] Compared to existing discharge schemes, the disclosed discharge operation saves physical space because the discharge operation utilizes existing components and does not require multiple external components (e.g., external resistors and FETs). The discharge operation does not consume additional GPIO pins and GPIO pin controls, thereby freeing up GPIO for other functions. The discharge operation provides flexibility, where the discharge rate can be controlled and programmed by changing the step increment (e.g., 10mV step increment or any other adjustable step increment) of the voltage reference value based on an external VBUS voltage cap (VBUS cap) and the time increment of the periodic interval (e.g., 0.5ms periodic interval or any other adjustable periodic interval). In addition, the discharge operation can be used for a primary-side controlled or secondary-side controlled USB-PD AC-DC converter. The discharge operation is implemented in a reliable manner because the transistor configuration (e.g., SR_FET) is external to the integrated circuit, so there is no on-die heating from the discharge of the VBUS voltage. The discharge operation is implemented at a lower die cost because no internal bulky resistors or FETs are required, and there is no need to upgrade the existing power and ground buses to support the discharge current.

[0023] Figure 1 A secondary controlled USB-PD AC-DC converter 100 is shown that can implement the disclosed discharge operation. It is understood that the secondary controlled AC-DC converter 100 is only one type of device that can implement the discharge operation, and the discharge operation can be implemented for other devices such as primary controlled AC-DC converters. The AC-DC converter 100 is a flyback AC-DC converter that provides galvanic isolation between the AC input 102 and the DC output 216. The AC-DC converter 100 includes a primary side 10 disposed on the AC input side of a flyback transformer 106 and a secondary side 20 disposed on the DC output side of the flyback transformer 106. An isolation barrier 150 having an isolation element 150a electrically isolates the primary side 10 from the secondary side 20.

[0024] In at least some embodiments, the primary side 10 of the AC-DC converter 100 includes an AC input 102, a bridge rectifier 104, a flyback transformer 106, a primary power switch (PS) field effect transistor (FET) 108, and a primary side controller 110. In addition, the secondary side 20 includes a secondary side controller 200, a synchronous rectifier (SR) circuit 210 (e.g., “SR”), a drain node (SR_DRAIN) 212, an output capacitor 214, and a universal serial bus (USB) Type-C connector 220.

[0025] In some embodiments, on the primary side 10, an AC input 102 is configured to receive alternating current from a power source such as a wall outlet (not shown). A bridge rectifier 104 is coupled between the AC input 102 and a flyback transformer 106 to rectify the input voltage received at the AC input 102. The flyback transformer 106 is coupled to conduct AC current from the bridge rectifier 104 through the primary coil and the primary PS-FET 108 to ground. An input capacitor may be coupled to the output of the bridge rectifier 104 to be charged to the input voltage (Vin) in the primary side 10 of the AC-DC converter 100. In some embodiments, a primary side controller 110 is coupled to the gate of the primary PS-FET 108 to control the on and off cycles of the flyback transformer 106.

[0026] In some embodiments, on the secondary side 20, an SR circuit 210 is coupled between the secondary coil of the flyback transformer 106 and an output capacitor 214. The SR circuit 210 (also referred to herein as "SR") includes a secondary PS-FET 208 (e.g., an SR transistor) coupled in parallel to a diode so that when the secondary PS-FET 208 is turned on, an induced current flows to a drain node 212. The SR circuit 210 is configured to charge the output capacitor 214 so that the output capacitor 214 can provide a regulated voltage to a DC output 216. The DC output 216 is coupled to a power connector 220. In some embodiments, a secondary side controller 200 is coupled to the drain node 212 of the SR circuit 210 to sense the voltage (and changes thereto) on the drain node. The secondary side controller 200 is also coupled to the gate of the secondary PS-FET 208 in the SR circuit 210 to turn the SR circuit 210 on and off.

[0027] In some embodiments, a feature that determines the efficiency of an AC-DC converter (e.g., such as AC-DC converter 100) is the operation of a secondary PS-FET switch (e.g., secondary PS-FET 208) that controls the operation of SR circuit 210. In the primary controlled mode, the secondary side controller 200 depends on the voltage level of the drain node (e.g., SR_DRAIN 212) of the SR circuit 210 because there is no other communication channel from the primary side 10 to the secondary side 20. In some embodiments, the voltage on the SR_DRAIN node is below 0V to instruct the secondary side controller 200 to turn on the secondary PS-FET 208. When the voltage on the SR_DRAIN node returns to 0V, the secondary side controller 200 detects this zero voltage crossing and turns off the secondary PS-FET 208.

[0028] In the case of a primary-side controlled AC-DC converter, false negative sense (NSN) detection may be a problem for a secondary-side controller 200 operating in the context of a primary-side controlled AC-DC converter. Such erroneous NSN detection occurs during resonant ringing when the AC-DC converter 100 is operating in discontinuous conduction mode (DCM). During such resonant ringing, the voltage on the SR_DRAIN node of the SR circuit 210 may be below <0V. This voltage may be erroneously interpreted by the secondary-side controller 200 as a valid NSN detection event, causing the secondary-side controller 200 to turn on the secondary PS-FET 208 of the SR circuit 210. This, in turn, results in efficiency loss due to unnecessary turn-on of the SR circuit 210, thereby discharging the output load capacitor 218, which brings the VBUS voltage (e.g., VBUS_IN) to ground. Additionally, if the primary side controller 110 turns on the primary PS-FET 108 at the same time, cross-conduction will result if both the primary side 10 and the secondary side 20 are turned on at the same time. However, such cross-conduction may result in very high secondary side currents, which may result in breakdown of the diode and transistor components of the SR circuit 210. This problem may be addressed by a secondary side controlled AC-DC converter such as the AC-DC converter 100. The secondary side controller 200 typically ensures that the PS-FET 108 is turned off when the PS-FET 208 is turned on, and vice versa, to prevent cross-conduction and promote efficient operation. This may be performed by a pull-down device, which will be related to Figure 3A and Figure 3B Further discussion.

[0029] In some embodiments, the secondary side 20 further includes an additional or secondary switch (SS) 217 ​​(such as an NFET) coupled between the third terminal of the flyback transformer 106 and the positive DC output to enable the secondary side controller 200 to shut down the DC output 216 to prevent overvoltage and / or undervoltage conditions and / or overcurrent conditions and / or short circuit conditions. In some embodiments, such overvoltage conditions can trigger a skip mode in which the secondary side controller 200 prevents power from being released from the AC-DC converter 100, such as releasing VBUS. SS 217 includes a voltage bus input pin (V BUS_IN ) drain node; coupled to the voltage bus control pin (V BUS_CTRL ) to drive or control the gate node of SS217. SS217 includes a voltage bus output pin (V BUS_C ) and the source node of the positive terminal of the DC output. BUS_C ), the secondary side controller 200 can monitor the VBUS voltage input (Vsink) drawn by the sink device coupled to the USB Type-C connector 220. Figure 2-4 As further discussed, a discharge operation may be performed to discharge the VBUS voltage of the AC-DC converter 100 .

[0030] Figure 2 It is a combination Figure 3A and Figure 3B 300 for discharging the VBUS voltage. The system 300 includes an integrated circuit 304. The integrated circuit 304 includes an amplifier (A1) 310 (e.g., an operational amplifier having resistors R3 and R4). The amplifier (A1) 310 is enabled by the discharge_en signal. The amplifier (A1) 310 takes a voltage reference value (Vref) as an input and outputs a voltage signal to a gate driver (D1) 312. The voltage signal can be a multiple of the voltage reference value (e.g., a 4x voltage gain, such as a 40mV voltage signal for a 10mV voltage reference value).

[0031] The voltage signal causes the gate driver (D1) 312 to apply a gate voltage (sr_gdrv) 314 to the gate of the transistor (SR_FET) 306 of the transistor configuration to provide a discharge path 350 for the universal serial bus voltage (VBUS) 302 to the ground 324, as shown in FIG. Figure 3B In some embodiments, the transistor configuration includes at least one of: a synchronous rectifier field effect transistor circuit (SR_FET); a single transistor; a transistor with a parallel diode; a transistor with a parallel buffer circuit, wherein the buffer circuit may have a series capacitor and a resistor, etc.

[0032] The integrated circuit 304 may include a discharge control component 322 that generates a discharge_en signal and / or performs other functions, such as detecting whether the pull-down device 316 is enabled. The integrated circuit 304 may include a control component (SR_FET control) 320 for controlling the transistor (SR_FET) 306 through the gate driver (D1) 312. The gate driver (D1) 312 may be tri-stateable, wherein the gate driver (D1) 312 may turn the transistor (SR_FET) 306 on or off, and may also have a floating state during a discharge operation. In the floating state, a voltage less than the on-voltage of the transistor (SR_FET) 306 may be applied to the gate of the transistor (SR_FET) 306 to create a discharge path (leakage path) configured through the transistor for discharging the VBUS voltage (VBUS) 302 to ground 324. The integrated circuit 304 also includes an ADC component 308, which is configured to measure the universal serial bus voltage (VBUS) 302.

[0033] An integrated circuit 304 (e.g., a USB-PD controller) may be configured to provide universal serial bus power delivery (USB PD) control for a power delivery connection between a primary device (e.g., a power provider) and a secondary device (e.g., a power consumer). A discharge operation, such as a simulated discharge operation, may be implemented for a universal serial bus voltage (VBUS) 302 associated with the USB-PD controller. The discharge operation may be implemented for a primary side controlled USB-PD AC-DC converter or a secondary side controlled USB-PD AC-DC converter.

[0034] ADC component 308 (e.g., an analog-to-digital converter controlled by firmware of integrated circuit 304) measures universal serial bus voltage (VBUS) 302. Universal serial bus voltage (VBUS) 302 is compared to a threshold value to determine whether universal serial bus voltage (VBUS) 302 exceeds the threshold value. In some embodiments, the threshold value may be defined by a PD contract negotiated between a power provider (e.g., a USB-PD AC-DC converter) and a power consumer (e.g., a USB-enabled phone or laptop). The value of the current or voltage negotiated under the PD contract may change over time (e.g., a phone may initially request a higher current or voltage until the phone reaches a certain battery charge level, and then may request a lower current or voltage), so the threshold value may change dynamically over time. When determining whether the universal serial bus voltage (VBUS) 302 exceeds the threshold value corresponding to the latest value of the contract, the dynamic change of the threshold value is taken into account.

[0035] Return to reference Figure 2In some embodiments, method 250 is performed by a USB-PD controller and / or components thereof (e.g., such as Figure 3A-3B ) is performed. During operation 252 of method 250, based on the universal serial bus voltage (VBUS) 302 exceeding a threshold, initiation of a discharge operation is triggered to discharge the universal serial bus voltage (VBUS) 302. As part of initiating the discharge operation, during operation 254 of method 250, gate driver (D1) 312 is tri-stated, and amplifier (A1) 310 and pull-down device 316 are enabled. In some embodiments, amplifier (A1) 310 is enabled based on the discharge control component 322 transmitting a discharge_en signal to amplifier 310. As part of the discharge operation, during operation 256 of method 250, an incrementally increasing voltage reference value is applied to amplifier (A1) 310 at periodic intervals (e.g., initially 10 mV, 20 mV after 0.5 ms, 30 mV after another 0.5 ms, etc.) until a discharge trigger point is reached. The discharge trigger point corresponds to the amount by which the universal serial bus voltage (VBUS) decreases within a periodic interval (e.g., a decrease of 100 mV within a 0.5 ms interval). Amplifier (A1) 310 outputs a voltage signal to output 314 of gate driver (D1) 312, which controls the gate of transistor (SR_FET) 306 to create a discharge path 350 for the universal serial bus voltage (VBUS) 302 to ground 324, as shown in FIG. Figure 3B shown.

[0036] During the discharge operation, during operation 258 of method 250, the ADC component 308 measures the universal serial bus voltage (VBUS) to determine whether the trigger point has been reached. If the trigger point has not been reached, the voltage reference value is continuously incremented according to the periodic interval. If the trigger point has been reached, during operation 260 of method 250, the voltage reference value is no longer incremented and remains at the current value. After the trigger point has been reached and the universal serial bus voltage (VBUS) is discharged through the discharge path 350, during operation 262 of method 250, the ADC component 308 measures the universal serial bus voltage (VBUS) to determine whether the target discharge voltage has been reached. If the target discharge voltage has not been reached, the discharge path is maintained.

[0037] If the target discharge voltage has been reached, the discharge operation is disabled during operation 264 of the method 250. The discharge operation is disabled by disabling the amplifier (A1) 310 (e.g., the discharge control component 322 stops transmitting the discharge_en signal to the amplifier (A1) 310). In addition, the gate driver (D1) 312 is enabled to begin controlling the gate of the transistor (SR_FET) 306 in a manner that disables the created discharge path 350. The gate driver (D1) 312 turns off the transistor (SR_FET) 306 by reducing or pulling down the voltage applied to the gate of the transistor (SR_FET) 306 so that the transistor (SR_FET) 306 no longer provides the discharge path 350. In addition, once the target discharge voltage is reached, the pull-down device 316 is disabled.

[0038] Before the target discharge voltage has been reached and before the pull-down device 316 is disabled, the pull-down device 316 may be used to pull down the gate voltage (sr_gdrv) 314 of the gate of the transistor (SR_FET) 306 to close the discharge path 350. The pull-down device 316 is triggered to pull down the gate voltage (sr_gdrv) 314 based on the drain voltage (sr_drain) 318 crossing the universal serial bus voltage (VBUS) 302, which may occur if the primary side FET is turned on when the transistor (SR_FET) 306 is controlled to create the discharge path 350.

[0039] Figure 4 400. The timing diagram 400 shows the values ​​of the following items: a universal serial bus voltage (VBUS) 408, a gate voltage (sr_gdrv) 406 of a transistor configuration (e.g., SR_FET) that provides a discharge path for the universal serial bus voltage (VBUS) 408, a discharge enable signal (discharge_en) 402 for enabling the amplifier to start a discharge operation, and a gate driver tristate enable signal (gdrv_tristate_en) 404 for tristate the gate driver to allow control to be given to the amplifier to control the gate of the transistor (SR_FET) of the transistor configuration. When the universal serial bus voltage (VBUS) 408 exceeds the threshold, the discharge enable signal (discharge_en) 402 goes high. This signals the amplifier to output a voltage signal based on the incrementally increasing voltage reference value input into the amplifier. In addition, based on the gate driver tristate enable signal (gdrv_tristate_en) 404 going high, the gate driver is tristate.

[0040] Based on the voltage signal output by the amplifier to the gate driver, the gate voltage (sr_gdrv) 406 of the transistor is increased incrementally by 40mV increments every 0.5ms periodic interval. When the universal serial bus voltage (VBUS) 408 reaches a trigger point 410 (e.g., a decrease of 100mV within a 0.5ms periodic interval), the amplifier stops increasing the voltage signal incrementally, and the voltage signal remains at a current value such as about 2.04V or any other value. Once the universal serial bus voltage (VBUS) 408 reaches the target discharge voltage, the gate driver tri-state enable signal 404 goes low to pull down the gate of the transistor. This causes the gate voltage (SR_gdrv) 406 to go low. Once the discharge operation is completed, the discharge enable signal (discharge_en) 402 goes low.

[0041] Figure 5 5 is a block diagram illustrating a system 500 for a USB device according to some embodiments. The system 500 may include a peripheral subsystem 502 including multiple components for USB power delivery (USB-PD). The peripheral subsystem 502 may include a peripheral interconnect 504 including a peripheral clock module (PCLK) 506 for providing clock signals to various components of the peripheral subsystem 502. The peripheral interconnect 504 may be a peripheral bus, such as a single-stage or multi-stage advanced high-performance bus (AHB), and may provide a data and control interface between the peripheral subsystem 502, the CPU subsystem 508, and the system resources 510. The peripheral interconnect 504 may include a controller circuit, such as a direct memory access (DMA) controller, which may be programmed to transfer data between peripheral blocks without input from the CPU subsystem 508, without control of the CPU subsystem 508, or without emphasizing the same transfer.

[0042] The peripheral interconnect 504 may be used to couple the peripheral subsystem 502 components to other components of the system 500. A plurality of general purpose input / outputs (GPIOs) 512 may be coupled to the peripheral interconnect 504 for sending and receiving signals. The GPIOs 512 may include circuits configured to implement various functions such as pull-ups, pull-downs, input threshold selection, input and output buffer enable / disable, signal multiplexing, etc. Other functions may also be implemented by the GPIOs 512. One or more timer / counter / pulse width modulators (TCPWMs) 514 may also be coupled to the peripheral interconnect and may include circuits for implementing timing circuits (timers), counters, pulse width modulators (PWMs), decoders, and other digital functions associated with I / O signal operation, and may provide digital signals to system components of the system 500. The peripheral subsystem 502 may also include one or more serial communication blocks (SCBs) 516 for implementing serial communication interfaces such as I2 C. Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), Controller Area Network (CAN), CXPI (Clock Extension Peripheral Interface), etc.

[0043] For USB power delivery applications, peripheral subsystem 502 may include USB power delivery subsystem 518 coupled to peripheral interconnect 504 and including a set of USB PD modules 520 for use with USB power delivery. USB PD modules 520 may be coupled to peripheral interconnect 504 via USB-PD interconnect 522. The USB PD module 520 may include: an analog-to-digital converter (ADC) module for converting various analog signals into digital signals; an error amplifier (AMP) for regulating the output voltage on the VBUS line through the PD contract; a high voltage (HV) regulator for converting the power supply voltage to a precise voltage (such as 3.5-5V) to power the system 500; a low-side current sense amplifier (LSCSA) for accurately measuring the load current, an overvoltage protection (OVP) module and an overcurrent protection (OCP) module for providing overcurrent and overvoltage protection on the VBUS line with configurable thresholds and response times; one or more gate drivers for external power field effect transistors (FETs) used in USB power delivery in provider and consumer configurations; and a communication channel PHY (CC-BB-PHY) module for supporting communication on the Type-C communication channel (CC) line. The USB PD module 520 may also include a charger detection module for determining whether a charging circuit is present and coupled to the system 500 and a VBUS discharge module for controlling the discharge of the voltage on the VBUS. The VBUS discharge module can be configured to couple to a power node on the VBUS line or to an output (power sink) node on the VBUS line and adjust the voltage on the VBUS line to a desired voltage level (i.e., a voltage level specified in the voltage level negotiated by the PD contract). The USB power delivery subsystem 518 may also include pads 524 for external connections and electrostatic discharge (ESD) suppression circuits 526 that may be required on the Type-C port. The USB PD module 520 may also include a communication module for retrieving information (e.g., control signals) and transmitting information (e.g., control signals), for example, from the secondary side controller 104 to the primary side controller 102.

[0044] The GPIO 512, TCPWM 514, and SCB 516 may be coupled to an input / output (I / O) subsystem 528, which may include a high-speed (HS) I / O matrix 530 connected to a plurality of GPIOs 532. The GPIO 512, TCPWM 514, and SCB 516 may be coupled to the GPIO 532 via the HS-I / O matrix 530.

[0045] A central processing unit (CPU) subsystem 508 is provided for processing instructions, storing program information and data. The CPU subsystem 508 may include one or more processing units 534 for executing instructions and reading and writing memory locations from multiple memories. The processing unit 534 may be a processor suitable for operation in an integrated circuit (IC) or a system on a chip (SOC) device. In some embodiments, the processing unit 534 may be optimized for low-power operation with extensive clock gating. In this embodiment, different internal control circuits may be implemented to handle unit operations in different power states. For example, the processing unit 534 may include a single-wire debug (SWD) module, a terminal count (TC) module, a wake-up interrupt controller (WIC) configured to wake up the processing unit from a sleep state (which may turn off the power when the IC or SOC is in a sleep state), a fast multiplier, a nested vector interrupt controller (NVIC), and an interrupt multiplexer (IRQMUX). The CPU subsystem 508 may include one or more memories, including flash memory 536, static random access memory (SRAM) 538, and read-only memory (ROM) 540. Flash memory 536 may be a non-volatile memory (NAND flash memory, NOR flash memory, etc.) configured to store data, programs, and / or other firmware instructions. Flash memory 536 may include system performance controller interface (SPCIF) registers and read accelerators, and improve access time by being integrated into CPU subsystem 508. SRAM 538 may be a volatile memory configured to store data and firmware instructions accessible by processing unit 534. ROM 540 may be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during operation of system 500. SRAM 538 and ROM 540 may have associated control circuits. Processing unit 534 and memory modules 536, 538, 540 may be coupled to system interconnect 542 to transmit signals to and from various components of CPU subsystem 508 to other blocks or modules of system 500. System interconnect 542 may be implemented as a system bus, such as a single-level or multi-level AHB. System interconnect 542 may be configured as an interface for coupling together various components of CPU subsystem 508. System interconnect 542 may be coupled to peripheral interconnect 504 to provide a signal path between CPU subsystem 508 and components of peripheral subsystem 502.

[0046] System resources 510 may include a power module 544, a clock module 546, a reset module 548, and a test module 550. The power module 544 may include a sleep control module, a wake-up interrupt control (WIC) module, a power-on reset (POR) module, multiple voltage references (REF), and a PWRSYS module. In some embodiments, the power module 544 may include circuits that allow the system 500 to draw power from an external source and / or provide power to an external source at different voltages and / or current levels and control operations in different power states (such as active, low power, or sleep). In various embodiments, more power states may be achieved when the system 500 throttles operations to achieve desired power consumption or power output. For example, the secondary side controller 104 may access secondary electrical parameters on the secondary side. The clock module 546 may include a clock control module, a watchdog timer (WDT), an internal low speed oscillator (ILO), and an internal main oscillator (IMO). The reset module 548 may include a reset control module and an external reset module (XRES module). The test module 550 may include modules for controlling and entering a test mode, and test control modules for analog and digital functions (digital test and analog DFT).

[0047] System 500 may be implemented in a monolithic (e.g., single) semiconductor die. In other embodiments, different portions or modules of system 500 may be implemented on different semiconductor dies. For example, memory modules 536, 538, 540 of CPU subsystem 508 may be on-chip or off-chip. In other embodiments, circuits with separate dies may be packaged in a single "chip," or kept separate and arranged as separate components on a circuit board (or in a USB cable connector).

[0048] System 500 can be implemented in multiple application contexts to provide USB PD functionality. In any application context, an electronic device (e.g., a USB-enabled device) can have an IC controller or SOC implementation embodied by system 500, which is arranged and configured to perform operations according to the technology described herein. In one embodiment, system 500 can be arranged and configured in a personal computer (PC) power adapter for a laptop computer, notebook computer, etc. In another embodiment, system 500 can be housed in a power adapter (e.g., a wall charger) for a mobile electronic device (e.g., a smart phone, a tablet computer, etc.). In another embodiment, system 500 can be placed and configured in a wall socket that is configured to provide power via a USB Type-A and / or Type-C port. In another embodiment, system 500 can be arranged and configured in a car charger that is configured to provide power via a USB Type-A and / or Type-C port. In yet another embodiment, system 500 can be arranged and configured in a mobile power supply that can be charged via a USB Type-A and / or Type-C port and then provide power to another electronic device. In other embodiments, systems such as system 500 may be configured with the power switch gate control circuits described herein and may be incorporated into various other USB-enabled electronic or electromechanical devices.

[0049] It should be understood that a system implemented on or as an IC controller (such as system 500) can be placed in a variety of applications that vary depending on the type of power source used and the direction of power supply. For example, in the case of a car charger, the power source is a car battery that provides DC power, while in the case of a mobile power adapter, the power source is an AC wall outlet. In addition, in the case of a PC power adapter, the flow of power input is from a provider device to a consumer device, while in the case of a mobile power supply, the flow of power input can be in either direction, depending on whether the mobile power supply is operating as a power provider (e.g., powering another device) or as a power consumer (e.g., allowing itself to be charged). For these reasons, the various applications of system 500 should be considered illustrative rather than restrictive.

[0050] Embodiments of the presently disclosed technology include a method for discharging a universal serial bus voltage. The method includes: in response to determining that the universal serial bus voltage exceeds a threshold, a universal serial bus power delivery (USB-PD) controller triggers a start of a discharge operation to discharge the universal serial bus voltage; and the USB-PD controller performs the discharge operation by: applying an incrementally increasing voltage reference value to an amplifier according to a periodic interval until a discharge trigger point is reached, wherein the amplifier outputs a voltage signal to a gate driver, the gate driver controls a gate of a transistor to provide a discharge path for discharging the universal serial bus voltage; and in response to reaching the discharge trigger point, stopping the incremental increase of the voltage reference value applied to the amplifier.

[0051] According to some embodiments, the method includes, in response to the universal serial bus voltage reaching a target discharge voltage, the USB-PD controller disabling the discharge operation by disabling the amplifier.

[0052] According to some embodiments, the threshold is defined by a contract negotiated between the USB-PD power converter and a peripheral device coupled thereto.

[0053] According to some embodiments, the method includes: detecting a change in the value of the threshold from a first value to a second value; and determining whether to subsequently trigger the discharge operation based on whether a current value of the universal serial bus voltage exceeds the second value.

[0054] According to some embodiments, the discharge trigger point corresponds to an amount by which the universal serial bus voltage decreases within periodic intervals.

[0055] According to some embodiments, the method includes controlling the gate driver to reduce a voltage applied to a gate of the transistor in response to the universal serial bus voltage reaching a target discharge voltage.

[0056] According to some embodiments, the method includes programming as adjustable parameters a periodic interval, an amount by which a voltage reference value is incremented, and an amount by which a voltage signal is incremented based on the voltage reference value.

[0057] According to some embodiments, performing the discharge operation includes enabling a pull-down device, and the method includes disabling the pull-down device in response to the universal serial bus voltage reaching a target discharge voltage.

[0058] According to some embodiments, the method is performed by a USB-PD controller for a power converter according to the USB-PD specification.

[0059] According to some embodiments, the method includes: in response to a drain voltage of a transistor crossing the USB voltage, controlling a pull-down device to pull down a gate voltage of a gate of the transistor to close a discharge path of the USB voltage.

[0060] Embodiments of the presently disclosed technology include an apparatus. The apparatus includes a transistor configuration configured to provide a discharge path for a universal serial bus voltage based on a voltage applied to a gate of the transistor; and a universal serial bus power delivery (USB-PD) controller instantiated as an integrated circuit configured to provide universal serial bus power delivery control, wherein the USB-PD controller includes a gate driver configured to control a voltage applied to a gate of the transistor to control the transistor to provide a discharge path for the discharge of the universal serial bus voltage; and an amplifier configured to output a voltage signal to the gate driver to control the gate driver, wherein the voltage signal is based on an incrementally increasing voltage value applied to the amplifier, wherein the incrementally increasing voltage value increases according to a periodic interval until a discharge trigger point is detected.

[0061] According to some embodiments, the discharge trigger point corresponds to an amount by which the universal serial bus voltage decreases within periodic intervals.

[0062] According to some embodiments, based on the USB voltage reaching a target discharge voltage, the amplifier and the gate driver are disabled without discharging the USB voltage.

[0063] According to some embodiments, the apparatus includes a pull-down device configured to pull down a voltage applied to a gate of the transistor to close a discharge path in response to a drain voltage of the transistor crossing the universal serial bus voltage.

[0064] According to some embodiments, wherein the device is a primary side controlled USB-PD power converter, and wherein the discharge path is established as part of a simulated discharge operation controlled by a secondary side controller of the USB-PD power converter.

[0065] According to some embodiments, wherein the device is a secondary-side controlled USB-PD power converter, and wherein the discharge path is established as part of a simulated discharge operation controlled by a secondary-side controller of the USB-PD power converter.

[0066] Embodiments of the presently disclosed technology include an apparatus. The apparatus includes: a transistor configuration configured to provide a discharge path for a universal serial bus voltage based on a voltage applied to a gate of the transistor; and a universal serial bus power delivery (USB-PD) controller instantiated as an integrated circuit configured to provide universal serial bus power delivery control, wherein the USB-PD controller includes a gate driver configured to control a voltage applied to a gate of the transistor to control the transistor configuration to provide a discharge path for the discharge of the universal serial bus voltage; an amplifier configured to output a voltage signal to the gate driver to control the gate driver, wherein the voltage signal is based on an incrementally increasing voltage value applied to the amplifier, wherein the incrementally increasing voltage value increases according to a periodic interval until a discharge trigger point is detected; and a pull-down device configured to pull down a voltage applied to a gate of the transistor in response to a drain voltage of the transistor crossing the universal serial bus voltage to close the discharge path.

[0067] According to some embodiments, based on the USB voltage reaching a target discharge voltage, the amplifier and the gate driver are disabled without discharging the USB voltage.

[0068] According to some embodiments, the pull-down device is disabled based on the universal serial bus voltage reaching a target discharge voltage.

[0069] According to some embodiments, wherein the device is one of a primary side controlled USB-PD power converter or a secondary side controlled USB-PD power converter.

[0070] Various operations of the embodiments are provided herein. In one embodiment, one or more of the operations described may constitute computer-readable instructions stored on one or more computer-readable media, which, if executed by a computing device such as a microcontroller or another type of integrated circuit (IC) controller, will cause the computing device to perform the described operations. The order in which some or all operations are described should not be interpreted as implying that these operations must be sequence-dependent. Those skilled in the art who benefit from this specification will understand alternative sequences. In addition, it should be understood that not all operations must be present in each embodiment provided herein. Moreover, it should be understood that in some embodiments, not all operations are required.

[0071] Furthermore, unless otherwise stated, "first," "second," etc. are not intended to imply a temporal aspect, a spatial aspect, a sequence, etc. Instead, these terms are merely used as identifiers, names, etc. of features, elements, items, etc. For example, a first object and a second object generally correspond to object A and object B or two different or two identical objects or identical objects.

[0072] In addition, "exemplary" and the like are used herein to represent examples, instances, descriptions, etc., and are not necessarily advantageous. As used herein, "or" is intended to represent an inclusive "or" rather than an exclusive "or". In addition, "a" and "an" used in this application can generally be interpreted as representing "one or more", unless otherwise specified or clearly pointed to the singular form from the context. In addition, at least one of A and B, etc. generally represent A or B and / or both A and B. In addition, with respect to the use of "including", "having", "has", "with" and / or its variants in the specific embodiments or claims, these terms are intended to be inclusive in a manner similar to the term "including".

[0073] In addition, although the present disclosure has been shown and described with respect to one or more embodiments, based on the reading and understanding of this specification and the drawings, those skilled in the art will think of equivalent changes and modifications. The present disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe these components are intended to correspond to any component (e.g., functionally equivalent) that performs the specified functions of the described components, even if they are not structurally equivalent to the disclosed structures. In addition, although the specific features of the present disclosure may have been disclosed only with respect to one of several embodiments, such features may be combined with one or more other features of other embodiments, as may be desirable and advantageous for any given or specific application.

Claims

1. A method for discharging a universal serial bus voltage, comprising: In response to determining that the USB voltage exceeds a threshold, a USB-PD controller triggers an initiation discharge operation to discharge the USB voltage; and The USB-PD controller performs the discharging operation by the following operations: applying an incrementally increasing voltage reference value to an amplifier according to periodic intervals until a discharge trigger point is reached, wherein the amplifier outputs a voltage signal to a gate driver, the gate driver controlling a gate of a transistor to provide a discharge path for discharge of the universal serial bus voltage; and Incremental increases of the voltage reference value applied to the amplifier are ceased in response to reaching the discharge trigger point.

2. The method according to claim 1, comprising: In response to the universal serial bus voltage reaching a target discharge voltage, the USB-PD controller disables the discharge operation by disabling the amplifier.

3. The method according to claim 1, wherein: The threshold is defined by a contract negotiated between the USB-PD power converter and the peripheral device coupled thereto.

4. The method according to claim 1, comprising: detecting a change in the value of the threshold from a first value to a second value; as well as Whether to subsequently trigger the discharge operation is determined based on whether the current value of the universal serial bus voltage exceeds the second value.

5. The method according to claim 1, wherein: The discharge trigger point corresponds to an amount by which the universal serial bus voltage decreases within the periodic interval.

6. The method according to claim 1, comprising: In response to the universal serial bus voltage reaching a target discharge voltage, the gate driver is controlled to reduce a voltage applied to a gate of the transistor.

7. The method according to claim 1, comprising: The periodic interval, the amount by which the voltage reference value is incremented, and the amount by which the voltage signal is incremented based on the voltage reference value are programmed as adjustable parameters.

8. The method according to claim 1, wherein: Performing the discharge operation includes enabling a pull-down device, and wherein the method comprises: In response to the universal serial bus voltage reaching a target discharge voltage, the pull-down device is disabled.

9. The method according to claim 1, wherein: The method is performed by the USB-PD controller for a power converter according to the USB-PD specification.

10. The method according to claim 1, comprising: In response to the drain voltage of the transistor crossing the universal serial bus voltage, the pull-down device is controlled to pull down the gate voltage of the gate of the transistor to close the discharge path of the universal serial bus voltage.

11. An apparatus comprising: a transistor configuration configured to provide a discharge path for a universal serial bus voltage based on a voltage applied to a gate of the transistor; as well as A universal serial bus power delivery (USB-PD) controller, the universal serial bus power delivery (USB-PD) controller being instantiated as an integrated circuit configured to provide universal serial bus power delivery control, wherein the USB-PD controller comprises: a gate driver configured to control the voltage applied to the gate of the transistor to control the transistor configuration to provide the discharge path for discharging the universal serial bus voltage; and an amplifier configured to output a voltage signal to the gate driver to control the gate driver, wherein the voltage signal is based on an incrementally increasing voltage value applied to the amplifier, wherein the incrementally increasing voltage value increases according to a periodic interval until a discharge trigger point is detected.

12. The device according to claim 11, wherein The discharge trigger point corresponds to an amount by which the universal serial bus voltage decreases within the periodic interval.

13. The device according to claim 11, wherein: Based on the universal serial bus voltage reaching a target discharge voltage, the amplifier and the gate driver are disabled without discharging the universal serial bus voltage.

14. The apparatus according to claim 11, comprising: A pull-down device is configured to pull down the voltage applied to the gate of the transistor in response to the drain voltage of the transistor crossing the universal serial bus voltage to close the discharge path.

15. The device according to claim 11, wherein The apparatus is a primary side controlled USB-PD power converter, and wherein the discharge path is established as part of a simulated discharge operation controlled by a secondary side controller of the USB-PD power converter.

16. The device according to claim 11, wherein The apparatus is a secondary-side controlled USB-PD power converter, and wherein the discharge path is established as part of a simulated discharge operation controlled by a secondary-side controller of the USB-PD power converter.

17. An apparatus comprising: a transistor configuration configured to provide a discharge path for a universal serial bus voltage based on a voltage applied to a gate of the transistor; as well as A universal serial bus power delivery (USB-PD) controller, the universal serial bus power delivery (USB-PD) controller being instantiated as an integrated circuit configured to provide universal serial bus power delivery control, wherein the USB-PD controller comprises: a gate driver configured to control a voltage applied to a gate of the transistor to control the transistor configuration to provide the discharge path for discharging the universal serial bus voltage; an amplifier configured to output a voltage signal to the gate driver to control the gate driver, wherein the voltage signal is based on an incrementally increasing voltage value applied to the amplifier, wherein the incrementally increasing voltage value increases according to a periodic interval until a discharge trigger point is detected; and A pull-down device is configured to pull down the voltage applied to the gate of the transistor in response to the drain voltage of the transistor crossing the universal serial bus voltage to close the discharge path.

18. The device according to claim 17, wherein: Based on the universal serial bus voltage reaching a target discharge voltage, the amplifier and the gate driver are disabled without discharging the universal serial bus voltage.

19. The device according to claim 17, wherein: The pull-down device is disabled based on the universal serial bus voltage reaching a target discharge voltage.

20. The device according to claim 17, wherein: The device is one of a primary side controlled USB-PD power converter or a secondary side controlled USB-PD power converter.

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