Apparatus for current sharing of converters connected in parallel

Abstract

The invention relates to an apparatus for current sharing of converters connected in parallel. A power converter system comprises an auxiliary resonant commutated pole (ARCP) converter branch, in particular an ARCP half-bridge branch, which is connected in parallel between a common dc system and a common ac system or between two common dc systems. The commutation of the converter branches connected in parallel is initiated by a simultaneous commutation command. A control device is provided to balance current sharing between parallel connected ARCP converter branches by means of having a separate autonomous branch-specific boost current adjustment for each of the parallel connected ARCP converter branches, a separate autonomous branch-specific boost current adjustment is used to adjust the boost current in a direction in which the differential output current decreases. Each individual boost current adjustment depends only on the magnitude of the leg current of the respective ARCP converter leg.

Description

Technical Field

[0001] The present invention relates to parallel connected power converters, and more particularly to current sharing of parallel connected power inverters and rectifiers. Background Art

[0002] A dc-ac or ac-dc converter (also referred to as an inverter or rectifier, respectively) converts power from a dc to ac or ac to dc system at a desired voltage and frequency. Thus, the inverter can be operated as a voltage source with adjustable frequency. The dc power input to the inverter can be obtained from the existing power grid through a rectifier, or from a battery, fuel cell, photovoltaic array, etc. The (multiple) filter capacitors across the input terminals of the inverter provide a fairly constant dc link voltage. The configuration of an ac to dc rectifier and a dc to ac inverter can be referred to as a dc link converter.

[0003] In some cases, a power inverter with increased output power capability is implemented by connecting multiple inverter units in parallel to each other to supply power to the same load. The inverter units connected in parallel can receive simultaneous and similar control signals to provide the desired output of the power inverter. However, due to parameter differences in the switch components and different impedances in the parallel branches, the current amplitudes between the units may not be equal. This current imbalance may cause the components to be unevenly stressed and prematurely wear the switch components with higher currents. Higher currents in the switch components may result in higher dissipated power and further lead to higher temperatures of the components.

[0004] Current imbalance has been addressed by modifying the switch control pulses in order to balance the currents. The control pulses may be modified by delaying the turn-on moment of the switch with the highest current or by delaying the turn-off moment of the switch with the lowest current. One such approach is disclosed in EP0524398. In these solutions, the conduction time of parallel components is modified to equalize the stress of the switch components based on the measured inverter cell currents.

[0005] US8432714 discloses a method for balancing loads between parallel connected inverter modules, wherein the temperature of each output branch of each inverter module is determined and switching commands for one or more parallel inverter modules are modified to control the temperature of the output branches.

[0006] WO 2017 / 0719125 A1 discloses a method in which the output voltages of all parallel-connected power devices are measured and the measurements are used to mitigate timing differences during output voltage state changes caused, for example, by gate driver circuit and switching component parameter tolerances.

[0007] US7068525 discloses a method of operating a plurality of inverters connected in parallel by individually regulating the individual currents of the inverters. Summary of the invention

[0008] It is an object of the invention to provide an improved power converter system with two or more converter branches connected in parallel. The power converter system is recited in the independent claim. Preferred embodiments are disclosed in the dependent claims.

[0009] One aspect of the present invention is a power converter system comprising

[0010] Two or more converter branches are connected in parallel between a common dc system and a common ac system or between two common dc systems, wherein commutation of the parallel-connected converter branches is initiated by simultaneous commutation commands,

[0011] a control device configured to balance current sharing between the parallel-connected converter branches,

[0012] The parallel-connected converter branches are auxiliary resonant commutated pole (ARCP) converter branches, in particular ARCP half-bridge branches, and wherein the control device is configured to balance the current sharing between the parallel-connected ARCP converter branches by means of having an individual autonomous branch-specific boost current adjustment for each of the parallel-connected ARCP converter branches, the individual autonomous branch-specific boost current adjustment being used to adjust the boost current in a direction of decreasing differential output current, wherein each individual boost current adjustment depends only on the amplitude of the branch current of the respective ARCP converter branch.

[0013] In an embodiment, each individual boost current adjustment depends on the branch current of the corresponding ARCP converter branch to autonomously adjust the boost current and / or boost time of the corresponding ARCP converter branch connected in parallel and / or the timely behavior of the voltage swing of the corresponding ARCP converter branch connected in parallel.

[0014] In an embodiment, each individual boost current adjustment is configured to depend on the amplitude of the branch current of the corresponding ARCP converter branch, such that in ARCP commutation mode A, the higher the amplitude of the branch current, the later and / or slower the voltage swing, and in ARCP commutation mode B, the higher the amplitude of the branch current, the earlier and / or faster the voltage swing.

[0015] In an embodiment, each individual boost current adjustment is configured to depend on the magnitude of the branch current of the corresponding ARCP converter branch, such that in ARCP commutation mode A, the higher the magnitude of the branch current, the lower the boost current and / or the shorter the boost time, and in ARCP commutation mode B, the higher the magnitude of the branch current, the higher the boost current and / or the longer the boost time.

[0016] In an embodiment, each individual boost current adjustment has the same predetermined dependency on the branch current of the corresponding ARCP converter branch.

[0017] In an embodiment, in ARCP commutation mode A, the boost current in each parallel-connected ARCP converter branch is autonomously reduced from a reference value depending on the actual value of the branch current of the corresponding branch, in such a way that a converter branch with a higher output current will reduce its boost current more than a converter branch with a lower branch current.

[0018] In an embodiment, in ARCP commutation mode A, each individual boost current adjustment depends on the magnitude of the branch current of the corresponding ARCP converter branch approximately according to the following equation, where

[0019] I bA x=|I on |(k IA -1)+I bA，r ,

[0020] n is the index,

[0021] I bAn is the boost current of ARCP converter branch n,

[0022] I on is the branch current of the ARCP converter branch n,

[0023] k IA is the multiplier, 0≤k IA <1,

[0024] I bA，r is the reference boost current.

[0025] In an embodiment, in ARCP commutation mode B, the boost current in each parallel-connected ARCP converter branch is autonomously increased from a reference value depending on the actual value of the branch current of the corresponding branch, in such a way that a converter branch with a higher branch current will increase its boost current more than a converter branch with a lower branch current.

[0026] In an embodiment, in ARCP commutation mode B, each individual boost current adjustment depends on the magnitude of the branch current of the corresponding ARCP converter branch approximately according to the following equation:

[0027] I bBn =I bB，min +k IB |I on |,

[0028] in

[0029] n is the index,

[0030] I bBn is the boost current of ARCP converter branch n,

[0031] I on is the branch current of the ARCP converter branch n,

[0032] k IB is the multiplier, k IB ≥0,

[0033] I bB，min It is in I o A value of zero is considered to be the minimum necessary boost current.

[0034] In an embodiment, a power converter system comprises two or more ARCP converters, each of the ARCP converters comprising one or more ARCP converter phase legs, wherein the parallel connected ARCP converter legs are corresponding ARCP converter phase legs of the two or more converters connected in parallel.

[0035] In an embodiment, each of the two or more ARCP converters includes

[0036] a dc link having a first dc rail and a second dc rail, and

[0037] a series connection of at least two dc-link capacitors between two rails of the dc-link, the midpoint of the series connection forming a neutral point (NP) of the dc-link, and wherein

[0038] Each of the ARCP converter phase legs comprises:

[0039] a series connection of at least two main switching devices between a first DC voltage rail and a second DC voltage rail for alternately connecting the first dc-link rail and the second dc-link rail to the phase leg output or input by PWM modulation from a control device,

[0040] a resonant capacitor connected in parallel with each of the at least two main switching devices such that at least one terminal of the capacitor is connected to one of the dc-link rails or a phase leg output or input, and

[0041] a series connection of a resonant inductor and at least one bidirectional auxiliary switch between the phase branch output or input and the neutral point, and wherein

[0042] The control means is configured to control switching of the at least one bidirectional auxiliary switch to balance current sharing between the parallel connected ARCP converter phase legs by means of having an individual autonomous boost current adjustment for each of the parallel connected ARCP converter phase legs, wherein each individual boost current adjustment has the same predetermined dependency on the magnitude of the branch current of the respective ARCP converter leg.

[0043] In an embodiment, the control arrangement comprises converter-specific controllers for two or more ARCP converters, each of the converter-specific controllers being configured to provide autonomous individual boost current regulation for each of the ARCP converter phase legs of the respective ARCP converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In the following, the invention will be described in more detail by means of exemplary embodiments with reference to the accompanying drawings, in which

[0045] Figure 1 is a block diagram schematically illustrating an exemplary inverter system having a plurality of inverters connected in parallel;

[0046] Figure 2 is a schematic block diagram of an exemplary ARCP inverter system having a plurality of inverters connected in parallel;

[0047] Figure 3 is a schematic block diagram of an ARCP switch controller having a PWM modulator and ARCP control functions;

[0048] Figures 4A to 4F is a diagram illustrating an example of mode A commutation;

[0049] Figures 5A to 5D is a diagram illustrating an example of mode B commutation;

[0050] Figure 6 and 7 is a flow chart illustrating an example of autonomous boost current adjustment according to an exemplary embodiment of parallel-connected ARCP inverter legs in Mode A and Mode B commutation, respectively;

[0051] as well as

[0052] Figures 8A to 8E is a signal diagram illustrating an example of the effect of boost current regulation according to an exemplary embodiment of two parallel-connected ARCP inverter branches. DETAILED DESCRIPTION

[0053] A dc-ac or ac-dc converter (also referred to as an inverter or rectifier, respectively) converts power from a dc to ac or ac to dc power system at a desired voltage and frequency. Further, a dc-dc converter (such as a dc chopper) converts power from a dc to dc power system. Although an inverter and an inverter system are used as examples to describe embodiments, the present invention is similarly applicable to rectifiers and rectifier systems and dc-dc converters. Inverters and rectifiers can be completely similar in structure, and the control operation can also be similar, with the difference being the direction of power flow. When the converter operates as an inverter (dc / ac converter), it converts power from a dc system to an ac system, that is, the ac side of the converter is referred to as the output side, and the dc side is considered to be the input side. When the converter operates as a rectifier (ac / dc converter), it converts power from an ac system to a dc system, that is, the ac side of the converter is considered to be the input side, and the dc side is considered to be the output side. Further, the ac / dc and dc / dc converters are connected in a back-to-back configuration (i.e., the dc sides are connected together) between the two ac systems, with one of the converters operating in rectifier mode and the other in inverter mode, depending on the power flow direction. The operating mode of the converter can change during operation because the power flow can change.

[0054] Figure 1 A block diagram is shown schematically illustrating an exemplary inverter system having a plurality of (i.e., two or more) inverters INV1, INV2, ..., INVN, which are connected in parallel from their DC side (e.g., DC link) terminals (e.g., dc+, dc-) and their AC side terminals (e.g., U1, V1, W1, U2, V2, W2). In the illustrated example, inverters INV1 and INV2 are three-phase inverters providing three-phase outputs U1, V1, W1 and U2, V2, W2, but it should be understood that the parallel-connected inverters can be implemented as single-phase inverters, or generally include any number of inverter phases or phase legs. The parallel-connected inverters are composed of a voltage U dc The inverters are powered by a common DC voltage source 4 and supply power to a common AC load 6. A typical application area of ​​parallel-connected inverters powered by a common DC voltage source 4 is a motor drive with an AC motor as a common load 6. At each phase output of each inverter there is a non-zero impedance, such as Figure 1In the embodiment of the present invention, the output inductance Lo is represented by the inductance Lo in the output inductance Lo. The output inductance Lo may be intentionally implemented (e.g., a coil, a choke, etc.), or it may be just some leakage impedance of actual components and materials (such as wiring). The output inductance Lo may be substantially equal, but does not necessarily have to be equal. The corresponding phase outputs U1, U2, V1, V2 and W1, W2 of the inverters INV1 and INV2 connected in parallel are respectively connected to the common phase outputs U, V and W through the output inductance Lo. The corresponding phase outputs U1, U2, V1, V2 and W1, W2 of the inverters INV1 and INV2 connected in parallel may be connected together immediately after the output inductance Lo, and a single cable or multiple cables for each phase U, V and W may be used to connect the phase output to the load 6. Alternatively, each inverter INV1 and INV2 connected in parallel may be connected to the load 6 by means of its own wiring, and the phase outputs U1, U2, V1, V2 and W1, W2 may first be connected in parallel at the terminals of the load 6. The output phase current Io of each phase U, V, W supplied to the load 6 is obtained by combining the phase output currents I1, U2, V1, V2 and W1, W2 of the corresponding phase outputs of the inverters INV1 and INV2 connected in parallel. o1 and I o2 The parallel connected inverter modules INV1 and INV2 of the common DC supply can be controlled to behave like one high power inverter. This can be achieved by controlling the parallel inverter units with substantially the same control commands.

[0055] Each inverter module INV1 and INV2 can have one or more bridge circuits (full bridge or half bridge), one bridge circuit for each inverter phase or phase branch. The bridge circuits of the same phase of different inverter modules are connected in parallel with each other. Each bridge circuit can include multiple electronic switching elements or devices (such as insulated gate bipolar transistors (IGBTs) operating in switching mode), which means that by providing a high switching frequency control pulse (commonly referred to as a switch control signal or a gating signal), they are controlled to transition from a blocking state (off state) to a conducting state (on state), and vice versa. In the PWM modulation scheme, the width of the control pulse provided to the control input of the switching device is varied to provide the desired output of the inverter. The parallel-connected inverter modules INV1 and INV2 may have a common switch control that provides a switch signal or a gating signal to operate the switch devices of all the inverter modules, or more preferably, each of the parallel-connected inverter modules INV1 and INV2 may have a dedicated switch control unit 81 and 82 that provides a switch signal or a gating signal to operate the switch devices of the corresponding inverter modules, such as Figure 1As shown. Alternatively, the control may be distributed between a common switch control unit and an inverter module specific switch control unit. In the latter case, the inverter modules may be common inverter modules that may be connected in parallel in this manner (i.e., may be used as a single unit). In an embodiment, the switch controls 81 and 82 of the inverter modules INV1 and INV2 connected in parallel may be controlled by an advanced control system 86 with simultaneous and substantially similar control signals or commands.

[0056] In an embodiment, the advanced control system 86 may be a motor control.

[0057] Electronic switching devices (such as IGBTs) have a finite switching time, i.e., they cannot switch instantaneously from the conducting state to the blocking state and vice versa. During this transition interval (commutation), the switch is neither completely blocked nor completely conducting, so the voltage across the switch and the current through the switch are not zero. In other words, there is a conceivable overlap between the voltage waveform and the current waveform. This simultaneous presence of the voltage across the switch and the current through the switch means that power is dissipated within the device during this overlapping period. This power loss, known as "switching loss", reduces the efficiency of the inverter and generates major thermal stresses on the switching device when dissipated in the switch. The ability of the switching device to remove heat is limited. As the thermal load increases, the temperature rises, which in turn reduces performance. Soft switching techniques aim to eliminate switching losses by forcing the switch to be in zero voltage or zero current conditions during the switching event. Switching at the zero voltage crossing is called zero voltage switching (ZVS), while switching at the zero current crossing is called zero current switching (ZCS). The auxiliary resonant commutated pole (ARCP) inverter is one of the most promising approaches to soft switching inverters and has significant potential benefits in motor drive applications. ARCP inverters can be implemented using a variety of topologies, all of which have similar performance. The output voltage waveform during commutation can be shaped to be motor-friendly via appropriate resonant circuit parameter selection. This reduces stress in the motor insulation and bearings. The basic configuration and operation of ARCP are described, for example, in the article "The auxiliary resonant commutated pole converter" published by RWDe Doncker et al. in the IEEE-IAS Conference Proceedings 1990, pages 1228 to 1235 and US5047913.

[0058] According to one aspect of the present invention, the inverter system is an auxiliary resonant commutated pole (ARCP) inverter system, including a plurality (i.e., two or more) ARCP inverters INV1, INV2, ..., INVN connected in parallel from their DC side (e.g., DC link) input terminals and their AC side output terminals (e.g., U1, V1, W1, U2, V2, W2). In an embodiment, the ARCP inverter includes dc link capacitors of equal size connected in series between a negative (N) dc link rail and a positive (P) dc link rail on the dc link side of the inverter. At the midpoint of the capacitors (referred to as a neutral point (NP)), a neutral point potential U NP , which essentially corresponds to the voltage U between the dc rails dc Half of. Each phase of the inverter is associated with at least one resonant capacitor to force a zero voltage disconnect switching condition. Further, an auxiliary branch including a resonant inductor and (multiple) auxiliary switching devices is connected between the neutral point and the phase output to operate under zero current switching conditions. In ARCP, commutation is achieved by an auxiliary circuit system within a limited amount of time. The auxiliary circuit is used only when the output needs to be commutated from one voltage rail to another. In order to ensure that the inverter output voltage reaches at least the positive dc rail voltage and the negative dc rail voltage during each resonant commutation cycle, the boost current is added to the resonant current by appropriately controlling the conduction time of the auxiliary switching device. The predetermined boost current level in the inductor adds sufficient energy to the resonant operation to ensure that the output voltage attempts to overshoot the corresponding converter anti-parallel diode and clamps the output voltage to the corresponding rail voltage. Ideally, the main switch is turned on and off under zero voltage conditions, and the (multiple) auxiliary switches are turned on or off under zero current conditions, which reduces the switching losses that occur. Therefore, the switching frequency can be increased without a considerable loss penalty. The low acoustic noise of such a driver is appreciated in many applications. The high switching frequency also enables higher fundamental output frequencies and low distortion, making the ARCP topology attractive for high-speed drive applications.

[0059] A schematic diagram of an exemplary ARCP inverter system having a plurality of (ie, two or more) inverters INV1, INV2, ..., INVN connected in parallel is shown in FIG. Figure 2 The illustrated and described herein are provided to facilitate understanding of the operation and configuration of embodiments of the present invention with respect to an exemplary basic ARCP. It is not intended to limit embodiments of the present invention to the described and illustrated (multiple) exemplary ARCPs having only two parallel inverters. It should be appreciated that current sharing control according to embodiments of the present invention is generally applicable to any type of ARCP inverter and its derivatives and modifications, regardless of the specific design, configuration, and operational variations of the inverter from the basic ARCP inverter.

[0060] The ARCP inverters INV1 and INV2 connected in parallel may preferably be the same modules having the same configuration and operation. Figure 2 The illustrated exemplary ARCP inverter INV1 includes a DC link 2 (including a first dc link rail 22 and a second dc link rail 24), a first dc link capacitor C coupled to the first dc link rail 22 and a dc link midpoint (referred to as a neutral point NP1). d11 and a second dc link capacitor C coupled to the second dc link rail 24 and the neutral point NP1 d12 During operation, the first dc link rail 22 is at a first voltage, the so-called positive (P) dc link potential, and the second dc link rail 24 is at a second voltage, the so-called negative (N) dc link potential, lower than the first DC voltage, and the dc link midpoint NP1 is at a midpoint voltage, the so-called neutral point voltage U NP . dc link capacitor C d11 and C d21 The capacitance is constant and equal, for example, C d11 =C d21 =2C dc , so that the dc link capacitor C connected in series between the dc link rails 22 and 24 d1 and C d2 The voltage U provided at both ends 11 and U 21 are substantially equal, that is, the dc link voltage U between the dc link rails 22 and 24 dc =U 11 +U 21 Therefore, the neutral point voltage or potential U NP It also basically corresponds to the voltage U dc In other words, U NP =U dc / 2. The exemplary ARCP inverter INV2 includes a similar DC link 2 having dc link rails 22 and 24, a dc link capacitor C d21 and C d22 , voltage U 21 and U 22 and the dc link midpoint NP2.

[0061] The dc link rails 22 (positive dc link potential P) of the ARCP inverters connected in parallel are connected to each other and to a first voltage terminal U 2 of the common DC power source 4 . dc+ The dc link rails 24 (negative dc link potential N) of the ARCP inverter modules are connected to each other and to the second voltage terminal U of the common DC power supply 4. dc- Further, the neutral points NP1 and NP2 of the ARCP inverter modules connected in parallel may be connected to each other, such as Figure 2As shown. The connection of neutral points NP1 and NP2 is not necessary for the present invention, and they may not be connected to each other. The common dc power input to the parallel-connected ARCP inverter modules INV1 and INV2 can be obtained from any kind of dc power supply 4, such as from an existing power supply grid through a rectifier, or from a battery, a fuel cell, a photovoltaic array, etc. It should be understood that the dc link 2 can be provided in a variety of forms and can have a variety of voltages and other attributes. It should also be understood that the voltage difference between the positive dc link rail and the negative dc link rail is flexible, depending on how the dc link 2 is charged or how the dc link 2 is discharged through the connected circuit. For example, some embodiments can use a front-end isolation transformer and rectifier connected to the dc link, where the positive and negative rails are floating, and the differential voltage is typically in the range of 50V to 1500V, but in principle also in other voltages outside this range. In other embodiments, the positive rail, midpoint, or negative rail can be grounded to the ground. Preferably, the positive rail and the negative rail are balanced. For example, if the dc link neutral point NP is at 0VDC, the dc link rail 22 will be at a positive voltage (e.g., in the range of +25VDC to +500VDC, in the range of +150VDC to +400VDC, or other positive voltage range), and the dc link rail 24 will be at a negative voltage corresponding to the positive voltage (e.g., in the range of -25VDC to -500VDC, in the range of -150VDC to -400VDC, or other negative voltage range corresponding to other positive voltage ranges). It should be appreciated that the foregoing examples are a few of the many voltage amplitudes and polarities that may be present in or associated with the operation of the dc link 2. It should additionally be appreciated that the voltage amplitudes of the foregoing examples may be subject to fluctuations, margins of error, tolerances, and other variations, and may not be strictly fixed to the precise example amplitudes specified. It should be further appreciated that the term bus may be used in place of the term link, such that, for example, a reference to a dc link is understood to cover a dc bus, and vice versa.

[0062] Figure 2 The illustrated exemplary ARCP inverters INV1 and INV2 may be three-phase bridge ARCP inverters including power sections 10 for each phase or phase leg U1, U2, V1, V2, W1, and W2, respectively. U , 10 V and 10 W The operation and configuration of the inverters INV1 and INV2 are illustrated and described in more detail herein mainly with respect to one phase or phase leg U1 and U2, but the other phases or phase legs V1, V2, W1 and W2 of the inverters INV1 and INV2 may have the same operation and configuration. In the ARCP inverter INV1, the power section 10 of the phase legs U1, V1 and W1 U , 10V and 10 W can be connected to the positive dc link rail 22, the neutral point NP1 and the negative dc link rail 24 of the common dc link 2, thereby connecting to the negative (N) dc link potential, the neutral point (NP) and the positive (P) dc link potential, such as Figure 2 Each power section 10 U , 10 V and 10 W The output node 110 is connected to the output terminal 111 via a non-zero impedance (usually represented by an output inductor L in this paper). o1 The non-zero impedance may be composed of the impedance of the connecting cable or busbar, and it may also have additional components if necessary. In the ARCP inverter INV2, the power section 10 of the phase legs U2, V2 and W2 U , 10 V and 10 W The common dc link 2 may be connected to the inverter INV2 in a similar manner as in the inverter INV1. Each power section 10 of the inverter INV2 U , 10 V and 10 W The phase output node 110 is connected to the output terminal 110 via a non-zero impedance (usually represented by an output inductor L in this paper). o2 ) is connected to the corresponding phase of the ac load 6, so that each phase output of the inverter INV2 is connected in parallel with the corresponding phase output of the inverter INV1. It should be understood that although a three-phase ARCP inverter is illustrated as an example herein, the ARCP inverter can be implemented as a single-phase inverter, or generally includes any number of inverter phases or phase legs. Moreover, although a half-bridge ARCP inverter is illustrated as an example herein, the ARCP inverter can have other configurations, particularly a full-bridge configuration.

[0063] Figure 2 An exemplary half-bridge power section 10 of the illustrated ARCP inverter INV1 U Includes a pair of main or power switching devices S 11 and S 21 , which are coupled in parallel to the dc link rails 22 and 24 of the dc link 2. The first main switching device S 11 The second main switching device S may have a first terminal electrically coupled to the positive dc link rail 22 and a second terminal electrically coupled to the output node 110. 21 The first main switching device S is connected to the output node 110 and has a first terminal coupled to the negative dc link rail 24. 11 The first anti-parallel diode D is connected at both ends11 , and a second main switching device S between the output node 110 and the negative dc link rail 24 21 A second anti-parallel diode D is connected at both ends 21 Furthermore, the first resonant capacitor C 11 Operable with the first main switching device S 11 connected in parallel (ie, directly or via additional components, such as an active or passive damping circuit connected in series with the resonant capacitor), and a second resonant capacitor C 21 Operable with the second main switch device S 21 More generally, there may be one or more resonant capacitors connected in such a way that at least one terminal of the resonant capacitor(s) is connected to one of the dc link rails (P, NP, N) and the other terminal(s) are operably connected to the phase output node 110. The first main switching device S 11 Operable to switch on and off in response to inputs from control and driver circuitry such as Figure 2 The inverter-specific ARCP switch controller 81 shown receives the control signal(s) G 11 , respectively connecting and disconnecting the dc link rail 22 and the output node 110. The second main switching device S 21 Operable to switch on and off in response to control signal(s) G received from control and driver circuitry such as ARCP switch controller 81 21 , respectively connect and disconnect the dc link rail 24 and the output node 110. All power sections 10 of the phase legs U1, V1 and W1 in the ARCP inverter INV1 U , 10 V and 10 W can be controlled by the same inverter-specific switch controller 81. Similarly, Figure 2 An exemplary half-bridge power section 10 of the illustrated ARCP inverter INV2 U Includes a pair of main or power switching devices S 12 and S 22 , the first anti-parallel diode D 12 and the first resonant capacitor C 12 , the second anti-parallel diode D 22 , the second resonant capacitor C 22 and a switch control signal G from a control and driver circuit system (such as an inverter-specific ARCP switch controller 82) 12 and G 22 All power sections 10 of the phase legs U2, V2 and W2 in the ARCP inverter INV2 U , 10 V and 10W can be controlled by the same inverter-specific switch controller 82. In an embodiment, the switch device S 11 , S 12 , S 21 and S 22 It may be an insulated gate bipolar transistor (IGBT) or another type of semiconductor switching device, such as an integrated gate commutated thyristor (IGCT), a metal oxide semiconductor field effect transistor (MOSFET), or a silicon carbide (SiC) MOSFET, to name a few examples.

[0064] In operation, when the first main switch S 11 / S 12 When turned on (to the on state), the first switch current I s11 / I s12 can flow between the dc link rail 22 and the output node 110. Similarly, when the second main switching device S 21 / S 22 When turned on (to the on state), the second switch current I s21 / I s22 can flow between the output node 110 and the dc link rail 24. On the other hand, when the first main switching device S 11 / S 12 When disconnected (to non-conducting state), the first switch current I s11 will not flow in the forward direction of the switch between the dc link rail 22 and the output node 110, although the current I d11 / I d12 The current can flow through the first main switching device S in the switching reverse direction. 11 / S 12 The first anti-parallel diode D 11 / D 12 Similarly, when the second main switching device S 21 / S 22 When disconnected (to non-conducting state), the second switch current I s21 / I s22 will not flow in the forward direction of the switch between the output node 110 and the dc link rail 24, although the current I d21 / I d22 The current can flow through the second switching device S in the reverse switching direction. 21 / S 22 The anti-parallel diode D 21 / D 22 Therefore, by switching on and off and closing the first main switching device S 11 / S 12 and the second main switchgear S 21 / S 22, the output voltage at the output node 110 will be controlled or commutated to the voltage P from the dc link rail 22 or the voltage N from the dc link rail 24. The resonant capacitor C 11 / C 12 and C 21 / C 22 The purpose of this is to limit the voltage slew rate at the output node; this ensures that the main switching device S 11 / S 12 and S 21 / S 22 The voltage across the two ends is U c11 / U c12 and U c21 / U c22 It does not change significantly during disconnection, so that the main switching device disconnects at essentially zero voltage.

[0065] Figure 2 An exemplary half-bridge power section 10 of the illustrated ARCP inverter INV1 U The auxiliary circuit also includes a resonant inductor L1 and a bidirectional auxiliary switch S1 connected in series between the neutral point NP1 and the output node 110. aux1 . Auxiliary switch S aux1 The auxiliary switch S is operable to switch on and off, thereby connecting and disconnecting the neutral point and the output node 110, respectively, in response to control signals received from a control and driver circuit system (such as the ARCP switch controller 81). aux1 The bidirectional auxiliary switch S may behave like a bidirectional thyristor: it may be triggered to conduct and to turn off when or before the current attempts to reverse direction. aux1 It may be implemented with a pair of common switching devices connected back to back, for example in a common emitter or common collector configuration, and provided with an anti-parallel diode. Figure 2 An exemplary auxiliary switch S is shown. aux1 , comprising a first auxiliary switching device Sa in common emitter series connection 11 and the second auxiliary switching device Sa 21 , connected to the first auxiliary switch device Sa 11 The first anti-parallel diode Da at both ends 11 and connected to the second auxiliary switching device Sa 21 The second anti-parallel diode Da at both ends 21 . In response to the control and driver circuit system (such as Figure 2 The control signal Ga received by the ARCP switch controller 81 is shown in FIG. 11 and Ga 21 , two auxiliary switchgear Sa 11 and Sa 21One of the auxiliary switching devices is turned on and conducts once, and the two anti-parallel diodes Da 11 and Da 21 The same is true for an antiparallel diode in . In each case, the auxiliary current I a1 The auxiliary switching device in the auxiliary circuit is switched on and off at zero current. 11 The second switching device Sa is switched on and 21 When disconnected, the auxiliary current I a1 Will flow through Sa in one direction 11 and Da 21 When the first auxiliary switching device Sa 11 The second switching device Sa is disconnected and 21 When turned on, the auxiliary current I a1 Will flow through Sa in the opposite direction 21 and Da 11 The auxiliary circuit is used only when it is required that the output node 110 be commutated from one voltage rail to another. The auxiliary circuit functions by generating a current pulse that, in combination with the resonant capacitor, is used to slew the output voltage on the output node 110. Similarly, Figure 2 An exemplary half-bridge power section 10 of the illustrated ARCP inverter INV2 A The auxiliary circuit also includes a resonant inductor L2 and a bidirectional auxiliary switch S connected in series between the neutral point NP2 and the output node 110. aux2 In an embodiment, the auxiliary switch S aux2 Can be connected with auxiliary switch S aux1 A similar approach is implemented using a pair of ordinary switches and anti-parallel diodes. Figure 2 An exemplary auxiliary switch S is shown. aux2 , comprising a first auxiliary switching device Sa in series connection 12 and the second auxiliary switching device Sa 22 , connected to the first auxiliary switch device Sa 12 The first anti-parallel diode Da at both ends 12 and connected to the second auxiliary switching device Sa 22 The second anti-parallel diode Da at both ends 22 . In response to the control and driver circuit system (such as Figure 2 The control signal Ga received by the ARCP switch controller 82 is shown 21 and Ga 22 , two auxiliary switchgear Sa 12 and Sa 22 One of the auxiliary switching devices is turned on and conducts once, and the two anti-parallel diodes Da12 and Da 22 The same is true for an anti-parallel diode in .

[0066] Figure 1 and 2 The ARCP switch control 81 ... 8 shown n Generally refers to any control functions, logic, hardware, firmware, software, etc. required to control the main switching devices and auxiliary switching devices in (multiple) ARCP phase legs based on one or more PWM signals. Given the PWM signal, a standard hard-switched inverter does not require much additional logic to form a complete inverter drive system. At a minimum, the direct PWM signal is sent to one switch, and the complement of the PWM input signal is sent to the other switch in the phase. On the other hand, ARCP requires more than just PWM modulation and control: it requires additional more complex control, especially due to the auxiliary circuits and (multiple) auxiliary switches.

[0067] Figure 3 8 is a schematic block diagram of an exemplary embodiment of an ARCP switch controller 81 having a separate PWM modulator 82 and an ARCP control function 84. In the illustrated example, the ARCP control 84 may include a dedicated ARCP control module 841. U ,841 V and 841 W , which is adapted to be based on a corresponding PWM signal PWM received from the PWM modulator 82 U 、PWM V and PWM W Provide control signals such as G to each ARCP phase leg U1, V1 and W1 respectively. 11 , G 21 , G a11 and G a21 ARCP control 84 or corresponding ARCP control module 841 U ,841 V and 841 W For each phase leg U1, V1 and W1, functions such as activating the correct auxiliary switch before commutating the main switch, controlling the boost time, ensuring that the main switch switches at substantially zero voltage, ensuring that the auxiliary switch switches at zero current, initially starting the switching sequence at power-up, etc. Depending on the selected ARCP control strategy, various sensing feedbacks FB may be required to implement the control algorithm, such as feedback from a main switch zero voltage sensor, an auxiliary switch zero current sensor, an auxiliary current sensor, an output (load) current sensor, a dc link voltage sensor, a (multiple) dc link capacitor sensor, a neutral point voltage sensor, etc.

[0068] As used herein, when the auxiliary circuit participates in commutation and provides a boost current, the output current I o From the diode to the switch (for example, the current I o1 From the diode D 21 Reversing to switch S 11 ) is called Mode A, and the output current I o From the switch to the diode (for example, the current I o1 From switch S 11 Commutation to diode D 21 ) is called Mode B. When the output current I o The high output current I o The mode of commutation from switch to diode is referred to herein as Mode O.

[0069] Mode A commutation: If the output current I o is positive (Io>0), and the output voltage U o From the potential N (dc link 24) to the potential P (dc link 22), the lower diode D 21 and D 22 The current (I d21 and I d22 ) are switched to the upper switch S 11 and S 12 If the output current I o is negative (Io<0), and the output voltage U o From the potential P (dc link 22) to the potential N (dc link 24), the upper diode D 11 and D 12 The current (I d11 and I d12 ) are switched to the lower switch S 21 and S 22 .

[0070] Mode B commutation: If the output current I o is positive (Io>0), and the output voltage U o From the potential P (dc link 22) to the potential N (dc link 24), the upper switch S 11 and S 12 The current is commutated to the lower diode D 21 and D 22 If the output current I o is negative (Io<0), and the output voltage U oFrom the potential N (dc link 24) to the potential P (dc link 22), the lower switch S 21 and S 22 The current is commutated to the diode D 11 and D 12 .

[0071] Hereinafter, examples of typical ARCP commutation in modes A and B are briefly described for a single phase, for example, ARCP phase V1, of the ARCP inverter INV1. Commutation modes A and B of the corresponding ARCP phase V2 of the ARCP inverter INV2 are similar.

[0072] As an example of mode A, refer to Figures 4A to 4F Describes the positive output current I o1 (Io>0) from the lower diode D 21 To the upper main switch S 11 And the output voltage U o Commutation from N to P.

[0073] Diode D 21 On-state output current I o1 (=I d21 ), diode D 21 Supply output current I o ( Figure 4A ), and switch S 11 , S a11 and S a21 Not conducting (off); during commutation S 21 Disconnect and S 11 Connected.

[0074] The commutation command is at time t Ao Auxiliary switch Sa 11 At time interval t wA1 After that, it is turned on (at zero current), which marks the boost interval t bA1 The neutral point voltage U NP1 is applied across the resonant inductor L1, which results in an auxiliary current I through the resonant inductor L1 a1 Linear ramp ( Figure 4C ), and diode D 21 The current I d21 Accordingly, as I d21 =I o1 -I a1 And reduce ( Figure 4A ). In order to disconnect the diode D 21 , auxiliary current I a1 The output current must be increased to I o1 level, or even exceeds (through the boost current IbA1 ), so that the final I a1 =I o1 +I bA1 The total inductor current I a1 The boost current portion I bA1 is transferred to the diode D 21 Parallel switch S 21 ( Figure 4B ), while the load 6 takes its own current, i.e., the output current I o1 .

[0075] Switch S 21 At time interval t bA1 After disconnection ( Figure 4B ), which marks the boost interval t ba1 The output voltage U c21 From N (zero) to P (all U dc ) starts the commutation swing. The boost current I bA1 must be large enough to force the output potential to swing from N to P, thereby applying a load to capacitor C 21 Charges and charges the capacitor C 11 If there is a slight imbalance in the half of the dc link voltage, causing U 21 11 , more boost current is needed, and if U 21 >U 11 , then less boost current is sufficient.

[0076] U C21 From Zero to U dc The interval of the swing has a duration t sA1 .

[0077]

[0078] in

[0079] I pA1 is the peak value of the resonant portion of the inductor current

[0080]

[0081] β is the phase angle

[0082] β=sin -1 (I BA / I pA ), (3)

[0083] And in Figure 2 In the exemplary topology B shown, C=C 11 +C21. The average voltage change rate is du / dt = U dc ​ / t sA1 .

[0084] WhenU c21 At time interval t sA1 After reaching U dc And U c11 When reaching zero ( Figure 4D ), the auxiliary current Ia1 exceeds the output current I o1 The diode D is partially turned on 11 , and is called I tA1 ( Figure 4C and 4D ). As long as U c21 Already reached U dc , you can turn on the switch S 11 . Boost time t bA1 It can be preferably arranged so that the current I tA1 minimizes the value close to zero. Thus, D 11 The losses and reverse recovery current as well as the duration of commutation will be minimized. This strategy reduces the window t tAx Therefore, the precise timing of S11 turning on is critical.

[0085] Because the diode D 11 and switch S 11 The output voltage is clamped to the positive dc potential P, so the inductor current I a1 In t tA decays linearly to zero during the time interval ( Figure 4C ).

[0086] Current I d11 At time t tAx First from I tA1 decays to zero, after which the switching current I s11 Increase linearly from zero to the load current level I o1 ( Figure 4F ), while I a1 Continue from I o1 Decrease towards zero ( Figure 4C ), after which the auxiliary diode Da21 is disconnected and the commutation sequence ends.

[0087] From the auxiliary switch Sa 21 The total duration from switching on to the completion of commutation in mode A is t A =t bA1 +t sA1 +t tA1 During this time interval, there is current in the auxiliary branch.

[0088] As an example of mode B, refer to Figures 5A to 5D Describes the positive output current Io1 (Io>0) from the upper main switch S 11 To the lower diode D 21 Commutation and output voltage U o Swing from N to P.

[0089] Switch S 11 On-state output current I o1 (I o1 =I s11 )( Figure 5A ), and switch S 21 , S a11 and S a21 Non-conducting (off); during commutation, the upper switch S 11 The lower diode D is disconnected and 21 Connected.

[0090] The commutation command is at time t B0 Arrived. During the waiting time t wB1 After that, the auxiliary switch S a21 is turned on, and the boost current I bB1 (In the negative direction in inductor L1, in S 11 (in the positive direction) linearly constructs a period of time t bB1 ( Figure 5B ).

[0091] The boost current is added to the switch S 11 The load current is above t bB1 At the end, the total current I is disconnected s11 =I o1 +I bB1 ( Figure 5A ). c11 From Zero to U dc The swing starts ( Figure 5C ). The output potential swing from P to N is determined by I o1 The linear part caused by I bB1 The duration of the swing is t sB1

[0092]

[0093] in

[0094] I pB1 is the peak value of the resonant portion of the inductor current,

[0095]

[0096] γ is the phase angle,

[0097]

[0098] And C = C 11 +C 21 The average voltage change rate is du / dt = U dc / t sB1 .

[0099] At the end of the swing, the residual current I a1 Initially added to the diode D 21 The output current I o1 Above, I d21 =I o1 +I tB When the inductor current is at time t tB When it reaches zero again, the diode current decays linearly to its final value I o ( Figure 5B and 5D ). In mode B, from trigger S a The total duration of the commutation to completion is t B =t bB +t sB +t tB .

[0100] The above description of modes A and B assumes that I o The positive direction of I o (I o <0) is the same, except that S 11 and S 21 , D 11 and D 21 and U c11 and U c21 The action is exchanged from mode A to mode B and vice versa.

[0101] For corresponding phases in a plurality of ARCP inverters connected in parallel, for example, ARCP phase V1 of ARCP inverter INV1 and ARCP phase V2 of ARCP inverter INV2, ARCP commutation may be initiated at the same time by similar commutation commands, for example, for mode A commutation at time t Ao , and for mode B commutation at time t Bo Ideally, the output current I of the ARCP inverters connected in parallel is o1 and I o2 However, the ideal behavior during commutation would require that the corresponding switches in the inverters operating in parallel (e.g., S 11 and S 12 ) When the output potential U oInverters connected in parallel should be switched on at the same moment when commutating from, for example, N to P. Likewise, they should be switched off at the same moment when commutating the output potential from P to N. Unfortunately, inverters operated in parallel do not behave similarly, e.g. due to parameter differences in the switching components and different impedances in the parallel branches, the amplitudes of the output currents from the parallel inverters may not be equal. In other words, there may be uneven current sharing between the inverters. For thermal and economic reasons, it is crucial that the inverters connected in parallel share the load current as evenly as possible.

[0102] According to one aspect of the present invention, current sharing between multiple parallel-connected ARCP inverter branches is balanced by having individual autonomous branch-specific boost current adjustments for each of the parallel-connected ARCP inverter branches, the individual autonomous branch-specific boost current adjustments being used to adjust the boost current between the differential output currents (e.g., I do =I o1 -I o2 ) to reduce the boost current, and each individual boost current adjustment depends only on the corresponding ARCP inverter branch (e.g. Figure 2 The magnitude of the branch output current of the phase branch U1 or U2 in the o1 |or|I o2 |). Ideally, when current sharing is balanced, the ARCP inverter branches connected in parallel (e.g. Figure 2 The output currents of the phase legs U1 and U2) in the circuit are equal, and their difference or differential output current I do is zero (for example, I do =I o1 -I o2 =0). Advantageously, the parallel ARCP inverter branches do not need to know each other's currents or differential currents, but balanced current sharing by adjusting the boost current can be implemented relying only on information that is readily available individually in each branch in the parallel connected branches: output current magnitude (e.g., I o1 or I o2 ) and optionally further information, such as one or more dc voltages (e.g. dc link voltage U dc Or NP voltage U dc / 2, or the dc link capacitor voltage U 11 , U 21 or U 12 , U 22). The benefits of autonomous (or distributed or decentralized) control derive from avoiding the need to exchange information between higher level control and lower level control entities or between lower level control entities (such as switching controls 81 and 82). Autonomous control systems are also typically simpler and more modular than centralized control systems, and are therefore easier to understand and maintain. Further, in order to keep the implementation cost effective, it is preferred that there are no additional component selection requirements or communication requirements between inverter units connected in parallel, i.e., normal "single inverter units" (such as inverters INV1 and INV2) can be connected in parallel in this way. On the other hand, the challenge is obvious: the autonomous units must operate with limited information.

[0103] In an embodiment, individual boost current adjustments may be dependent on the corresponding ARCP inverter branch (eg Figure 2 The branch output current (e.g. |I o1 |or|I o2 |) so that in ARCP commutation mode A, the higher the branch output current, the higher the boost current (for example, I bA1 or I bA2 ) and / or the rise time (e.g. t sA1 or sA2 ) is shorter, and in ARCP commutation mode B, the higher the branch output current, the higher the boost current (for example, I bA1 or I bA2 ) and / or the boost time (e.g. t sA1 or sA2 ) is longer.

[0104] In an embodiment, current sharing is balanced by manipulating the effective volt-second difference via voltage swing time adjustment, which is performed by each of the parallel connected inverter branches (e.g. Figure 2 This is produced by separate autonomous boost current regulation in the phase branches U1 and U2).

[0105] In an embodiment, the individual autonomous boost current adjustments may be dependent on the corresponding ARCP inverter branches (eg Figure 2 The magnitude of the branch output current of the phase branch U1 or U2 in the o1 |or|I o2|), such that in ARCP commutation mode A, the higher the branch output current, the later and / or slower the output voltage swings, and such that in ARCP commutation mode B, the higher the branch output current, the earlier and / or faster the output voltage swings. If the output currents of the branches have equal amplitudes, the autonomous boost current adjustments of the branches will (independently of each other) cause their output voltages to commutate to swing in an approximately similar manner, such as approximately simultaneously and / or at the same rate. If the output currents of the branches have different amplitudes, the autonomous boost current adjustments of the branches will (independently of each other) cause their output voltages to commutate, depending on their output current amplitudes to reduce the differential output current (e.g., I do =I o1 -I o2 ) in different ways. In other words, the output voltage (e.g., U c21 and U c22 , cited Figure 2 These differences in the timely behavior of the N potential in the output current will tend to reduce the output current difference I do The direction of the loop inductance (ΔL = L o1 +L o2 ) produces an effective volt-second difference.

[0106] In an embodiment, the boost current is adjusted by adjusting the boost time and thereby adjusting the timely behavior of the output voltage swing, such as the voltage swing time. Adjusting the boost time will cause the boost current to change as desired, thereby affecting the voltage swing time. sA and t sB The presented equations (1) and (4) indicate that the swing time depends on the boost current I bA and I bB Further, it can be shown that the swing time t of the ARCP inverter branches INV1 and INV2 in commutation mode A sA1 and t sA2 The difference between the ARCP inverter branches INV1 and INV2 in commutation mode B is shown in Figure 2. sB1 and t sB2 The difference in the total timing difference Δt between the ARCP inverter branches INV1 and INV2 for commutation modes A and B respectively A and Δt B Further, it can be shown that the total timing difference Δt A and Δt B The differential output current I do The increment ΔI doA and ΔI doB Related.

[0107] In an embodiment, each individual boost current adjustment has the same predetermined dependency on the magnitude of the branch output current of the corresponding ARCP inverter branch. In other words, all parallel connected ARCP branches may have a common rule that defines a variable boost current for each individual branch as a function of the output current magnitude of the individual branch.

[0108] In an embodiment, in ARCP commutation mode A, the boost current in each parallel-connected ARCP inverter branch is autonomously reduced from a reference value according to an actual measured value of the branch output current amplitude of the corresponding branch, such as Figure 6 As illustrated in steps 62 and 64 of the exemplary flow chart shown, an inverter branch having a higher output current magnitude will thereby reduce its boost current more than an inverter branch having a lower branch output current magnitude.

[0109] For example, the autonomous regulation of the boost current (output current from diode commutation to switch) in ARCP mode A can be achieved by introducing a factor k in the calculation of the reference boost time in both branches. IA To implement, the factor k IA is positive and less than 1 (can be a constant), as I o The multiplier is such that the reference boost time will be calculated as follows:

[0110] t bA，r1 =(k IA |I o1 |+I bA，r )L / U 21 (7)

[0111] t bA，r2 =(k IA |I o2 |+I bA，r )L / U 22 (8)

[0112] in

[0113] t bA.r1 is the reference boost time of ARCP inverter branch U1;

[0114] t bA.r2 is the reference boost time of ARCP inverter branch U2;

[0115] I o1 is the branch output current of ARCP inverter branch U1;

[0116] I o2 is the branch output current of ARCP inverter branch U2;

[0117] k IA is the multiplier, 0≤kIA <1;

[0118] I bA，r is the reference boost current;

[0119] U 21 is the dc link capacitor C of branch U1 d21 the dc voltage across it; and

[0120] U 22 is the dc link capacitor C of branch U2 d22 The dc voltage across the terminals.

[0121] Now, the actual boost current I in branches U1 and U2 is bA1 and I bA2 will be

[0122]

[0123]

[0124] The difference in boost current between branches U1 and U2 will be

[0125] I bA1 -I bA2 =(|I o1 |-|I o2 |)(k IA -1) (11)

[0126] Because k IA <1 and |I o1 |>|I o2 |, then |I bA2 |>|I bA1 |.

[0127] In an embodiment, the voltage U dc / 2 to replace the voltage U in equations (7) to (10) 21 and U 22 , assuming that NP imbalance will be insignificant or controlled to an insignificant level.

[0128] In an embodiment, in ARCP commutation mode B, the boost current in each parallel-connected ARCP inverter branch is autonomously increased from a reference value according to the actual measured value of the branch output current of the corresponding branch, such as Figure 7 As illustrated in steps 72 and 74 of the exemplary flow chart shown, the inverter branch with the higher output current will increase its boost current more than the inverter branch with the lower branch output current.

[0129] For example, autonomous regulation of the boost current (output current from switch commutation to the diode) in ARCP mode B can be achieved by utilizing the term k that varies with the magnitude of the output current. IB |I|o) controls the reference boost current I bB，r To implement. Factor k IB is a positive number (can be a constant). Now, the inverter branch determines its corresponding boost current reference as

[0130] I bB，r1 =I bB，min +k IB |I o1 | (12)

[0131] I bB，r2 =I bB，min +k IB |I o2 | (13)

[0132] in

[0133] I bB.r1 is the reference boost current of ARCP inverter branch U1;

[0134] I bB.r2 is the reference boost current of ARCP inverter branch U2;

[0135] I o1 is the branch output current of ARCP inverter branch U1;

[0136] I o2 is the branch output current of ARCP inverter branch U2;

[0137] k IB is the multiplier, k IB ≥0; and

[0138] I bB，min It is in I o A value of zero is considered to be the minimum necessary boost current.

[0139] Reference boost time t of inverter branches U1 and U2 bB，r1 and t bB，r2 can be calculated separately as usual:

[0140] t bB，r1 =I bB，r1 L / U 11 (14)

[0141] t bB，r2 =I bB，r2 L / U 12 (15)

[0142] in

[0143] U 11 is the dc link capacitor C of branch U1 d11 the dc voltage across it; and

[0144] U 12 is the dc link capacitor C of branch U2 d12 The dc voltage across the terminals.

[0145] Now, the actual boost current I in branches U1 and U2 is bA1 and I bA2 will be

[0146] I bB1 =I bB，r1 (16)

[0147] I bB2 =I bB，r2 (17)

[0148] The difference in boost current between branches U1 and U2 is

[0149] I bB1 -I bB2 =I bB，r1 -I bB，r2 =k IB (|I o1 |-|I o2 |) (18)

[0150] Because k IB >1 and |I o1 |>|I o2 |, then |I bB2 |>|I bB1 |.

[0151] In an embodiment, the voltage U dc / 2 to replace the voltage U in equations (14) to (15) 11 and U 12 , assuming that NP imbalance will be insignificant or controlled to an insignificant level.

[0152] Figures 8A to 8E A signal diagram is shown illustrating the voltage drop according to two ARCP inverter branches connected in parallel (eg Figure 2 1 and 2) of the inverter branches U1 and U2 shown in FIG. 1 . More specifically, Figures 8A to 8Eis a simplified signal diagram illustrating the principle of controlling the swing time via a reduction in boost current in mode A and an increase in boost current in mode B proportional to the output current amplitude and how the adjustment of the boost current level affects the speed of voltage commutation. Otherwise, the ARCP commutation in modes A and B of each branch may be normal, for example as described above with reference to Figures 4A to 4F 5A to 5D are described for a single phase (eg, ARCP phase V1 ) of the ARCP inverter INV1 . Figures 4A to 4F The same reference symbols in 5A to 5D and 8A to 8E refer to the same voltages, currents and times.

[0153] Fig. 8A Depicted are the same carrier cycle-based PWM commands (initiating commutation mode B / mode A) received by the autonomous boost current regulation units (e.g., switch controls 81 and 82) of the parallel-connected branches (e.g., branches U1 and U2) of the ARCP inverter (e.g., INV1 and INV2) from a higher-level controller (e.g., motor control 86). Figure 8B and 8D The auxiliary current I of branches U1 and U2 are depicted respectively a1 and I a2 For simplicity, the auxiliary current I a1 and I a2 is extracted to show only the boost interval t bB1 and t bB2 or bA1 and t bA2 . Figure 8C and 8E The output voltage U of branches U1 and U2 are depicted respectively. c21 and U c22 For simplicity, U c21 and U c22 The voltage swing is represented by a linear slope. The output current I o1 and I o2 It is assumed to be negative in the figures. o1 The magnitude is greater than I o2 The amplitude.

[0154] The command for mode B commutation is given at time t B0 Arrives at ARCP branches U1 and U2. During the waiting time t wB1 After that, the auxiliary switch S a11 is turned on, and the auxiliary current I a1 Linearly builds to level I bB1 The boost time t bB1 ( Figure 8B ), and similarly, during the waiting time t wB2 After that, the auxiliary switch S a12 is turned on, and the auxiliary current Ia1 Linearly builds to level I bB2 The boost time t bB2 ( Fig.8D ). Boost time t bB2 and t bB2 and / or the corresponding boost current I bB1 and I bB2 It can be calculated according to, for example, equations (12) to (17). o1 Greater than I o2 , boost time t bB1 Longer than the boost time t bB2 , and the boost current I bB1 Higher than the boost current I bB2 , which leads to U C22 The swing time t sB2 Slower than U C21 The swing time t sB1 ( Figure 8B and 8E ).

[0155] The command for mode A commutation is given at time t A0 Arrives at ARCP branches U1 and U2. During the waiting time t wA1 After that, the auxiliary switch S a21 is turned on, and the auxiliary current I a1 Linearly build up to the boost time t bA1 ( Figure 8B ), and similarly, during the waiting time t wA2 After that, the auxiliary switch S a22 is turned on, and the auxiliary current I a2 Linearly build up to the boost time t bA2 ( Fig.8D ). Boost time t Ba1 and t bA2 and / or the corresponding boost current I bA1 and I bA2 It can be calculated according to, for example, equations (7) to (10). o1 Greater than I o2 , boost time t bA1 Longer than the boost time t bA2 , and the boost current I bA1 Higher than the boost current I bA2 , which leads to U C21 The swing time t sA1 Slower than U C22 The swing time t sA2 ( Figure 8B and 8E ).

[0156] Voltage swing U c21 and U c22 The effective (pulse) duration t peff1 and t peff2 Respectively Fig. 8E As shown at the bottom of the figure. peff1 T peff2 long, so the output current I o1 will have a positive increment, thus reducing its magnitude (because I o1 is negative). Similarly, the output current I o2 will have a negative increment, increasing its magnitude (because I o2 is negative).

[0157] The switch control and boost current adjustment techniques described herein can be implemented by various components. For example, these techniques can be implemented in hardware (one or more devices), firmware (one or more devices), software (one or more modules), or a combination thereof. For firmware or software, the implementation method can be implemented by a module (e.g., a program, a function, etc.) that performs the functions described herein. The software code can be stored in any suitable processor / (multiple) computer-readable data storage medium or (multiple) memory unit and executed by one or more processors / computers. The data storage medium or memory unit can be implemented within the processor / computer or outside the processor / computer, in which case it can be communicatively coupled to the processor / computer via various components known in the art. In addition, the components of the system described herein can be rearranged and / or envisioned by additional components to facilitate the realization of various aspects, objectives, advantages, etc. described therein, and they are not limited to the precise configurations set forth in the given figures, as will be appreciated by those skilled in the art.

[0158] The description and related drawings are intended only to illustrate the principles of the present invention by way of example. Based on this description, various alternative embodiments, variations and changes will be apparent to those skilled in the art. The present invention is not intended to be limited to the examples described herein, but the present invention may vary within the scope and spirit of the appended claims.

Claims

1. A power converter system, comprising: two or more converter branches connected in parallel between a common dc system and a common ac system or between two common dc systems, wherein commutation of the converter branches connected in parallel is initiated by simultaneous commutation commands, control means configured to balance current sharing between the converter branches connected in parallel, wherein the converter branches connected in parallel are auxiliary resonant commutated pole ARCP converter branches, in particular ARCP half-bridge branches, and wherein the control device is configured to balance the current sharing between the ARCP converter branches connected in parallel by means of having for each of the ARCP converter branches connected in parallel an individual autonomous branch specific boost current adjustment for adjusting the boost current in a direction of a decreasing differential output current, wherein each individual boost current adjustment depends only on the amplitude of the branch current of the respective ARCP converter branch.

2. The power converter system of claim 1 , wherein each individual boost current adjustment depends on the branch current of the corresponding ARCP converter branch to autonomously adjust the boost current and / or boost time of the corresponding ARCP converter branch connected in parallel, and / or the timely behavior of the voltage swing of the corresponding ARCP converter branch connected in parallel.

3. The power converter system of claim 1 , wherein each individual boost current adjustment is configured to depend on the magnitude of the branch current of the corresponding ARCP converter branch, such that in ARCP commutation mode A, the higher the magnitude of the branch current, the later and / or slower the voltage swing, and in ARCP commutation mode B, the higher the magnitude of the branch current, the earlier and / or faster the voltage swing.

4. The power converter system of claim 1 , wherein each individual boost current adjustment is configured to depend on the magnitude of the branch current of the corresponding ARCP converter branch, such that in ARCP commutation mode A, the higher the magnitude of the branch current, the lower the boost current and / or the shorter the boost time, and in ARCP commutation mode B, the higher the magnitude of the branch current, the higher the boost current and / or the longer the boost time. 5 . The power converter system of claim 1 , wherein each individual boost current adjustment has the same predetermined dependency on the branch current of the corresponding ARCP converter branch.

6. The power converter system according to claim 1, wherein: In ARCP commutation mode A, the boost current in each parallel-connected ARCP converter branch is autonomously reduced from a reference value depending on the actual value of the branch current of the corresponding branch, in such a way that a converter branch with a higher output current will reduce its boost current more than a converter branch with a lower branch current.

7. The power converter system of claim 1 , wherein in ARCP commutation mode A, each individual boost current adjustment depends on the magnitude of the branch current of the corresponding ARCP converter branch approximately according to the following equation, wherein I bAn =|I on |(k IA -1)+I bA,r , n is the index, I bAn is the boost current of the ARCP converter branch n, I on is the branch current of the ARCP converter branch n, k IA is the multiplier, 0≤k IA <1, I bA,r is the reference boost current.

8. The power converter system of claim 1 , wherein in ARCP commutation mode B, the boost current in each parallel-connected ARCP converter branch is autonomously increased from a reference value according to an actual value of the branch current of the corresponding branch, in such a way that a converter branch with a higher branch current will increase its boost current more than a converter branch with a lower branch current.

9. The power converter system of claim 1 , wherein in ARCP commutation mode B, each individual boost current adjustment depends on the magnitude of the branch current of the corresponding ARCP converter branch approximately according to the following equation, I bBn =I bB,min +k IB |I on |, in n is the index, I bBn is the boost current of the ARCP converter branch n, I on is the branch current of the ARCP converter branch n, k IB is the multiplier, k IB ≥0, I bB,min It is in I o A value of zero is considered to be the minimum necessary boost current.

10. The power converter system of claim 1, wherein the power converter system comprises two or more ARCP converters, each of the ARCP converters comprising one or more ARCP converter phase legs, wherein the ARCP converter legs connected in parallel are corresponding ARCP converter phase legs of the two or more converters connected in parallel.

11. The power converter system of claim 10, wherein each of the two or more ARCP converters comprises: a dc link having a first dc rail and a second dc rail, and a series connection of at least two dc-link capacitors between two rails of the dc-link, a midpoint of the series connection forming a neutral point (NP) of the dc-link, and wherein each of the ARCP converter phase legs comprises: a series connection of at least two main switching devices between a first DC voltage rail and a second DC voltage rail for connecting the first dc-link rail and the second dc-link rail alternately to the phase leg output or input by PWM modulation from a control device, a resonant capacitor connected in parallel with each of said at least two main switching devices in such a way that at least one terminal of said capacitor is connected to one of said dc-link rails or to said phase leg output or input, as well as a series connection of a resonant inductor and at least one bidirectional auxiliary switch between the phase branch output or input and the neutral point, and wherein The control device is configured to control switching of the at least one bidirectional auxiliary switch to balance the current sharing between the ARCP converter phase legs connected in parallel by means of having an individual autonomous boost current adjustment for each of the ARCP converter phase legs connected in parallel, wherein each individual boost current adjustment has the same predetermined dependency on the magnitude of the branch current of the respective ARCP converter leg.

12. The power converter system of claim 10 , wherein the control arrangement comprises converter-specific controllers for the two or more ARCP converters, each of the converter-specific controllers being configured to provide autonomous individual boost current regulation for each of the ARCP converter phase legs of the respective ARCP converter.

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