Apparatus for current sharing of converters connected in parallel

Abstract

The invention relates to an apparatus for current sharing of converters connected in parallel. The current sharing between a plurality of ARCPs or hard-switching converter branches connected in parallel is balanced by a control device. The control device senses a branch output current in each of the converter branches connected in parallel and has a separate autonomous branch-specific switching time adjustment for the main switch of each converter branch, the first mode A commutation of the respective converter leg is shifted later in time and the second mode B commutation of the respective converter leg is shifted earlier in time by a variable time step, which is proportional to the value of the sensed leg current of the respective converter leg. In other words, if the value of the sensed branch output current in one converter branch is greater than the value of the other converter branch, the higher current branch will be commutated later than the lower current branch in mode A, and the higher current branch will be commutated earlier than the lower current branch in mode B.

Description

Technical Field

[0001] The present invention relates to parallel connected power converters, and more particularly to current sharing of parallel connected power inverters and rectifiers. Background Art

[0002] A dc to ac or ac to dc converter (also referred to as an inverter or rectifier, respectively) converts power from a dc to ac or ac to dc system at a desired voltage and frequency. Thus, the inverter can be operated as a voltage source with adjustable frequency. The dc power input to the inverter can be obtained from the existing power grid through a rectifier, or from a battery, fuel cell, photovoltaic array, etc. The (multiple) filter capacitors across the input terminals of the inverter provide a fairly constant dc link voltage. The configuration of an ac to dc rectifier and a dc to ac inverter can be referred to as a dc link converter.

[0003] In some cases, a power inverter with increased output power capability is implemented by connecting multiple inverter units in parallel to each other to supply power to the same load. The inverter units connected in parallel can receive simultaneous and similar control signals to provide the desired output of the power inverter. However, due to parameter differences in the switch components and different impedances in the parallel branches, the current amplitudes between the units may not be equal. This current imbalance may cause the components to be unevenly stressed and prematurely wear the switch components with higher currents. Higher currents in the switch components may result in higher dissipated power and further lead to higher temperatures of the components.

[0004] Current imbalance has been addressed by modifying the switch control pulses in order to balance the currents. The control pulses may be modified by delaying the turn-on moment of the switch with the highest current or by delaying the turn-off moment of the switch with the lowest current. One such approach is disclosed in EP0524398. In these solutions, the on-time of the parallel components is modified to equalize the stress of the switch components based on the measured inverter cell currents.

[0005] US8432714 discloses a method for balancing loads between parallel connected inverter modules, wherein the temperature of each output branch of each inverter module is determined and switching commands for one or more parallel inverter modules are modified to control the temperature of the output branches.

[0006] WO 2017 / 079125 A1 discloses a method in which the output voltages of all parallel-connected power devices are measured and the measurement results are used to mitigate timing differences during output voltage state changes caused, for example, by gate driver circuit and switching component parameter tolerances.

[0007] US7068525 discloses a method of operating a plurality of inverters connected in parallel by individually regulating the individual currents of the inverters. Summary of the invention

[0008] It is an object of the invention to provide an improved power converter system with two or more converter branches connected in parallel. The power converter system is recited in the independent claim. Preferred embodiments are disclosed in the dependent claims.

[0009] One aspect of the present invention is a power converter system comprising

[0010] Two or more converter branches connected in parallel between a common DC system and a common AC system or between two common DC systems, wherein each of the converter branches comprises a first controllable main switching device having a first anti-parallel diode and a second controllable switching device having a second anti-parallel diode, the first controllable main switching device and the second controllable switching device being connected in series between a first DC voltage rail and a second DC voltage rail to alternately connect the first DC link rail and the second DC link rail to the converter branch output or input,

[0011] wherein each of the parallel-connected converter branches comprises a commutation mode A and a commutation mode B, in which the branch current is commutated from the first antiparallel diode or the second antiparallel diode to the second controllable main switching device or the first controllable main switching device, respectively, and in which the branch current is commutated from the first controllable main switching device or the second controllable main switching device to the second antiparallel diode or the first antiparallel diode, respectively,

[0012] wherein commutation of the converter branches connected in parallel is initiated by substantially simultaneous commutation commands,

[0013] A control device is configured to sense a branch current in each of the parallel connected inverter branches, and wherein the control device is configured to balance the current sharing between the parallel connected inverter branches by means of having separate autonomous branch specific switching timing adjustments of the main switches for each of the parallel connected converter branches to shift mode A commutation of the corresponding converter branch later in time by a variable time step and shift mode B commutation of the corresponding converter branch earlier in time by a variable time step, which variable time step is proportional to the value of the sensed branch current of the corresponding converter branch.

[0014] In an embodiment, each individual autonomous branch-specific switching timing adjustment is configured to shift the start of the branch voltage swing later in time by a variable time step during mode A commutation of the corresponding converter branch, and to shift the start of the branch voltage swing earlier in time by a variable time step during mode B commutation of the corresponding converter branch, the variable time step being proportional to the value of the sensed branch current of the corresponding converter branch.

[0015] In an embodiment, the size of the variable time step of the individual offset later in time during the individual mode A commutation and the size of the variable time step of the individual offset earlier in time during the individual mode B commutation are configured to depend on the value of the sensed branch current of the corresponding converter branch, in such a way that the size of the variable time step of the individual offset in time increases with an increasing value of the sensed branch current and decreases with a decreasing value of the sensed branch current.

[0016] In an embodiment, each individual autonomous branch-specific switching moment adjustment of the main switching device has a first predetermined dependency on the value of the sensed branch current of the corresponding converter branch in mode A commutation and a second predetermined dependency in mode B commutation, and wherein, optionally, the first predetermined dependency and the second predetermined dependency of different parallel-connected converter branches having different nominal branch current ratings are selected to scale the current sharing between the parallel-connected converter branches according to the nominal branch currents of the parallel-connected converter branches.

[0017] In an embodiment, the parallel-connected converter branches are auxiliary resonant commutated pole (ARCP) converter branches, in particular ARCP half-bridge branches, and wherein the control means is configured to advance each ARCP mode B commutation sequence and delay each ARCP mode A commutation sequence in time in such a way that the size of the variable time step increases with an increasing value of a sensed branch current of the respective converter branch and decreases with a decreasing value of the sensed branch current.

[0018] In an embodiment, the ARCP commutation sequence includes a sequence from a turn-on time of at least one auxiliary switching device to a turn-off time of the main switching device that is always on.

[0019] In an embodiment, the control device is configured to delay both the turn-on instant of at least one auxiliary switching device and the turn-off instant of the main switching device by a first variable time step t in mode A commutation. wA , the first variable time step t wAThe control device is configured to delay both the turn-on instant of the at least one auxiliary switching device and the turn-off instant of the main switching device by a second variable time step t in mode B commutation. wB , the second variable time step t wB It decreases with increasing values ​​of the sensed branch current of the corresponding converter branch and increases with decreasing values ​​of the sensed branch current, thereby advancing the turn-off time of the main switching device in proportion to the value of the sensed branch current.

[0020] In an embodiment, the control device is configured to increase the first variable time step t wA The turning-off time of the main switching device in the mode A commutation is delayed by adding the second variable time step t wB The reference turn-off timing of the main switching device is added to advance the turn-off timing of the main switching device in mode B commutation.

[0021] In an embodiment, the first variable time step is t wA =k A |I o |, where I o is the value of the sensed branch current sample of the corresponding converter branch, and k A is a constant, k A For all converter branches with equal nominal branch current ratings, the second variable time step is equal to t wB =t c -k B |I o |, where t wB ≥0, I o is the value of the sensed branch current sample of the corresponding converter branch, t c is constant time, and k B is a constant, k B The branches are equal for all converters having equal nominal branch current ratings.

[0022] In an embodiment, the converter branches connected in parallel have different nominal branch current ratings, and wherein the constant k in the converter branches connected in parallel is A and / or k B is chosen to scale with the nominal branch current of the converter branch so that the constant k A With the nominal branch current I N The product of is the same in all parallel-connected converter branches and the constant k BWith the nominal branch current I N The product of is essentially the same in all parallel-connected converter branches.

[0023] In an embodiment, the parallel-connected converter branches are hard-switching converter branches, in particular half-bridge branches, and wherein the control means is configured to delay the turn-off instant of the main switching device that is always on by a first variable time step t in mode B commutation. d,off , the first variable time step t d,off The control device is configured to delay the turn-on instant of the main switching device that starts conducting by a second variable time step t in mode A commutation, with an increasing value of the sensed branch current of the corresponding converter branch and with a decreasing value of the sensed branch current, and the control device is configured to delay the turn-on instant of the main switching device that starts conducting by a second variable time step t d,on , the second variable time step t d,on It increases with increasing values ​​of the sensed branch current of the respective converter branch and decreases with decreasing values ​​of the sensed branch current.

[0024] In an embodiment, the first variable time step t d,off According to k off *|I o | decreases with increasing value of the sensed branch current, where I o is the value of the sensed branch current of the corresponding converter branch and k B is a constant, k B For all converter branches with equal nominal branch current ratings, the second variable time step t d,on According to k on *|I o | increases with increasing value of the sensed branch current, where Io is the value of the sensed branch current of the corresponding converter branch and k on is a constant, k on The branches are equal for all converters having equal nominal branch current ratings.

[0025] In an embodiment, the first variable time step is t d,off =t c -k off |I o |, where t c is a constant time that defines the adjustment range, and where the second variable time step is t d,on =t D +k on |I o |, where k D is an optional constant turn-on delay to avoid simultaneous turning-on of the main switching devices.

[0026] In an embodiment, the converter branches connected in parallel have different nominal branch current ratings, and wherein the constant k in the converter branches connected in parallel is on or k off is chosen to scale with the nominal branch current of the converter branch so that the constant k on With the nominal branch current I N The product of is the same in all parallel-connected converter branches and the constant k off With the nominal branch current I N The product of is the same in all parallel-connected converter branches.

[0027] In an embodiment, the control arrangement comprises a branch-specific controller for each converter branch of two or more parallel-connected converter branches to adjust the switching moments of the main switching devices.

[0028] In an embodiment, the power inverter system comprises two or more converters, each of the converters comprising one or more converter phase legs, wherein the parallel connected converter legs are corresponding converter phase legs of the two or more converters connected in parallel.

[0029] In an embodiment, the control arrangement comprises converter-specific switch controllers for two or more converters, each of the converter-specific switch controllers being configured to provide autonomous adjustment of switching moments for each of the converter phase legs of the respective converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the following, the invention will be described in more detail by means of exemplary embodiments with reference to the accompanying drawings, in which

[0031] Figure 1 is a block diagram schematically illustrating an exemplary inverter system having a plurality of inverters connected in parallel;

[0032] Figure 2 is a schematic diagram of an exemplary inverter system having two hard-switching inverters connected in parallel;

[0033] Figure 3 is a schematic block diagram of an exemplary ARCP inverter system having a plurality of inverters connected in parallel;

[0034] Figure 4 is a schematic block diagram of an ARCP switch controller having a PWM modulator and ARCP control functions;

[0035] Figures 5A to 5F is a diagram illustrating an example of mode A commutation;

[0036] Figures 6A to 6D is a diagram illustrating an example of mode B commutation;

[0037] Figure 7 is a flow chart illustrating an exemplary operation of a control device according to an aspect of the present invention;

[0038] Figures 8A to 8C is a timing diagram illustrating an example of shifting the switching moments in a single converter leg;

[0039] Fig.9A and 9B shows a timing diagram illustrating simulated operation of a method according to an embodiment of the present invention for a negative output current; and

[0040] Fig.10 A timing diagram is shown illustrating an exemplary simulation of two parallel-connected ARCP converter legs dimensioned for a nominal current ratio of 2:1. DETAILED DESCRIPTION

[0041] A dc to ac or ac to dc converter (also referred to as an inverter or rectifier, respectively) converts power from a dc to ac or ac to dc power system at a desired voltage and frequency. Further, a dc to dc converter (such as a dc chopper) converts power from a dc to dc power system. Although embodiments are described using inverters and inverter systems as examples, the present invention is similarly applicable to rectifiers and rectifier systems and dc to dc converters. Inverters and rectifiers can be completely similar in structure, and control operations can be similar, with the difference being the direction of power flow. When the converter operates as an inverter (dc / ac converter), it converts power from a dc system to an ac system, i.e., the ac side of the converter is referred to as the output side, and the dc side is considered the input side. When the converter operates as a rectifier (ac / dc converter), it converts power from an ac system to a dc system, i.e., the ac side of the converter is considered the input side, and the dc side is considered the output side. Further, the ac / dc and dc / dc converters are connected in a back-to-back configuration (i.e., the dc sides are connected together) between the two ac systems, with one of the converters operating in rectifier mode and the other in inverter mode, depending on the power flow direction. The operating mode of the converter can change during operation because the power flow can change.

[0042] Figure 1A block diagram is shown schematically illustrating an exemplary inverter system having a plurality of (i.e., two or more) inverters INV1, INV2, ..., INVN, which are connected in parallel from their DC side (e.g., DC link) terminals (e.g., dc+, dc-) and their AC side terminals (e.g., U1, V1, W1, U2, V2, W2). In the illustrated example, inverters INV1 and INV2 are three-phase inverters providing three-phase outputs U1, V1, W1 and U2, V2, W2, but it should be understood that the parallel-connected inverters can be implemented as single-phase inverters, or generally include any number of inverter phases or phase branches. The parallel-connected inverters are composed of a voltage U dc The inverters are powered by a common DC voltage source 4 and supply power to a common AC load 6. A typical application area of ​​parallel-connected inverters powered by a common DC voltage source 4 is a motor drive with an AC motor as a common load 6. There is a non-zero impedance at each phase output of each inverter, such as Figure 1 In the inductance Lo. The output inductance Lo may be intentionally implemented (e.g., a coil, a choke, etc.), or it may be just some leakage impedance of actual components and materials (such as wiring). The output inductance Lo may be substantially equal, but not necessarily necessarily. The corresponding phase outputs U1, U2, V1, V2 and W1, W2 of the inverters INV1 and INV2 connected in parallel are connected to the common phase outputs U, V and W respectively through the output inductance Lo. The corresponding phase outputs U1, U2, V1, V2 and W1, W2 of the inverters INV1 and INV2 connected in parallel may be connected together immediately after the output inductance Lo, and a single cable or multiple cables for each phase U, V and W may be used to connect the phase output to the load 6. Alternatively, each inverter INV1 and INV2 connected in parallel may be connected to the load 6 by means of its own wiring, and the phase outputs U1, U2, V1, V2 and W1, W2 may first be connected in parallel at the terminals of the load 6. The output phase current Io of each phase U, V, W supplied to the load 6 is obtained by combining the phase output currents I1, U2, V1, V2 and W1, W2 of the corresponding phase outputs of the inverters INV1 and INV2 connected in parallel. o1 and I o2 The parallel connected inverter modules INV1 and INV2 of the common DC supply can be controlled to behave like one high power inverter. This can be achieved by controlling the parallel inverter units with substantially the same control commands.

[0043] Each inverter module INV1 and INV2 can have one or more bridge circuits (full bridge or half bridge), one bridge circuit for each inverter phase or phase branch. The bridge circuits of the same phase of different inverter modules are connected in parallel with each other. Each bridge circuit can include a plurality of controllable electronic switching elements or devices (such as insulated gate bipolar transistors (IGBTs) operating in switching mode), which means that by providing a high switching frequency control pulse (commonly referred to as a switch control signal or a gating signal), they are controlled to transition from a blocking state (off state) to a conducting state (on state), and vice versa. In the PWM modulation scheme, the width of the control pulse provided to the control input of the switching device is varied to provide the desired output of the inverter. The parallel-connected inverter modules INV1 and INV2 may have a common switch control that provides a switch signal or a gating signal to operate the switch devices of all the inverter modules, or more preferably, each of the parallel-connected inverter modules INV1 and INV2 may have a dedicated switch control unit 81 and 82 that provides a switch signal or a gating signal to operate the switch devices of the corresponding inverter modules, such as Figure 1 As shown. Alternatively, the control may be distributed between a common switch control unit and an inverter module specific switch control unit. In the latter case, the inverter modules may be common inverter modules that may be connected in parallel (i.e., may be used as a single unit). In an embodiment, the switch controls 81 and 82 of the inverter modules INV1 and INV2 connected in parallel may be controlled by a higher level control system 86 with simultaneous and substantially similar control signals or commands.

[0044] In an embodiment, the higher level control system 86 may be a motor control or the like. It may also include a common PWM generation function (eg, a PWM modulator) for all system elements and phases.

[0045] A schematic diagram of an exemplary inverter system (eg, a single-phase inverter system) having two so-called hard-switching inverters INV1 and INV2 connected in parallel is shown in FIG. Figure 2 As illustrated, and described herein, to facilitate understanding of the operation and configuration of the embodiments of the present invention with respect to the exemplary basic parallel connected inverters. It is not intended to limit the embodiments of the present invention to the exemplary inverters described and illustrated. It should be understood that the current sharing control according to the embodiments of the present invention is generally applicable to any number of parallel inverters, any type of inverters and their derivatives and modifications, regardless of the specific design, configuration and operation variations of the inverters from the exemplary inverters.

[0046] The inverters INV1 and INV2 connected in parallel may preferably be identical inverters having the same configuration and operation. The inverters INV1 and INV2 include a power switching section 10 such as a half-bridge circuit, and a dc link rail 22 (positive dc link potential P) is connected to a first voltage terminal U of a common dc power source 4. dc+ , and the dc link rail 24 (negative dc link potential N) is connected to the second voltage terminal U of the common DC power supply 4 dc- The DC link can be used with the following reference Figure 3 The DC link 2 discussed above is implemented in a similar manner. The output node 110 of each power switching section 10 can be connected to the corresponding output inductor L o1 and L o2 The corresponding phase terminals of the ac load 6, such as an ac motor or an ac grid or any applicable electrical load, are connected so that the corresponding phase outputs 110 (eg, phase legs U1 and U2) of the inverters INV1 and INV2 are connected via L o1 and L o2 It should be appreciated that although a half-bridge inverter is illustrated herein as an example, the inverter may have other configurations, in particular a full-bridge configuration.

[0047] Figure 2 The illustrated exemplary half-bridge power section 10 of the inverter INV1 U Includes a pair of main or power switching devices S 11 and S 21 , which are coupled in parallel to the dc link rails 22 and 24. The first (upper) main switching device S 11 The second (lower) main switching device S may have a first terminal electrically coupled to the positive dc link rail 22 and a second terminal electrically coupled to the output node 110. 21 The upper main switching device S is connected to the output node 110 and has a first terminal coupled to the output node 110 and a second terminal coupled to the negative dc link rail 24. 11 The first anti-parallel diode D is connected at both ends 11 , and the lower main switching device S between the output node 110 and the negative dc link rail 24 21 A second anti-parallel diode D is connected at both ends 21 . In response to the control and driver circuit system (such as Figure 2 The inverter-specific switch controller 81 shown receives the control signal(s) G 11 , upper main switchgear S 21 The switch 81 is operable to switch on and off, thereby connecting and disconnecting the dc link rail 22 and the output node 110, respectively. In response to control signals G received from the control and driver circuitry (such as the switch controller 81), the switch 81 is operable to switch on and off, thereby connecting and disconnecting the dc link rail 22 and the output node 110, respectively.21 , lower main switchgear S 21 is operable to switch on and off, thereby connecting and disconnecting the dc link rail 24 and the output node 110, respectively. Figure 2 The illustrated exemplary half-bridge power section 10 of the inverter INV2 U Includes a pair of main or power switching devices S 12 and S 22 , the first anti-parallel diode D 12 , the second anti-parallel diode D 22 and a switch control signal G from a control and driver circuit system (such as an inverter specific switch controller 82) 12 and G 22 In an embodiment, the switch device S 11 , S 12 , S 21 and S 22 It may be an insulated gate bipolar transistor (IGBT) or other types of semiconductor switching devices such as an integrated gate commutated thyristor (IGCT), a metal oxide semiconductor field effect transistor (MOSFET), or a silicon carbide (SiC) MOSFET, to name a few.

[0048] Electronic switching devices (such as IGBTs) have a finite switching time, i.e., they cannot switch instantaneously from the conducting state to the blocking state and vice versa. During this transition interval (commutation), the switch is neither fully blocked nor fully conducting, so the voltage across the switch and the current through the switch are not zero. In other words, there is a worthy overlap between the voltage waveform and the current waveform. This simultaneous presence of the voltage across the switch and the current through the switch means that power is dissipated within the device during this overlapping period. This power loss, called "switching loss", reduces the efficiency of the inverter and generates major thermal stresses on the switching device when dissipated in the switch. The ability of the switching device to remove heat is limited. As the thermal load increases, the temperature rises, which in turn reduces performance.

[0049] Conventional PWM inverters (such as Figure 2 The exemplary inverter in FIG. 1 operates under such "hard switching" conditions, where the voltage across the switch and the current through the switch suddenly change from a high value to zero at a high switching frequency fs, and vice versa, and there is overlap between the voltage and current waveforms, resulting in switching losses and generating a large amount of electromagnetic interference. The switching losses are proportional to the switching frequency fs, thereby limiting the maximum switching frequency. The high level of EMI is caused by the wide spectrum harmonics contained in the rectangular PWM waveform.

[0050] Soft switching techniques aim to eliminate switching losses by forcing the switch to be in zero voltage or zero current conditions during switching events. Switching at zero voltage crossing is called zero voltage switching (ZVS), while switching at zero current crossing is called zero current switching (ZCS). The auxiliary resonant commutated pole (ARCP) inverter is one of the most promising approaches to soft switching inverters and has obvious potential benefits in motor drive applications. ARCP inverters can be implemented using various topologies, all of which have essentially similar performance. The output voltage waveform during commutation can be shaped to be motor-friendly via appropriate resonant circuit parameter selection. This reduces stress in motor insulation and bearings. The basic configuration and operation of ARCP are described, for example, in the article "The auxiliary resonant commutated pole converter" published by RWDe Doncker et al. in the IEEE-IAS Conference Proceedings 1990, pages 1228 to 1235 and US5047913.

[0051] According to one aspect of the present invention, the inverter system is an auxiliary resonant commutated pole (ARCP) inverter system, including a plurality (i.e., two or more) ARCP inverters INV1, INV2, ..., INVN connected in parallel from their DC side (e.g., DC link) input terminals and their AC side output terminals (e.g., U1, V1, W1, U2, V2, W2). In an embodiment, the ARCP inverter includes dc link capacitors of equal size connected in series between a negative (N) dc link rail and a positive (P) dc link rail on the dc link side of the inverter. At the midpoint of the capacitors (referred to as a neutral point (NP)), a neutral point potential U NP , which essentially corresponds to the voltage U between the dc rails dcHalf of. Each phase of the inverter is associated with at least one resonant capacitor to force a zero voltage turn-off switching condition. Further, an auxiliary branch including a resonant inductor and (multiple) auxiliary switching devices is connected between the neutral point and the phase output to operate under zero current switching conditions. In ARCP, commutation is achieved in a limited amount of time by an auxiliary circuit system. The auxiliary circuit is used only when the output needs to be commutated from one voltage rail to another. In order to ensure that the inverter output voltage reaches at least the positive dc rail voltage and the negative dc rail voltage during each resonant commutation cycle, the boost current is added to the resonant current by appropriately controlling the conduction time of the auxiliary switching device. The predetermined boost current level in the inductor adds sufficient energy to the resonant operation to ensure that the output voltage attempts to overshoot the corresponding converter anti-parallel diode and clamps the output voltage to the corresponding rail voltage. Ideally, the main switch is turned on and off under zero voltage conditions, and the (multiple) auxiliary switches are turned on and off under zero current conditions, which reduces the switching losses that occur. Therefore, the switching frequency can be increased without a considerable loss penalty. The low acoustic noise of such a driver is appreciated in many applications. The high switching frequency also enables higher fundamental output frequencies and low distortion, making the ARCP topology attractive for high-speed drive applications.

[0052] A schematic diagram of an exemplary ARCP inverter system having a plurality of (ie, two or more) inverters INV1, INV2, ..., INVN connected in parallel is shown in FIG. Figure 3 The illustrated and described herein are provided to facilitate understanding of the operation and configuration of embodiments of the invention with respect to an exemplary basic ARCP. It is not intended to limit embodiments of the invention to the described and illustrated (multiple) exemplary ARCPs having only two parallel inverters. It should be appreciated that current sharing control according to embodiments of the invention is generally applicable to any type of ARCP inverter and its derivatives and modifications, regardless of the specific design, configuration, and operational variations of the inverter from the basic ARCP inverter.

[0053] The ARCP inverters INV1 and INV2 connected in parallel may preferably be the same modules having the same configuration and operation. Figure 3 The illustrated exemplary ARCP inverter INV1 includes a DC link 2 (including a first dc link rail 22 and a second dc link rail 24), a first dc link capacitor C coupled to the first dc link rail 22 and a dc link midpoint (referred to as a neutral point NP1). d11 and a second dc link capacitor C coupled to the second dc link rail 24 and the neutral point NP1 d12During operation, the first dc link rail 22 is at a first voltage, the so-called positive (P) dc link potential, and the second dc link rail 24 is at a second voltage, the so-called negative (N) dc link potential, lower than the first DC voltage, and the dc link midpoint NP1 is at a midpoint voltage, the so-called neutral point voltage U NP . dc link capacitor C d11 and C d21 The capacitance is basically the same, for example, C d11 =C d21 =2C dc , so that the dc link capacitor C connected in series between the dc link rails 22 and 24 d1 and C d2 The voltage U provided at both ends 11 and U 21 are substantially equal, that is, the dc link voltage U between the dc link rails 22 and 24 dc =U 11 +U 21 Therefore, the neutral point voltage or potential U NP It also basically corresponds to the voltage U dc In other words, U NP =U dc / 2. The exemplary ARCP inverter INV2 includes a similar DC link 2 having dc link rails 22 and 24, a dc link capacitor C d21 and C d22 , voltage U 21 and U 22 and the dc link midpoint NP2.

[0054] The dc link rails 22 (positive dc link potential P) of the ARCP inverters connected in parallel are connected to each other and to a first voltage terminal U 2 of a common DC power source 4 . dc+ The dc link rails 24 (negative dc link potential N) of the ARCP inverter modules are connected to each other and to the second voltage terminal U of the common DC power supply 4. dc- Further, the neutral points NP1 and NP2 of the ARCP inverter modules connected in parallel may be connected to each other, such as Figure 3 The connection of the neutral points NP1 and NP2 is not essential to the present invention, and they may not be connected to each other.

[0055] The common dc power input to the parallel connected ARCP or hard-switching inverter modules INV1 and INV2 can be obtained from any kind of dc power supply 4, such as from an existing power grid through a rectifier, or from a battery, a fuel cell, a photovoltaic array, etc. It should be understood that the dc link 2 can be provided in a variety of forms and can have a variety of voltages and other attributes. It should also be understood that the voltage difference between the positive dc link rail and the negative dc link rail is flexible, depending on how the dc link 2 is charged by the connected circuit or how the dc link 2 is discharged. For example, some embodiments can use a front-end isolation transformer and rectifier connected to the dc link, where the positive and negative rails are floating, and the differential voltage is typically in the range of 50V to 1500V, but in principle also in other voltages outside this range. In other embodiments, the positive rail, midpoint, or negative rail can be grounded to the ground. Preferably, the positive rail and the negative rail are balanced. For example, if the dc link neutral point NP is at 0VDC, the dc link rail 22 will be at a positive voltage (e.g., in the range of +25VDC to +500VDC, in the range of +150VDC to +400VDC, or other positive voltage range), and the dc link rail 24 will be at a negative voltage corresponding to the positive voltage (e.g., in the range of -25VDC to -500VDC, in the range of -150VDC to -400VDC, or other negative voltage range corresponding to other positive voltage ranges). It should be appreciated that the foregoing examples are a few of the many voltage values ​​and polarities that may be present in or associated with the operation of the dc link 2. It should additionally be appreciated that the voltage values ​​of the foregoing examples may be subject to fluctuations, margins of error, tolerances, and other variations, and may not be strictly fixed to the precise example values ​​specified. It should be further appreciated that the term bus may be used in place of the term link, such that, for example, a reference to a dc link is understood to cover a dc bus, and vice versa.

[0056] Figure 3 The illustrated exemplary ARCP inverters INV1 and INV2 may be three-phase bridge ARCP inverters including a power section 10 for each phase or phase leg U1, U2, V1, V2, W1, and W2, respectively. U , 10 V and 10 W The operation and configuration of the inverters INV1 and INV2 are illustrated and described in more detail herein mainly with respect to one phase or phase leg U1 and U2, but the other phases or phase legs V1, V2, W1 and W2 of the inverters INV1 and INV2 may have the same operation and configuration. In the ARCP inverter INV1, the power section 10 of the phase legs U1, V1 and W1 U , 10 V and 10 Wcan be connected to the positive dc link rail 22, the neutral point NP1 and the negative dc link rail 24 of the common dc link 2, thereby connecting to the negative (N) dc link potential, the neutral point (NP) and the positive (P) dc link potential, such as Figure 2 Each power section 10 U , 10 V and 10 W The output node 110 is connected to the output terminal 111 via a non-zero impedance (usually represented by an output inductor L in this paper). o1 The non-zero impedance may be composed of the impedance of the connecting cable or busbar, and it may also have additional components if necessary. In the ARCP inverter INV2, the power section 10 of the phase legs U2, V2 and W2 U , 10 V and 10 W The common dc link 2 may be connected to the inverter INV2 in a similar manner as in the inverter INV1. Each power section 10 of the inverter INV2 U , 10 V and 10 W The phase output node 110 is connected to the output terminal 110 via a non-zero impedance (usually represented by an output inductor L in this paper). o2 ) is connected to the corresponding phase of the ac load 6, so that each phase output of the inverter INV2 is connected in parallel with the corresponding phase output of the inverter INV1. It should be understood that although a three-phase ARCP inverter is illustrated as an example herein, the ARCP inverter can be implemented as a single-phase inverter, or generally includes any number of inverter phases or phase branches. Moreover, although a half-bridge ARCP inverter is illustrated as an example herein, the ARCP inverter can have other configurations, specifically a full-bridge configuration.

[0057] Figure 3 An exemplary half-bridge power section 10 of the illustrated ARCP inverter INV1 U Includes a pair of main or power switching devices S 11 and S 21 , which are coupled in parallel to the dc link rails 22 and 24 of the dc link 2. The first main switching device S 11 The second main switching device S may have a first terminal electrically coupled to the positive dc link rail 22 and a second terminal electrically coupled to the output node 110. 21 The first main switching device S is connected to the output node 110 and has a first terminal coupled to the negative dc link rail 24. 11 The first anti-parallel diode D is connected at both ends 11, and a second main switching device S between the output node 110 and the negative dc link rail 24 21 A second anti-parallel diode D is connected at both ends 21 Furthermore, the first resonant capacitor C 11 Operable with the first main switching device S 11 connected in parallel (ie, directly or via additional components, such as an active or passive damping circuit connected in series with the resonant capacitor), and a second resonant capacitor C 21 Operable with the second main switch device S 21 More generally, there may be one or more resonant capacitors connected in such a way that at least one terminal of the resonant capacitor(s) is connected to one of the dc link rails (P, NP, N) and the other terminal(s) are operably connected to the phase output node 110. In response to a signal from a control and driver circuit system (such as Figure 3 The inverter-specific ARCP switch controller 81 shown receives the control signal(s) G 11 , the first main switch device S 11 The dc link rail 22 and the output node 110 are operative to be switched on and off, respectively, to connect and disconnect the dc link rail 22 and the output node 110. In response to control signals G received from the control and driver circuitry (such as ARCP switch controller 81), the dc link rail 22 and the output node 110 are operative to be switched on and off, respectively, to connect and disconnect the dc link rail 22 and the output node 110. 21 . Second main switch device S 21 The ARCP inverter INV1 is operable to switch on and off, thereby connecting and disconnecting the dc link rail 24 and the output node 110, respectively. U , 10 V and 10 W can be controlled by the same inverter specific switch controller 81. Similarly, Figure 3 An exemplary half-bridge power section 10 of the illustrated ARCP inverter INV2 U Includes a pair of main or power switching devices S 12 and S 22 , the first anti-parallel diode D 12 and the first resonant capacitor C 12 , the second anti-parallel diode D 22 , the second resonant capacitor C 22 and a switch control signal G from a control and driver circuit system (such as an inverter-specific ARCP switch controller 82) 12 and G 22 All power sections 10 of the phase legs U2, V2 and W2 in the ARCP inverter INV2 U , 10 V and 10 Wcan be controlled by the same inverter specific switch controller 82. In an embodiment, the switch device S 11 , S 12 , S 21 and S 22 It may be an insulated gate bipolar transistor (IGBT) or another type of semiconductor switching device such as an integrated gate commutated thyristor (IGCT), a metal oxide semiconductor field effect transistor (MOSFET), or a silicon carbide (SiC) MOSFET, to name a few.

[0058] In operation, when the first main switch S 11 / S 12 When turned on (to the on state), the first switch current I s11 / I s12 can flow between the dc link rail 22 and the output node 110. Similarly, when the second main switching device S 21 / S 22 When turned on (to the on state), the second switch current I s21 / I s22 can flow between the output node 110 and the dc link rail 24. On the other hand, when the first main switching device S 11 / S 12 When turned off (to non-conducting state), the first switch current I s11 will not flow in the forward direction of the switch between the dc link rail 22 and the output node 110, although the current I d11 / I d12 The current can flow through the first main switching device S in the switching reverse direction. 11 / S 12 The first anti-parallel diode D 11 / D 12 Similarly, when the second main switching device S 21 / S 22 When turned off (to non-conducting state), the second switch current I s21 / I s22 will not flow in the forward direction of the switch between the output node 110 and the dc link rail 24, although the current I d21 / I d22 The current can flow through the second switching device S in the reverse switching direction. 21 / S 22 The anti-parallel diode D 21 / D 22 Therefore, by switching on and off the first main switching device S 11 / S 12 and the second main switchgear S 21 / S 22, the output voltage at the output node 110 will be controlled or commutated to the voltage P from the dc link rail 22 or the voltage N from the dc link rail 24. The resonant capacitor C 11 / C 12 and C 21 / C 22 The purpose of this is to limit the voltage slew rate at the output node; this ensures that the main switching device S 11 / S 12 and S 21 / S 22 The voltage across the two ends is U c11 / U c12 and U c21 / U c22 It does not change significantly during turn-off, so that the main switching device turns off at essentially zero voltage.

[0059] Figure 3 An exemplary half-bridge power section 10 of the illustrated ARCP inverter INV1 U The auxiliary circuit also includes a resonant inductor L1 and a bidirectional auxiliary switch S1 connected in series between the neutral point NP1 and the output node 110. aux1 In response to a control signal received from a control and driver circuit system (such as ARCP switch controller 81), the auxiliary switch S aux1 The auxiliary switch S is operable to switch on and off, thereby connecting and disconnecting the neutral point and the output node 110, respectively. aux1 The bidirectional auxiliary switch S may behave like a bidirectional thyristor: it may be triggered to conduct and to turn off when or before the current attempts to reverse its direction. aux1 It may be implemented with a pair of common switching devices connected back to back, for example in a common emitter or common collector configuration, and provided with an anti-parallel diode. Figure 3 An exemplary auxiliary switch S is shown. aux1 , comprising a first auxiliary switching device S connected in series with a common emitter a11 and the second auxiliary switching device S a21 , connected to the first auxiliary switch device S a11 The first anti-parallel diode D at both ends a11 and connected to the second auxiliary switching device S a21 The second anti-parallel diode D a21 . In response to the control and driver circuit system (such as Figure 3 The control signal G received by the ARCP switch controller 81) is shown in FIG. a11 and G a21 , two auxiliary switching devices S a11 and S a21One of the auxiliary switching devices is turned on and conducts once, and the two anti-parallel diodes D a11 and D a21 The same is true for an antiparallel diode in . In each case, the auxiliary current I a1 The auxiliary switching device in the auxiliary circuit is switched on and off at zero current. a11 The second switching device S is switched on and a21 When turned off, the auxiliary current I a1 will flow through S in one direction a11 and D a21 When the first auxiliary switching device S a11 The second switching device S is turned off and a21 When turned on, the auxiliary current I a1 will flow through S in the opposite direction a21 and D a11 The auxiliary circuit is used only when it is required that the output node 110 commutate from one voltage rail to another. The auxiliary circuit operates by generating a current pulse that, in combination with the resonant capacitor, is used to slew the output voltage on the output node 110. Similarly, Figure 3 An exemplary half-bridge power section 10 of the illustrated ARCP inverter INV2 U The auxiliary circuit also includes a resonant inductor L2 and a bidirectional auxiliary switch S connected in series between the neutral point NP2 and the output node 110. aux2 In an embodiment, the auxiliary switch S aux2 Can be connected with auxiliary switch S aux1 A similar approach is implemented using a pair of ordinary switches and anti-parallel diodes. Figure 3 An exemplary auxiliary switch S is shown. aux2 , comprising a first auxiliary switching device S in series connection a12 and the second auxiliary switching device S a22 , connected to the first auxiliary switch device S a12 The first anti-parallel diode D at both ends a12 and connected to the second auxiliary switching device S a22 The second anti-parallel diode D a22 . In response to the control and driver circuit system (such as Figure 3 The control signal G received by the ARCP switch controller 82 is shown a21 and G a22 , two auxiliary switching devices S a12 and S a22 One of the auxiliary switching devices is turned on and conducts once, and the two anti-parallel diodes D a12 and D a22The same is true for an anti-parallel diode in .

[0060] Figure 1 , 2 and 3 shown in the switch control 81 ... 8 n Generally refers to any control functions, logic, hardware, firmware, software, etc. required to control the switching devices in (multiple) hard-switched or ARCP phase legs based on one or more PWM signals. Given the PWM signal, a standard hard-switched inverter does not require much additional logic to form a complete inverter drive system. At a minimum, the direct PWM signal is sent to one switch, and the complement of the PWM input signal is sent to the other switch in the phase. ARCP, on the other hand, requires more than just PWM modulation and control: it requires additional more complex control, especially due to the auxiliary circuits and (multiple) auxiliary switches.

[0061] Figure 4 8 is a schematic block diagram of an exemplary embodiment of an ARCP switch controller 81 having a separate PWM modulator 82 and an ARCP control function 84. In the illustrated example, the ARCP control 84 may include a dedicated ARCP control module 841. U ,841 V and 841 W , which is adapted to be based on a corresponding PWM signal PWM received from the PWM modulator 82 U 、PWM V and PWM W Provide control signals such as G to each ARCP phase leg U1, V1 and W1 respectively. 11 , G 21 , G a11 and G a21 ARCP control 84 or corresponding ARCP control module 841 U ,841 V and 841 W For each phase leg U1, V1 and W1, functions such as activating the correct auxiliary switch before commutating the main switch, controlling the boost time, ensuring that the main switch switches at substantially zero voltage, ensuring that the auxiliary switch switches at zero current, initially starting the switching sequence at power-up, etc. Depending on the selected ARCP control strategy, various sensing feedbacks (FB) may be required to implement the control algorithm, such as feedback from a main switch zero voltage sensor, an auxiliary switch zero current sensor, an auxiliary current sensor, an output (load) current sensor, a dc link voltage sensor, a (multiple) dc link capacitor sensor, a neutral point voltage sensor, etc.

[0062] As used herein, when the auxiliary circuit participates in commutation and provides a boost current, the output current I oFrom the diode to the switch (for example, the current I o1 From the diode D 21 Reversing to switch S 11 ) is called Mode A, and the output current I o From the switch to the diode (for example, the current I o1 From switch S 11 Commutation to diode D 21 ) is called Mode B. When the output current Io itself is sufficient to drive the output voltage from one dc link rail to the other dc link rail and no auxiliary circuits are involved, the high output current I o The mode of commutation from switch to diode is referred to herein as Mode O. The terms Mode A and Mode B are also used herein for hard-switched commutation from diode to switch and from switch to diode, respectively, e.g. Figure 2 In the inverter shown.

[0063] Mode A commutation: If the output current I o is positive (Io>0), and the output voltage U o From the potential N (dc link 24) to the potential P (dc link 22), the lower diode D 21 and D 22 The current (I d21 and I d22 ) are switched to the upper switch S 11 and S 12 If the output current I o is negative (Io<0), and the output voltage U o From the potential P (dc link 22) to the potential N (dc link 24), the upper diode D 11 and D 12 The current (I d11 and I d12 ) are switched to the lower switch S 21 and S 22 .

[0064] Mode B commutation: If the output current I o is positive (Io>0), and the output voltage U o From the potential P (dc link 22) to the potential N (dc link 24), the upper switch S 11 and S 12 The current is commutated to the lower diode D 21 and D 22 If the output current I o is negative (Io<0), and the output voltage U oFrom the potential N (dc link 24) to the potential P (dc link 22), the lower switch S 21 and S 22 The current is commutated to the diode D 11 and D 12 .

[0065] Hereinafter, examples of typical ARCP commutation in modes A and B are briefly described for a single phase, for example, ARCP phase V1, of ARCP inverter INV1. Modes A and B of commutation of the corresponding ARCP phase V2 of ARCP inverter INV2 are similar.

[0066] As an example of mode A, refer to Figures 5A to 5F Describes the positive output current I o1 (Io>0) from the lower diode D 21 To the upper main switch S 11 And the output voltage U o Commutation from N to P.

[0067] Diode D 21 On-state output current I o1 (=I d21 ), diode D 21 Supply output current I o ( Figure 5A ), and switch S 11 , S a11 and S a21 Not conducting (off); during commutation S 21 Shutdown and S 11 Connected.

[0068] The commutation command is at time t Ao Auxiliary switch S a11 At time interval t wA1 After that, it is turned on (at zero current), which marks the boost interval t bA1 The neutral point voltage U NP1 is applied across the resonant inductor L1, which results in an auxiliary current I through the resonant inductor L1 a1 Linear ramp ( Figure 5C ), and diode D 21 The current I d21 Accordingly, as I d21 =I o1 -I a1 And reduce ( Figure 5A ). In order to turn off the diode D 21 , auxiliary current I a1 The output current must be increased to I o1 level, or even exceeds (through the boost current I bA1), so that the final I a1 =I o1 +I bA1 The total inductor current I a1 The boost current portion I bA1 is transferred to the diode D 21 Parallel switch S 21 ( Figure 5B ), while the load 6 takes its own current, i.e., the output current I o1 .

[0069] Switch S 21 At time interval t bA1 After shutdown ( Figure 5B ), which marks the boost interval t ba1 The output voltage U c21 From N (zero) to P (all U dc ) starts the commutation swing. The boost current I bA1 must be large enough to force the output potential to swing from N to P, thereby applying a load to capacitor C 21 Charges and charges the capacitor C 11 If there is a slight imbalance in the half of the dc link voltage, causing U 21 11 , more boost current is needed, and if U 21 >U 11 , then less boost current is sufficient.

[0070] U C21 From Zero to U dc The interval of the swing has a duration t sA1 .

[0071]

[0072] in

[0073] Ip A1 is the peak value of the resonant portion of the inductor current

[0074]

[0075] β is the phase angle

[0076] β=sin -1 (I bA / I pA ) (3)

[0077] And in Figure 3 In the exemplary topology shown, C = C 11 +C 21 The average value of the voltage change rate is du / dt = U dc / t​sA1 .

[0078] WhenU c21 At time interval t sA1 After reaching U dc And U c11 When reaching zero ( Figure 5D ), auxiliary current I a1 Exceeding the output current I o1 The diode D is partially turned on 11 , and is called I tA1 ( Figure 5C and 5D ). As long as U c21 Already reached U dc , you can turn on the switch S 11 . Boost time t bA1 It can be preferably arranged so that the current I tA1 minimized to zero. Thus, D 11 The losses and reverse recovery current as well as the duration of commutation will be minimized. This strategy reduces the window t tAx Therefore, S 11 The precise timing of switching on is critical.

[0079] Because the diode D 11 and switch S 11 The output voltage is clamped to the positive dc potential P, so the inductor current I a1 In tt A linearly decays to zero during the time interval ( Figure 5C ).

[0080] Current I d11 At time t tAx First of all, from I tA1 decays to zero, after which the switching current I s11 Increase linearly from zero to the load current level I o1 ( Fig. 5F ), while I a1 Continue from I o1 Decrease towards zero ( Figure 5C ), after which the auxiliary diode D a21 turns off and the commutation sequence ends.

[0081] From the auxiliary switch S a21 The total duration from switching on to the completion of commutation in mode A is t A =t bA1 +t sA1 +t tA1 During this time interval, there is current in the auxiliary branch.

[0082] As an example of mode B, refer to Figures 6A to 6D Describes the positive output current I o1 (Io>0) from the upper main switch S 11 To the lower diode D 21 Commutation and output voltage U o Swing from N to P.

[0083] Switch S 11 On-state output current I o1 (I o1 =I s11 )( Fig. 6A ), and switch S 21 , S a11 and S a21 Non-conducting (off); during commutation, the upper switch S 11 The lower diode D is turned off and 21 Connected.

[0084] The commutation command is at time t B0 Arrived. During the waiting time t wB1 After that, the auxiliary switch S a21 is turned on, and the boost current I bB1 (In the negative direction in inductor L1, in S 11 (in the positive direction) linearly constructs a period of time t bB1 ( Figure 6B ).

[0085] The boost current is added to the switch S 11 The load current is above t bB1 At the end, the total current I is turned off s11 =I o1 +I bB1 ( Fig. 6A ). c11 From Zero to U dc The swing starts ( Figure 6C ). The output potential swing from P to N is determined by I o1 The linear part caused by I bB1 The duration of the swing is t sB1

[0086]

[0087] in

[0088] I pB1 is the peak value of the resonant portion of the inductor current,

[0089]

[0090] γ is the phase angle,

[0091]

[0092] And C = C 11 +C 21 The average value of the voltage change rate is du / dt = U dc / t sB1 .

[0093] At the end of the swing, the residual current I a1 Initially added to the diode D 21 The output current I o1 Above, I d21 =I o1 +I tB When the inductor current is at time t tB When it reaches zero again, the diode current decays linearly to its final value I o ( Figure 6B and 6D ). In mode B, from trigger S a The total duration of the commutation to completion is t B =t bB +t sB +t tB .

[0094] The above description of modes A and B assumes that I o The positive direction of I o (I o <0) is the same, except that S 11 and S 21 , D 11 and D 21 and U c11 and U c21 The effect is switched from mode A to mode B and vice versa.

[0095] Commutation of corresponding phases in multiple parallel-connected inverters may be initiated by similar commutation commands at the same time. For example, ARCP commutation of ARCP phase V1 of ARCP inverter INV1 and ARCP phase V2 of ARCP inverter INV2 may be initiated at time t for mode A commutation. Ao and the time t for mode B commutation Bo Initiated by similar commutation commands. Ideally, the output current I o1 and I o2 However, the ideal behavior during commutation would require that the corresponding switches in the inverters (e.g., S 11 and S 12 ) when the output potential U oInverters connected in parallel should be switched on at the same moment when commutating from, for example, N to P. Likewise, when commutating the output potential from P to N, they should be switched off at the same moment. Unfortunately, inverters operated in parallel do not behave similarly, e.g. due to parameter differences in the switching components and different impedances in the parallel branches, the values ​​of the output currents from the parallel inverters may not be equal. In other words, there may be uneven current sharing between the inverters. For thermal and economic reasons, it is crucial that the inverters connected in parallel share the load current as evenly as possible.

[0096] According to one aspect of the invention, current sharing between multiple parallel connected ARCP or hard switching converter legs is balanced by a control device, such as switch control function 84 or switch control modules 841U, 841V and 841W. Figure 7 A flow chart illustrating an exemplary operation of the control device is shown. The control device may sense the branch output current I in each converter branch of the parallel-connected converter branches. o (step 72), and the individual autonomous branch-specific switching instants of the main switches for each of the converter branches connected in parallel are adjusted to shift the first mode A commutation of the respective converter branch later in time and shift the second mode B commutation of the respective converter branch earlier in time by a variable time step that is proportional to the value of the sensed branch current of the respective converter branch (step 74). In other words, if the value of the sensed branch output current is greater in one converter branch than in another converter branch, then in mode A the higher current branch will commutate later than the branch with the smaller current, and in mode B the higher current branch will commutate earlier than the branch with the smaller current.

[0097] Ideally, when current sharing is balanced, the converter branches connected in parallel (e.g. Figure 3 The output currents of the phase legs U1 and U2) in the circuit are equal, and their difference or differential output current I do is zero (for example, I do =I o1 -I o2 =0). For example, if the branch output currents sensed by the parallel-connected converter branches have equal values, then the autonomous switching timing adjustments of the parallel-connected branches will (independently of each other, each based only on its own sensed branch output current) cause their output voltage swing commutation to start at approximately the same time. On the other hand, if the branch output currents sensed by the parallel-connected branches have different values, then the autonomous switching timing adjustments of the branches will (independently of each other) cause their output voltage swing commutation to start in different ways, i.e., earlier or later, respectively, depending on its own sensed branch output current value, so that (in one direction) the differential output current (e.g., I do =Io1 -I o2 ) is reduced. In other words, the output voltage swing (for example, U c21 and U c22 , cited Figure 3 These differences in the starting time of the N potential in the output current will tend to reduce the output current difference I do The direction of the loop inductance (ΔL = L o1 +L o2 ) produces an effective volt-second difference. The shift in time of the output voltage swing can also be called a pulse shift. Thus, the control device can fine-tune the switching timing so that the commutation induced output current difference between the parallel-connected inverter branches is towards zero, while the switching timing can be generated in a conventional manner.

[0098] Advantageously, the parallel inverter branches do not need to know each other's current or differential current, but current sharing by adjusting the boost current balance can be implemented relying only on information that is easily available individually in each of the parallel connected branches, i.e., the output current value (e.g., I o1 or I o2 ). The benefits of autonomous (or distributed or decentralized) control derive from avoiding the need to exchange information between higher-level control and lower-level control entities or between lower-level control entities (such as switching controls 81 and 82). Autonomous control systems are also typically simpler and more modular than centralized control systems, and are therefore easier to understand and maintain. Further, in order to keep the implementation cost effective, it is preferred that there are no additional component selection requirements or communication needs between inverter units connected in parallel, i.e., normal "single inverter units" (such as inverters INV1 and INV2) can be connected in parallel in this way. On the other hand, the challenge is obvious: autonomous units must operate with limited information. Embodiments of the present invention overcome this challenge.

[0099] In a typical case, the converter branches connected in parallel have similar nominal branch current ratings. In an embodiment, the autonomous branch-specific switching moment adjustments of all parallel-connected converter branches have the same first predetermined dependency on the value of the sensed branch current of the respective converter branch in mode A commutation and the same second predetermined dependency in mode B commutation.

[0100] However, the autonomous branch-specific switching moment adjustment of the present invention may also be applied in case the parallel-connected phase legs have different nominal current ratings. In an embodiment, a first predetermined dependency and a second predetermined dependency of different parallel-connected converter legs having different nominal branch current ratings are selected to scale the current sharing between the parallel-connected converter legs according to the nominal branch currents of the parallel-connected converter legs.

[0101] Let us examine the application of the principles of the present invention to an ARCP converter system such as Figure 3 An example of autonomous branch-specific switching timing adjustment in the illustrated system). Typically, the turn-on timing of the auxiliary switch and the turn-off timing of the main switch are offset by the same amount, applicable to both mode A and mode B. This means that each ARCP commutation sequence is offset in time in this way. In the parallel connection of branches 1 and 2, based on their respective branch output currents I o1 and I o2 , autonomously determining the offset. The duration of the boost time and the boost current level are not affected by the offset caused by the autonomous branch-specific switching moment adjustment according to an embodiment of the present invention. It should be understood that the boost current may have been manipulated if some other control method relying on such manipulation was applied at the same time. The examples presented herein assume that both converter branches target the same boost current, and the reference value of the boost current is I for mode A. bA1,r1 =I bA,r2 , and for mode B is I bB,r1 =I bB,r2 .

[0102] Figures 8A to 8C An exemplary timing diagram is shown schematically illustrating the offset principle of a single converter branch. In the illustrated timing diagram, Fig. 8A The PWM signal is shown as providing a commutation command which is applied simultaneously to each of the converter branches in the parallel connected converter branches to initiate commutation. In the illustrated example, the leading edge (rising edge) of the incoming PWM signal is at time t B0 Initiate mode B commutation, and the trailing edge (falling edge) at time t A0 Initiate Mode A commutation. Figure 8B Schematic diagram of the auxiliary current I of a single converter branch a For simplicity, only the boost period t bB and t bA The auxiliary current I a . Figure 8C Schematically shows the capacitor voltage V C2 The timing of the output voltage swing. Again, for simplicity, the voltage V C2 The swing time is reduced to zero. In the illustrated example, mode B commutation is advanced, and mode A commutation is with output current I o The sensed value is delayed in proportion to the Figures 8A to 8B Assuming the output current I o is negative polarity, but I o should be interpreted as I oThe absolute value of , as will be discussed in the following equation. Therefore, the polarity of the output current does not affect the basic principle of the autonomous branch-specific switching timing adjustment method according to an embodiment of the present invention.

[0103] Let us assume that the branch output current I o is positive, and I o1 >I o2 , so that the differential output current I d >0. In mode A, the lower main switch S 21 The turn-off time t offS21 The voltage swing in the APCP inverter branch INV1 begins, and the lower main switch S 22 The turn-off time t offS22 The voltage swing in the APCP inverter branch INV2 begins. In mode B, the upper main switch S 11 The voltage swing in the APCP inverter branch INV1 begins at the turn-off time, and the lower main switch S 12 The turn-off time t offS12 The voltage swing in the APCP inverter branch INV2 starts.

[0104] In an exemplary embodiment, let us define the difference in the turn-off instant of the main switch in mode A as follows

[0105] Δt S2 =t offS21 -t offS22 (7)

[0106] In mode B, the difference in turn-off instant is defined as

[0107] Δt S1 =t offS11 -t offS12 (8)

[0108] where t offS21 and t offS22 They are S 21 and S 22 The turn-off time in mode A. Similarly, t offS11 and t offS12 They are S 11 and S 12 The turn-off moment in mode B.

[0109] Considering the possible unequal swing intervals t in mode A sA1 and t sA2 , the effective total timing difference during commutation is

[0110]

[0111] Likewise, considering the possibly unequal swing intervals t in mode B sB1 and t sB2 , the effective total timing difference during commutation is

[0112]

[0113] At the positive output current I o Under the assumption that A or Δt B The differential current I d =(I o1 -I o2 ) / 2 increases in mode A

[0114]

[0115] And in mode B, it increases

[0116]

[0117] In mode A, if converter branch INV1 is slower than converter branch INV2, it turns off its lower switch S 22 Later, the upper switch S is turned off. 21 , then the difference in turn-off time Δt S2 will be positive. Therefore, if the swing time t sA1 and t sA2 equal (i.e., the boost current I bA1 =I bA2 , which actually means that the equivalent boost time interval t bA1 =t bA2 ), then Δt in equation (9) A will have a negative term, which will make the differential current ΔI in equation (11) dA Determined to be negative.

[0118] If the entire commutation sequence from the switching on of the auxiliary switch to the switching off of the main switch in mode A is adjusted to occur later in the converter branch with the higher output current value, the differential current ΔI dA To achieve this desired behavior, the auxiliary switch S a1 The switch-on time t onSa1 From the time t of the two branches A0 Delay individual variable increments or time steps

[0119] t wA1 =k A |I o1 | (13)

[0120] as well as

[0121] twA2 =k A |I o2 | (14).

[0122] Boost time t bA1 and t bA2 No change. Factor proportional control gain k A is a design parameter (a positive constant) that should be equal if the nominal current ratings of the two branches are equal. In order to offset the entire commutation sequence in time, S 21 and S 22 The reference value of the switch-off instant will also be delayed by a separate variable increment or time step t wA1 and t wA2 .

[0123] t offS21，r =t wA1 +t bA，r (15)

[0124] t offS22,r =t wA2 +t bA,r (16)

[0125] It is assumed that the reference boost time t bA,r (and the corresponding reference boost current I bA,r ) are equal in the branch.

[0126] Because |I o1 |>|I o2 |, the autonomous branch-specific switching time adjustment method makes the lower switch S in the converter branch INV1 21 The lower switch S in the converter branch INV2 22 Later shutdown

[0127] Δt S2,r =t offS21,r -t offS22,r =k A (|I o1 |-|I o2 |) (17)

[0128] Thus, at the time when the main switch is turned off, term k A (|I o1 |-|I o2 |) will be added to the difference Δt S2 , which tends to make the difference Δt S2 Correction (because |I o1 |>|I o2 |), thereby reducing the differential current I d In an embodiment, the factor k AIt can conveniently be expressed in units of [ns / A], and may perhaps reach values ​​of 0.5…2, so that, for example, a differential current of 50 A will give a time difference Δt S2 A change of 50ns…200ns occurs.

[0129] Similar reasoning can be applied to mode B, but now the converter branch with the higher current must have its commutation sequence shifted earlier in time. Because the incoming PWM edge providing the command to start commutation cannot be advanced in time, in an embodiment, the incoming PWM edge is first conceptually shifted from the instant t of the two converter branches. B0 "Delay" constant time t c Therefore, an adjustment range is provided to allow for an advance in time from this "delay" command. In an embodiment, in each parallel-connected converter branch, the auxiliary switch S a2 The switch-on time t onSa2 The following will be based on the incoming PWM edge (time t B0 ) variable waiting interval or time step t wB After

[0130] t wB =t c -k B |I o | (18) where k B is the advance factor (normal constant). The turn-off time t of the upper main switch S1 offS1 for

[0131] t offS1 =t wB +t bB (19)

[0132] With the output current I o becomes higher, waiting for interval t wB becomes smaller, and because the boost time t bB No change, so the shutdown time t offS1 It will be ahead of schedule, that is the goal.

[0133] In the illustrated example, the parallel connected branches INV1 and INV2 will accordingly calculate their respective waiting times as

[0134] t wB1 =t c -k B |I o1 | (20)

[0135] as well as

[0136] t wB2 =t c -kB |I o2 | (21)

[0137] Make switch S 11 and S 12 The reference value of the switch-off moment will be

[0138] t offS11，r =t wB1 +t bB，r (twenty two)

[0139] as well as

[0140] t offS12，r =t wB2 +t bB，r (twenty three)

[0141] It is assumed that the reference boost time t bB,r (and the reference boost current I bB,r ) are equal in the branch.

[0142] Because |I o1 |>|I o2 |, the autonomous branch-specific switching time adjustment method makes the upper switch S in the converter branch INV1 11 The upper switch S in the converter branch INV2 12 Shut down earlier Δt S1，r =t offS11，r -t offS12，r =-k B (|I o1 |-| Io 2|) (24)

[0143] Fig.9A and 9B An exemplary simulated timing diagram is shown, illustrating the timing of a negative output current I according to an embodiment of the present invention. o The bottom trace I o1 and I o2 The factor k in equations (13) to (14) and (20) to (21) is A and k B The square wave signal PWM represents the incoming PWM command, while the higher amplitude ramp signal represents the branch output voltage U with reference to the N potential. o Note that the effective voltage pulse length of U0 increases with the total output current. This is a disadvantage of this approach as it leads to current-dependent distortions, which can, however, be compensated for using prior art methods. Fig.9A and9B The auxiliary current I a Behavior in Modes A and B. Auxiliary current pulse I a Positive for mode B and negative for mode A.

[0144] exist Fig.9A The total output current I of the converter branches connected in parallel is o =I o1 +I o2 is -200A, but it is initially shared unevenly between the converter branches INV1 and INV2, with the branch output current I o1 is -90A, the branch output voltage I o2 is -110A. Fig.9A When the output current is relatively low, the auxiliary current I a is larger in mode B and smaller in mode A. Since |I o2 |>|I o1 |, this method causes the mode B commutation of branch INV2 to start later than branch INV1, so that the auxiliary current I of branch INV2 a2 and output voltage swing U o Than INV1 a1 and U o starts earlier (i.e., the main switch S2 is turned off). Therefore, the output current I o1 and I o2 converge towards each other and are already aligned after mode B commutation, as Fig.9A As shown in the figure. Ideally, when the output current I o1 and I o2 When now equal, the auxiliary currents and the output voltage swings of the parallel-connected branches are now also approximately aligned in the subsequent commutation.

[0145] exist Fig. 9B The total output current I of the converter branches connected in parallel is o =I o1 +I o2 is -1800A, but it is initially shared unevenly between the converter branches INV1 and INV2, with the branch output current INV1 of branch INV2 being o1 is -720A, and the branch output current I o2 is -980A. Fig.9A compared to, Fig. 9B The output current increases, the auxiliary current I aIt decreases in mode B and increases in mode A. In mode B, the output current speeds up the voltage swing in the resonant capacitor; therefore, the auxiliary current has less time to be generated in the resonant inductor at higher output currents. In mode A, the auxiliary current must always be larger than the output current before the output voltage swing can begin (i.e., the main switch S2 is turned off.) Fig. 9B In, due to |I o2 |>|I o1 |, this method causes the mode B commutation of branch INV2 to start earlier than branch INV1, so that the auxiliary current I of branch INV2 a2 and output voltage swing U o Than INV1 a1 and U o Therefore, although the output current I o1 and I o2 Converging towards each other during the first mode B commutation, they are still not equal, as Fig.9A In the subsequent mode A commutation, due to |I o2 |>|I o1 |, this method causes the mode A commutation of branch INV2 to start later than branch INV1, so that the auxiliary current I of branch INV2 a2 and output voltage swing U o Than INV1 a1 and U o Starts later (i.e., main switch S2 is turned off). Now, the output current I o1 and I o2 converge toward each other and align during mode B commutation, as Fig. 9B As shown in the figure. Ideally, the output current I o1 and I o2 As a result, the auxiliary current and the output voltage swing of the parallel-connected branches are now also approximately aligned in the subsequent commutation.

[0146] The autonomous branch-specific switching timing adjustment method can be applied to parallel connected hard-switching (HS) converter branches, such as Figure 2 In this case, mode A corresponds to the switching on of the main switch that will start conducting (current commutates from the diode to the switch), while mode B corresponds to the switching off of the switch that is already conducting (current commutates from the switch to the diode).

[0147] Let us examine Figure 2 An exemplary case of current sharing balance between parallel connected HS inverter branches is shown.

[0148] First, the upper dc rail 22 (U DC+) to the lower dc rail 24 (U DC- ), i.e., the upper main switch S in INV1 11 The turn-off sequence and the lower main switch S 21 The turn-on sequence of the upper main switch S in INV2 12 The turn-off sequence and the lower main switch S 22 The switch-on sequence:

[0149] HS1) Upper switch S 11 and S 12 are connected, and the branch output 110 is connected to the upper dc rail 22 (U DC+ ).

[0150] HS1.pos) If the current is positive, I o >0, the upper switch S 11 and S 12 The switches carry currents respectively, and the turn-off event is similar to the mode B (switch to diode) commutation in the ARCP converter:

[0151] a) Similar to ARCP Mode B commutation, the converter branch with the higher current must have its commutation sequence shifted earlier in time. Because the incoming PWM edge providing the command to start commutation cannot be advanced in time, in an embodiment, the incoming PWM edge is first conceptually shifted from the instant t B0 "Delay" constant time t c Therefore, an adjustment range is provided to allow for an advance in time from the "delay" command, i.e., the total delay decreases as the branch output current increases. According to an embodiment, the upper switch S 11 and S 12 The shutdown events are advanced by a variable time step t d,off =t c -k off *|I o |, where k off is the same as K in ARCP mode B B1 The corresponding advance factor (normal number).

[0152] b) Output current I o1 and I o2 Respectively switch to the lower diode D 21 and D 22 .

[0153] c) In the embodiment, the lower main switch S 21 and S 22 can be switched on at a predetermined delay t DAfter that, it is turned on, which is commonly used in the art to prevent the upper switch and the lower switch in a hard-switching converter from being turned on at the same time, that is, to avoid a DC link short circuit.

[0154] d) The branch output 110 is connected to the lower dc rail 24 (U DC- ).

[0155] HS1.pos) If the current is negative, I o <0, the upper diode D 11 and D 12 Carrying current I o1 and I o2 , and the turn-off event is similar to the Mode A (from diode to switch) commutation in the ARCP converter:

[0156] a) According to the embodiment, the upper switch S 11 and S 12 The turn-off event is not delayed at all but can occur immediately. The upper diode D 21 and D 22 Keep conducting respectively.

[0157] b) Similar to ARCP mode A commutation, the commutation is related to the output current I o1 and I o2 In an embodiment, the lower switch S 21 and S 22 The switch-on events are delayed by a variable time step t d,on =t D +K on *|I o |, where t D is the predetermined turn-on delay, and K on is the same as k in ARCP mode A A The corresponding factor proportional control gain (positive constant).

[0158] c) Current I o1 and I 02 Respectively switch to the lower switch S 21 and S 22 , and the branch output 110 is connected to the lower dc rail 24 (U DC -).

[0159] Similarly, from the lower dc rail 24 (U DC- ) to upper dc rail 22 (U DC+ ) are the lower switch S 21 and S 22 The turn-off sequence of the upper switch S 11 and S 12 The switch-on sequence:

[0160] HS2) Lower switch S 21 The lower switch S 22 is turned on in branch INV2, and the branch output 110 is connected to the lower dc rail 24 (U DC- ).

[0161] HS2.pos) If the current is positive, I o >0, the lower diode D 21 and D 22 The diodes carry current respectively, and the turn-off event is similar to the mode A (from diode to switch) commutation in the ARCP converter:

[0162] a) According to the embodiment, the lower switch S 21 and S 22 The turn-off event is not delayed at all but can occur immediately. 21 and D 22 Keep conducting respectively.

[0163] b) Similar to ARCP mode A commutation, the commutation is related to the output current I o1 and I o2 In an embodiment, the upper switch S 11 and S 12 The switch-on events are delayed by a variable time step t d,on =t D +K on *|I o |, where t D is the predetermined turn-on delay, and K on is the same as k in ARCP mode A A The corresponding factor proportional control gain (positive constant).

[0164] c) Current I o1 and I o2 Respectively switch to the upper switch S 11 and S 12 , and the branch output 110 is connected to the upper dc rail 22 (U DC+ ).

[0165] HS2.neg) If the current is negative, I o <0, the lower switch S 21 and S 22 The switches carry currents respectively, and the turn-off event is similar to the Mode B (switch to diode) commutation in the ARCPI converter:

[0166] a) Similar to ARCP Mode B commutation, the converter branch with higher current must have its commutation sequence shifted earlier in time. In an embodiment, the lower switch S 21 and S 22 The switch-off events are delayed by a variable time step t d,off =t c -k off *|I o |, where t c is the constant delay time of the two converter legs starting from the incoming PWM edge providing the command to start commutation, similar to the time t in the case of ARCP B0 , and k off is the same as K in ARCP mode B B1 The corresponding advance factor (normal number).

[0167] b) Current I o1 and I o2 Respectively switch to the upper diode D 11 and D 12 .

[0168] c) Upper switch S 11 and S 12 At the predetermined switch-on delay t D This is usually used to prevent the upper switch and the lower switch in a hard-switching converter from being turned on at the same time, ie, to avoid a DC link short circuit.

[0169] d) The branch output 110 is connected to the upper dc rail 22 (U DC+ ).

[0170] The autonomous branch-specific switching moment adjustment according to the invention can also be applied in case of parallel connected phase branches having different nominal current ratings.For thermal and economic reasons it is of vital importance that the loading of the branches is as close as possible to their respective nominal ratings.

[0171] At the nominal rating I N1 and I N2 Under different circumstances, the expected current share should be

[0172] or

[0173] Let us denote the ratio I by r1 o1 / I N1 And r2 represents the ratio I o2 / I N2 Because I o1 and I o2is a time-varying variable (usually sinusoidal), so the ratio r1 and r2 is also time-varying. In ideal current sharing, it is clear that r1 = r2.

[0174] Let us examine connecting ARCP converter legs of different nominal current ratings in parallel. In mode B, the load current I o Participating in the resonance capacitor C 11 and C 12 The voltage swings in charging and discharging of the parallel connected ARCP branches are shown in Figure 2. This feature provides a natural current balancing mechanism in the parallel connected ARCP branches, because the branch with a higher ratio r will have a faster voltage swing, which tends to make the value of the difference r1-r2 smaller. It can be shown that the natural balance in mode B tends to make the voltage swing slopes in the parallel ARCP branches the same during commutation. (Provided that there is no deviation in the turn-off instant of the main switch.)

[0175] Let us assume that the resonant capacitors C of the converter branches INV1 and INV2 are 11 / C 21 and C 12 / C 22 Basically different, for example, in branch INV1 there is a total of 1μF, but in branch INV2 there is only a total of 500nF. If the size of branch INV1 is twice the nominal current of branch INV2, so that I N1 =2I N2 , this will be the case. Therefore, the resonant inductor L1 in branch INV1 will be half the size of the resonant inductor L2 in branch INV2, so that the resonant frequencies in both branches will be equal. In this case, the output current of branch INV1 will tend to be twice that of branch INV2. Otherwise, the voltage slopes will not be the same. Under these conditions, mode B forces the parallel connected branches to share current in a 2:1 ratio. This happens without any control, it is just a natural characteristic of the circuit. Deviations in timing and other aspects violate this ideal situation, but the effect is quite strong.

[0176] In an embodiment, according to k A1 I N1 =k A2 I N2 and k B1 I N1 =k B2 I N2 , choose the factor k in equations (13), (14) and (20), (21) A and k B is scaled with the nominal current in branches INV1 and INV2, where k A1 and k B1 is a factor and I N1is the nominal current of branch INV1, and k A2 and k B2 is a factor and I N2 is the nominal current of branch INV2. The scaling can be applied to any number of parallel branches. In the special case where the converter branches connected in parallel have equal nominal branch currents, i.e., I N1 =I N2 …=I NN , for all converter branches, the factor k A and k B are also equal, that is, k A1 =k A2 …=k AN And k B1 =k B2 …=k BN .

[0177] Fig.10 A timing diagram of an exemplary simulation is shown, illustrating the case where two ARCP converter branches sized for a nominal current ratio of 2:1 are connected in parallel. The ARCP branch INV1 is sized to C 11 =C 21 =500nF, L1=625nH, k A1 =1, k B1 =1,L o1 =625nH, I bA,r1 =I bB,r1 =150A. The size of ARCP branch INV2 is C 12 =C 22 =250nF, L2=1250nH, k A2 =2, k B2 =2,L o2 =1250nH, I bA,r2 =I bB,r2 =75A. Therefore, the target current sharing between the converter branches is 2:1. Autonomous current balancing is applied to the two converter branches INV1 and INV2. The total output current is -1350A, initially evenly sharing -675A and -675A. In addition, in the simulation, the main switch turn-off moment is delayed by 50ns in branch INV2 and the auxiliary switch turn-on moment is delayed by 100ns in branch NV2 to show the effectiveness of the balancing algorithm in real non-ideal situations. The initial condition has equal current sharing, which is too far from the target because branch INV1 should take -900A and branch INV2 should take -450A. Two carrier cycles in this simulation are sufficient to balance the branch output current I o1 and I o2This occurs despite the errors introduced in the switching timings and the mismatch between the main switch and the diode characteristics.

[0178] Similarly, in case the parallel connected hard-switched converter branches have different nominal current ratings, the autonomous branch-specific switching timing adjustment according to the present invention may also be applied. on or k off With the nominal branch current I of the converter branches INV1 and INV2 N1 and I N2 Scaling so that the constant k on With the nominal branch current I N The product of is the same in both parallel-connected converter branches and the constant k off With the nominal branch current I N The product of is the same in the two parallel-connected converter branches, i.e., k on1 I N1 =k on2 I N2 And k off1 I N1 =k off2 I N2 The scaling can be applied to any number of parallel branches. In the special case where the converter branches connected in parallel have equal nominal branch currents, i.e., I N1 =I N2 …=I NN , for all converter branches, the factor k on and k off are also equal, that is, k on1 =k on2 …=k onN And k off1 =k off2 …=k offN .

[0179] The switch control and current sharing techniques described herein may be implemented by various components. For example, these techniques may be implemented in hardware (one or more devices), firmware (one or more devices), software (one or more modules), or a combination thereof. For firmware or software, implementation may be performed by modules (e.g., programs, functions, etc.) that perform the functions described herein. The software code may be stored in any suitable (multiple) processor / computer readable data storage medium or (multiple) memory unit and executed by one or more processors / computers. The data storage medium or memory unit may be implemented within a processor / computer or outside a processor / computer, in which case it may be communicatively coupled to the processor / computer via various components known in the art. Additionally, the components of the system described herein may be re-installed and / or conceived by additional components to facilitate the realization of various aspects, objectives, advantages, etc. described therein, and they are not limited to the precise configurations set forth in a given figure, as will be appreciated by those skilled in the art.

[0180] The description and related drawings are intended only to illustrate the principles of the present invention by way of example. Based on this description, various alternative embodiments, variations and changes will be apparent to those skilled in the art. The present invention is not intended to be limited to the examples described herein, but the present invention may vary within the scope and spirit of the appended claims.

Claims

1. A power converter system, comprising: Two or more converter branches connected in parallel between a common DC system and a common AC system or between two common DC systems, wherein each of the converter branches comprises a first controllable main switching device having a first anti-parallel diode and a second controllable switching device having a second anti-parallel diode, the first controllable main switching device and the second controllable switching device being connected in series between a first DC voltage rail and a second DC voltage rail to alternately connect the first DC link rail and the second DC link rail to a converter branch output or a converter branch input, wherein each of the converter branches connected in parallel comprises a commutation mode A and a commutation mode B, in which mode A the branch current is commutated from the first anti-parallel diode or the second anti-parallel diode to the second controllable main switching device or the first controllable main switching device, respectively, and in which mode B the branch current is commutated from the first controllable main switching device or the second controllable main switching device to the second anti-parallel diode or the first anti-parallel diode, respectively, wherein commutation of the parallel-connected converter branches is initiated by substantially simultaneous commutation commands, A control device is configured to sense the branch current in each of the parallel-connected inverter branches, and wherein the control device is configured to balance the current sharing between the parallel-connected inverter branches by means of having individual autonomous branch-specific switching timing adjustments of the main switches of each of the parallel-connected converter branches to shift the mode A commutation of the respective converter branch later in time by a variable time step and shift the mode B commutation of the respective converter branch earlier in time by the variable time step, the variable time step being proportional to the value of the sensed branch current of the respective converter branch.

2. The power converter system of claim 1 , wherein each individual autonomous branch-specific switching timing adjustment is configured to shift the start of a branch voltage swing later in time by a variable time step during the mode A commutation of the corresponding converter branch, and to shift the start of a branch voltage swing earlier in time by the variable time step during the mode B commutation of the corresponding converter branch, the variable time step being proportional to the value of the sensed branch current of the corresponding converter branch.

3. A power converter system according to claim 1, wherein the size of the variable time step of the individual offset later in time during the individual mode A commutation and the size of the variable time step of the individual offset earlier in time during the individual mode B commutation are configured to depend on the value of the sensed branch current of the corresponding converter branch, in such a way that the size of the variable time step of the individual offset in time increases with increasing value of the sensed branch current and decreases with decreasing value of the sensed branch current.

4. A power converter system according to claim 1, wherein each individual autonomous branch-specific switching moment adjustment of the main switching device has a first predetermined dependency on the value of the sensed branch current of the corresponding converter branch in the mode A commutation and a second predetermined dependency in the mode B commutation, and wherein optionally, the first predetermined dependency and the second predetermined dependency of different parallel-connected converter branches having different nominal branch current ratings are selected to scale the current sharing between the parallel-connected converter branches according to the nominal branch currents of the parallel-connected converter branches.

5. The power converter system of claim 1 , wherein the parallel-connected converter branches are auxiliary resonant commutated pole ARCP converter branches, in particular ARCP half-bridge branches, and wherein the control means is configured to advance each ARCP mode B commutation sequence and retard each ARCP mode A commutation sequence in time in such a way that the size of the variable time step increases with increasing values ​​of the sensed branch current of the respective converter branch and decreases with decreasing values ​​of the sensed branch current. 6 . The power converter system of claim 5 , wherein the ARCP commutation sequence includes a sequence from a turn-on timing of at least one auxiliary switching device to a turn-off timing of the main switching device that is always turned on.

7. The power converter system according to claim 5, wherein the control device is configured to delay both the turn-on instant of the at least one auxiliary switching device and the turn-off instant of the main switching device by a first variable time step t in the mode A commutation. wA , the first variable time step t wA increases with the increasing value of the sensed branch current of the respective converter branch and decreases with the decreasing value of the sensed branch current, and wherein the control means is configured to delay both the turn-on instant of the at least one auxiliary switching device and the turn-off instant of the main switching device in the mode B commutation by a second variable time step t wB , the second variable time step t wB The switching time of the main switching device is reduced with the increasing value of the sensed branch current of the corresponding converter branch and increased with the decreasing value of the sensed branch current, thereby advancing the switch-off time of the main switching device in proportion to the value of the sensed branch current.

8. The power converter system according to claim 7, wherein the control device is configured to: wA The turning-off time of the main switching device in the mode A commutation is delayed by adding the second variable time step t to the reference turning-off time of the main switching device, and wherein the control device is configured to delay the turning-off time of the main switching device in the mode A commutation by adding the second variable time step t wB The reference turn-off timing of the main switching device is added to advance the turn-off timing of the main switching device in the mode B commutation.

9. The power converter system of claim 7, wherein the first variable time step is t wA =k A |I o |, where I o is the value of the sensed branch current sample of the respective converter branch, and k A is a constant, k A is equal for all converter branches having equal nominal branch current ratings, and wherein the second variable time step is t wB =t c -k B |I o |, where t wB ≥0, I o is the value of the sensed branch current sample of the respective converter branch, t c is constant time, and k B is a constant, k B The branches are equal for all converters having equal nominal branch current ratings.

10. The power converter system of claim 9, wherein the parallel-connected converter branches have different nominal branch current ratings, and wherein the constant k in the parallel-connected converter branches A and / or k B is chosen to scale with the nominal branch current of the converter branch so that the constant k A With the nominal branch current I N The product of is the same in all parallel-connected converter branches and the constant k B With the nominal branch current I N The product of is essentially the same in all parallel-connected converter branches.

11. The power converter system according to claim 1 , wherein the parallel-connected converter branches are hard-switching converter branches, in particular half-bridge branches, and wherein the control device is configured to delay the turn-off instant of the main switching device that is always turned on by a first variable time step t in the mode B commutation. d,off , the first variable time step t d,off The control device is configured to delay the turn-on instant of the main switching device to start conducting in the mode A commutation by a second variable time step t d,on , the second variable time step t d,on The voltage regulator increases with the increasing value of the sensed branch current of the respective converter branch and decreases with the decreasing value of the sensed branch current.

12. The power converter system of claim 11, wherein the first variable time step t d,off According to k off *|I o | Decreases with the increasing value of the sensed branch current, where I o is the value of the sensed branch current of the respective converter branch and k B is a constant, k B is equal for all converter branches having equal nominal branch current ratings, and wherein the second variable time step t d,on According to k on *|I o | increases with the increased value of the sensed branch current, where I o is the value of the sensed branch current of the respective converter branch and k on is a constant, k on The branches are equal for all converters having equal nominal branch current ratings.

13. The power converter system of claim 11 , wherein the first variable time step is t d,off =t c -k off |I o |, where t c is a constant time defining the adjustment range, and wherein the second variable time step is t d,on =t D +k on |I o |, where t D is an optional constant turn-on delay to avoid simultaneous turning-on of the main switching devices.

14. The power converter system of claim 12, wherein the parallel-connected converter branches have different nominal branch current ratings, and wherein the constant k in the parallel-connected converter branches on or the constant k off is chosen to scale with the nominal branch current of the converter branch so that the constant k on With the nominal branch current I N The product of is the same in all parallel-connected converter branches and the constant k off With the nominal branch current I N The product of is the same in all parallel-connected converter branches.

15. The power converter system according to claim 1, wherein the control means comprises a branch-specific controller for each converter branch of the two or more parallel-connected converter branches to adjust the switching timing of the main switching device.

16. The power converter system of claim 1, wherein the power inverter system comprises two or more converters, each of the converters comprising one or more converter phase branches, wherein the parallel-connected converter branches are corresponding converter phase branches of the two or more converters connected in parallel.

17. A power inverter system according to claim 16, wherein the control device includes converter-specific switch controllers for the two or more converters, each of the converter-specific switch controllers being configured to provide autonomous adjustment of switching timing for each of the converter phase legs of the corresponding converter.

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