SAR ADC Sampling Circuit, ADC Circuit and Device

Abstract

The present invention discloses a SAR ADC sampling circuit, which includes: a front-end driving module for buffering and amplifying an input signal and outputting an amplified signal; a sampling capacitor array for signal sampling and quantization conversion; and a control module for controlling the sampling capacitor of the sampling capacitor array to be pre-charged by the amplified signal output by the input driving module after the start of a sampling period, and controlling the sampling capacitor array to sample the input signal after a set delay. By using the solution of the present invention, the sampling capacitor array can adopt a larger unit capacitor and ensure the sampling accuracy.

Description

Technical Field

[0001] The present invention relates to the field of circuit technologies, and particularly to a SAR ADC sampling circuit, an ADC circuit and a device. Background Art

[0002] A SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a common analog-to-digital converter, and its working principle is to achieve the conversion from an analog signal to a digital signal through successive approximation. The precision of a SAR ADC can range from 8 bits to 16 bits, and the throughput rate can range from extremely slow on-demand conversion requests to more than one million conversions per second. Due to its flexibility in speed and performance, the SAR ADC is widely used in chips such as MCUs.

[0003] A SAR ADC generally uses a capacitor array (C-DAC) with a pure capacitor structure to implement signal sampling and conversion. The number of unit capacitors in the capacitor array is related to the precision, which is 2 N , where N is the bit number of the SAR ADC. For a SAR ADC with high precision (bit number N>12), the size of the traditional capacitor array increases exponentially (2 N ) with the increase of the bit number. Moreover, with the increase of the bit number N, the requirement for unit capacitor mismatch is more stringent, and a larger unit capacitor is needed to reduce the mismatch to meet the requirement of ADC output linearity.

[0004] During the sampling stage, a SAR ADC requires a pre-stage drive circuit to charge and discharge the sampling capacitor, and stabilize the voltage on the sampling capacitor within the ADC precision requirement range within a specified time. Obviously, the larger the unit capacitor in the capacitor array, the higher the requirement for the front-end drive. To address this problem, the following two methods are usually adopted: (1) The segmented capacitor structure method, that is, the entire capacitor array is divided into a high-bit segment and a low-bit segment to reduce the capacitance quantity of the high-bit segment. However, no matter how it is segmented, once the segmented structure is determined, the capacitor size is also determined. In some applications, it cannot be guaranteed that the input signals provided to all channels can meet the drive requirements. (2) The method of increasing the front-end drive circuit, that is, the input signal is first buffer-amplified by the front-end drive circuit and then sampled by the ADC sampling capacitor. This method will introduce the error of the front-end drive circuit, affecting the precision of the ADC. Moreover, the range of the input signal is limited by the internal buffer of the front-end drive circuit. Summary of the Invention

[0005] An embodiment of the present invention provides a SAR ADC sampling circuit, an ADC circuit and a device, so as to reduce the driving requirement of the ADC for the input signal, enable the ADC to adapt to a wider input signal range, and ensure the sampling accuracy.

[0006] On the one hand, an embodiment of the present invention provides a SAR ADC sampling circuit, and the circuit includes:

[0007] A front-end driving module, configured to buffer and amplify an input signal and output an amplified signal;

[0008] A sampling capacitor array, configured to perform signal sampling and quantization conversion;

[0009] A control module, configured to control the sampling capacitors of the sampling capacitor array to be pre-charged with the amplified signal output by the front-end driving module after the start of the sampling period, and control the sampling capacitor array to sample the input signal after a set delay.

[0010] Optionally, the control module includes: a control unit, a first switch, and a second switch; the first switch is respectively connected to the output end of the front-end driving module and the input end of the sampling capacitor array; the second switch is respectively connected to the input end of the front-end driving module and the input end of the sampling capacitor array;

[0011] The control unit is configured to control the first switch to close and the second switch to open after the start of the sampling period; and after a certain delay, control the first switch to open and the second switch to close.

[0012] Optionally, the first switch and the second switch are any one of the following: MOS transistor, triode.

[0013] Optionally, the control unit includes:

[0014] A first control signal generating unit, configured to generate a first control signal according to an external reset signal to control the first switch to close after the start of sampling and open after a certain delay;

[0015] An inverter, configured to invert the first control signal;

[0016] A second control signal generating unit, configured to generate a second control signal according to a sampling signal to control the second switch to close and open after the end of the sampling period.

[0017] Optionally, the first control signal generation unit includes a first D flip-flop, the clock signal of the first D flip-flop is the ADC clock signal, and the control signal of the first D flip-flop is the external reset signal; the second control signal generation unit includes a second D flip-flop, the clock signal of the second D flip-flop is the output signal of the inverter, and the control signal of the second D flip-flop is the sampling signal.

[0018] Optionally, the front-end drive module includes: a unity gain amplifier.

[0019] Optionally, the sampling capacitor array includes any one of the following: a capacitor array with a pure capacitor structure, a capacitor structure array with a segmented structure.

[0020] Optionally, the sampling method of the sampling capacitor array includes any one of the following: upper plate sampling, lower plate sampling.

[0021] On the other hand, an embodiment of the present invention further provides an ADC circuit, and the ADC circuit includes the SAR ADC sampling circuit described above.

[0022] On the other hand, an embodiment of the present invention further provides an ADC device, and the device includes: a multiplexer, and the ADC circuit described above;

[0023] The multiplexer is connected to multiple external inputs and is used to select one of the external inputs as the input signal of the ADC circuit;

[0024] The ADC circuit is used to sample and convert the input signal and output the converted digital signal.

[0025] In the SAR ADC sampling circuit provided by the embodiment of the present invention, after the sampling period starts, the front-end drive module is first used to buffer and amplify the input signal, sample the amplified output signal, and then sample the input signal. The driving ability of the input signal is improved through the front-end drive module, the driving requirement of the ADC for the input signal is reduced, so that the ADC can adapt to a wider range of input signals. Moreover, since the front-end drive module only plays an auxiliary role and the sampling signal is finally driven by an external circuit, the error of the front-end drive module itself will not affect the accuracy of the sampling result.

[0026] By using the SAR ADC sampling circuit provided by the embodiment of the present invention, the design index of the internal sampling capacitor array of the ADC can be relaxed, and a larger unit capacitor can be used for the sampling capacitor array to meet the linearity requirement of the ADC and ensure the sampling accuracy.

[0027] Compared with the existing segmented C-DAC, the SAR ADC sampling circuit provided by the embodiment of the present invention allows the ADC to select a larger unit capacitance and input capacitance during design, thereby reducing the mismatch of the capacitance array.

[0028] Compared with the existing circuit using the front-end drive method, the front-end drive module in the SAR ADC sampling circuit provided by the embodiment of the present invention only plays an auxiliary role, and the error it brings will not affect the sampling accuracy of the ADC; moreover, it can also reduce the requirements for the performance of the front drive module in the design.

[0029] In addition, by using the SAR ADC sampling circuit provided by the embodiment of the present invention, the ADC can be equipped with a front-end multiplexer, so that the input signal can have a wider application range. Moreover, the multiplexer can arbitrarily increase the number of channels and only one front-end drive module is needed, effectively saving the chip area of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0031] Figure 1 is a schematic diagram of the segmented capacitance structure in the existing SAR ADC;

[0032] Figure 2 is a schematic diagram of the sampling capacitance array and the front-end drive circuit in the existing SAR ADC with an added front-end drive circuit;

[0033] Figure 3 is a schematic diagram of the structure of the SAR ADC sampling circuit provided by the embodiment of the present invention;

[0034] Figure 4 is a schematic diagram of the control principle of the sampling signal by the control module in the embodiment of the present invention;

[0035] Figure 5 is a specific schematic diagram of the structure of the SAR ADC sampling circuit and the control module provided by the embodiment of the present invention;

[0036] Figure 6 is Figure 5 a schematic diagram of the timing relationship of each signal in the shown embodiment;

[0037] Figure 7 is a schematic diagram of two common sampling methods of the ADC;

[0038] Figure 8 It is a schematic structural diagram of a sampling capacitor array in a SAR ADC sampling circuit provided by an embodiment of the present invention, adopting a segmented structure and a lower-plate sampling method;

[0039] Figure 9 It is Figure 8 a schematic diagram of the working state during sampling of the shown SAR ADC sampling circuit;

[0040] Figure 10 It is a schematic structural diagram of a sampling capacitor array in a SAR ADC sampling circuit provided by an embodiment of the present invention, adopting a segmented structure and a lower-plate sampling method;

[0041] Figure 11 It is Figure 10 a schematic diagram of the working state during sampling of the shown SAR ADC sampling circuit;

[0042] Figure 12 It is a schematic structural diagram of a sampling capacitor array in a SAR ADC sampling circuit provided by an embodiment of the present invention, adopting a non-segmented structure and an upper-plate sampling method;

[0043] Figure 13 It is Figure 12 a schematic diagram of the working state during sampling of the shown SAR ADC sampling circuit. Detailed implementation manners

[0044] The principles and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the drawings. It should be understood that describing these embodiments is only for enabling those skilled in the art to better understand and thus implement the present invention, rather than limiting the scope of the present invention in any way.

[0045] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present invention.

[0046] The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0047] A high-precision SAR ADC needs to increase the unit capacitance in the sampling capacitor array, and the increase in unit capacitance poses higher requirements for the front-end drive. First, the segmented capacitor structure method and the method of increasing the front-end drive circuit adopted in the existing technology for this problem are briefly introduced below.

[0048] Referring to Figure 1 shown is a schematic diagram of the segmented capacitor structure in the existing SAR ADC.

[0049] The segmented capacitor structure divides the entire capacitor array into a high-bit segment (M high capacitors) and a low-bit segment (L low capacitors), where M + L = N, and N is the total number of bits of the ADC. The segmented capacitor structure proportionally reduces (i.e., 2 L ) the number of capacitors in the high-bit segment through the bridging capacitor, so that the capacitance size at the input is reduced by 2 L times.

[0050] Taking 8 bits as an example, the input capacitance of the traditional structure is 256C, while using the Figure 1 shown segmented capacitor structure, the capacitor array is segmented into 4 - 4 through the bridging capacitor Ca, that is, 4 bits in the high-bit segment and 4 bits in the low-bit segment, and the sampling capacitor can be reduced to 16C (C is the unit capacitance).

[0051] Figure 1 In

[0052] Vin is the sampling voltage and Vrefp is the reference voltage. In this segmented capacitor structure, the reduction ratio of the capacitance will be deviated due to the influence of parasitic capacitance, resulting in the non-linearity of the ADC. Therefore, the choice of L should not be too large, otherwise it will affect the linearity of the ADC output; while too small L will make the number of capacitors in the high-bit segment too many, resulting in a still large input capacitance.

[0053] In addition, in some applications, the input of the SAR ADC will pass through a multiplexer, allowing multiple channels to call the ADC, and the above-mentioned segmented capacitor structure is sometimes difficult to meet the driving requirements of all channels, that is, the driving capabilities of multiple channels are different. The external input circuits of some channels can drive the capacitors inside the ADC to work normally, while for some channels with weak driving capabilities, their external input circuits may not be able to drive the capacitors inside the ADC to work normally.

[0054] Referring to Figure 2 shown is a schematic diagram of the structure of the sampling capacitor array and the front-end drive circuit in the existing SAR ADC with an increased front-end drive circuit.

[0055] The input signal Vin first passes through the front-end drive circuit 21, and the output of the front-end drive circuit 21 is then sampled by the sampling capacitor. The front-end drive circuit 21 is generally connected by an amplifier to form a unity-gain amplifier, and there will be a gain error in the output. For example, if the amplifier gain is 40 dB, then there will be a 1% gain error in the output, that is, when the input is 1 V, the output is 0.99 V. When the gain is 80 dB, there will be a 0.01% gain error, that is, when the input is 1 V, the output is 0.9999 V. In any case, there will be a gain error in the output. Secondly, even for a rail-to-rail (i.e., full-swing) amplifier, since the PMOS transistor and the NMOS transistor in the buffer will each consume a source-drain voltage Vds, and Vds is generally about 100 mV to 200 mV. For example, when the input is 0 mV, the output will be around Vds; when the input is Vdd, the output will be around Vdd - Vds.

[0056] Therefore, this way of adding the front-end drive circuit will cause the error of the front-end drive circuit 21 to be sampled by the ADC as well, directly affecting the accuracy of the ADC. At the same time, the input buffer in the front-end drive circuit 21 will limit the input range of the ADC because the output of the front-end drive circuit 21 cannot reach the actual input range of the input signal, which is 0 to Vdd.

[0057] For this reason, the embodiment of the present invention provides a SAR ADC sampling circuit. After the sampling period starts, the input signal is first buffered and amplified by the front-end drive module, the amplified signal output is sampled, and then the input signal is sampled. By the front-end drive module, the driving ability of the input signal is improved, the driving requirement of the ADC for the input signal is reduced, so that the ADC can adapt to a wider input signal range. Moreover, since the front-end drive module only plays an auxiliary role and the sampling signal is finally driven by an external circuit, the error of the front-end drive module itself will not affect the accuracy of the sampling result.

[0058] As Figure 3 shown, it is a schematic structural diagram of a SAR ADC sampling circuit provided by the embodiment of the present invention.

[0059] The SAR ADC sampling circuit 300 includes: a front-end drive module 301, a sampling capacitor array 302, and a control module 303. Among them:

[0060] The front-end drive module 301 is used to buffer and amplify the input signal and output an amplified signal;

[0061] The sampling capacitor array 302 is used for signal sampling and quantization conversion;

[0062] The control module 303 is used to control the pre - charging of the sampling capacitors of the sampling capacitor array by the amplified signal output by the front - end driving module after the start of the sampling period, and to control the sampling of the input signal by the sampling capacitor array after a set delay time.

[0063] The front - end driving module 301 can be implemented by a unity - gain amplifier.

[0064] The sampling capacitor array 302 can be a pure - capacitor - structured capacitor array (C - DAC) or a segmented - structured capacitor array.

[0065] In a non - restrictive embodiment, the control module 303 can implement the above functions through corresponding switches.

[0066] As Figure 4 shown, it is a schematic diagram of the control principle of the control module for the sampling signal in the embodiment of the present invention.

[0067] In the SAR ADC sampling circuit provided by the embodiment of the present invention, the sampling is divided into two stages:

[0068] In the first stage, the first switch K1 is closed, and the input signal Vin passes through the front - end driving module 301 to quickly sample the signal with error (i.e., the output signal of the front - end driving module 301) onto the input capacitor.

[0069] In the second stage, the front - end driving module 301 is turned off, the second switch K2 is closed, and through an external drive, the accurate input signal Vin is directly sampled onto the input capacitor. Then, wait for the ADC to enter the conversion stage.

[0070] It can be seen that in the solution of the present invention, the front - end driving module 301 only plays an auxiliary role, so that the voltage on the input capacitor is quickly increased to be close to the actual input signal Vin, and the input signal Vin driven externally ultimately determines the size of the sampling voltage. Therefore, regardless of the error size of the front - end driving module 301, it will not affect the sampling signal of the ADC.

[0071] In some embodiments, Figure 3 the control module 303 in Figure 4 may include: a control unit, a first switch, and a second switch. Referring to

[0072] The control unit is configured to control the first switch K1 to close and the second switch K2 to open after the start of the sampling period; after a certain delay, control the first switch K1 to open and the second switch K2 to close. It should be noted that, in order to further reduce power consumption, when the first switch K1 is open, the front-end driving module 301 can also be turned off simultaneously, or only the front-end driving module 301 can be turned off to stop its output. The embodiments of the present invention do not limit this.

[0073] The closing or opening of the above-mentioned first switch K1 and second switch K2 can be controlled by a corresponding control unit ( Figure 4 not shown in the figure) to generate a first control signal and a second control signal.

[0074] In a non-limiting embodiment, the control unit may include:

[0075] A first control signal generating unit, configured to generate a first control signal according to an external reset signal to control the first switch to close after the start of sampling and to open after a certain delay;

[0076] An inverter, configured to invert the first control signal;

[0077] A second control signal generating unit, configured to generate a second control signal according to a sampling signal to control the second switch to close and to open after the end of the sampling period.

[0078] In specific implementation, the above-mentioned first switch K1 and second switch K2 can be implemented by any one of the following devices: MOS transistors, bipolar transistors, etc.

[0079] Taking an NMOS transistor as an example, as Figure 5 shown, it is a schematic structural diagram of a specific SAR ADC sampling circuit and control module provided by an embodiment of the present invention.

[0080] In this example, the control module 303 includes a first NMOS transistor N1, a second NMOS transistor N2, and a control unit composed of a first D flip-flop 331, a second D flip-flop 332, and an inverter 333.

[0081] Figure 5 In the figure, CLK is the clock of the ADC; SMP is the sampling signal, input to the reset terminal of the second D flip-flop, and the sampling duration is Ts; RST is the reset signal of the first D flip-flop 331.

[0082] Figure 5 The timing relationship of each signal in the figure is as Figure 6 shown.

[0083] At the same time, referring to Figure 5 and Figure 6, after power-on, RST and SMP are at high level, and the first sampling period is entered. Since RST is at high level, the first control signal S1 output from the Q terminal of the first D flip-flop 331 is pulled high to Vdd (Vdd is the operating voltage of the D flip-flop) at the rising edge of the clock signal CLK, and the first control signal S1 controls the first NMOS transistor N1 to conduct; during the period when the first control signal S1 remains at high level, the second control signal S2 output from the Q terminal of the second D flip-flop is at low level, and the second control signal S2 controls the second NMOS transistor N2 to turn off. The duration of the high level of RST is T1. During this period, the amplified signal with error output by the front-end drive module 301 quickly charges the sampling capacitor array 302, and the charging duration is T1.

[0084] Then, RST becomes low level. Correspondingly, the first control signal S1 is reset to 0. Triggered by the falling edge of the first control signal S1, the second control signal output by the second D flip-flop 332 is pulled high to Vdd for a duration of T2. During this period, the first control signal S1 controls the first NMOS transistor N1 to turn off, and the second control signal S2 controls the second NMOS transistor N2 to conduct. The input signal Vin charges the sampling capacitor array 302 to achieve sampling of the input signal Vin. When the continuous charging duration reaches T2, the sampling ends, and the sampling signal SMP is set to 0 to end this round of sampling. The total sampling duration Ts = T1 + T2.

[0085] It should be noted that in specific implementation, the conduction time of the P1 and P2 switches can be flexibly adjusted according to the bandwidth of the sampling buffer.

[0086] The above Figure 5 In the above-described embodiment, the first switching transistor and the second switching transistor are taken as PMOS transistors for illustration. In specific implementation, other switching devices can also be used to achieve the above functions, and the principle is similar, so it will not be elaborated here.

[0087] Using the SAR ADC sampling circuit provided by the embodiment of the present invention, the driving requirement of the ADC for the input signal can be reduced, so that the ADC can adapt to a wider range of input signals. Moreover, since the front-end drive module only plays an auxiliary role and the sampling signal is finally driven by an external circuit, the error of the front-end drive module itself will not affect the accuracy of the sampling result.

[0088] In the SAR ADC sampling circuit provided by the embodiment of the present invention, Figure 3 the sampling capacitor array 302 in it can be a capacitor array with a pure capacitor structure or a segmented capacitor array; the sampling method can be upper-plate sampling or lower-plate sampling.

[0089] SAR ADC sampling can be divided into two schemes: upper-plate sampling and lower-plate sampling. For example, Figure 7As shown, (a) is the sampling of the upper plate, and (b) is the sampling of the lower plate.

[0090] For the sampling of the upper plate, if the switch SW connected to the input signal source Vin is disconnected, then the sampling capacitor C completes the sampling. The lower plate sampling structure consists of two switches SWb and SWt. At the end of sampling, the switch SWb is disconnected first, and then the switch SWt connected to the input signal source Vin is disconnected.

[0091] The following examples are used to illustrate different structures and sampling methods of the sampling capacitor array in the SAR ADC sampling circuit provided by the embodiments of the present invention.

[0092] Example 1: Refer to Figure 8 and Figure 9 , Figure 8 is a schematic structural diagram of the sampling capacitor array in the SAR ADC sampling circuit provided by the embodiments of the present invention, which adopts a segmented structure and a lower plate sampling method. Figure 9 is Figure 8 a schematic diagram of the working state during sampling of the SAR ADC sampling circuit shown.

[0093] In the figure, VCM is the input common-mode voltage of the SAR ADC, and Vrefp is the reference voltage of the SAR ADC. During sampling, the upper plate switch is controlled by the sampling signal SMP to conduct. The upper plate of the high-bit segment is connected to VCM, and the lower plate is connected to the input signal Vin. The lower plates of all capacitors in the low-bit segment are grounded. After sampling, the upper plate switch of the high-bit segment is disconnected and floats, and the lower plate switch is also disconnected. The lower plates of the capacitors in the low-bit segment remain grounded. At this time, the input signal is sampled and stored in the sampling capacitor array. The total stored charge Q can be calculated by the following formula:

[0094] Q = C total,MSB ×(VCM - Vin);

[0095] where C total,MSB represents the total capacitance of the high-bit segment.

[0096] Example 2: Refer to Figure 10 and Figure 11 , Figure 10 is a schematic structural diagram of the sampling capacitor array in the SAR ADC sampling circuit provided by the embodiments of the present invention, which adopts a traditional non-segmented structure and a lower plate sampling method. Figure 11 is Figure 10 a schematic diagram of the working state during sampling of the SAR ADC sampling circuit shown.

[0097] In the figure, VCM is the input common-mode voltage of the SAR ADC, and Vrefp is the reference voltage of the SAR ADC.

[0098] During sampling, the upper plate switch is turned on under the control of the sampling signal SMP. The upper plates of the capacitors in the capacitor array are connected to VCM, and the lower plates are connected to the input signal Vin. After sampling, the upper plate switch is turned off, and the lower plate switch is also turned off. At this time, the input signal is stored in the capacitor array. The total stored charge Q can be calculated by the following formula:

[0099] Q = C total × (VCM - Vin);

[0100] where C total represents the total capacitance of the capacitor array.

[0101] Example 3: Referring to Figure 12 and Figure 13 , Figure 12 is a schematic structural diagram of the sampling capacitor array in the SAR ADC sampling circuit provided by the embodiment of the present invention, adopting a non-segmented structure and an upper plate sampling method, Figure 13 is Figure 12 a schematic diagram of the working state during sampling of the SAR ADC sampling circuit shown.

[0102] In the figure, VCM is the input common-mode voltage of the SAR ADC, and Vrefp is the reference voltage of the SAR ADC. During sampling, first, under the control of the first control signal S1, the upper plates of the capacitors in the capacitor array are connected to the amplified signal of the input signal Vin, and then, under the control of the second control signal S2, the upper plates are connected to the input signal Vin, and the lower plates are connected to Vcm. After sampling, the upper plate switch is turned off, and the lower plate switch is also turned off. At this time, the input signal is stored in the capacitor array. The total stored charge Q can be calculated by the following formula:

[0103] Q = C total × (Vin - VCM);

[0104] where C total represents the total capacitance of the capacitor array.

[0105] Correspondingly, the embodiment of the present invention also provides an ADC circuit, and this ADC circuit includes the above-mentioned SAR ADC sampling circuit.

[0106] Correspondingly, the embodiment of the present invention also provides an ADC device, and this ADC device includes a multiplexer and the ADC circuit described above. Among them:

[0107] The multiplexer is connected to multiple external inputs and is used to select one of the external inputs as the input signal of the ADC circuit;

[0108] The ADC circuit is used to sample and convert the input signal and output the converted digital signal.

[0109] The ADC device provided by the embodiment of the present invention can adapt to input signals in a variety of different ranges. In some applications that require ADC conversion of signals in a variety of different ranges, it can greatly save the area of the ADC chip, and is more conducive to the integrated and miniaturized design of the product.

[0110] In a specific implementation, for each device and product described in the above embodiments, each module / unit included therein can be a software module / unit, a hardware module / unit, or can be partially a software module / unit and partially a hardware module / unit.

[0111] For example, for each device and product applied to or integrated into a chip, each module / unit included therein can be implemented in a hardware manner such as a circuit. Or, at least some modules / units can be implemented in a software program manner, and the software program runs on a processor integrated inside the chip. The remaining (if any) part of the modules / units can be implemented in a hardware manner such as a circuit; for each device and product applied to or integrated into a chip module, each module / unit included therein can be implemented in a hardware manner such as a circuit. Different modules / units can be located in the same component (such as a chip, a circuit module, etc.) or different components of the chip module. Or, at least some modules / units can be implemented in a software program manner, and the software program runs on a processor integrated inside the chip module. The remaining (if any) part of the modules / units can be implemented in a hardware manner such as a circuit; for each device and product applied to or integrated into a terminal, each module / unit included therein can be implemented in a hardware manner such as a circuit. Different modules / units can be located in the same component (such as a chip, a circuit module, etc.) or different components inside the terminal. Or, at least some modules / units can be implemented in a software program manner, and the software program runs on a processor integrated inside the terminal. The remaining (if any) part of the modules / units can be implemented in a hardware manner such as a circuit.

[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A SAR ADC sampling circuit, characterized in that, The circuit includes: A front-end drive module for buffering and amplifying an input signal and outputting an amplified signal; A sampling capacitor array for signal sampling and quantization conversion; A control module for controlling the sampling capacitors of the sampling capacitor array to be pre-charged by the amplified signal output by the front-end drive module after the start of a sampling period, and after delaying a set time, controlling the sampling capacitor array to sample the input signal until the end of this sampling; The control module includes: a control unit, a first switch, and a second switch; the first switch is respectively connected to the output end of the front-end drive module and the input end of the sampling capacitor array; the second switch is respectively connected to the input end of the front-end drive module and the input end of the sampling capacitor array; The control unit is used to control the first switch to close and the second switch to open after the start of the sampling period; and after delaying a certain time, control the first switch to open and the second switch to close until the end of this sampling and then open; the control unit includes: a first control signal generation unit, an inverter, and a second control signal generation unit; The first control signal generation unit is used to generate a first control signal according to an external reset signal to control the first switch to close after the start of sampling and open after delaying a certain time; The inverter is used to invert the first control signal; The second control signal generation unit is used to generate a second control signal according to a sampling signal to control the second switch to close and open after the end of the sampling period; Wherein, the first control signal generation unit includes a first D flip-flop, the clock signal of the first D flip-flop is the ADC clock signal, and the control signal of the first D flip-flop is the external reset signal; Wherein, the second control signal generation unit includes a second D flip-flop, the clock signal of the second D flip-flop is the output signal of the inverter, and the control signal of the second D flip-flop is the sampling signal.

2. The SAR ADC sampling circuit according to claim 1, wherein The first switch and the second switch are any one of the following: MOS transistor, bipolar transistor.

3. The SAR ADC sampling circuit according to claim 1, characterized in that The front-end drive module includes: a unity gain amplifier.

4. The SAR ADC sampling circuit according to any one of claims 1 to 3, characterized in that The sampling capacitor array includes any one of the following: a capacitor array with a pure capacitor structure, a capacitor structure array with a segmented structure.

5. The SAR ADC sampling circuit according to any one of claims 1 to 3, characterized in that The sampling method of the sampling capacitor array includes any one of the following: upper plate sampling, lower plate sampling.

6. An ADC circuit, characterized in that, The ADC circuit includes the SAR ADC sampling circuit according to any one of claims 1 to 5.

7. An ADC device, characterized in that, The device includes: a multiplexer, and the ADC circuit according to claim 6; The multiplexer is connected to a plurality of external inputs for selecting one of the external inputs as the input signal of the ADC circuit; The ADC circuit is used to sample and convert the input signal and output the converted digital signal.

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