Ferroelectric memory device and method of manufacturing ferroelectric memory device

Abstract

The invention relates to a ferroelectric memory device and a manufacturing method of the ferroelectric memory device. A ferroelectric memory device includes a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive layers alternately stacked. The ferroelectric memory device also includes a channel layer extending in a vertical direction (stack direction) in the gate stack structure. The ferroelectric memory device further includes a ferroelectric pattern interposed between the plurality of conductive layers and the channel layer. The ferroelectric memory device additionally includes an anti-ferroelectric pattern interposed between the plurality of interlayer insulating layers and the channel layer.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to ferroelectric memory devices and methods of manufacturing ferroelectric memory devices. Background Art

[0002] Memory devices may be classified into volatile memory devices in which stored data disappears when power is interrupted and nonvolatile memory devices in which stored data is retained even if power is interrupted.

[0003] Non-volatile memory devices may include NAND flash memory, NOR flash memory, resistive random access memory (ReRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc.

[0004] Ferroelectric memory devices including ferroelectric random access memory can use the spontaneous polarization characteristics of ferroelectric materials to store data. Therefore, the ferroelectric memory device can use a material with ferroelectric characteristics as a data storage layer, and the electrical characteristics of the ferroelectric memory device can be changed according to the characteristics of the material used as the data storage layer. Summary of the invention

[0005] According to an embodiment of the present disclosure, a ferroelectric memory device includes: a gate stack structure, which includes a plurality of interlayer insulating layers and a plurality of conductive layers stacked alternately; a channel layer, which extends in a vertical direction (stacking direction) in the gate stack structure; a ferroelectric pattern, which is inserted between the plurality of conductive layers and the channel layer; and an antiferroelectric pattern, which is inserted between the plurality of interlayer insulating layers and the channel layer.

[0006] According to another embodiment of the present disclosure, there is a method for manufacturing a ferroelectric memory device, the method comprising: forming a hole penetrating a stacked structure in which first material layers and second material layers are alternately stacked in a vertical direction (stacking direction); forming a first recessed area by etching the sidewalls of each second material layer exposed through the hole to a depth in a horizontal direction perpendicular to the vertical direction; forming a deoxidation layer in the first recessed area; forming a ferroelectric base layer and a channel layer in sequence along the sidewalls of the hole; forming some areas of the ferroelectric base layer adjacent to the deoxidation layer into a ferroelectric pattern by performing an annealing process; exposing the sidewalls of the first material layer and the second material layer by etching the stacked structure; forming a second recessed area by removing each of the exposed second material layer and the deoxidation layer; and forming a conductive layer by filling a conductive material in the second recessed area.

[0007] According to another embodiment of the present disclosure, a ferroelectric memory device includes: a gate stack structure, which includes a plurality of interlayer insulating layers and a plurality of conductive layers stacked alternately; a channel layer, which extends in a vertical direction (stacking direction) in the gate stack structure; a ferroelectric pattern, which is inserted between the plurality of conductive layers and the channel layer; an antiferroelectric pattern, which is inserted between the plurality of interlayer insulating layers and the channel layer; and a deoxidation layer, which contacts a side wall of each of the plurality of conductive layers.

[0008] According to another embodiment of the present disclosure, a method for manufacturing a ferroelectric memory device includes: forming a hole that penetrates a stacked structure in which a first material layer and a second material layer are alternately stacked in a vertical direction (stacking direction); forming a ferroelectric base layer and a channel layer in sequence along the side walls of the hole; exposing the side walls of the first material layer and the second material layer by etching the stacked structure; forming a recessed area exposing some areas of the ferroelectric base layer by removing the exposed second material layer; forming a deoxidation layer in contact with some areas of the ferroelectric base layer along the surface of the recessed area; forming an adjacent area of ​​the ferroelectric base layer including some areas in contact with the deoxidation layer into a ferroelectric pattern by performing an annealing process; and forming a conductive layer by filling the recessed area with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to enable the present disclosure to be implemented by those skilled in the art.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0011] Figure 1 is a diagram illustrating a ferroelectric memory device according to an embodiment of the present disclosure.

[0012] Figure 2 is a diagram illustrating a hysteresis curve of a ferroelectric random access memory.

[0013] Figure 3 is a cross-sectional view illustrating a ferroelectric memory device according to an embodiment of the present disclosure.

[0014] FIG. 4A to FIG. 4G is a cross-sectional view illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present disclosure.

[0015] Figure 5is a cross-sectional view illustrating a ferroelectric memory device according to another embodiment of the present disclosure.

[0016] FIG. 6A to FIG. 6D is a cross-sectional view illustrating a method of manufacturing a ferroelectric memory device according to another embodiment of the present disclosure.

[0017] Figure 7 is a diagram illustrating a solid-state drive (SSD) system to which the ferroelectric memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0018] The specific structural or functional descriptions disclosed herein are merely exemplified for the purpose of describing the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein.

[0019] Some embodiments of the present disclosure relate to a ferroelectric memory device capable of reducing or preventing interference characteristics between adjacent memory cells and a method of manufacturing the ferroelectric memory device.

[0020] Figure 1 is a diagram illustrating a ferroelectric memory device 1100 according to an embodiment of the present disclosure.

[0021] Reference Figure 1 , the ferroelectric memory device 1100 may include a memory cell array 110 in which data is stored and peripheral circuits 120 to 170 capable of performing a program operation, a read operation, or an erase operation.

[0022] The memory cell array 110 may include a plurality of memory blocks in which data is stored. Each memory block may include a ferroelectric random access memory cell, and the ferroelectric random access memory cell may be implemented in a three-dimensional structure in which the ferroelectric random access memory cell is stacked in a vertical direction above a substrate. The ferroelectric random access memory cell may store data by using polarization that varies according to a voltage applied to an electrode. Although power supply may be interrupted, the ferroelectric random access memory cell may retain the stored data by a spontaneous polarization characteristic.

[0023] The peripheral circuits 120 to 170 may include a row decoder 120 , a voltage generator 130 , a page buffer group 140 , a column decoder 150 , an input / output circuit 160 , and a control logic circuit 170 .

[0024] The row decoder 120 may select a memory block from among memory blocks included in the memory cell array 110 according to the row address RADD and transmit an operating voltage Vop to the selected memory block.

[0025] The voltage generator 130 may generate and output an operation voltage Vop required for various operations in response to the operation code OPCD.

[0026] The page buffer group 140 may be connected to the memory cell array 110 through a bit line. For example, the page buffer group 140 may include a sensing circuit connected to each bit line. The sensing circuit may operate simultaneously in response to a sensing signal PBSIG and temporarily store data in a programming operation or a reading operation. The sensing circuit may sense a voltage or current of a bit line that varies according to a threshold voltage of a ferroelectric random access memory cell in a reading operation or a verification operation.

[0027] The column decoder 150 may transfer data DATA between the input / output circuit 160 and the page buffer group 140 according to the column address CADD.

[0028] The input / output circuit 160 may be connected to an external device through an input / output line IO. For example, the external device may be a controller capable of sending a command CMD, an address ADD, or data DATA to the ferroelectric memory device 1100. The input / output circuit 160 may input / output a command CMD, an address ADD, and data DATA through the input / output line IO. For example, the input / output circuit 160 may send a command CMD and an address ADD received from an external device through the input / output line IO to the control logic circuit 170, and send data DATA received from an external device through the input / output line IO to the column decoder 150. The input / output circuit 160 may output the data DATA received from the column decoder 150 to the external device through the input / output line IO.

[0029] The control logic circuit 170 outputs an operation code OPCD, a row address RADD, a sensing signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. For example, the control logic circuit 170 may include software configured to execute an algorithm in response to the command CMD and hardware configured to output the address ADD and various control signals.

[0030] Figure 2 is a diagram illustrating a hysteresis curve of a ferroelectric random access memory.

[0031] Reference Figure 2 , hysteresis is a phenomenon in which when a material responds to an external stimulus, the material is affected not only by the intensity of the external stimulus but also by the material's current state or the history of past external stimuli. The hysteresis curve in ferroelectric random access memory represents a curve in which magnetization changes according to the voltage level applied to the electrode, which is also called a "self-hysteresis curve".

[0032] For example, in the initial state INT (E=0) where no voltage is applied to the ferroelectric random access memory, the polarization P becomes 0. When a positive voltage is applied to the ferroelectric random access memory with the polarization P of 0, the polarization P increases (1), and therefore, the ferroelectric random access memory can be in a saturated state. In the present embodiment, the saturation state caused by the positive voltage is defined as a first saturation state 1ST. When the supply of voltage to the ferroelectric random access memory in the first saturation state 1ST is suspended, the polarization P decreases (2). The polarization P does not return to 0 as the initial state INT, but can maintain a specific value. The polarization P is called residual polarization. In the present embodiment, the residual polarization maintained after the first saturation state 1ST is defined as a first residual polarization 1RP.

[0033] When a negative voltage is applied to the ferroelectric random access memory in the first residual polarization 1RP state, the polarization P decreases again. The voltage at which the polarization P becomes 0 is called the coercive field CF1. When a negative voltage lower than the coercive field CF1 is further applied to the ferroelectric random access memory, the polarization P can be further reduced (3), and the ferroelectric random access memory can be in the second saturation state 2ST. The directions of the positive ions and negative ions in the first saturation state 1ST and the second saturation state 2ST are opposite to each other. When the supply of a voltage higher than the coercive field CF2 to the ferroelectric random access memory in the second saturation state 2ST is suspended, the polarization P increases again. The polarization P of the ferroelectric random access memory can be maintained in the second residual polarization 2RP state.

[0034] When a positive voltage is applied to the FRAM in the second remnant polarization 2RP state, the polarization P increases again until the first saturation state IS T .

[0035] In the above manner, the polarization P of the ferroelectric random access memory can be changed according to the level of the voltage applied to the electrode. When no voltage is applied, the polarization P of the ferroelectric random access memory can be maintained at a constant level. The ferroelectric random access memory can store data according to the characteristics of the polarization P.

[0036] Figure 3 is a cross-sectional view illustrating a ferroelectric memory device according to an embodiment of the present disclosure.

[0037] Reference Figure 3 , the ferroelectric memory device may include a memory block including a ferroelectric random access memory cell, and Figure 3 A portion of a memory string included in a memory block is illustrated in FIG.

[0038] The string may include a plurality of ferroelectric random access memory cells MC, and the plurality of ferroelectric random access memory cells MC may be connected to a conductive layer CDL corresponding to a word line. Each of the plurality of ferroelectric random access memory cells MC may include a ferroelectric layer FL and a channel layer CHL, and an insulating pattern IP may be disposed between the ferroelectric layers FL of the respective ferroelectric random access memory cells MC adjacent to each other.

[0039] The interlayer insulating layer ISL may be formed between the conductive layers CDL. The conductive layer CDL and the interlayer insulating layer ISL may constitute a gate stack structure GST. The conductive layer CDL and the interlayer insulating layer ISL may extend in the X direction, which is a horizontal direction parallel to the substrate SUB. For example, the interlayer insulating layer ISL and the conductive layer CDL may be alternately stacked in a vertical direction on top of a lower structure (not shown). The lower structure may include a substrate SUB and at least one of a source line, a source selection line, and a peripheral circuit formed on the substrate SUB. The conductive layer CDL may be used as a word line and at least one selection line. For example, when it is assumed that the interlayer insulating layer ISL and the conductive layer CDL are alternately stacked on the substrate SUB, the conductive layer CDL may include a word line and a drain selection line and a source selection line. The interlayer insulating layer ISL may be formed of an oxide, and the conductive layer CDL may be formed of a metal such as tungsten.

[0040] The conductive layer CDL may extend further toward the channel layer CHL than the interlayer insulating layer ISL. That is, the conductive layer CDL may protrude further in the direction in which the conductive layer CDL is adjacent to the channel layer CHL than the interlayer insulating layer ISL. The thickness D2 of the protruding portion of each conductive layer CDL may be thicker than the thickness D1 of each conductive layer CDL interposed between the interlayer insulating layers ISL. That is, the end of each conductive layer CDL in the direction in which the conductive layer CDL is adjacent to the channel layer CHL may have a "T" shape.

[0041] The channel layer CHL may be formed while penetrating the gate stack structure GST in a Z direction, which is a direction perpendicular to the substrate SUB. That is, the channel layer CHL may be formed in the gate stack structure GST to extend in a Z direction, which is a direction perpendicular to the substrate SUB. The channel layer CHL may be used to allow current to flow in the string. The channel layer CHL may be formed of polysilicon.

[0042] The ferroelectric layer FL may be interposed between the channel layer CHL and the conductive layer CDL. The ferroelectric layer FL is made of a material that is electrically polarized by an external electric field but can maintain polarization even when no electric field is applied from the outside. Electrically maintaining polarization means storing data by maintaining different polarities. The ferroelectric layer FL may be formed of at least one material of PbZrTiO3 (PSZ), SrBi2Ta2O9 (STB), BiFeO3 (BFO), HfO2, HfO2ZrO2 (HZO), and HfSiO4 (HSO). For example, the ferroelectric layer FL may be formed of any one of the above layers, or may be formed of a mixed layer of the above layers or a stacked layer of the above layers.

[0043] The thickness D3 of each ferroelectric layer FL may be thinner than the thickness D2 of the protruding portion of each adjacent conductive layer CDL.

[0044] The insulating pattern IP may be interposed between the ferroelectric layers FL adjacent to each other in a vertical direction. The insulating pattern IP may be made of an antiferroelectric material. The insulating pattern IP may be defined as an antiferroelectric pattern.

[0045] The barrier layer BO may be interposed between the insulating pattern IP and the interlayer insulating layer ISL. The barrier layer BO may include a high dielectric constant material. For example, the barrier layer BO may include hafnium oxide (HfO 2 ).

[0046] A core insulating layer CO extending in the Z direction, which is a vertical direction, may be interposed inside the channel layer CHL. The core insulating layer CO may include oxide.

[0047] The ferroelectric layer FL and the insulating pattern IP may be formed using the same material. Compared with the insulating pattern IP, oxygen present inside the ferroelectric layer FL may be removed. Therefore, the ferroelectric layer FL may have ferroelectric properties due to oxygen vacancies, and the insulating pattern IP may have antiferroelectric properties.

[0048] FIG. 4A to FIG. 4G is a cross-sectional view illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present disclosure.

[0049] Reference Figure 4A , a stacked structure ST is formed on a substrate SUB. The stacked structure ST may include first material layers 11 and second material layers 12 that are alternately stacked. The first material layers 11 and the second material layers 12 may be stacked in a direction perpendicular to the substrate SUB. The first material layers 11 and the second material layers 12 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0050] The first material layer 11 may include a material having a high etching selectivity with respect to the second material layer 12. In an example, the first material layer 11 may include an insulating material such as oxide, and the second material layer 12 may include a sacrificial material such as nitride.

[0051] Subsequently, a hard mask pattern (not shown) may be formed on the stack structure ST, and a hole H penetrating at least a portion of the stack structure ST may be formed by performing an etching process using the hard mask pattern. The hole H may partially extend to the inside of the substrate SUB.

[0052] Reference Figure 4B The first recessed region R1 is formed by etching the second material layer 12 exposed through the hole H to a certain depth in a direction horizontal to the substrate SUB. That is, the sidewall of the second material layer 12 is etched to a certain depth so that the first material layer 11 further protrudes in the horizontal direction than the second material layer 12.

[0053] Reference Figure 4C , a barrier layer 13 is formed along the sidewall of the hole H. The barrier layer 13 may include hafnium oxide (HfO2). The barrier layer 13 may be formed in a linear form along the sidewall of the first recessed region R1. For example, the barrier layer 13 may be formed along the sidewall of the second material layer 12 and the surface of the protruding first material layer 11. The barrier layer 13 may be formed by adjusting its thickness so as not to completely fill the first recessed region R1.

[0054] Thereafter, the deoxidation layer 14 is formed so as to completely fill the first recessed region R1. For example, after the deoxidation layer 14 is formed on the surface of the barrier layer 13 so as to completely fill the first recessed region R1, the deoxidation layer 14 formed outside the first recessed region R1 may be removed by performing an etching process. For example, the deoxidation layer 14 may include titanium (Ti) or polysilicon. The deoxidation layer 14 may be formed of a material having a relatively high bonding force with oxygen.

[0055] Reference Figure 4D A ferroelectric base layer 15 and a channel layer 16 are sequentially formed along the exposed surfaces of the barrier layer 13 and the deoxidation layer 14 .

[0056] The ferroelectric base layer 15 can be formed by at least one material of PbZrTiO3 (PSZ), SrBi2Ta2O9 (STB), BiFeO3 (BFO), HfO2, HfO2ZrO2 (HZO), and HfSiO4 (HSO). For example, the ferroelectric base layer 15 can be formed by any one of the above layers, or can be formed by a mixed layer of the above layers or a stacked layer of the above layers. The ferroelectric base layer 15 is formed to be in direct contact with the outer wall of the deoxidation layer 14. Additionally, a dopant can be implanted into the ferroelectric base layer 15 by performing an ion implantation process, and the dopant can be Si.

[0057] The channel layer 16 may be formed of polysilicon.

[0058] Thereafter, the core insulating layer 17 may be formed so as to completely fill the inside of the hole H. The core insulating layer 17 may include an oxide layer.

[0059] Reference Figure 4E , by performing an annealing process, the ferroelectric base layer ( Figure 4D Some areas adjacent to the deoxidized layer 14 in the ferroelectric pattern 15A are formed. That is, the ferroelectric base layer ( Figure 4D Some areas adjacent to the deoxidation layer 14 in the ferroelectric pattern 15 shown in FIG. 15A can be changed into the ferroelectric pattern 15A. For example, by annealing process, the ferroelectric base layer ( Figure 4D The oxygen in some areas adjacent to the deoxidized layer 14 in the ferroelectric substrate 15 shown in FIG. 1 moves to the deoxidized layer 14 and then bonds to the deoxidized layer. Figure 4D 15) in some areas adjacent to the deoxidized layer 14. Figure 4D Some areas adjacent to the deoxidation layer 14 and the ferroelectric base layer ( Figure 4D Differences between crystals may occur in other regions not adjacent to the deoxidized layer 14 in the ferroelectric base layer ( 15 ) from which oxygen is removed. Figure 4D The ferroelectric substrate ( 15 ) shown in FIG. 1 may have ferroelectric characteristics due to oxygen vacancies, and a region including oxygen vacancies may be defined as a ferroelectric pattern 15A. Figure 4D The other portions except the ferroelectric pattern 15A in the illustrated 15) may be antiferroelectric patterns having antiferroelectric characteristics, and these portions may be defined as insulating patterns 15B.

[0060] Reference Figure 4F , an etching process is performed so that the stacked structure ( Figure 4E The sidewall of the ST shown is exposed, and the exposed second material layer ( Figure 4E 12 shown). The second material layer is removed therefrom ( Figure 4E The space shown in 12) can be defined as a second recessed region R2.

[0061] The portion of the etching stop layer 13 exposed through the second recessed region R2 is etched to expose the deoxidation layer ( Figure 4E 14 shown). Thereafter, the exposed deoxidized layer ( Figure 4E 14). Therefore, the ferroelectric pattern 15A may be exposed through the second recessed region R2. A portion of the barrier layer 13 between the first material layer 11 and the insulating pattern 15B may be retained.

[0062] Reference Figure 4G , by filling the second recessed region ( Figure 4F The conductive layer 19 may include a conductive material such as polysilicon, tungsten or other metals.

[0063] A gate stack structure GST including the first material layer 11 and the conductive layer 19 may be defined.

[0064] Figure 5 is a cross-sectional view illustrating a ferroelectric memory device according to another embodiment of the present disclosure.

[0065] Reference Figure 5 , the ferroelectric memory device may include a memory block including a ferroelectric random access memory cell, and Figure 5 A portion of a memory string included in a memory block is illustrated in FIG.

[0066] The string may include a plurality of ferroelectric random access memory cells MC, and the plurality of ferroelectric random access memory cells MC may be connected to a conductive layer CDL corresponding to a word line. Each of the plurality of ferroelectric random access memory cells MC may include a ferroelectric layer FL and a channel layer CHL, and an insulating pattern IP may be disposed between the ferroelectric layers FL of the respective ferroelectric random access memory cells MC adjacent to each other. The insulating pattern IP may be defined as an antiferroelectric pattern.

[0067] The interlayer insulating layer ISL may be formed between the conductive layers CDL. The conductive layer CDL and the interlayer insulating layer ISL may constitute a gate stack structure GST. The conductive layer CDL and the interlayer insulating layer ISL may extend in the X direction, which is a horizontal direction parallel to the substrate SUB. For example, the interlayer insulating layer ISL and the conductive layer CDL may be alternately stacked on top of a lower structure (not shown). The lower structure may include a substrate SUB and at least one of a source line, a source selection line, and a peripheral circuit formed on the substrate SUB. The conductive layer CDL may be used as a word line and at least one selection line. For example, when it is assumed that the interlayer insulating layer ISL and the conductive layer CDL are alternately stacked on the substrate SUB, the conductive layer CDL may include a word line and a drain selection line and a source selection line. The interlayer insulating layer ISL may be formed of an oxide.

[0068] Each conductive layer CDL may include a first conductive layer CD1 and a second conductive layer CD2. The first conductive layer CD1 may be formed to surround one sidewall, an upper surface, and a lower surface of the second conductive layer CD2. The first conductive layer CD1 may be a deoxidized layer. The first conductive layer CD1 may be formed of a material having a strong oxygen bonding force, such as titanium. The second conductive layer CD2 may be formed of a metal such as tungsten.

[0069] The channel layer CHL may be formed while penetrating the gate stack structure GST in a Z direction, which is a direction perpendicular to the substrate SUB. That is, the channel layer CHL may be formed in the gate stack structure GST to extend in a Z direction, which is a direction perpendicular to the substrate SUB. The channel layer CHL may be used to allow current to flow in the string. The channel layer CHL may be formed of polysilicon.

[0070] The ferroelectric layer FL may be interposed between the channel layer CHL and the conductive layer CDL. The ferroelectric layer FL is made of a material that is electrically polarized by an external electric field but is able to maintain polarization even when no electric field is applied from the outside. Electrically maintaining polarization means storing data by maintaining different polarities. The ferroelectric layer FL may be formed of at least one material of PbZrTiO3 (PSZ), SrBi2Ta2O9 (STB), BiFeO3 (BFO), HfO2, HfO2ZrO2 (HZO), and HfSiO4 (HSO). For example, the ferroelectric layer FL may be formed of any one of the above layers, or may be formed of a mixed layer of the above layers or a stacked layer of the above layers.

[0071] The insulating pattern IP may be interposed between the ferroelectric layers FL adjacent to each other in a vertical direction. The insulating pattern IP may be made of an antiferroelectric material or a high dielectric constant material.

[0072] A core insulating layer CO extending in the Z direction, which is a vertical direction, may be interposed inside the channel layer CHL. The core insulating layer CO may include oxide.

[0073] The ferroelectric layer FL and the insulating pattern IP may be formed using the same material. Compared with the insulating pattern IP, oxygen present inside the ferroelectric layer FL may be removed. Therefore, the ferroelectric layer FL may have ferroelectric properties due to oxygen vacancies, and the insulating pattern IP may have antiferroelectric properties.

[0074] FIG. 6A to FIG. 6D is a cross-sectional view illustrating a method of manufacturing a ferroelectric memory device according to another embodiment of the present disclosure.

[0075] Reference Fig. 6A, a stacked structure ST is formed on the substrate SUB. The stacked structure ST may include first material layers 21 and second material layers 22 that are alternately stacked. The first material layers 21 and the second material layers 22 may be stacked in a direction perpendicular to the substrate SUB. The first material layers 21 and the second material layers 22 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0076] The first material layer 21 may include a material having a high etching selectivity with respect to the second material layer 22. In an example, the first material layer 21 may include an insulating material such as oxide, and the second material layer may include a sacrificial material such as nitride.

[0077] Subsequently, a hard mask pattern (not shown) may be formed on the stack structure ST, and a hole H penetrating at least a portion of the stack structure ST may be formed by performing an etching process using the hard mask pattern. The hole H may partially extend to the inside of the substrate SUB.

[0078] Reference Figure 6B , a ferroelectric base layer 23 and a channel layer 24 are sequentially formed along the side wall of the hole H.

[0079] The ferroelectric base layer 23 can be formed by at least one material of PbZrTiO3 (PSZ), SrBi2Ta2O9 (STB), BiFeO3 (BFO), HfO2, HfO2ZrO2 (HZO), and HfSiO4 (HSO). For example, the ferroelectric base layer 23 can be formed by any one of the above layers, or can be formed by a mixed layer of the above layers or a stacked layer of the above layers. Additionally, dopants can also be injected into the ferroelectric base layer 23 by performing an ion implantation process, and the dopant can be Si.

[0080] The channel layer 24 may be formed of polysilicon.

[0081] Thereafter, the core insulating layer 25 may be formed so as to completely fill the inside of the hole H. The core insulating layer 25 may include an oxide layer.

[0082] Reference Figure 6C , performing an etching process to expose the stacked structure ( Figure 6B The sidewall of the ST shown in FIG. 1 is removed, and the exposed second material layer ( Figure 6B 22 shown). The second material layer ( Figure 6B The space shown in 22) can be defined as a recessed area R.

[0083] Thereafter, a deoxidation layer 26 is formed along some sidewalls of the ferroelectric base layer 23 and the upper and lower surfaces of the first material layer 21 exposed via the recessed region R. The deoxidation layer 26 may include titanium (Ti) or polysilicon. The deoxidation layer 26 may be formed of a material having a relatively high bonding force with oxygen. The deoxidation layer 26 may be used as a conductive layer for a word line.

[0084] Reference Fig.6D , by performing an annealing process, the ferroelectric base layer ( Figure 6C Some areas adjacent to the deoxidation layer 26 in FIG. 23) are formed as a ferroelectric pattern 23A.

[0085] For example, through the annealing process, the ferroelectric base layer ( Figure 6C Oxygen in some areas adjacent to the deoxidized layer 26 in the ferroelectric substrate 23 shown in FIG. 2 moves to the deoxidized layer 26 and then bonds to the deoxidized layer 26. Thus, the ferroelectric substrate ( Figure 6C 23) in some areas adjacent to the deoxidized layer 26. Figure 6C Some areas adjacent to the deoxidation layer 26 and the ferroelectric base layer ( Figure 6C Differences between crystals may occur in other regions of the ferroelectric substrate ( 23 ) not adjacent to the deoxidized layer 26. Figure 6C The ferroelectric pattern 23 shown in FIG. 23 may have ferroelectric characteristics due to oxygen vacancies, and a region including oxygen vacancies may be defined as a ferroelectric pattern 23A. Figure 6C The other portions except the ferroelectric pattern 23A in FIG. 23) shown may be antiferroelectric patterns having antiferroelectric characteristics, and these portions may be defined as insulating patterns 23B.

[0086] Thereafter, by filling the recessed area with a conductive material ( Figure 6C The conductive layer 27 may be formed by using a conductive material such as polysilicon, tungsten or metal. Therefore, the deoxidation layer 26 may be formed to one side wall, the upper surface and the lower surface of each conductive layer 27.

[0087] A gate stack structure GST including a first material layer 21 , a deoxidation layer 26 , and a conductive layer 27 may be defined.

[0088] In another embodiment, the conductive layer 27 may be formed after the deoxidation layer 26 is removed before the conductive layer 27 is formed.

[0089] Figure 7 is a diagram illustrating a solid-state drive (SSD) system 4000 to which the ferroelectric memory device of the present disclosure is applied.

[0090] Reference Figure 7, the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001, and be powered through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of ferroelectric memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0091] According to an embodiment of the present disclosure, each of the plurality of ferroelectric memory devices 4221 to 422n may be connected to a reference Figure 1 The ferroelectric memory device 1100 described is configured identically.

[0092] The controller 4210 may control the plurality of ferroelectric memory devices 4221 to 422n in response to a signal received from the host 4100. Exemplarily, the signal may be sent based on an interface between the host 4100 and the SSD 4200. For example, the signal may be defined by at least one interface such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0093] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive power input from the host 4100. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 may provide power to the SSD 4200. Exemplarily, the auxiliary power supply 4230 may be located in the SSD 4200, or located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and provide auxiliary power to the SSD 4200.

[0094] The buffer memory 4240 may be used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of ferroelectric memory devices 4221 to 422n, or temporarily store metadata (e.g., a mapping table) of the plurality of ferroelectric memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0095] According to the present disclosure, ferroelectric patterns of respective memory cells adjacent to each other are separated from each other by the antiferroelectric pattern, so that interference characteristics between the memory cells can be reduced or prevented.

[0096] Although the present disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various modifications in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0097] In the above-mentioned embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0098] In addition, the embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used here, this is only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and there may be many variations within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure.

[0099] CROSS-REFERENCE TO RELATED APPLICATIONS

[0100] This application claims the priority of Korean Patent Application No. 10-2023-0079539 filed in the Korean Intellectual Property Office on June 21, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A ferroelectric memory device, the ferroelectric memory device comprising: A gate stack structure, the gate stack structure comprising a plurality of interlayer insulating layers and a plurality of conductive layers stacked alternately; a channel layer extending in a vertical direction as a stacking direction in the gate stack structure; a ferroelectric pattern interposed between the plurality of conductive layers and the channel layer; as well as An antiferroelectric pattern is interposed between the plurality of interlayer insulating layers and the channel layer.

2. The ferroelectric memory device according to claim 1, wherein: The ferroelectric pattern and the antiferroelectric pattern include the same material, and wherein the ferroelectric pattern includes oxygen vacancies.

3. The ferroelectric memory device according to claim 1, wherein: Each of the antiferroelectric patterns is interposed between the ferroelectric patterns adjacent to each other in the vertical direction. 4 . The ferroelectric memory device according to claim 1 , further comprising a barrier layer interposed between the plurality of interlayer insulating layers and the antiferroelectric pattern.

5. The ferroelectric memory device according to claim 1, wherein: Each of the plurality of conductive layers includes a protruding portion that protrudes farther toward the channel layer than the plurality of interlayer insulating layers.

6. The ferroelectric memory device according to claim 5, wherein: The protruding portion of each of the plurality of conductive layers has a thickness in the vertical direction thicker than a thickness of other portions of each of the plurality of conductive layers interposed between the plurality of interlayer insulating layers in the vertical direction.

7. The ferroelectric memory device according to claim 5, wherein: The thickness of each of the ferroelectric patterns in the vertical direction is thinner than the thickness of the protruding portion in the vertical direction.

8. The ferroelectric memory device according to claim 1, wherein: An end portion of each of the plurality of conductive layers in a direction toward the channel layer has a “T” shape.

9. A method for manufacturing a ferroelectric memory device, the method comprising the steps of: forming a hole penetrating a stacked structure in which first material layers and second material layers are alternately stacked in a vertical direction as a stacking direction; forming a first recessed region by etching a sidewall of each of the second material layers exposed through the hole to a specific depth in a horizontal direction perpendicular to the vertical direction; forming a deoxidation layer in the first recessed region; forming a ferroelectric base layer and a channel layer in sequence along the sidewall of the hole; By performing an annealing process, some areas of the ferroelectric base layer adjacent to the deoxidation layer are formed into ferroelectric patterns; Exposing sidewalls of the first material layer and the second material layer by etching the stacked structure; forming a second recessed region by removing each of the exposed second material layer and the deoxidation layer; as well as A conductive layer is formed by filling a conductive material in the second recessed region.

10. The method according to claim 9, wherein: The step of performing the annealing process includes the step of forming oxygen vacancies in some regions of the ferroelectric base layer adjacent to the deoxidation layer by removing oxygen through the deoxidation layer.

11. The method according to claim 9, wherein: In the annealing process, other regions of the ferroelectric base layer except the some regions of the ferroelectric base layer have antiferroelectric characteristics.

12. The method according to claim 9, wherein: The deoxidation layer includes titanium Ti or polycrystalline silicon.

13. The method according to claim 9, further comprising the steps of: A barrier layer is formed along the sidewalls of the hole before forming the deoxidation layer.

14. A ferroelectric memory device, the ferroelectric memory device comprising: A gate stack structure, the gate stack structure comprising a plurality of interlayer insulating layers and a plurality of conductive layers stacked alternately; a channel layer extending in a vertical direction as a stacking direction in the gate stack structure; a ferroelectric pattern interposed between the plurality of conductive layers and the channel layer; an antiferroelectric pattern interposed between the plurality of interlayer insulating layers and the channel layer; as well as A deoxidation layer is in contact with one side wall of each of the plurality of conductive layers.

15. The ferroelectric memory device according to claim 14, wherein: The deoxidation layer surrounds the upper and lower surfaces of each of the plurality of conductive layers.

16. The ferroelectric memory device according to claim 14, wherein: The deoxidation layer includes titanium Ti or polycrystalline silicon.

17. The ferroelectric memory device according to claim 14, wherein: The ferroelectric pattern and the antiferroelectric pattern include the same material, and wherein the ferroelectric pattern includes oxygen vacancies.

18. The ferroelectric memory device according to claim 14, wherein: Each of the antiferroelectric patterns is interposed between the ferroelectric patterns adjacent to each other in the vertical direction.

19. A method for manufacturing a ferroelectric memory device, the method comprising the steps of: forming a hole penetrating a stacked structure in which first material layers and second material layers are alternately stacked in a vertical direction as a stacking direction; forming a ferroelectric base layer and a channel layer in sequence along the sidewall of the hole; Exposing sidewalls of the first material layer and the second material layer by etching the stacked structure; forming a recessed area exposing some areas of the ferroelectric base layer by removing the exposed second material layer; forming a deoxidation layer in contact with the regions of the ferroelectric base layer along the surface of the recessed region; forming adjacent regions of the ferroelectric base layer including the regions contacting the deoxidation layer into a ferroelectric pattern by performing an annealing process; as well as A conductive layer is formed by filling the recessed area with a conductive material.

20. The method according to claim 19, wherein: The step of performing the annealing process includes the step of forming oxygen vacancies by removing oxygen from the adjacent regions of the ferroelectric base layer including the regions in contact with the deoxidation layer through the deoxidation layer.

21. The method according to claim 19, wherein: In the annealing process, other regions of the ferroelectric base layer except the adjacent region of the ferroelectric base layer have antiferroelectric characteristics.

22. The method according to claim 19, wherein: The deoxidation layer includes titanium Ti or polycrystalline silicon.

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