Test method of integrated circuit and non-volatile readable storage medium
By acquiring the measurement unit in the integrated circuit and adding marking information, performing simulation operations to generate measurement files, the problem of failure to effectively verify the timing of the integrated circuit in the prior art is solved, and the verification coverage and circuit performance optimization capabilities are improved.
Patent Information
- Application Number
- CN202310737643.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-19
- Publication Date
- 2024-12-27
AI Technical Summary
The existing integrated circuit verification methods only simulate logic functions and fail to effectively consider the timing information in the actual circuit, resulting in the inability to accurately simulate and verify the timing information of the actual circuit.
By obtaining the measurement unit in the integrated circuit, adding marking information, including preset timing parameters, performing simulation operations, generating simulation results, and generating measurement files based on the measurement timing parameters and preset timing parameters, to determine whether the integrated circuit meets the timing requirements.
Improves coverage of integrated circuit verification, can identify weaknesses in the design, optimize circuit performance, and intuitively report nodes with insufficient timing margins, ensuring that the integrated circuit meets timing requirements under various conditions.
Smart Images
Figure CN119199466A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a testing method for an integrated circuit and a non-volatile readable storage medium. Background Art
[0002] After the integrated circuit design is completed, the integrated circuit needs to be verified. Existing simulation tools (such as Finesim or Spice, etc.) generate a large number of measurement stimuli (patterns) to verify whether different logic functions and the mutual combination of each logic function are correct.
[0003] However, these verifications are only simulations of logic functions and do not take into account the timing information in the actual circuit, and are unable to simulate the timing information of the actual circuit. Summary of the invention
[0004] According to a first aspect of an embodiment of the present disclosure, a method for testing an integrated circuit is provided, comprising:
[0005] Acquire a measurement unit in the integrated circuit;
[0006] Adding marking information to the measuring unit; wherein the marking information includes a preset timing parameter of the measuring unit;
[0007] Performing a simulation operation on the integrated circuit to generate a simulation result; wherein the simulation result at least includes a measurement timing parameter of the measurement unit;
[0008] A measurement file is generated according to the measured timing parameters and the preset timing parameters; wherein the measurement file is used to indicate whether the integrated circuit meets the timing requirements.
[0009] In some embodiments, the measurement unit includes a latch and / or a flip-flop;
[0010] The preset timing parameters include: setup time margin and hold time margin;
[0011] The measurement timing parameters include: setup time and hold time.
[0012] In some embodiments, the measuring unit includes a latch and / or a trigger; and obtaining the measuring unit in the circuit includes:
[0013] Acquire multiple feedback units in the integrated circuit according to the first instruction; wherein the feedback unit includes a feedback structure, and the feedback structure includes a first sub-element and a second sub-element; the output end of the first sub-element is coupled to the input end of the second sub-element, and the output end of the second sub-element is coupled to the input end of the first sub-element;
[0014] The plurality of feedback units are screened to determine the measurement unit.
[0015] In some embodiments, screening the plurality of feedback units to determine the measurement unit includes:
[0016] When the feedback unit includes a transmission gate, the feedback unit is determined to be the measurement unit.
[0017] In some embodiments, the preset timing parameters include: setup time margin and hold time margin; the measured timing parameters include: setup time and hold time;
[0018] The generating a measurement file according to the measurement timing parameter and the preset timing parameter includes:
[0019] When the setup time satisfies the setup time margin and the hold time satisfies the hold time margin, generating the measurement file, wherein the measurement file indicates that the integrated circuit satisfies the timing requirement;
[0020] or,
[0021] When the setup time does not satisfy the setup time margin, and / or the hold time does not satisfy the hold time margin, the measurement file is generated, and the measurement file indicates that the integrated circuit does not satisfy the timing requirement.
[0022] In some embodiments, when the setup time satisfies the setup time margin, and the hold time satisfies the hold time margin, the measurement file includes the preset timing parameters;
[0023] When the setup time does not satisfy the setup time margin, the measurement file includes the setup time; and / or when the hold time does not satisfy the hold time margin, the measurement file includes the hold time.
[0024] In some embodiments, adding tag information to the measurement unit includes:
[0025] The marking information is added to the measurement unit according to a second instruction; wherein the second instruction is different from the first instruction.
[0026] In some embodiments, adding tag information to the measurement unit includes:
[0027] Generate a measurement table; wherein the measurement table includes the name of the measurement unit and the preset timing parameters of the measurement unit;
[0028] The marking information is added to the measurement unit according to the measurement table.
[0029] In some embodiments, the preset timing parameters include: preset timing parameters of the measurement unit at different process angles.
[0030] According to a second aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the test method as described in any one of the embodiments of the first aspect of the present disclosure is implemented.
[0031] According to a third aspect of an embodiment of the present disclosure, a non-volatile readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the test method as described in any embodiment of the first aspect of the embodiment of the present disclosure is implemented.
[0032] In the disclosed embodiment, a measurement unit in an integrated circuit is obtained; marking information is added to the measurement unit, the marking information includes preset timing parameters of the measurement unit; a simulation operation is performed on the integrated circuit to generate a simulation result, the simulation result includes at least the measurement timing parameters of the measurement unit; a measurement file is generated according to the measurement timing parameters and the preset timing parameters, the measurement file is used to indicate whether the integrated circuit meets the timing requirements; on the one hand, a measurement file including the measurement timing parameters and the preset timing parameters can be generated in the full-chip simulation of the integrated circuit to check whether the design of the integrated circuit meets the timing requirements, improve the coverage of the integrated circuit verification, find the weak points in the integrated circuit design, thereby adjusting the design of the integrated circuit and optimizing the performance of the integrated circuit; on the other hand, the measurement file can intuitively report the nodes with insufficient timing margin in the circuit design, making it easier for designers to optimize the circuit; on the other hand, the judgment criteria (i.e., the preset timing parameters) can be accurately set, making it easier to analyze the measurement results. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 is a flow chart of a method for testing an integrated circuit according to an embodiment of the present disclosure;
[0034] Figure 2 is a schematic diagram of multiple feedback units according to an embodiment of the present disclosure;
[0035] Figure 3 is a schematic diagram of a test table according to an embodiment of the present disclosure;
[0036] Figure 4 is a schematic diagram of a feedback unit for adding marking information according to an embodiment of the present disclosure;
[0037] Figure 5It is a schematic diagram of a testing method of an integrated circuit according to an embodiment of the present disclosure.
[0038] Description of reference numerals:
[0039] Feedback unit: A, B, C, D;
[0040] First sub-element: 201a, 201b, 201c, 201d;
[0041] Second sub-components: 202a, 202b, 202c, 202d. DETAILED DESCRIPTION
[0042] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0043] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.
[0044] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0045] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.
[0046] After the integrated circuit design is completed, full chip simulation is required. For example, by generating a large number of measurement stimuli (patterns), it is necessary to verify whether different logic functions and the combination of each logic function are correct.
[0047] In principle, as the number of measurement stimuli continues to grow, a higher coverage rate can be achieved to ensure product performance. However, since the full-chip simulation of each measurement stimulus takes a long time, the simulation time is long; and the simulation of the logic function does not take into account the timing information in the actual circuit, and cannot simulate the timing information of the actual circuit.
[0048] In view of this, embodiments of the present disclosure provide a method for testing an integrated circuit and a non-volatile readable storage medium.
[0049] Figure 1 1 is a flow chart of a method for testing an integrated circuit according to an embodiment of the present disclosure. Figure 1 As shown, the test method includes at least the following steps:
[0050] Step S110: obtaining a measurement unit in the integrated circuit;
[0051] Step S120: adding marking information to the measurement unit; wherein the marking information includes preset timing parameters of the measurement unit;
[0052] Step S130: performing a simulation operation on the integrated circuit to generate a simulation result; wherein the simulation result at least includes a measurement timing parameter of the measurement unit;
[0053] Step S140: Generate a measurement file according to the measured timing parameters and the preset timing parameters; wherein the measurement file is used to indicate whether the integrated circuit meets the timing requirements.
[0054] The integrated circuit testing method provided by the embodiment of the present disclosure is further described in detail below in conjunction with specific embodiments.
[0055] In step S110, a measurement unit in the integrated circuit is obtained. For example, a simulation tool (eg, Finesim or Spice) is used to obtain the measurement unit in the integrated circuit. The number of the measurement unit may be one or more, and the present disclosure has no particular limitation on this.
[0056] In some embodiments, the measurement unit in the integrated circuit can be automatically captured by running a script. The script is an executable file written according to a certain format, usually saved in text (ASCII), and used to control software applications. The script is usually interpreted or compiled when it is called. Those skilled in the art can write different scripts according to the design of different integrated circuits and / or different testing requirements, and the present disclosure does not specifically limit this.
[0057] Taking Dynamic Random Access Memory (DRAM) as an example, DRAM is usually designed using fully customized circuit design. Although most functional units (such as latches or triggers) have been made into standard units, there are still a large number of flattened structures and customized structures. Designers need to find these structures one by one, which is not only time-consuming and labor-intensive, but also may result in omissions, resulting in reduced test efficiency and test accuracy.
[0058] In this example, by writing a script to automatically search for measurement units in the integrated circuit, not only can the functional units in the integrated circuit (including flattern structures and custom structures) be quickly matched, but also the full coverage of the functional units can be ensured, which is conducive to saving test time, improving test coverage, and thus improving test efficiency and accuracy.
[0059] It should be noted that the type of integrated circuit is not limited to the DRAM in this example, but may also be other types of semiconductor devices known in the art.
[0060] In some embodiments, the measuring unit includes a latch and / or a flip-flop.
[0061] In some embodiments, the above step S110 includes: acquiring a plurality of feedback units in the integrated circuit according to the first instruction; and screening the plurality of feedback units to determine the measurement unit.
[0062] The first instruction may be a script written in a programming language (eg, C language, etc.), and the first instruction is used to capture a feedback unit in an integrated circuit; the first instruction may be stored in a memory and may be executed when loaded by a processor.
[0063] The feedback unit is a unit in the integrated circuit that includes a feedback structure. Figure 2 A plurality of feedback units, such as feedback unit A, feedback unit B, feedback unit C, and feedback unit D, are shown obtained according to the first instruction. Figure 2 It is not shown in the figure, but it should be understood that the feedback unit may also include other structures. It should be noted that Figure 2 The four feedback units in the embodiment are merely exemplary, and the types of feedback units in the integrated circuit are not limited thereto.
[0064] In some embodiments, the script (i.e., the first instruction) may capture the feedback unit according to the equal names of the input terminal and the output terminal of the functional unit in the integrated circuit. For example, if the names of the input terminal and the output terminal are equal, it is determined that the functional unit is a feedback unit; if the names of the input terminal and the output terminal are not equal, it is determined that the functional unit is not a feedback unit.
[0065] In some embodiments, the feedback structure includes a first sub-element and a second sub-element; the output terminal of the first sub-element is coupled to the input terminal of the second sub-element, and the output terminal of the second sub-element is coupled to the input terminal of the first sub-element.
[0066] Reference Figure 2 As shown, the output end of the first sub-element 201a is coupled to the input end of the second sub-element 202a, and the output end of the second sub-element 202a is coupled to the input end of the first sub-element 201a. The first sub-element 201a and the second sub-element 202a constitute a feedback unit A.
[0067] Still refer to Figure 2 As shown, the output end of the first sub-element 201b is coupled to the input end of the second sub-element 202b, and the output end of the second sub-element 202b is coupled to the input end of the first sub-element 201b. The first sub-element 201b and the second sub-element 202b constitute a feedback unit B.
[0068] Still refer to Figure 2 As shown, the output end of the first sub-element 201c is coupled to the input end of the second sub-element 202c, and the output end of the second sub-element 202c is coupled to the input end of the first sub-element 201c. The first sub-element 201c and the second sub-element 202c constitute a feedback unit C.
[0069] Still refer to Figure 2 As shown, the output end of the first sub-element 201d is coupled to the input end of the second sub-element 202d, and the output end of the second sub-element 202d is coupled to the input end of the first sub-element 201d. The first sub-element 201d and the second sub-element 202d constitute a feedback unit D.
[0070] It should be noted that the multiple feedback units captured according to the first instruction are not all measurement units, and further evaluation (i.e., screening) is required to screen out the measurement unit from the multiple feedback units. For example, feedback unit A, feedback unit B, feedback unit C, and feedback unit D are screened to determine the measurement unit.
[0071] In the disclosed embodiment, multiple feedback units can be captured from a large number of functional units in the integrated circuit according to the first instruction; the captured multiple feedback units are screened to determine the measurement unit, and the screening range of the measurement unit can be narrowed, thereby saving test time and helping to further improve test efficiency.
[0072] Furthermore, the embodiments of the present disclosure can compensate for the loophole of only detecting standard units in the prior art by capturing the feedback unit including the feedback structure, thereby improving the test coverage.
[0073] In some embodiments, the screening of the plurality of feedback units to determine the measurement unit includes: when the feedback unit includes a transmission gate (TG), determining the feedback unit as the measurement unit.
[0074] Taking the measurement unit as a latch and / or a trigger as an example, after obtaining multiple feedback units according to the first instruction, the latch and / or trigger can be screened out from the multiple feedback units by manual judgment. Here, the standard of manual judgment is: the feedback unit with a feedback structure and a transmission gate is a latch and / or a trigger (i.e., a measurement unit). Here, the method of screening out latches and / or triggers from multiple feedback units is not limited to transmission gates, and other methods can also be used to ensure that latches and / or triggers are screened out from multiple feedback units.
[0075] Of course, in other embodiments, the measurement unit may be screened out from a plurality of feedback units by writing a script, and the embodiment of the present disclosure has no special limitation on the method of screening the measurement unit.
[0076] In the disclosed embodiment, by searching for a functional unit having a transmission gate and a feedback structure among multiple feedback units, a measurement unit can be quickly found and tested, which helps save time in determining the measurement unit and further saves testing time.
[0077] In step S120, marking information is added to the measuring unit; wherein the marking information includes preset timing parameters of the measuring unit.
[0078] In some embodiments, reference Figure 3 As shown, the above step S120 includes: generating a measurement table; wherein the measurement table includes the name of the measurement unit (Cell_Name) and the preset timing parameters of the measurement unit; and adding marking information to the measurement unit according to the measurement table.
[0079] After obtaining the measurement unit, a measurement table can be generated, such as Figure 3 As shown, the measurement table includes multiple measurement units, for example, Figure 3 13 measurement units are shown, namely CDCKHLATF1, CDCKHLATF2, CDCKHLATF3, ..., CDCKHLATRPNF1, etc. The measurement table also includes information such as the data signal (Data_Signal, D), the clock signal (CLK_Signal, CK) and the preset timing parameters corresponding to each measurement unit.
[0080] In some embodiments, the preset timing parameters include: setup time margin (Set up_Margin) and hold time margin (Hold_Margin). The preset timing parameters are used to evaluate whether the timing of the integrated circuit meets the timing requirements. The setup time margin and the hold time margin can be preset values or value ranges. Those skilled in the art can reasonably set the preset timing parameters according to the timing constraints corresponding to the actual integrated circuit. Different integrated circuits can set different preset timing parameters, and the present disclosure has no special restrictions on this.
[0081] In some embodiments, marker information (Marker) may be added to each measurement unit, for example, according to Figure 3 The measurement table shown adds corresponding marking information in the blank space next to each measurement unit, such as Figure 4 The tag information includes the rising edge and falling edge of the data signal corresponding to each measurement unit, the rising edge and falling edge of the clock signal, the preset timing parameters, etc.
[0082] In some embodiments, the preset timing parameters include: preset timing parameters of the measurement unit at different process corners. The process corners of the measurement unit include: SS (Slow Slow), TT (Typical Typical), and FF (Fast Fast), etc. When designing an integrated circuit, the speed fluctuation range of the NMOS transistor and the PMOS transistor is limited to a rectangle determined by four corners. SS, TT, and FF are the corner of the lower left corner of the rectangle, the center of the rectangle, and the corner of the upper right corner of the rectangle, respectively. Here, the measurement unit includes an NMOS transistor and a PMOS transistor.
[0083] It should be noted that the delay of integrated circuits is generally affected by three factors: process, voltage and temperature, collectively known as PVT parameters. For the same process library, different delays will occur under different PVT conditions, so when measuring the timing of integrated circuits, it is necessary to consider whether the timing can converge under various conditions (i.e., meet the timing constraints).
[0084] In some embodiments, the setup time margin includes: the setup time margin of the measurement unit at different process corners; the setup time margin of the measurement unit at different process corners may be the same or different. Figure 3As shown, Setup_Margin includes Setup_Margin_FF, Setup_Margin_TT and Setup_Margin_SS, etc. In a specific embodiment, Setup_Margin_FF is 100p, and Setup_Margin_TT and Setup_Margin_SS are 125p.
[0085] In some embodiments, the hold time margin includes: the hold time margin of the measurement unit at different process corners; the hold time margin of the measurement unit at different process corners may be the same or different. Figure 3 As shown, Hold_Margin includes Hold_Margin_FF, Hold_Margin_TT and Hold_Margin_SS, etc. In a specific embodiment, Hold_Margin_FF, Hold_Margin_TT and Hold_Margin_SS are all 100p.
[0086] In the embodiment of the present disclosure, by setting preset timing parameters including preset timing parameters of the measurement unit at different process angles, the preset timing parameters at different process angles can reflect the timing constraints of the integrated circuit under different process / voltage / temperature and other parameters, thereby determining whether the timing of the integrated circuit can converge under various conditions, which is beneficial to ensuring the reliability of the timing of the integrated circuit.
[0087] In some embodiments, the above step S120 includes: adding marking information to the measurement unit according to a second instruction; wherein the second instruction is different from the first instruction.
[0088] The second instruction may be a script written in a programming language (e.g., C language, etc.), and the second instruction is used to add tag information to the measurement unit. For example, by executing the second instruction, Figure 3 Corresponding marking information is added to each measurement unit in the test table, so that the adding of marking information is completed automatically, which is conducive to saving test time and improving test efficiency.
[0089] In step S130, a simulation operation is performed on the integrated circuit to generate a simulation result, wherein the simulation result at least includes a measurement timing parameter of the measurement unit. For example, after adding the tag information, a simulation operation is performed on the measurement unit.
[0090] In some embodiments, the measured timing parameters include: setup time and hold time.
[0091] When performing timing analysis on an integrated circuit, the indicators that need to be analyzed include at least: setup time and hold time; setup time refers to the time before the rising edge of the clock signal arrives, the data is stable and unchanged. If the setup time is not enough, the data will not be entered into the measurement unit on the rising edge of the clock signal; hold time refers to the time after the rising edge of the clock signal arrives, the data is stable and unchanged. If the hold time is not enough, the data cannot be entered into the measurement unit either.
[0092] In this example, by performing simulation operations on the integrated circuit, at least the setup time and the hold time of the integrated circuit can be obtained, thereby determining whether the design of the integrated circuit meets the timing requirements.
[0093] In some embodiments, the measured timing parameters include: the measured timing parameters of the measuring unit at different process angles. Here, the measured timing parameters of the measuring unit at different process angles can be compared with the preset timing parameters of the measuring unit at different process angles to determine whether the timing of the integrated circuit can converge under various conditions.
[0094] In some embodiments, the setup time includes: the setup time of the measurement unit at different process corners; the setup time of the measurement unit at different process corners may be the same or different.
[0095] In some embodiments, the holding time includes: the holding time of the measurement unit at different process angles; the holding time of the measurement unit at different process angles may be the same or different.
[0096] In step S140, a measurement file is generated according to the measured timing parameters and the preset timing parameters; wherein the measurement file is used to indicate whether the integrated circuit meets the timing requirements.
[0097] In some embodiments, after the simulation results are generated, the measurement timing parameters may be saved in a measurement table, and the measurement table (eg, Figure 3 As shown in FIG. 1 , for example, the rising edge and falling edge of the data signal corresponding to the setup time (Setup_Data_Edge) and the rising edge and falling edge of the clock signal corresponding to the setup time (Setup_CLK_Edge) are saved. Here, the measurement file is the updated measurement table.
[0098] In some other embodiments, after the simulation results are generated, a new measurement table may be generated based on the generated measurement timing parameters and the preset timing parameters. Here, the measurement file is the newly generated measurement table.
[0099] In the embodiments of the present disclosure, there is no special limitation on the method of generating the measurement file, and those skilled in the art may make a selection according to actual needs.
[0100] In some embodiments, the above step S140 includes: when the setup time satisfies the setup time margin and the hold time satisfies the hold time margin, generating a measurement file, wherein the measurement file indicates that the integrated circuit meets the timing requirement.
[0101] In some embodiments, the above step S140 includes: when the setup time does not meet the setup time margin, and / or the hold time does not meet the hold time margin, generating a measurement file, the measurement file indicating that the integrated circuit does not meet the timing requirement.
[0102] It can be understood that only when both the setup time and the hold time meet the timing constraints, the timing of the integrated circuit meets the timing requirements, and the integrated circuit passes the test and can enter the next design stage; when at least one of the setup time and the hold time does not meet the timing constraints, the timing of the integrated circuit does not meet the timing requirements, and the design of the integrated circuit needs to be adjusted and tested again.
[0103] In some embodiments, when the setup time satisfies the setup time margin and the hold time satisfies the hold time margin, the measurement file includes preset timing parameters; when the setup time does not satisfy the setup time margin, the measurement file includes the setup time; and / or, when the hold time does not satisfy the hold time margin, the measurement file includes the hold time.
[0104] For example, when the setup time falls within the range of the setup time margin and the hold time falls within the range of the hold time margin, the setup time margin and the hold time margin are output normally.
[0105] For another example, when the setup time does not fall within the range of the setup time margin, the timing requirement is not met, an error is reported, and an error value (i.e., the measured setup time) is output; and / or, when the hold time does not fall within the range of the hold time margin, the timing requirement is not met, an error is reported, and an error value (i.e., the measured hold time) is output.
[0106] In some embodiments, when the integrated circuit does not meet timing requirements, the measurement file includes error values for outputs, such as measured setup times and / or hold times.
[0107] In some embodiments, the test method further includes: when the integrated circuit does not meet the timing requirements, adjusting the integrated circuit until the integrated circuit meets the timing requirements. Here, the weaknesses in the integrated circuit design can be analyzed according to the measurement file, and the functional units in the integrated circuit and the connection relationship between the functional units can be adjusted, thereby optimizing the integrated circuit design.
[0108] In some embodiments, the above test method is applied to static timing analysis of integrated circuits, for example, the timing verification process of DDR4 or DDR5.
[0109] The present disclosure provides a test method for an integrated circuit, the method comprising: obtaining a measurement unit in the integrated circuit; adding marking information to the measurement unit; wherein the marking information includes a preset timing parameter of the measurement unit; performing a simulation operation on the integrated circuit to generate a simulation result; wherein the simulation result includes at least the measurement timing parameter of the measurement unit; generating a measurement file according to the measurement timing parameter and the preset timing parameter; wherein the measurement file is used to indicate whether the integrated circuit meets the timing requirements. By executing the test method for the integrated circuit provided by the present disclosure, on the one hand, a measurement file including the measurement timing parameter and the preset timing parameter can be generated in the full chip simulation of the integrated circuit, and the design of the integrated circuit can be checked to see whether it meets the timing requirements, the coverage of the integrated circuit verification can be improved, and the weak points in the integrated circuit design can be found, thereby adjusting the design of the integrated circuit and optimizing the performance of the integrated circuit; on the other hand, the measurement file can intuitively report the nodes with insufficient timing margin in the circuit design, making it easier for designers to optimize the circuit; on the other hand, the judgment criteria (i.e., the preset timing parameters) can be accurately set, making it easier to analyze the measurement results.
[0110] Based on the above-mentioned integrated circuit testing method, the embodiment of the present disclosure further provides an integrated circuit testing device, which is used to implement the testing method in any of the above-mentioned embodiments. The integrated circuit testing device in the embodiment of the present disclosure is used to execute the above-mentioned testing method, and thus has at least the advantages of the above-mentioned testing method. The specific effects are referred to above and will not be repeated here.
[0111] Based on the above-mentioned integrated circuit testing method, an embodiment of the present disclosure also provides an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, it implements the testing method in any of the above-mentioned embodiments.
[0112] Based on the above-mentioned integrated circuit testing method, the embodiments of the present disclosure further provide a non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the testing method in any of the above-mentioned embodiments is implemented.
[0113] The following provides specific examples in combination with any of the above embodiments:
[0114] Example 1:
[0115] Figure 5 is a schematic diagram of a method for testing an integrated circuit according to an embodiment of the present disclosure. Figure 5 As shown, the test method includes the following steps:
[0116] Step S501: Automatically search for triggers (Delay flip-flops, DFF) and / or latches (LATCH, LAT). The triggers and / or latches in the integrated circuit can be automatically captured by the script, and a measurement table is generated, which includes the name of the trigger and / or latch, the data signal and clock signal corresponding to the trigger and / or latch, and the preset timing parameters of the trigger and / or latch.
[0117] Step S502: Adding marking information. Marking information can be added to the trigger and / or latch according to the measurement table, for example, adding corresponding marking information in the blank position next to the trigger and / or latch, and the marking information includes the rising edge and falling edge of the data signal corresponding to the trigger and / or latch, the rising edge and falling edge of the clock signal, preset timing parameters, etc.
[0118] Step S503: Generate a measurement file. A simulation operation may be performed on a logic circuit including a flip-flop and / or a latch, the generated measurement timing parameters may be saved in a measurement table, and the measurement table may be updated as a measurement file.
[0119] Step S504: Timing violation. The measurement file is used to indicate whether the integrated circuit has a timing violation, that is, whether the timing requirement is met.
[0120] Step S505: Determine whether there is a design weakness. If the measurement file indicates that there is no timing violation, that is, the integrated circuit does not have a design weakness and meets the timing requirements, then the timing verification ends; if the measurement file indicates that there is a timing violation, then execute step S506.
[0121] Step S506: Adjustment. When the measurement file indicates that there is a timing violation, an error may be reported and an error value may be output; the integrated circuit is adjusted according to the output error value, and the modulated integrated circuit performs steps S501 to S505 again until the timing requirements are met, thereby optimizing the integrated circuit design.
[0122] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A method for testing an integrated circuit, characterized in that: include: Acquire a measurement unit in the integrated circuit; Adding marking information to the measuring unit; wherein the marking information includes a preset timing parameter of the measuring unit; Performing a simulation operation on the integrated circuit to generate a simulation result; wherein the simulation result at least includes a measurement timing parameter of the measurement unit; A measurement file is generated according to the measured timing parameters and the preset timing parameters; wherein the measurement file is used to indicate whether the integrated circuit meets the timing requirements.
2. The testing method according to claim 1, characterized in that: The measuring unit comprises a latch and / or a trigger; The preset timing parameters include: setup time margin and hold time margin; The measurement timing parameters include: setup time and hold time.
3. The testing method according to claim 1, characterized in that: The measuring unit includes a latch and / or a trigger; the obtaining the measuring unit in the circuit includes: Acquire multiple feedback units in the integrated circuit according to the first instruction; wherein the feedback unit includes a feedback structure, and the feedback structure includes a first sub-element and a second sub-element; the output end of the first sub-element is coupled to the input end of the second sub-element, and the output end of the second sub-element is coupled to the input end of the first sub-element; The plurality of feedback units are screened to determine the measurement unit.
4. The testing method according to claim 3, characterized in that: The screening of the plurality of feedback units to determine the measurement unit includes: When the feedback unit includes a transmission gate, the feedback unit is determined to be the measurement unit.
5. The testing method according to claim 3, characterized in that: The preset timing parameters include: setup time margin and hold time margin; the measured timing parameters include: setup time and hold time; The generating a measurement file according to the measurement timing parameter and the preset timing parameter includes: When the setup time satisfies the setup time margin and the hold time satisfies the hold time margin, generating the measurement file, wherein the measurement file indicates that the integrated circuit satisfies the timing requirement; or, When the setup time does not satisfy the setup time margin, and / or the hold time does not satisfy the hold time margin, the measurement file is generated, and the measurement file indicates that the integrated circuit does not satisfy the timing requirement.
6. The testing method according to claim 5, characterized in that: When the setup time satisfies the setup time margin, and the hold time satisfies the hold time margin, the measurement file includes the preset timing parameters; When the setup time does not satisfy the setup time margin, the measurement file includes the setup time; and / or when the hold time does not satisfy the hold time margin, the measurement file includes the hold time.
7. The testing method according to claim 3, characterized in that: The adding mark information to the measurement unit includes: The marking information is added to the measurement unit according to a second instruction; wherein the second instruction is different from the first instruction.
8. The testing method according to claim 1, characterized in that: The adding mark information to the measurement unit includes: Generate a measurement table; wherein the measurement table includes the name of the measurement unit and the preset timing parameters of the measurement unit; The marking information is added to the measurement unit according to the measurement table.
9. The testing method according to claim 1, characterized in that: The preset timing parameters include: preset timing parameters of the measurement unit at different process angles.
10. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the test method according to any one of claims 1 to 9 is implemented.