Photoelectric co-packaging structure

Abstract

The invention provides a photoelectric co-packaging structure, which comprises a host chip, a photonic integrated chip and an electronic integrated chip, and is characterized in that the host chip and the photonic integrated chip are respectively arranged on the electronic integrated chip, and the electronic integrated chip bears the host chip and the photonic integrated chip; the host chip is electrically connected with the electronic integrated chip, and the electronic integrated chip is electrically connected with the photon integrated chip. According to the photoelectric co-packaging structure provided by the embodiment of the invention, the electronic integrated chip is used as the active adapter plate, so that the transmission path of an electric signal is shortened, and the communication efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an optoelectronic co-packaging structure. Background Art

[0002] As the bandwidth demand of data centers increases, silicon photonics system packaging has evolved from pluggable optical devices, onboard optics, near-package optics to co-packaged optics (CPO). CPO is a multi-chip heterogeneous integrated packaging method used to achieve integration between the optical engine (OE) composed of a photonic integrated chip (PIC) and an electronic integrated chip (EIC) and the host chip (Application Specific Integrated Circuit, ASIC).

[0003] CPO shortens the wiring distance between OE and host chip, reduces power loss and signal attenuation caused by copper wiring, and achieves better electrical performance. In order to reduce power loss and signal attenuation caused by copper wiring. In the prior art, the OE structure is to stack PIC and EIC vertically, and the OE structure and the ASIC host dedicated integrated circuit need to use a packaging substrate or a passive adapter board assembly for interconnection. Therefore, how to propose an optoelectronic co-packaging structure that can further shorten the communication distance between OE and host chip has become an important issue to be solved in this field. Summary of the invention

[0004] In view of the problems in the prior art, an embodiment of the present invention provides an optoelectronic co-packaging structure, which can at least partially solve the problems in the prior art.

[0005] The present invention provides an optoelectronic co-packaging structure, comprising a host chip, a photonic integrated chip and an electronic integrated chip, wherein:

[0006] The host chip and the photon integrated chip are respectively arranged on the electronic integrated chip, and the electronic integrated chip carries the host chip and the photon integrated chip; the host chip is electrically connected to the electronic integrated chip, and the electronic integrated chip is electrically connected to the photon integrated chip.

[0007] Furthermore, the electronic integrated chip comprises a first redistribution layer, and the first redistribution layer is arranged on a surface of the electronic integrated chip.

[0008] Furthermore, a first through silicon via is provided in the electronic integrated chip.

[0009] Furthermore, the host chip includes a computing unit core particle and / or a storage unit core particle, and the computing unit core particle and / or the storage unit core particle are respectively bonded to the electronic integrated chip, or integrated on the electronic integrated chip after three-dimensional stacking, and the computing unit core particle and the storage unit core particle are electrically connected to the electronic integrated chip.

[0010] Furthermore, the optoelectronic co-packaging structure provided by the embodiment of the present invention also includes a passive adapter board, which is arranged on the electronic integrated chip, and the host chip includes a computing unit core particle and / or the storage unit core particle, and the computing unit core particle and / or the storage unit core particle are respectively bonded to the passive adapter board, or integrated on the passive adapter board after three-dimensional stacking; the passive adapter board includes a second redistribution layer.

[0011] Furthermore, a second through silicon via is provided in the passive adapter board.

[0012] Furthermore, the passive transfer board is bump bonded or hybrid bonded on the electronic integrated chip.

[0013] Further, the computing unit core grain and / or the storage unit core grain are bonded to the passive adapter board through corresponding bumps, or the computing unit core grain and / or the storage unit core grain are hybrid bonded to the passive adapter board.

[0014] Furthermore, the host chip and the photonic integrated chip are respectively bonded on the electronic integrated chip through corresponding bump bonding or hybrid bonding.

[0015] Furthermore, at least one module among a power management module, a signal management module and an electrostatic protection module is integrated on the electronic integrated chip.

[0016] The optoelectronic co-packaging structure provided by the embodiment of the present invention includes a host chip, a photonic integrated chip and an electronic integrated chip. The host chip and the photonic integrated chip are respectively arranged on the electronic integrated chip, and the electronic integrated chip carries the host chip and the photonic integrated chip; the host chip is electrically connected to the electronic integrated chip, and the electronic integrated chip is electrically connected to the photonic integrated chip. Since the host chip and the photonic integrated chip are arranged on the electronic integrated chip, the electronic integrated chip is used as an active adapter board, which shortens the transmission path of the electrical signal and improves the communication efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 It is a structural schematic diagram of the optoelectronic co-packaging structure provided by the first embodiment of the present invention.

[0019] Figure 2 It is a structural schematic diagram of the optoelectronic co-packaging structure provided by the second embodiment of the present invention.

[0020] Figure 3 It is a structural schematic diagram of the optoelectronic co-packaging structure provided by the third embodiment of the present invention.

[0021] Figure 4 It is a structural schematic diagram of the optoelectronic co-packaging structure provided by the fourth embodiment of the present invention.

[0022] Figure 5 It is a structural schematic diagram of the optoelectronic co-packaging structure provided by the fifth embodiment of the present invention.

[0023] Figure 6 It is a structural schematic diagram of the optoelectronic co-packaging structure provided by the sixth embodiment of the present invention.

[0024] Figure 7 It is a structural schematic diagram of the optoelectronic co-packaging structure provided by the seventh embodiment of the present invention.

[0025] Figure 8 It is a structural schematic diagram of the optoelectronic co-packaging structure provided by the eighth embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined arbitrarily with each other. The acquisition, storage, use, and processing of data in the technical scheme in this application all comply with the relevant provisions of laws and regulations.

[0027] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0028] In the prior art, the OE structure and the host ASIC need to use a packaging substrate or a passive adapter board component for interconnection. There is also a certain communication distance between the OE structure and the host ASIC, which affects signal transmission. At the same time, there are problems such as the difficulty in smooth compatibility between the chip interfaces and the difficulty in integrating functions such as power management and electrostatic protection.

[0029] Therefore, an embodiment of the present invention provides an optoelectronic co-packaging structure, using the EIC in the OE structure as an active adapter board for the integration of PIC and host ASIC, shortening the signal transmission path, reducing the energy required for signal driving, reducing data delay, and achieving better electrical performance. Functional modules such as power management, signal conversion and equalization, and electrostatic protection can be integrated on the EIC, which can enhance the system signal integrity and power integrity, while reducing power consumption, cost, and achieving high-density integration. In addition, due to the reduction of components in the package, it is beneficial to reduce the complexity of the manufacturing process. In the present invention, the host ASIC includes but is not limited to switches, CPUs, GPUs, FPGAs, memories, etc.

[0030] Figure 1 is a schematic structural diagram of an optoelectronic co-packaging structure provided by a first embodiment of the present invention, Figure 2 is a schematic structural diagram of an optoelectronic co-packaging structure provided by a second embodiment of the present invention, such as Figure 1 and Figure 2 As shown, the optoelectronic co-packaging structure provided by the embodiment of the present invention includes a host chip 1, a photonic integrated chip 2 and an electronic integrated chip 3, wherein:

[0031] The host chip 1 and the photon integrated chip 2 are respectively arranged on the electronic integrated chip 3 , and the electronic integrated chip 3 carries the host chip 1 and the photon integrated chip 2 ; the host chip 1 is electrically connected to the electronic integrated chip 3 , and the electronic integrated chip 3 is electrically connected to the photon integrated chip 2 .

[0032] Specifically, in an embodiment of the present invention, the electronic integrated chip 3 serves as an active adapter board to carry the host chip 1 and the photon integrated chip 2. The host chip 1 can be integrated on the electronic integrated chip 3 by a hybrid bonding process, or by bump bonding on the electronic integrated chip 3. The host chip 1 can be electrically connected to the electronic integrated chip 3. The photon integrated chip 2 can be integrated on the electronic integrated chip 3 by a hybrid bonding process, or by bump bonding on the electronic integrated chip 3. The electronic integrated chip 3 is electrically connected to the photon integrated chip 2. Among them, the bump bonding can be performed by solder bump bonding, micro bump bonding, etc., which can be selected according to actual needs, and the embodiment of the present invention does not limit it.

[0033] The optoelectronic co-packaging structure provided by the embodiment of the present invention includes a host chip, a photonic integrated chip and an electronic integrated chip. The host chip and the photonic integrated chip are respectively arranged on the electronic integrated chip, and the electronic integrated chip carries the host chip and the photonic integrated chip; the host chip is electrically connected to the electronic integrated chip, and the electronic integrated chip is electrically connected to the photonic integrated chip. Since the host chip and the photonic integrated chip are arranged on the electronic integrated chip, the electronic integrated chip is used as an active adapter board, which shortens the transmission path of the electrical signal and improves the communication efficiency.

[0034] like Figure 1 and Figure 2 As shown, on the basis of the above embodiments, further, the electronic integrated chip 3 includes a first redistribution layer 3 - 1 , and the first redistribution layer 3 - 1 is arranged on the surface of the electronic integrated chip 3 .

[0035] Specifically, the electronic integrated chip 3 includes a first redistribution layer 3-1, which can be arranged on the surface of the electronic integrated chip 3 on one side of the host chip 1 and the electronic integrated chip 3 to realize the electrical connection between the host chip 1 and the electronic integrated chip 3, and the electrical connection between the photonic integrated chip 2 and the electronic integrated chip 3.

[0036] For example, Figure 1 As shown, the host chip 1 is bonded to the electronic integrated chip 3 through the first bump 5, and the photon integrated chip 2 is bonded to the electronic integrated chip 3 through the second bump 6. The host chip 1 is electrically connected to the electronic integrated chip 3 through the first bump 5 and the first rewiring layer 3-1. The photon integrated chip 2 is electrically connected to the electronic integrated chip 3 through the second bump 6 and the first rewiring layer 3-1. The host chip 1 can be electrically connected to the photon integrated chip 2 through the first rewiring layer 3-1.

[0037] For example, Figure 2 As shown, the host chip 1 is integrated on the electronic integrated chip 3 through hybrid bonding technology, and the photonic integrated chip 2 is integrated on the electronic integrated chip 3 through hybrid bonding technology. The host chip 1 is electrically connected to the electronic integrated chip 3 through the first redistribution layer 3-1. The photonic integrated chip 2 is electrically connected to the electronic integrated chip 3 through the first redistribution layer 3-1. The host chip 1 can be electrically connected to the photonic integrated chip 2 through the first redistribution layer 3-1.

[0038] like Figure 1 and Figure 2 As shown, on the basis of the above embodiments, further, a first through silicon via 3 - 2 is provided in the electronic integrated chip 3 , and power supply and data transmission can be realized through the first through silicon via 3 - 2 .

[0039] Furthermore, a third rewiring layer may be provided on the other side surface of the electronic integrated chip 3 opposite to the surface on which the first rewiring layer 3-1 is provided, and the first through silicon via 3-2 may electrically connect the first rewiring layer 3-1 with the third rewiring layer.

[0040] Figure 3 is a schematic structural diagram of an optoelectronic co-packaging structure provided by a third embodiment of the present invention, Figure 4 is a schematic structural diagram of an optoelectronic co-packaging structure provided by a fourth embodiment of the present invention, Figure 5 is a schematic structural diagram of an optoelectronic co-packaging structure provided by a fifth embodiment of the present invention. Figure 3 , Figure 4 and Figure 5 As shown, on the basis of the above embodiments, further, the host chip 1 includes a computing unit core particle 1-1 and / or a storage unit core particle 1-2, and the computing unit core particle 1-1 and / or the storage unit core particle 1-2 are respectively bonded to the electronic integrated chip 3, or integrated on the electronic integrated chip 3 after three-dimensional stacking, and the computing unit core particle 1-1 and the storage unit core particle 1-2 are electrically connected to the electronic integrated chip 3.

[0041] Specifically, the host chip 1 may include a computing unit (Comp) core 1-1 and a memory unit (MEM) core 1-2; the host chip 1 may include only the computing unit core 1-1; or the host chip 1 may include only the memory unit core 1-2. The computing unit core 1-1 is used for data processing, and the memory unit core 1-2 is used for data storage.

[0042] The computing unit core particle 1-1 can be integrated on the electronic integrated chip 3 by hybrid bonding technology, or by bump bonding on the electronic integrated chip 3. The storage unit core particle 1-2 can be integrated on the electronic integrated chip 3 by hybrid bonding technology, or by bump bonding on the electronic integrated chip 3. The computing unit core particle 1-1 and the storage unit core particle 1-2 can be electrically connected through the first rewiring layer on the electronic integrated chip 3.

[0043] The computing unit core grain 1-1 can be stacked on the storage unit core grain 1-2 to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated into the electronic integrated chip 3; or the storage unit core grain 1-2 is stacked on the computing unit core grain 1-1 to form a three-dimensional stacked structure, and then the three-dimensional stacked structure is integrated into the electronic integrated chip 3. Among them, the computing unit core grain 1-1 can be stacked on the storage unit core grain 1-2 by hybrid bonding or bump bonding, and similarly, the storage unit core grain 1-2 can be stacked on the computing unit core grain 1-1 by hybrid bonding or bump bonding.

[0044] The computing unit core particle 1-1 can be electrically connected to the electronic integrated chip 3. The electronic integrated chip 3 can send the electrical signal from the computing unit core particle 1-1 to the photon integrated chip 2. The storage unit core particle 1-2 can be electrically connected to the electronic integrated chip 3. The electronic integrated chip 3 can send the electrical signal sent by the storage unit core particle 1-2 to the photon integrated chip 2.

[0045] The computing unit core particle 1-1 can be electrically connected to the storage unit core particle 1-2. The computing unit core particle 1-1 and the storage unit core particle 1-2 are electrically interconnected, and integrated with the associated OE and its components as a flexible and efficient way to achieve the miniaturization of the optoelectronic co-sealed architecture. The electrically interconnected computing unit core particle 1-1 and the storage unit core particle 1-2 are horizontally integrated with the photonic integrated chip 2 on the electronic integrated chip 3.

[0046] For example, Figure 3 As shown, the computing unit core particle 1-1 is bonded to the electronic integrated chip 3 through the third bump 7, the storage unit core particle 1-2 is bonded to the electronic integrated chip 3 through the fourth bump 8, and the photon integrated chip 2 is bonded to the electronic integrated chip 3 through the second bump 6. The computing unit core particle 1-1 is electrically connected to the electronic integrated chip 3 through the third bump 7, and the storage unit core particle 1-2 is electrically connected to the electronic integrated chip 3 through the fourth bump 8. The photon integrated chip 2 is electrically connected to the electronic integrated chip 3 through the second bump 6. The computing unit core particle 1-1 is electrically connected to the storage unit core particle 1-2 through the third bump 7 and the fourth bump 8.

[0047] For example, Figure 4 As shown, the computing unit core particle 1-1 is integrated on the electronic integrated chip 3 through hybrid bonding technology, the storage unit core particle 1-2 is integrated on the electronic integrated chip 3 through hybrid bonding technology, and the photon integrated chip 2 is integrated on the electronic integrated chip 3 through hybrid bonding technology. The computing unit core particle 1-1 is electrically connected to the electronic integrated chip 3, and the storage unit core particle 1-2 is electrically connected to the electronic integrated chip 3. The photon integrated chip 2 is electrically connected to the electronic integrated chip 3. The computing unit core particle 1-1 is electrically connected to the storage unit core particle 1-2 through the electronic integrated chip 3.

[0048] For example, Figure 5 As shown, the computing unit core particle 1-1 is bonded to the storage unit core particle 1-2 through the fifth bump 9, the storage unit core particle 1-2 is bonded to the electronic integrated chip 3 through the sixth bump 10, and the photon integrated chip 2 is bonded to the electronic integrated chip 3 through the second bump 6. The computing unit core particle 1-1 is electrically connected to the storage unit core particle 1-2 through the fifth bump 9, and the storage unit core particle 1-2 is electrically connected to the electronic integrated chip 3 through the sixth bump 10. The photon integrated chip 2 is electrically connected to the electronic integrated chip 3 through the second bump 6.

[0049] Figure 6 is a schematic structural diagram of an optoelectronic co-packaging structure provided by a sixth embodiment of the present invention, Figure 7 is a schematic structural diagram of an optoelectronic co-packaging structure provided by a seventh embodiment of the present invention, Figure 8 is a schematic structural diagram of an optoelectronic co-packaging structure provided by an eighth embodiment of the present invention, such as Figure 6 , Figure 7 and Figure 8 As shown, on the basis of the above embodiments, further, the optoelectronic co-packaging structure provided in the embodiment of the present invention also includes a passive adapter board 11, the passive adapter board 11 is arranged on the electronic integrated chip 3, the host chip 1 includes a computing unit core particle 1-1 and / or a storage unit core particle 1-2, the computing unit core particle 1-1 and / or the storage unit core particle 1-2 are respectively bonded to the passive adapter board 11, or integrated on the passive adapter board 11 after three-dimensional stacking; the passive adapter board 11 includes a second redistribution layer 11-1.

[0050] Specifically, the passive adapter board 11 can be integrated on the electronic integrated chip 3 through a hybrid bonding technology, or bonded on the electronic integrated chip 3 through corresponding bumps. The passive adapter board 11 can be made of materials such as silicon.

[0051] The host chip 1 may include a computing unit chip 1 - 1 and a storage unit chip 1 - 2 ; the host chip 1 may include only the computing unit chip 1 - 1 ; or the host chip 1 may include only the storage unit chip 1 - 2 .

[0052] The computing unit chip 1-1 can be integrated on the passive transfer board 11 by hybrid bonding technology, or by bump bonding on the passive transfer board 11. The storage unit chip 1-2 can be integrated on the passive transfer board 11 by hybrid bonding technology, or by bump bonding on the passive transfer board 11. The computing unit chip 1-1 and the storage unit chip 1-2 can be electrically connected through the second rewiring layer 11-1 included in the passive transfer board 11.

[0053] The computing unit core grain 1-1 can be stacked on the storage unit core grain 1-2 to form a three-dimensional stacking structure, and then the three-dimensional stacking structure is integrated onto the passive adapter board 11; the storage unit core grain 1-2 is stacked on the computing unit core grain 1-1 to form a three-dimensional stacking structure, and then the three-dimensional stacking structure is integrated onto the passive adapter board 11. Multiple computing unit core grains 1-1 can be stacked to form a three-dimensional stacking structure, and then the three-dimensional stacking structure is integrated onto the passive adapter board 11; multiple storage unit core grains 1-2 can be stacked to form a three-dimensional stacking structure, and then the three-dimensional stacking structure is integrated onto the passive adapter board 11. Among them, the computing unit core grain 1-1 can be stacked on the storage unit core grain 1-2 by hybrid bonding or bump bonding; the storage unit core grain 1-2 can be stacked on the computing unit core grain 1-1 by hybrid bonding or bump bonding; multiple computing unit core grains 1-1 can be stacked by hybrid bonding or bump bonding; multiple storage unit core grains 1-2 can be stacked by hybrid bonding or bump bonding.

[0054] like Figure 6 , Figure 7 and Figure 8 As shown, based on the above embodiments, a second through silicon via 11-2 is further provided in the passive adapter board 11. The second through silicon via 11-2 is used to realize the electrical connection between the computing unit core particle 1-1 and the electronic integrated chip 3, and / or realize the electrical connection between the storage unit core particle 1-2 and the electronic integrated chip 3.

[0055] For example, Figure 6 As shown, the host chip 1 includes a computing unit core particle 1-1 and a storage unit core particle 1-2. The passive adapter board 11 is bonded to the electronic integrated chip 3 through the seventh bump 12. The computing unit core particle 1-1 is bonded to the passive adapter board 11 through the eighth bump 13, and the storage unit core particle 1-2 is bonded to the passive adapter board 11 through the ninth bump 14. The passive adapter board 11 includes a second redistribution layer 11-1 and a second through silicon via 11-2. The computing unit core particle 1-1 is electrically connected to the electronic integrated chip 3 through the eighth bump 13, the second redistribution layer 11-1, the second through silicon via 11-2, and the seventh bump 12. The storage unit core particle 1-2 is electrically connected to the electronic integrated chip 3 through the ninth bump 14, the second redistribution layer 11-1, the second through silicon via 11-2, and the seventh bump 12. The computing unit chip 1 - 1 is electrically connected to the memory unit chip 1 - 2 through the eighth bump 13 , the second redistribution layer 11 - 1 and the ninth bump 14 .

[0056] For example, Figure 7As shown, the host chip 1 includes a computing unit core particle 1-1 and a storage unit core particle 1-2. The computing unit core particle 1-1 is integrated on the passive adapter board 11 by hybrid bonding, and the storage unit core particle 1-2 is integrated on the passive adapter board 11 by hybrid bonding. The passive adapter board 11 is integrated on the electronic integrated chip 3 by hybrid bonding. The passive adapter board 11 includes a second rewiring layer 11-1 and a second silicon through-via 11-2. The computing unit core particle 1-1 is electrically connected to the electronic integrated chip 3 through the second rewiring layer 11-1 and the second silicon through-via 11-2. The computing unit core particle 1-1 is electrically connected to the storage unit core particle 1-2 through the second rewiring layer 11-1.

[0057] For example, Figure 8 As shown, the host chip 1 includes a computing unit core particle 1-1 and a storage unit core particle 1-2. The storage unit core particle 1-2 is bonded to the computing unit core particle 1-1 through the tenth bump 16, and the computing unit core particle 1-1 is bonded to the passive adapter board 11 through the eleventh bump 15. The passive adapter board 11 is bonded to the electronic integrated chip 3 through the seventh bump 12. The passive adapter board 11 includes a second redistribution layer 11-1 and a second silicon through-hole 11-2. The storage unit core particle 1-2 is electrically connected to the computing unit core particle 1-1 through the tenth bump 16. The computing unit core particle 1-1 is electrically connected to the electronic integrated chip 3 through the eleventh bump 15, the second redistribution layer 11-1, the second silicon through-hole 11-2, and the seventh bump 12.

[0058] like Figure 6 As shown, on the basis of the above embodiments, further, the passive adapter board 11 is bonded to the electronic integrated chip 3 through corresponding bumps. When the passive adapter board 11 is bump-bonded to the electronic integrated chip 3, if the host chip includes a computing unit core grain and a storage unit core grain, the computing unit core grain and the storage unit core grain can be bonded to the passive adapter board 11 through their corresponding bumps, the computing unit core grain and the storage unit core grain can be mixedly bonded to the passive adapter board 11, or the computing unit core grain and the storage unit core grain can be three-dimensionally stacked and integrated on the passive adapter board 11. If the host chip includes multiple computing unit core grains, each computing unit core grain can be bonded to the passive adapter board 11 through its corresponding bumps, each computing unit core grain can be mixedly bonded to the passive adapter board 11, or multiple computing unit core grains can be three-dimensionally stacked and integrated on the passive adapter board 11. If the host chip includes multiple storage unit core particles, each computing unit core particle can be bonded to the passive adapter board 11 through its corresponding bump, each storage unit core particle can be mixed bonded to the passive adapter board 11, or multiple storage unit core particles can be three-dimensionally stacked and integrated on the passive adapter board 11.

[0059] like Figure 7As shown, on the basis of the above embodiments, further, the passive adapter board 11 can be hybrid bonded to the electronic integrated chip 3. When the passive adapter board 11 is hybrid bonded to the electronic integrated chip 3, if the host chip includes a computing unit core grain and a storage unit core grain, the computing unit core grain and the storage unit core grain can be bonded to the passive adapter board 11 through their corresponding bumps, the computing unit core grain and the storage unit core grain can be hybrid bonded to the passive adapter board 11, or the computing unit core grain and the storage unit core grain can be three-dimensionally stacked and integrated on the passive adapter board 11. If the host chip includes multiple computing unit core grains, each computing unit core grain can be bonded to the passive adapter board 11 through its corresponding bumps, each computing unit core grain can be hybrid bonded to the passive adapter board 11, or multiple computing unit core grains can be three-dimensionally stacked and integrated on the passive adapter board 11. If the host chip includes multiple storage unit core particles, each computing unit core particle can be bonded to the passive adapter board 11 through its corresponding bump, each storage unit core particle can be mixed bonded to the passive adapter board 11, or multiple storage unit core particles can be three-dimensionally stacked and integrated on the passive adapter board 11.

[0060] like Figure 6 As shown, on the basis of the above embodiments, further, the computing unit core particle 1-1 and / or the storage unit core particle 1-2 are bonded to the passive adapter board 11 through corresponding bumps.

[0061] For example, Figure 6 As shown, the host chip 1 includes a computing unit chip 1-1 and a storage unit chip 1-2. The computing unit chip 1-1 is bonded to the passive transfer board 11 through the eighth bump 13, and the storage unit chip 1-2 is bonded to the passive transfer board 11 through the ninth bump 14.

[0062] For example, the host chip 1 includes a plurality of computing unit core particles 1 - 1 , and each computing unit core particle 1 - 1 can be bonded to the passive transfer board 11 through a corresponding bump.

[0063] For example, the host chip 1 includes a plurality of storage unit core particles 1 - 2 , and each storage unit core particle 1 - 2 can be bonded to the passive transfer board 11 through a corresponding bump.

[0064] like Figure 7 As shown, on the basis of the above embodiments, further, the computing unit core grain 1 - 1 and / or the storage unit core grain 1 - 2 are hybrid-bonded on the passive adapter board 11 .

[0065] For example, Figure 7 As shown, the host chip 1 includes a computing unit chip 1-1 and a storage unit chip 1-2. The computing unit chip 1-1 is hybrid-bonded on the passive adapter board 11, and the storage unit chip 1-2 is hybrid-bonded on the passive adapter board 11.

[0066] For example, the host chip 1 includes a plurality of computing unit core particles 1 - 1 , and each computing unit core particle 1 - 1 can be hybrid-bonded on the passive transfer board 11 .

[0067] For example, the host chip 1 includes a plurality of memory unit chips 1 - 2 , and each memory unit chip 1 - 2 can be hybrid-bonded on the passive transfer board 11 .

[0068] like Figure 2 As shown, on the basis of the above embodiments, further, the host chip 1 and the photonic integrated chip 2 are hybrid-bonded on the electronic integrated chip 3 respectively.

[0069] Specifically, the host chip 1 can be integrated into the electronic integrated chip 3 through a hybrid bonding process, and the photonic integrated chip 2 can be integrated into the electronic integrated chip 3 through a hybrid bonding process.

[0070] The host chip 1 is stacked on the electronic integrated chip, and the OE structure and the host-specific integrated circuit do not need to use a separate packaging substrate or a passive adapter board for interconnection, which further shortens the transmission path of the electrical signal and improves the communication efficiency.

[0071] like Figure 1 As shown, the host chip 1 and the photonic integrated chip 2 are bonded to the electronic integrated chip 3 through corresponding bumps.

[0072] Specifically, the host chip 1 is bonded to the electronic integrated chip 3 through the first bump 5, and the photon integrated chip 2 is bonded to the electronic integrated chip 3 through the second bump 6. The host chip 1 is electrically connected to the electronic integrated chip 3 through the first bump 5 and the first redistribution layer 3-1. The photon integrated chip 2 is electrically connected to the electronic integrated chip 3 through the second bump 6 and the first redistribution layer 3-1. The host chip 1 can be electrically connected to the photon integrated chip 2 through the first redistribution layer 3-1. The specific number of the first bump 5 and the second bump 6 is set according to actual needs, and the embodiment of the present invention does not limit it.

[0073] On the basis of the above embodiments, further, at least one module among a power management module, a signal management module and an electrostatic protection module is integrated on the electronic integrated chip 3 .

[0074] Specifically, at least one of a power management module, a signal management module, and an electrostatic protection module may be integrated on the electronic integrated chip 3. For example, a power management module, a signal management module, or an electrostatic protection module is provided on the electronic integrated chip 3. For example, any two of a power management module, a signal management module, and an electrostatic protection module are provided on the electronic integrated chip 3. For example, a power management module, a signal management module, and an electrostatic protection module are provided on the electronic integrated chip 3.

[0075] By arranging a power management module, a signal management module and an electrostatic protection module on the electronic integrated chip 3 , the signal integrity and power integrity of the system can be enhanced.

[0076] The optoelectronic co-packaging structure provided by the embodiment of the present invention uses the EIC in the OE as an active adapter board for the integration of the PIC and the host ASIC or the PIC and the dedicated Comp-MEM core module, shortening the signal path. Functional modules such as power management, signal conversion and equalization, and electrostatic protection can be integrated on the EIC to enhance the signal integrity and power integrity of the system. While achieving high-performance optoelectronic conversion, it reduces the complexity of the integration process, power consumption and cost, and achieves high functional density integration.

[0077] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0078] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An optoelectronic co-packaging structure, characterized in that: Including host chip, photonic integrated chip and electronic integrated chip, among which: The host chip and the photon integrated chip are respectively arranged on the electronic integrated chip, and the electronic integrated chip carries the host chip and the photon integrated chip; the host chip is electrically connected to the electronic integrated chip, and the electronic integrated chip is electrically connected to the photon integrated chip.

2. The optoelectronic co-packaging structure according to claim 1, characterized in that: The electronic integrated chip comprises a first redistribution layer, and the first redistribution layer is arranged on a surface of the electronic integrated chip.

3. The optoelectronic co-packaging structure according to claim 1, characterized in that: A first through silicon via is provided in the electronic integrated chip.

4. The optoelectronic co-packaging structure according to claim 1, characterized in that: The host chip includes a computing unit core particle and / or a storage unit core particle, and the computing unit core particles and / or the storage unit core particles are respectively bonded to the electronic integrated chip, or integrated on the electronic integrated chip after three-dimensional stacking, and the computing unit core particles and the storage unit core particles are electrically connected to the electronic integrated chip.

5. The optoelectronic co-packaging structure according to claim 1, characterized in that: It also includes a passive adapter board, which is arranged on the electronic integrated chip. The host chip includes computing unit core particles and / or storage unit core particles, and the computing unit core particles and / or storage unit core particles are respectively bonded to the passive adapter board, or integrated on the passive adapter board after three-dimensional stacking; the passive adapter board includes a second redistribution layer.

6. The optoelectronic co-packaging structure according to claim 5, characterized in that: A second through silicon via is provided in the passive adapter plate.

7. The optoelectronic co-packaging structure according to claim 5, characterized in that: The passive transfer board is bump bonded or hybrid bonded on the electronic integrated chip.

8. The optoelectronic co-packaging structure according to claim 5, characterized in that: The computing unit core grain and / or the storage unit core grain are bonded to the passive adapter board through corresponding bumps, or the computing unit core grain and / or the storage unit core grain are hybrid bonded to the passive adapter board.

9. The optoelectronic co-packaging structure according to claim 1, characterized in that: The host chip and the photonic integrated chip are respectively bonded to the electronic integrated chip through corresponding bump bonding or hybrid bonding.

10. The optoelectronic co-packaging structure according to any one of claims 1 to 9, characterized in that: At least one of a power management module, a signal management module and an electrostatic protection module is integrated on the electronic integrated chip.

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