Display panel

Abstract

The embodiment of the invention discloses a display panel, which comprises a plurality of sub-pixels arranged in an array, a substrate and a shielding electrode, the sub-pixel is located on the substrate, and the shielding electrode is located between the substrate and the sub-pixel; wherein the sub-pixel comprises a pixel electrode, at least one part of the shielding electrode is located in the opening area of the sub-pixel, the first side edge of the shielding electrode and the first side edge of the pixel electrode are not overlapped, and the first side edge of the shielding electrode is the side edge, close to the non-opening area of the sub-pixel, of the shielding electrode; the first side edge of the pixel electrode is the side edge, close to the non-opening area, of the pixel electrode. In the non-opening area of the sub-pixel, the first side edge of the shielding electrode and the first side edge of the pixel electrode are not overlapped, the electric field effect of the shielding electrode and the pixel electrode can be effectively avoided, liquid crystal sorting disorder is prevented, and then the light emitting efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] The current liquid crystal display (LCD) usually uses metal as the common electrode on the array side of the device to reduce the impact of parasitic capacitance on the display. However, due to the opacity of the metal layer, the light-emitting area is reduced, that is, the transmittance is reduced. Based on this, the transparent shielding and storage electrode (TSS) structure, by adding a layer of transparent electrode (TSS ITO layer) to replace part of the original metal electrode as a storage capacitor and shielding electrode, can reduce the dark area of ​​the pixel and increase the aperture ratio, thereby improving the panel transmittance.

[0003] However, the superposition of the TSS ITO layer and other metal layers will lead to a complex edge field of the pixel structure, causing disorder in the liquid crystal order, which in turn causes unsatisfactory light output. Summary of the invention

[0004] The embodiments of the present application provide a display panel to at least solve the technical problem in the existing pixel structure that the edge field of the pixel structure is complex due to the superposition of metal layers, which causes the liquid crystal arrangement to be disordered and further causes unsatisfactory light output.

[0005] An embodiment of the present application provides a display panel, which includes a plurality of sub-pixels arranged in an array, and the display panel also includes: a substrate, on which the sub-pixels are located; a shielding electrode, which is located between the substrate and the sub-pixels; wherein the sub-pixels include a pixel electrode, at least a portion of the shielding electrode is located in an opening area of ​​the sub-pixel, a first side edge of the shielding electrode and a first side edge of the pixel electrode do not overlap, the first side edge of the shielding electrode is a side edge of the shielding electrode close to a non-opening area of ​​the sub-pixel, and the first side edge of the pixel electrode is a side edge of the pixel electrode close to the non-opening area.

[0006] In one embodiment, the non-opening area includes a thin film transistor, and the pixel electrode is connected to the thin film transistor through a via hole located in the non-opening area; wherein the distance from the first side of the shielding electrode to the via hole is greater than the distance from the first side of the pixel electrode to the via hole.

[0007] In one embodiment, a distance L1 between the first side of the shielding electrode and the via hole satisfies the following range: L1 ≥ 5 μm.

[0008] In one embodiment, the display panel also includes a common electrode, the common electrode includes a common electrode routing, the common electrode routing is located between the substrate and the shielding electrode, and the common electrode routing is located at the junction of the opening area and the non-opening area; wherein, the spacing from the first side edge of the common electrode routing to the via hole is smaller than the spacing from the first side edge of the shielding electrode to the via hole, and the first side edge of the common electrode routing is a side edge of the common electrode routing away from the via hole.

[0009] In one embodiment, the non-opening area includes a thin film transistor, and the pixel electrode is connected to the thin film transistor through a via hole located in the non-opening area; wherein the distance from the first side of the shielding electrode to the via hole is smaller than the distance from the first side of the pixel electrode to the via hole.

[0010] In one embodiment, the display panel also includes a data line arranged between adjacent sub-pixels, the data line is located between the substrate and the shielding electrode, and the orthographic projection of the data line on the substrate partially overlaps with the orthographic projection of the frame of the pixel electrode on the substrate in the width direction of the data line.

[0011] In one embodiment, the overlapping width of the orthographic projection of the data line on the substrate and the orthographic projection of the frame of the pixel electrode on the substrate is set to L2, the pixel interval between two adjacent sub-pixels is L3, and the ratio of L3 to L2 satisfies: L3 / L2>1.6.

[0012] In one embodiment, a value range of an overlapping width L2 between an orthographic projection of the data line on the substrate and an orthographic projection of the frame of the pixel electrode on the substrate satisfies: L2≤3 μm.

[0013] In one embodiment, a value range of a pixel interval L3 between two adjacent sub-pixels satisfies: L3 ≥ 5 μm.

[0014] In one embodiment, the display panel further includes a color resist layer, and the color resist layer is disposed on a side of the shielding electrode close to the substrate.

[0015] The beneficial effects provided by the embodiments of the present application include at least:

[0016] The embodiment of the present application provides a display panel, including a plurality of sub-pixels arranged in an array, and also including a substrate and a shielding electrode; the sub-pixel is located on the substrate, and the shielding electrode is located between the substrate and the sub-pixel; wherein the sub-pixel includes a pixel electrode, at least a portion of the shielding electrode is located in the opening area of ​​the sub-pixel, the first side of the shielding electrode and the first side of the pixel electrode do not overlap, the first side of the shielding electrode is a side of the shielding electrode close to the non-opening area of ​​the sub-pixel, and the first side of the pixel electrode is a side of the pixel electrode close to the non-opening area. In the embodiment of the present application, the sub-pixel can be a rectangular structure, and metal wirings such as a thin film transistor (TFT) and a common electrode are generally arranged in the short side area of ​​the sub-pixel. The voltage difference between the transparent shielding electrode (TSS ITO) and the pixel electrode will cause the edge electric field of the short side of the sub-pixel to be disordered. Therefore, in the non-opening area of ​​the sub-pixel, the first side of the shielding electrode and the first side of the pixel electrode do not overlap, that is, the shielding electrode moves up or down to avoid the pixel electrode at the via hole, which can effectively avoid the electric field effect between the shielding electrode and the pixel electrode, prevent the liquid crystal from being disordered, and thus improve the light extraction efficiency.

[0017] Other beneficial effects of the embodiments of the present application will be further described in the following specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a display panel provided in an optional embodiment of the present application;

[0019] Figure 2 is a schematic structural diagram of a sub-pixel provided in an optional embodiment of the present application;

[0020] Figure 3 is a schematic structural diagram of a junction area between an opening area and a non-opening area of ​​a sub-pixel provided in an optional embodiment of the present application;

[0021] Figure 4 A schematic diagram of a pixel structure of a display panel provided in an optional embodiment of the present application;

[0022] Figure 5 yes Figure 4 Schematic diagram of the AA section;

[0023] Figure 6 is a schematic structural diagram of a spacing region between adjacent sub-pixels provided in an optional embodiment of the present application;

[0024] Figure 7 is a cross-sectional schematic diagram of another spacing region between adjacent sub-pixels provided in an optional embodiment of the present application;

[0025] Figure 8is a simulation schematic diagram of an alignment improvement effect provided in an optional embodiment of the present application;

[0026] Fig. 9 is a simulation schematic diagram of a color shift improvement effect provided in an optional embodiment of the present application;

[0027] Fig.10 It is a structural schematic diagram of a display terminal provided in an optional embodiment of the present application.

[0028] Description of Reference Numerals

[0029] 1. Display panel;

[0030] 10, substrate; 11, sub-pixel; A, opening area; B, non-opening area; 111, common electrode wiring; 1111, first side of common electrode wiring; 112, shielding electrode; 1121, first side of shielding electrode; 113, pixel electrode; 1130, first side of pixel electrode; 1131, first main body; 1132, second main body; 1133, first branch; 1134, second branch; 1135, frame of pixel electrode; 114, first metal layer; 1141, first wiring; 1142, data line; 115, via; 116, color resist layer; 1161, first color resist layer; 1162, second color resist layer; 117, liquid crystal;

[0031] 20. Color filter substrate;

[0032] 2. Display terminal;

[0033] 3; Terminal body. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0035] In addition, the term "plurality" in the embodiments of the present application refers to two or more than two. The terms "first" and "second" in the embodiments of the present application are used to distinguish different technical features, and do not represent any order, quantity or importance.

[0036] The directional terms mentioned in this application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate this application, and are not used to limit the scope of protection of this application.

[0037] In the drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for the convenience of understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and the present application does not limit the size and thickness of each component.

[0038] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0039] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0040] Reference Figure 1 As shown, an embodiment of the present application provides a display panel 1, including a display area AA and a non-display area NA arranged on a substrate 10, wherein the display area AA includes a plurality of sub-pixels 11 arranged in an array. Each sub-pixel 11 corresponds to one of the three colors of red, green and blue. In the embodiment of the present application, a rectangular sub-pixel is used as an example to explain the scheme.

[0041] The display panel 1 of the present application adopts a vertical alignment (VA) technology driving architecture. Figure 1 and Figure 5 As shown, the display panel 1 includes an array substrate 10, a liquid crystal layer 117 and an opposing substrate 20 (which may be a color filter substrate) arranged in sequence. The common electrode arranged on the opposing substrate 20 and the pixel electrode of the array substrate 10 form a vertical electric field after being connected to different voltages to drive the liquid crystal of the liquid crystal layer 117 to deflect, thereby realizing picture display.

[0042] Reference Figure 2 and Figure 3 As shown, the display panel 1 also includes: a substrate 10, on which the sub-pixel 11 is located; a shielding electrode 112, which is located between the substrate 10 and the sub-pixel 11; wherein the sub-pixel 11 includes a pixel electrode 113, at least a portion of the shielding electrode 112 is located in an opening area A of the sub-pixel 11, a first side edge 1121 of the shielding electrode 112 and a first side edge 1131 of the pixel electrode 113 do not overlap, the first side edge 1121 of the shielding electrode 112 is a side edge of the shielding electrode 112 close to a non-opening area B of the sub-pixel 11, and the first side edge 1130 of the pixel electrode is a side edge of the pixel electrode 113 close to the non-opening area B.

[0043] In the embodiment of the present application, metal wirings such as TFT and common electrode are generally arranged in the non-opening area of ​​the sub-pixel. The voltage difference between the transparent shielding electrode (TSS ITO) and the pixel electrode will cause the edge electric field of the short side of the sub-pixel to be disordered. Therefore, in the short side area of ​​the sub-pixel (which can be understood as the non-opening area B), the complex topography of the short side of the sub-pixel can be improved by the staggered design of each film layer, and the influence of the complex edge electric field of the short side on the central electric field of the normal display area can be improved. In the embodiment of the present application, in the non-opening area B of the sub-pixel, the first side edge 1121 of the shielding electrode and the first side edge 1130 of the pixel electrode do not overlap, that is, the shielding electrode moves up or down to avoid the pixel electrode at the via, which can effectively avoid the electric field effect of the shielding electrode 112 and the pixel electrode 113, prevent the liquid crystal sorting disorder, and thus improve the light extraction efficiency.

[0044] In an optional embodiment, the non-opening area B includes a thin film transistor 116, and the pixel electrode 113 is connected to the thin film transistor 116 through a via 115 located in the non-opening area B; wherein, the distance from the first side 1121 of the shielding electrode to the via 115 is greater than the distance from the first side 1131 of the pixel electrode to the via 115.

[0045] In an optional embodiment, the distance L1 between the first side 1121 of the shielding electrode and the via hole 115 satisfies the following range: L1 ≥ 5 μm. For example, L1 can be set to 5 μm, 6 μm or 7 μm, so that the shielding electrode 112 moves up or down to avoid the pixel electrode 113 at the via hole 115, which can effectively avoid the electric field effect between the shielding electrode and the pixel electrode, prevent the liquid crystal from being disordered, and thus improve the light extraction efficiency.

[0046] The shielding electrode 112 can be a TSS transparent electrode, which can be used in a vertical alignment liquid crystal display (VA-LCD) and can replace the traditional shielding and storage metal electrodes. The shielding electrode 112 can be a metal layer set on the entire surface, and holes are dug in the opening area and part of the non-opening area of ​​the sub-pixel. Its main purpose is to improve the transmittance and optical efficiency of the display, thereby achieving energy saving. In traditional liquid crystal displays, shielding and storage electrodes are usually made of metal materials, which absorb part of the light and reduce the transmittance of the display. The TSS transparent electrode reduces the absorption of light by using transparent materials, thereby improving the transmittance.

[0047] In an optional embodiment, the display panel 1 also includes a common electrode, the common electrode includes a common electrode wiring 111, the common electrode wiring 111 is located between the substrate 10 and the shielding electrode 112, and the common electrode wiring 111 is located at the junction of the opening area A and the non-opening area B; wherein, the spacing from the first side 1111 of the common electrode wiring to the via 115 is smaller than the spacing from the first side 1121 of the shielding electrode to the via 115, and the first side 1111 of the common electrode wiring is a side of the common electrode wiring 111 away from the via 115.

[0048] Reference Figure 2 and Figure 3 As shown, in an optional embodiment, the pixel electrode 113 includes a frame 1135 of the pixel electrode, a first main body 1131 arranged along the length direction of the sub-pixel 11 (as shown in the Y direction), one or more second main bodies 1132 arranged perpendicular to the first main body 1131, a plurality of first branches 1133, and a second branch 1134 connected to the first branch. The first main body 1131 and the second main body 1132 divide the sub-pixel 11 into multiple domains, and the first branches 1133 are arranged parallel to each other and spaced apart at a preset angle in each domain, and the orthographic projection of the portion where the first branch 1133 and the second branch 1134 are connected on the substrate 10 does not overlap with the orthographic projection of the shielding electrode 1121 on the substrate 10.

[0049] It should be noted that the sub-pixel 11 in the embodiment of the present application is a multi-domain pixel, such as four domains, six domains or eight domains, etc., which can be selected according to actual applications, and the present application does not limit this. In this embodiment, a four-domain sub-pixel is taken as an example for description in conjunction with the accompanying drawings, that is, the pixel electrode 113 in this embodiment includes a first main body 1131 and a second main body 1132 perpendicular to the first main body 1131, dividing the sub-pixel 11 into four areas.

[0050] The staggered design of each film layer can improve the complex topography of the short side of the sub-pixel (which can be understood as the non-opening area B), and improve the influence of the complex edge electric field of the short side on the central electric field of the normal display area. The orthographic projection of the portion where the first branch 1133 and the second branch 1134 are connected on the substrate 10 does not overlap with the orthographic projection of the common electrode wiring 111 on the substrate 10, that is, the corner of the pixel electrode 113 in the short side area of ​​the sub-pixel (refer to Figure 3 The common electrode wiring 111 is staggered with the pixel electrode 110 to effectively avoid the electric field effect between the pixel electrode and the common electrode, prevent the liquid crystal from being disordered, and thus improve the light extraction efficiency.

[0051] Continue to refer to Figure 2 and Figure 3As shown, in an optional embodiment, the display panel further includes a first metal layer 114, which is disposed between the common electrode wiring 111 and the shielding electrode 112. The first metal layer 114 includes a first wiring 1141 disposed in the sub-pixel 11, and the first wiring 1141 is connected to the second branch 1134 of the pixel electrode through the via 115; wherein the orthographic projection of the portion where the first branch 1133 of the pixel electrode and the second branch 1134 are connected on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10.

[0052] The staggered design of each film layer can improve the complex topography of the non-opening area B of the sub-pixel, and improve the influence of the complex edge electric field of the short side of the non-opening area B on the central electric field of the normal display area. The orthographic projection of the part where the first branch 1133 and the second branch 1134 are connected on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10, that is, the corner of the pixel electrode 113 in the non-opening area of ​​the sub-pixel is staggered with the via 115, which can effectively avoid the formation of a complex edge electric field between the position of the pixel electrode 113 at the via 115 and the first wiring 1141 of the first metal layer 114 and the second branch 1134 of the pixel electrode, thereby preventing the liquid crystal from being disordered and thereby improving the light output efficiency.

[0053] In an optional embodiment, the orthographic projection of the shielding electrode 112 on the substrate 10 does not overlap with the orthographic projection of the via hole 115 on the substrate 10 .

[0054] In an optional embodiment, the orthographic projection of the common electrode trace 111 on the substrate 10 does not overlap with the orthographic projection of the via hole 115 on the substrate 10 .

[0055] By staggering the shielding electrode 112 or the common electrode wiring 111 and the via hole 115, it is possible to effectively avoid the formation of a complex fringe electric field between multiple film layers, prevent the disorder of liquid crystal sorting, and thus improve the light extraction efficiency.

[0056] In an optional embodiment, the first side edge 1121 of the shielding electrode and the first side edge 1111 of the common electrode wiring are in the first direction (eg Figure 3 The spacing distance in the Y direction (shown) ranges from 1 to 3 μm. By shifting the TSS downward or upward, the short-side edge electric field can be controlled to reduce the short-side edge dark lines.

[0057] Figure 4 is a schematic diagram of a pixel structure of a display panel provided in an optional embodiment of the present application, Figure 5 yes Figure 4 In the AA cross-section diagram, it should be noted that: Figure 4 Shown is a single sub-pixel, Figure 5 FIG. 1 is a schematic cross-sectional view of adjacent long sides of two adjacent sub-pixels. Figure 4 and Figure 5 As shown, the first metal layer 114 also includes a data line 1142 disposed between adjacent sub-pixels. The gap between the data line 1142 and the pixel electrode 113 between adjacent sub-pixels is too large. For example, the horizontal distance between the data line 1142 and the left and right pixel electrodes 113 is about 1.4 μm. There is a lateral electric field between the shielding electrode 1121 and the pixel electrode 113, and the liquid crystal 117 between the data line 1142 and the pixel gap is deflected, causing light leakage in the pixel, which in turn causes color shift on the panel.

[0058] To solve the above problems, refer to Figures 2 to 7 As shown, the orthographic projection of the data line 1142 on the substrate 10 in the embodiment of the present application partially overlaps with the orthographic projection of the frame 1135 of the pixel electrode on the substrate 10 in the width direction of the data line 1142 .

[0059] In one embodiment, the non-opening area includes a thin film transistor 116, and the pixel electrode 113 is connected to the thin film transistor 116 through a via hole 115 located in the non-opening area B; wherein, the spacing from the first side edge 1121 of the shielding electrode to the via hole 115 is smaller than the spacing from the first side edge 1131 of the pixel electrode to the via hole 115. The side of the shielding electrode 112 close to the via hole 115 and the side of the pixel electrode 113 close to the via hole 115 are staggered, and the shielding electrode 112 moves up or down to avoid the pixel electrode 113 at the via hole 115, which can effectively avoid the electric field effect between the shielding electrode 112 and the pixel electrode 113, prevent the liquid crystal from being disordered, and thus improve the light extraction efficiency.

[0060] In one embodiment, the display panel 1 also includes a data line 1142 arranged between adjacent sub-pixels 11, the data line 1142 is located between the substrate 10 and the shielding electrode 112, and the orthographic projection of the data line 1142 on the substrate 10 partially overlaps with the orthographic projection of the pixel electrode frame 1135 on the substrate 10 in the width direction of the data line 1142.

[0061] In one embodiment, the overlap width of the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the frame 1135 of the pixel electrode on the substrate 10 is set to L2, the pixel interval between two adjacent sub-pixels 11 is L3, and the ratio relationship between L3 and L2 satisfies: L3 / L2>1.6. By controlling the ratio range of L2 and L3, for example, setting the ratio to 1.65, 1.7, 1.75, etc., the degree of disorderly tilting of the liquid crystal under the TSS electric field can be reduced, the azimuth angle of the liquid crystal is closer to 45°, and the alignment dark pattern is optimized to improve the transmittance Tr%. As shown in Table 1 below, when L3 / L2>1.6, Tr% is effectively improved from 4.46% to 4.75%.

[0062] Table 1

[0063] Penetration Before improvement After improvement Tr％ 4.46％ 4.75％

[0064] Under the premise of satisfying L3 / L2>1.6, or when the ratio of L3 / L2 is not considered, the transmittance of the display panel can be improved and the color deviation can be improved by setting the value ranges of L2 and L3 respectively.

[0065] Continue to refer Figure 6 and Figure 7 As shown, in one embodiment, the overlap width L2 of the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the frame 1135 of the pixel electrode on the substrate 10 satisfies the value range of L2≤3μm. In an optional embodiment, the overlap width of the Trunk portion and the data line can be adjusted by widening the width L4 of the data line 1142. Optionally, the overlap width of the orthographic projection of the data line 1142 on the substrate 10 and the frame 1135 of the pixel electrode (equivalent to Figure 6 The overlapping width range L2 of the orthographic projection of the Trunk portion (as shown) on the substrate may be less than or equal to 3 μm, for example, set to 1.5 to 3 μm.

[0066] In one embodiment, the pixel interval L3 between two adjacent sub-pixels 11 satisfies the following range: L3 ≥ 5 μm. Figure 7 As shown, in an optional embodiment, the pixel interval L3 between two adjacent sub-pixels can be greater than or equal to 5μm, for example, set to 5μm, or 6μm, or 7μm, and the width of the data line 1142 can be greater than the pixel interval between two adjacent sub-pixels. By setting a suitable pixel interval, the color resistance can be prevented from entering the adjacent sub-pixels due to process fluctuations to cause color deviation.

[0067] The first branches 1133 of the pixel electrode 113 can be connected together at the edge to form a vertical strip keel structure (Trunk), that is, the frame 1135 of the pixel electrode. Figure 6 As shown in the dotted box, it can also be understood that the entire pixel electrode 113 is a whole rectangular ITO electrode, and includes hollow parts arranged in parallel and at intervals in the divided multi-domain area. In the embodiment of the present application, the width of the Trunk can be appropriately reduced, for example, the Trunk width is set to 2.5 to 4μm, so that the Trunk part and the data line 1142 are further overlapped in the width direction. By matching the appropriate Trunk width, the dark lines caused by the edge field of the long side of the sub-pixel can be improved, so that the luminous area of ​​the normal display area is larger, thereby improving the light extraction efficiency.

[0068] Selecting the appropriate Trunk width can effectively reduce the interference between signal lines. A width that is too narrow may lead to increased electromagnetic interference between signal lines, while a width that is too wide may increase the complexity and cost of the circuit board. At the same time, when designing the data line, ensure that the data line can completely block edge light leakage. This can be achieved by performing an Overlay design between the data line and the pixel, that is, the data line covers the edge of the pixel to prevent light leakage. Through the Overlay design, the data line can completely block edge light leakage, reduce light leakage from the edge, and thus improve the display effect. Further, ensure that the distance between pixels is appropriate to avoid color resistance crosstalk caused by being too close. In a display panel, color resistance crosstalk refers to the color interference between different pixels due to resistance changes. This interference can be reduced by optimizing the distance between pixels. On the one hand, a suitable pixel spacing can reduce color resistance crosstalk under process fluctuations and ensure the stability of the display effect. On the other hand, during the manufacturing process, process fluctuations may cause changes in resistance and capacitance, thereby affecting the display effect. Through reasonable design, the impact of this fluctuation on the display effect can be reduced.

[0069] During the design process, the embodiment of the present application determines the optimal Trunk width and data line layout through simulation and testing. Ensure that the data line can completely cover the edge of the pixel and reduce light leakage. According to the actual test results, adjust the distance between Pixel and Pixel (which can be understood as the distance between adjacent sub-pixels) to ensure that good display effects can be maintained at different grayscales and viewing angles. Referring to Table 2 below, when the value range of the overlapping width L2 of the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the frame 1135 of the pixel electrode on the substrate 10 satisfies L2≤3μm, and the pixel spacing L3≥5μm, the contrast viewing angle is effectively improved. Contrast Ratio Viewing Angle (CR) refers to the change in the contrast of the display at different viewing angles. The contrast refers to the brightness ratio of the display when displaying the brightest (white) and darkest (black) images. High contrast means clearer images and brighter colors. CR (-30) represents the contrast value measured at a viewing angle of -30 degrees. -30 degree viewing angle and +30 degree viewing angle refer to the position that deviates 30 degrees to the left or right from the front of the display. The higher the value of the contrast viewing angle, the better the contrast of the display can be maintained at a -30 degree viewing angle, and the image quality is better. In the embodiment of the present application, a reasonable pixel spacing value is set, and the CR (-30) before improvement is 38.8%, the CR (-30) after improvement is 55.4%, the CR (+30) before improvement is 37.3%, and the CR (+30) after improvement is 54.9%, indicating that the contrast of the display at a -30 degree viewing angle is significantly improved, and the image quality is improved.

[0070] Table 2

[0071] Contrast viewing angle Before improvement After improvement CR(-30) 38.80％ 55.40％ CR(+30) 37.30％ 54.90％

[0072] Reference Figure 8 and Fig. 9 As shown, Figure 8 FIG. 1 is a simulation diagram of the alignment improvement effect provided in an optional embodiment of the present application. Fig. 9 It is a simulation diagram of the color deviation improvement effect provided in the optional embodiment of the present application. It can be seen that the display panel structure provided in the embodiment of the present application effectively improves the dark lines and color deviation on the short and long sides of the pixels, and the images displayed in the luminous area are all normal images.

[0073] Reference Figure 5 As shown, in an optional embodiment, the display panel also includes: an amorphous silicon layer 118, which is arranged on the side of the data line 1142 close to the substrate 10; wherein, between adjacent sub-pixels 11, the orthographic projection of the data line 1142 on the substrate 10 covers the orthographic projection of the amorphous silicon layer 118 on the substrate 10.

[0074] In one embodiment, the display panel further includes: a color resist layer 116 disposed on a side of the shielding electrode 112 close to the substrate 10 .

[0075] In the embodiment of the present application, the color resist layer 116 may include a plurality of red color resists, green color resists, and blue color resists. The color resists of each color in the color resist layer are used to convert white light into color light of corresponding colors. In the display area, one color resist is set corresponding to one sub-pixel 11. Figure 7 As shown, the color resist layers of two adjacent sub-pixels are color resists of different colors, for example, the color resist layer 1161 and the color resist layer 1162 can be blue and red, or green and red, respectively. The sub-pixel 11 provided with a red color resist is a red sub-pixel, the sub-pixel 11 provided with a green color resist is a green sub-pixel, and the sub-pixel 11 provided with a blue color resist is a blue sub-pixel. The color resist layer 116 is usually composed of tiny red, green, and blue (RGB) filters, which are precisely placed on each sub-pixel of the liquid crystal panel. Each sub-pixel corresponds to a color, and by controlling the color and brightness of the light passing through the sub-pixel, a full-color image is finally combined. The structure of the color resist layer usually includes: a filter, made of organic dyes or inorganic pigments, used to filter light of a specific wavelength; a black matrix (Black Matrix), which is arranged between the filters to absorb excess light, prevent interference between colors, and improve the contrast and clarity of the display; a protective layer, covering the filter and the black matrix, to prevent physical damage and environmental impact.

[0076] It should be understood that in the present embodiment, the display panel 1 is a panel with a COA (Color Filter on Array) structure, and the color filter substrate 20 is arranged relative to the substrate 10 (Array substrate). By setting the display panel 1 as a panel with a COA structure, the color resist layer 116 and the pixel electrode 113 can be arranged on the same substrate 10, thereby avoiding the loss of aperture ratio due to the alignment deviation of the two substrates when the color resist layer 116 and the pixel electrode 113 are arranged on different substrates, that is, the use of the COA structure helps to increase the alignment accuracy of the color resist layer 116 and the pixel electrode 113, and improve the aperture ratio of the display panel 1.

[0077] The display panel in the embodiment of the present application may also include an insulating layer, a passivation layer or a planarization layer arranged between different metal layers. The insulating layer may be an insulating layer composed of inorganic materials, such as glass, quartz, ceramics, aluminum oxide, boron nitride, magnesium oxide, calcium silicate, borate glass, etc. The passivation layer may be formed by an inorganic material, such as silicon nitride. The planarization layer is used to smooth the surface of the substrate to reduce surface roughness and unevenness, thereby providing better conditions for subsequent manufacturing processes. The materials of the planarization layer generally include oxides, nitrides, polysilicon, polymers, etc. The selection of these materials depends on the required electrical properties, mechanical properties, and chemical properties. The manufacturing process of the planarization layer includes chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, spray coating, etc. These processes can ensure that the planarization layer is evenly distributed on the substrate to form a smooth surface. In the embodiment of the present application, the planarization layer is used to ensure the uniformity and consistency of the display panel.

[0078] The shielding electrode 112 and the pixel electrode 113 can be transparent metals, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), etc.

[0079] Reference Fig. 9 As shown, another embodiment of the present application further provides a display terminal 2, comprising the display panel 1 and the terminal body 3 described in any of the above embodiments, wherein the display panel 1 and the terminal body 3 are combined into one. The terminal body 3 may include a backlight module, which is arranged on a side of the substrate 10 of the display panel 1 away from the color resist layer 116. The backlight module is used to provide a light source for the display panel 1.

[0080] The display terminal can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0081] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of sub-pixels arranged in an array, and the display panel further includes: a substrate, the sub-pixels being located on the substrate; a shielding electrode, the shielding electrode being located between the substrate and the sub-pixel; Wherein, the sub-pixel includes a pixel electrode, at least a portion of the shielding electrode is located in the opening area of ​​the sub-pixel, the first side edge of the shielding electrode and the first side edge of the pixel electrode do not overlap, the first side edge of the shielding electrode is a side edge of the shielding electrode close to the non-opening area of ​​the sub-pixel, and the first side edge of the pixel electrode is a side edge of the pixel electrode close to the non-opening area.

2. The display panel according to claim 1, characterized in that: The non-opening area includes a thin film transistor, and the pixel electrode is connected to the thin film transistor through a via hole located in the non-opening area; Wherein, the distance from the first side of the shielding electrode to the via hole is greater than the distance from the first side of the pixel electrode to the via hole.

3. The display panel according to claim 2, characterized in that: A distance L1 between the first side of the shielding electrode and the via hole satisfies the following range: L1 ≥ 5 μm.

4. The display panel according to claim 2, characterized in that: The display panel further includes a common electrode, the common electrode includes a common electrode wiring, the common electrode wiring is located between the substrate and the shielding electrode, and the common electrode wiring is located at the junction of the opening area and the non-opening area; The distance between the first side of the common electrode line and the via hole is smaller than the distance between the first side of the shielding electrode and the via hole, and the first side of the common electrode line is a side of the common electrode line away from the via hole.

5. The display panel according to claim 1, characterized in that: The non-opening area includes a thin film transistor, and the pixel electrode is connected to the thin film transistor through a via hole located in the non-opening area; Wherein, the distance between the first side of the shielding electrode and the via hole is smaller than the distance between the first side of the pixel electrode and the via hole.

6. The display panel according to claim 1, characterized in that: The display panel also includes a data line arranged between adjacent sub-pixels, the data line is located between the substrate and the shielding electrode, and the orthographic projection of the data line on the substrate partially overlaps with the orthographic projection of the frame of the pixel electrode on the substrate in the width direction of the data line.

7. The display panel according to claim 1, characterized in that: The overlapping width of the orthographic projection of the data line on the substrate and the orthographic projection of the frame of the pixel electrode on the substrate is set to L2, the pixel interval between two adjacent sub-pixels is L3, and the ratio relationship between L3 and L2 satisfies: L3 / L2>1.

6.

8. The display panel according to claim 7, characterized in that: The value range of the overlapping width L2 between the orthographic projection of the data line on the substrate and the orthographic projection of the frame of the pixel electrode on the substrate satisfies: L2≤3 μm.

9. The display panel according to claim 7, characterized in that: The value range of the pixel interval L3 between two adjacent sub-pixels satisfies: L3 ≥ 5 μm.

10. The display panel according to any one of claims 1 to 9, characterized in that: The display panel further includes a color resist layer, and the color resist layer is arranged on a side of the shielding electrode close to the substrate.

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