Power-off timing circuit and electrical equipment

Abstract

The invention relates to the technical field of control circuits, in particular to a power-off timing circuit and electrical equipment. According to the technical scheme, the power-off timing circuit of the control chip is provided, the power supply end of the control chip is connected with a power supply signal, and the power-off timing circuit comprises a following loop of which the output end is connected with the input end of the control chip; the conduction end of the one-way conduction loop is connected with the output end of the control chip, and the cut-off end of the one-way conduction loop is connected with the input end of the following loop; and the timing loop is connected between the cut-off end of the one-way conduction loop and the input end of the following loop. According to the power-off timing circuit, the external circuit with a simple structure, namely the timing circuit, is used for timing, and the whole control chip does not need to be powered during power off, so that an energy storage element with smaller capacitance and volume can be adopted, and the volume and the production and manufacturing cost of the power-off timing circuit of the whole control chip are reduced.

Description

Technical Field

[0001] The invention relates to the technical field of control circuits, and in particular to a power-off timing circuit and electrical equipment. Background Art

[0002] When electrical equipment is working normally, it can perform timing work through components such as internal timers; when the electrical equipment is powered off, if the power off time still needs to be recorded, an auxiliary energy storage unit is required to power the components with timing functions inside the equipment separately when the entire electrical equipment is powered off. For example, the button battery installed on the computer motherboard can still power the motherboard after the computer is powered off.

[0003] Figure 1 It is a power-off timing circuit of a control chip in the prior art. Figure 1 As shown, the control chip M0 is connected to the power signal PG of the external AC power supply, and when the control chip M0 works normally, it is powered by the external AC power supply. In addition, an external power supply capacitor C0 is also connected between the DC power supply terminal VDD and the ground terminal GND of the control chip M0. When the control chip M0 is powered off, that is, the external AC power supply is disconnected, the external power supply capacitor C0 starts to supply power to the entire control chip M0, so that the control chip M0 can continue to work for a period of time when the external AC power supply is disconnected, such as timing a period of time; when the control chip M0 resumes power supply, that is, the control chip M0 detects that the external power signal is restored, the control chip M0 can calculate the power-off time of the external power supply of the control chip M0 according to the time when the external power signal is disconnected and restored.

[0004] In the above-mentioned prior art, the external power supply capacitor C0 needs to maintain the entire control chip M0 working for a period of time when the external power supply is cut off. Therefore, the energy storage element such as the external power supply capacitor C0 needs to have a large capacitance to maintain the power supply to the control chip M0 for as long as possible. Usually, the capacitance of the external power supply capacitor C0 needs to reach several hundred μF or more. Accordingly, the volume and cost of the external power supply capacitor C0, i.e., the energy storage element, will increase, and the volume of the power-off timing circuit of the overall control chip M0 will also increase, which is not conducive to the miniaturization design of the power-off timing circuit of the control chip M0 and the electrical components equipped with the power-off timing circuit. Summary of the invention

[0005] In view of the above problems, the present invention provides a power-off timing circuit and an electrical device. The power-off timing circuit of the control chip in the present invention performs timing through an external circuit with a simple structure, and does not need to supply power to the entire control chip when the power is off, so that energy storage elements with smaller capacitance and volume can be used to reduce the volume of the control circuit.

[0006] In the technical solution of the present invention, a power-off timing circuit of a control chip is provided, in which the power supply end of the control chip is connected to the power supply signal, including: a following loop, in which the output end of the following loop is connected to the input end of the control chip; a unidirectional conducting loop, in which the conducting end of the unidirectional conducting loop is connected to the output end of the control chip, and the cut-off end of the unidirectional conducting loop is connected to the input end of the following loop; and a timing loop, in which the timing loop is connected between the cut-off end of the unidirectional conducting loop and the input end of the following loop.

[0007] According to the technical solution of the present invention, when the control chip works normally, the power signal is input into the control chip through the power supply terminal; when the external power supply of the control chip is powered off, that is, when the control chip detects that there is no power signal, the control chip outputs a control signal to the timing circuit through the output terminal, and the timing circuit starts to work. The working voltage of the timing circuit starts to decrease with the discharge time. When the power signal at the power supply terminal of the control chip is restored, the control chip immediately detects the voltage signal at the input terminal of the control chip. The working voltage of the timing circuit can be transmitted to the input terminal of the control chip without loss through the following loop, and the discharge time, that is, the power-off time of the control chip, can be calculated according to the relationship between the working voltage of the timing circuit and the time. The power-off timing circuit of the above-mentioned control chip has a simple structure, and only a small-power timing circuit is required to perform discharge timing, so as to realize the external power-off timing circuit of the control chip, and can conveniently and accurately measure the power-off time of the control chip. At the same time, energy storage elements with smaller capacitance and volume can be used to reduce the volume of the power-off timing circuit of the overall control chip.

[0008] Preferably, in the technical solution of the present invention, the timing circuit includes a capacitor and a discharge load, one end of the capacitor is connected between the cutoff end of the unidirectional conduction circuit and the input end of the following circuit; the discharge load is connected in parallel with the capacitor.

[0009] According to the technical solution of the present invention, when the external power supply of the control chip is powered off, the control chip outputs a control signal to the capacitor through the output terminal, the capacitor and the parallel discharge load form a discharge circuit, the capacitor starts to discharge, and the amount of electricity in the capacitor begins to decrease with the discharge time, so that the voltage value at both ends of the discharge load also begins to decrease with the discharge time; when the power signal at the power supply end of the control chip is restored, the control chip immediately detects the voltage signal at the input end of the control chip, and the voltage value at both ends of the discharge load can be transmitted to the input end of the control chip without loss through the following loop, and the discharge time, i.e., the power-off time of the control chip, can be calculated according to the relationship between the voltage value at both ends of the discharge load and the time. The power-off timing circuit structure of the above-mentioned control chip is simple, and only a small-capacity capacitor and an adapted discharge load are required to form a small-capacity capacitor discharge circuit, so as to realize the external power-off timing circuit of the control chip, and the power-off time of the control chip can be conveniently and accurately measured. At the same time, a capacitor with smaller capacitance and volume can be used as an energy storage element to reduce the volume of the power-off timing circuit of the overall control chip.

[0010] Preferably, in the technical solution of the present invention, the capacitance of the capacitor in the power-off timing circuit is nF level. Using a capacitor with a low capacitance, that is, using a capacitor with a smaller volume, can further reduce the volume of the power-off timing circuit, so as to further miniaturize and compact the overall circuit, and further reduce the production cost.

[0011] Preferably, in the technical solution of the present invention, the follower loop in the power-off timing circuit includes an operational amplifier, the in-phase input terminal of the operational amplifier is connected to the output terminal of the control chip, and the inverting input terminal and output terminal of the operational amplifier are connected to the input terminal of the control chip.

[0012] According to the technical solution of the present invention, a voltage following loop is formed by an operational amplifier connected to the inverting input terminal and the output terminal, and while keeping the voltage of the output terminal consistent with the voltage of the input terminal, the input terminal and the output terminal are isolated by utilizing the characteristics of its high input impedance, so that the load when the capacitor is discharged has only the discharge load connected in parallel with it, so as to ensure the accuracy of calculating the discharge time according to the voltage. In addition, the operational amplifier itself has a simple structure and a small size, which is conducive to the miniaturization and low-cost design of the overall power-off timing circuit.

[0013] Furthermore, in the technical solution of the present invention, the power-off timing circuit also includes a current-limiting resistor connected between the capacitor and the follower loop.

[0014] According to the technical solution of the present invention, the current limiting resistor is arranged at the input end of the operational amplifier, so as to play a role in regulating the magnitude of the current flowing into the operational amplifier.

[0015] Preferably, in the technical solution of the present invention, the unidirectional conduction loop in the power-off timing circuit includes a diode, the anode of the diode is connected to the output end of the control chip, and the cathode of the diode is connected to the positive end of the capacitor.

[0016] According to the technical solution of the present invention, the on-off characteristics of the diode itself are utilized to ensure that the RC voltage reaches the required value instantly during the charging process, and to prevent the capacitor charge from flowing back to the control chip through the output end of the control chip during the discharging process, thereby obtaining a higher timing accuracy. In addition, the diode itself has the advantages of small size and low cost, which is conducive to the miniaturization and low-cost design of the overall power-off timing circuit.

[0017] In the power-off timing circuit provided by the technical solution of the present invention, the control chip can execute a power-off timing method, and the power-off timing method includes: a discharging step, when the control chip detects that there is no power signal at the power supply end, the output end of the control chip sends a discharge signal, and the capacitor discharges; a detection step, after the control chip detects that the power signal at the power supply end is restored, the input end of the control chip detects the input signal; a power-off time determination step, determining the power-off time of the power supply end of the control chip according to the input signal and a preset power-off timing curve.

[0018] According to the technical solution of the present invention, through the above-mentioned power-off timing method, the power-off timing circuit of the control chip can be externalized, and the accurate detection and calculation of the power-off time of the control chip can be achieved through the external power-off timing circuit with simple structure and low cost.

[0019] Preferably, in the technical solution of the present invention, the power-off timing method of the power-off timing circuit also includes: a charging restoration step, after the detection step is completed, the output end of the control chip outputs a charging signal, and the capacitor is charged until it is fully charged.

[0020] According to the technical solution of the present invention, through the above-mentioned charging restoration step, the capacitor can be fully charged in time after the power signal connected to the control chip is restored, so as to be ready for the next use.

[0021] Preferably, in the power-off timing circuit provided by the technical solution of the present invention, the control chip can execute a method for generating a power-off timing curve, and the method for generating a power-off timing curve includes: a discharging step, in which the output end of the control chip sends a discharge signal, and the capacitor discharges; a detection step, in which the control chip times while the capacitor discharges in the discharging step, and the input end of the control chip detects the input signal at a preset time interval; a curve generating step, in which a power-off timing curve of the capacitor is generated and stored according to the input signal and the timing time of the control chip.

[0022] According to the technical solution of the present invention, the above-mentioned method for generating the power-off timing curve can simulate the power-off situation when the control chip is working normally, and combine the timing circuit of the control chip itself to draw, correct and store the actual relationship curve between voltage and discharge time. Therefore, the measurement and component errors of the control chip and the power-off timing circuit itself can be eliminated, and the calculation accuracy of the power-off time can be improved.

[0023] The technical solution of the present invention further provides an electrical device, which is equipped with the above-mentioned power-off timing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of a power-off timing circuit provided in the prior art;

[0025] Figure 2is a schematic diagram of a power-off timing circuit provided in an embodiment of the present invention;

[0026] Figure 3 is a flow chart of a power-off timing method provided in an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of a voltage waveform when a power-off timing circuit performs a power-off timing method provided in an embodiment of the present invention;

[0028] Figure 5 is a flow chart of a method for generating a power-off timing curve provided in an embodiment of the present invention;

[0029] Figure 6 It is a schematic diagram of a voltage waveform when a power-off timing circuit provided in an embodiment of the present invention executes a method for generating a power-off timing curve.

[0030] Explanation of the accompanying drawings: 1-power-off timing circuit, 2-following loop, 3-unidirectional conduction loop, 4-timing loop, control chip M0, external power supply capacitor C0, DC power supply terminal VDD, ground terminal GND, capacitor C, diode D, control chip M, operational amplifier O, discharge load R1, current limiting resistor R2. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032]

Power-off timing circuit

[0033] Figure 2 It is a schematic diagram of a power-off timing circuit provided in an embodiment of the present invention.

[0034] like Figure 2 As shown, in an embodiment of the present invention, a power-off timing circuit 1 of a control chip M is provided, and the power supply end of the control chip M is connected to the power supply signal PG, and the power supply signal PG of the external AC power supply flows therefrom; wherein, the control chip M can be a microprocessor chip, a single-chip control chip, a dedicated integrated chip, or other chips or integrated circuits of various types and functions, and is not limited here.

[0035] First, the power-off timing circuit 1 of the control chip M includes: a timing circuit 4, the timing circuit 4 includes a capacitor C, the positive end of the capacitor C is connected to the output terminal I / O of the control chip M, and the negative end is grounded, the capacitor C can receive a control signal from the output terminal I / O of the control chip M, and charge / discharge according to the control signal; a discharge load R1 is connected in parallel with the capacitor C, and forms a capacitor discharge loop with the capacitor C.

[0036] Preferably, in the embodiment of the present invention, the capacitance of the capacitor C in the capacitor discharge circuit is nF level, wherein nF level refers to the capacitance of 1-999nF, and the capacitance of the capacitor C is only one thousandth of the capacitance of the external power supply capacitor C0 required to provide electrical energy for the entire control chip in the prior art, which greatly reduces the capacitance. At the same time, as the requirements for the capacitance of the capacitor C are reduced, a smaller capacitor C can also be used, which can reduce the volume of the power-off timing circuit 1, so that the overall power-off timing circuit 1 is miniaturized and compact. Similarly, the resistance value of the discharge load R1 also needs to be selected in accordance with the capacitance of the capacitor C to avoid the capacitor C discharging too fast or too slow, so that the capacitor C can maintain a stable discharge for a period of time, so that the amount of electricity in the capacitor C can gradually decrease over time, forming a stable change curve.

[0037] In the embodiment of the present invention, the timing circuit 4 composed of the capacitor C and the resistor R1 has the advantages of simple structure, small size and low cost. However, in the practical application of the present invention, the timing circuit 4 can also be composed of circuits or components other than the RC discharge circuit, such as a small chip or component with a discharge timing function, or a timing circuit 4 composed of other energy storage components and a discharge load, etc., which is not limited here.

[0038] Secondly, the power-off timing circuit 1 also includes a follower loop 2, one end of which is connected to the positive terminal of the capacitor C, and the other end of the follower loop 2 is connected to the input terminal ADC of the control chip M. The follower loop 2 plays a role in transmitting and isolating the voltage signal. It can transmit the voltage value of the positive terminal of the capacitor C to the input terminal ADC of the control chip M, while isolating the capacitor discharge loop from the input terminal ADC of the control chip M, so that the load when the capacitor C is discharged is only the discharge load R1 connected in parallel with it, so as to ensure the accuracy of calculating the discharge time according to the voltage value of the positive terminal of the capacitor C, that is, the discharge load R1.

[0039] Preferably, in the embodiment of the present invention, the follower loop 2 is composed of an operational amplifier O, the in-phase input terminal of the operational amplifier O is connected to the positive terminal of the capacitor C, the inverting input terminal and the output terminal of the operational amplifier O are connected to the input terminal of the control chip M, and the operational amplifier O connected with the inverting input terminal and the output terminal forms a voltage follower loop, while keeping the output terminal voltage of the operational amplifier O consistent with the input terminal voltage, the high input impedance and low output impedance characteristics of the operational amplifier O itself are used to isolate its in-phase input terminal and output terminal. In addition, the operational amplifier O itself has a simple structure and a small size, which is conducive to the miniaturization and low-cost design of the overall power-off timing circuit 1.

[0040] It is worth mentioning that, in the practical application of the present invention, the following loop 2 can also be composed of other components and circuits such as a voltage follower that can achieve voltage isolation and following, which is not limited here.

[0041] Finally, the power-off timing circuit 1 further includes a unidirectional conduction loop 3 , the conduction end of which is connected to the output end I / O of the control chip M, and the cut-off end of which is connected to the positive terminal of the capacitor C.

[0042] By setting the above-mentioned unidirectional conduction loop 3, the control signal of the output terminal I / O of the control chip M can be effectively transmitted to the capacitor C, while ensuring that the current of the capacitor C will not flow back into the output terminal I / O of the control chip M when it is discharged.

[0043] Preferably, in the embodiment of the present invention, the unidirectional conduction loop 3 in the power-off timing circuit 1 includes a diode D, the anode of the diode D is connected to the output terminal I / O of the control chip M, and the cathode of the diode D is connected to the positive terminal of the capacitor C. The diode itself has the advantages of small size and low cost, which is conducive to the miniaturization and low-cost design of the overall power-off timing circuit 1.

[0044] It is worth mentioning that in the practical application of the present invention, the unidirectional conduction loop 3 can also be composed of other elements and circuits such as relays that can achieve unidirectional conduction of signals, and there is no limitation here.

[0045] The power-off timing circuit 1 of the control chip M has a simple structure, and only requires a small-capacity capacitor C and an adapted discharge load R1 to form a small-capacity capacitor discharge circuit, so as to realize the external power-off timing circuit 1 of the control chip M, and can conveniently and accurately measure the power-off time of the control chip M. At the same time, a capacitor C with smaller capacitance and volume can be used as an energy storage element to reduce the volume and production cost of the power-off timing circuit 1 of the overall control chip M.

[0046] In an embodiment of the present invention, an electrical device is also provided, and the electrical device is equipped with the above-mentioned power-off timing circuit 1. The electrical device can calculate the power-off time through the power-off timing circuit 1, and then can use the power-off time as a control signal to perform different adjustment control actions according to different power-off times. Among them, the electrical device can be any type of electrical device such as an LED lighting device, and is not limited here.

[0047]

Power off timing method

[0048] Figure 3 It is a flow chart of a power-off timing method provided in an embodiment of the present invention.

[0049] like Figure 3 As shown, in an embodiment of the present invention, the control chip M in the power-off timing circuit 1 can execute a power-off timing method, and the power-off timing method includes: a discharging step S1, after the control chip M detects that the power signal PG at the power end is disconnected, the output end I / O of the control chip M sends a discharging signal, and the capacitor C discharges; a detection step S2, after the control chip M detects that the power signal PG at the power end is restored, the input end ADC of the control chip M detects the input signal; a power-off time determination step S3, determining the power-off time of the power end of the control chip M according to the input signal and a preset power-off timing curve.

[0050] Preferably, in an embodiment of the present invention, the power-off timing method of the power-off timing circuit 1 further includes: a charging restoration step S4, after the detection step S2 is completed, the output end of the control chip M outputs an I / O charging signal, and the capacitor C is charged until it is fully charged.

[0051] Figure 4 It is a schematic diagram of a voltage waveform when a power-off timing circuit provided in an embodiment of the present invention executes a power-off timing method.

[0052] refer to Figure 4 , when time T is 0, the control chip M works normally, and the AC voltage U of the external AC power supply AC The control chip M detects the state of the power supply signal PG at the power supply end to obtain the monitoring signal U PG is high level; at this time, the voltage value U of the DC power supply terminal VDD of the control chip M VDD is 5V, and the control signal U of the output I / O of the control chip M I / O The voltage at the positive terminal of capacitor C, i.e., the voltage at both ends of discharge load R1, is 5V. After synchronous transmission by following loop 2, the input signal U of the ADC at the input end of control chip M is ADC Equal to the voltage value U across the discharge load R1 R1 Equal to 5V.

[0053] At time T=t0, the external AC power supply of the control chip M is cut off, and the AC voltage U AC becomes 0, the control chip M detects the signal U PG is low level; at this time, i.e., at time t0, the voltage value U of the DC power supply terminal VDD of the control chip M VDD The voltage starts to decrease gradually from 5V to 0V, and the control signal U at the output I / O of the control chip M is I / O becomes low level (0V), and the capacitor C receives the control signal U I / O Entering the discharge state, the positive terminal of capacitor C discharges to the discharge load R1. The charge of capacitor C decreases over time, causing the voltage value across the positive terminal of capacitor C, i.e., the discharge load R1, to decrease over time, i.e., the voltage value across the discharge load R1 is U R1 Start from 5V and decrease;

[0054] At time T=t1, the power signal PG of the external AC power supply of the control chip M is restored, and the AC voltage U AC The normal AC waveform is changed back, and the control chip M detects the state of the power supply signal PG at the power supply end to obtain the monitoring signal U PG changes back to high level; at this time, the voltage value U of the DC power supply terminal VDD of the control chip M VDD When the voltage is restored to 5V, the follower loop 2 also resumes working state. Through the synchronous transmission of the follower loop 2, the input signal U of the ADC at the input end of the control chip M is ADC Equal to the voltage value U across the discharge load R1 R1 The value at time t1, that is, the input terminal ADC of the control chip M immediately reads the current input signal U ADC is 0.2V; then, the control signal U at the output I / O of the control chip M I / O Changes back to high level (5V), capacitor C receives the control signal U I / O At the beginning of the charging state, after the capacitor C is fully charged, the input signal U of the ADC at the input terminal of the control chip M ADC That is, the voltage value U across the discharge load R1 R1 Also restored to 5V.

[0055] According to the preset power-off timing curve, i.e. the pre-stored measured relationship between the power-off time and the voltage, the input signal U read by the input terminal ADC of the control chip M at the time t1 when the external AC power supply of the control chip M is restored ADC The value of can be used to calculate the power recovery time t1, and the power failure time of the control chip M can be obtained as t1-t0.

[0056] In the embodiment of the present invention, the power-off time of the control chip M is the discharge time of the capacitor C, and the discharge time of the capacitor C is directly related to the capacitance of the capacitor C in the discharge circuit and the resistance value of the discharge load R1. The larger the capacitance of the capacitor C, the longer the discharge time that the capacitor C can maintain; the larger the resistance value of the discharge load R1, the slower the discharge speed of the capacitor C.

[0057] Specifically, it has been proved through experiments that the voltage value U across the discharge load R1 is R1 When the voltage drops from 5V to 1V, the corresponding discharge time when the capacitance of capacitor C is 100nF, 220nF and 470nF respectively and the resistance value of discharge load R1 is 3.3MΩ, 5.1MΩ and 6.8MΩ respectively is shown in the following table:

[0058]

[0059] Experiments have shown that the voltage value U across the discharge load R1 R1 When the voltage drops from 5V to 0.5V, the corresponding discharge time when the capacitance of capacitor C is 100nF, 220nF and 470nF respectively and the resistance value of discharge load R1 is 3.3MΩ, 5.1MΩ and 6.8MΩ respectively is shown in the following table:

[0060]

[0061] It is worth mentioning that in the practical application of the present invention, the capacitance of the capacitor C in the discharge circuit and the resistance value of the discharge load R1 can be adjusted and designed according to factors such as the specifications of the control chip and the timing time requirements, and are not limited here.

[0062] According to the above power-off timing method, when the power signal PG connected to the control chip M is disconnected, the control chip M outputs a control signal to the capacitor C through the output terminal I / O, and the capacitor C and the parallel discharge load R1 form a discharge circuit, the capacitor C starts to discharge, and the charge of the capacitor C gradually decreases as the discharge proceeds, so that the voltage value across the discharge load R1 also gradually decreases as the discharge proceeds; when the power signal PG connected to the control chip M is restored, the control chip M immediately detects the ADC voltage signal at the input terminal of the control chip M, and makes the ADC input signal U ADC Equal to the voltage value U across the discharge load R1 R1 , the discharge time, i.e., the power-off time of the control chip M, can be calculated according to the relationship between the voltage signal and time.

[0063] [Method for generating power-off timing curve]

[0064] Figure 5 It is a flow chart of a method for generating a power-off timing curve provided in an embodiment of the present invention.

[0065] like Figure 5 As shown, in an embodiment of the present invention, the control chip M in the power-off timing circuit 1 can also execute a method for generating a power-off timing curve, and the method for generating a power-off timing curve includes: a discharging step S1, in which the output terminal I / O of the control chip M sends a discharge signal, and the capacitor C discharges; a detection step S2, in which while the capacitor C is discharging in the discharging step S1, the control chip M times, and the input terminal ADC of the control chip M detects the input signal at a preset time interval; a curve generating step S3, in which a power-off timing curve of the capacitor C is generated and stored according to the input signal and the timing time of the control chip M.

[0066] Figure 6 It is a schematic diagram of a voltage waveform when a power-off timing circuit provided in an embodiment of the present invention executes a method for generating a power-off timing curve.

[0067] refer to Figure 6 When the power-off timing circuit 1 executes the method for generating the power-off timing curve, the control chip M is always in a normal power supply state, that is, the AC voltage U of the external AC power supply is AC The control chip M detects the state of the power supply signal PG at the power supply end to obtain the monitoring signal U PG And the voltage value U of the DC power supply terminal VDD of the control chip M VDD It is also always high (5V).

[0068] At time T=0, the control signal U at the output terminal I / O of the control chip M I / O The voltage across the positive terminal of capacitor C, i.e., the discharge load R1, is U R1 is 5V, and after synchronous transmission by following loop 2, the input signal U of the ADC at the input terminal of the control chip M is ADC Also 5V.

[0069] At time T=t0, the control signal U at the output terminal I / O of the control chip M is I / O becomes low level (0V), and the capacitor C receives the control signal U I / O Entering the discharge state, the positive terminal of capacitor C discharges to the discharge load R1. The charge of capacitor C decreases over time, making the voltage at the positive terminal of capacitor C equal to the voltage value U across the discharge load R1. R1 Decreases over time; at the same time, the input ADC of the control chip M continuously measures and inputs the signal U according to the preset time interval ADC , after synchronous transmission by following loop 2, the input signal U of the ADC at the input end of the control chip M ADC Equal to the voltage value U across the discharge load R1 R1, the control chip M according to the timing time and the corresponding input signal U ADC The input signal U can be obtained ADC The curve of the change with time is the power-off timing curve of capacitor C.

[0070] At time T=t1, the capacitor C is exhausted, and the control signal U at the output terminal I / O of the control chip M is I / O Changes back to high level (5V), capacitor C receives the control signal U I / O Start charging. After the capacitor C is fully charged, the input signal U of the ADC at the input terminal of the control chip M is ADC That is, the voltage value U across the discharge load R1 R1 Also restored to 5V.

[0071] The above-mentioned power-off timing curve generation method can draw, correct and store the voltage value U across the discharge load R1 by simulating the power-off situation and combining the timing circuit of the control chip M itself when the control chip M is normally powered. R1 The actual relationship curve between the discharge time and the discharge time. Thus, the measurement and component errors of the control chip M and the power-off timing circuit 1 can be eliminated, and the calculation accuracy of the power-off time can be improved.

[0072] So far, the technical solution of the present invention has been described in conjunction with the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to the above-mentioned specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A power-off timing circuit for a control chip, wherein the power supply terminal of the control chip is connected to a power supply signal, characterized in that: The power-off timing circuit comprises: A follower loop, wherein the output end of the follower loop is connected to the input end of the control chip; A unidirectional conduction loop, wherein the conduction end of the unidirectional conduction loop is connected to the output end of the control chip, and the cut-off end of the unidirectional conduction loop is connected to the input end of the follower loop; A timing loop is connected between the cutoff end of the unidirectional conducting loop and the input end of the following loop.

2. The power-off timing circuit according to claim 1, characterized in that: The timing circuit includes A capacitor, one end of which is connected between the cutoff end of the unidirectional conduction loop and the input end of the follower loop; A discharge load is connected in parallel with the capacitor.

3. The power-off timing circuit according to claim 2, characterized in that: The capacitance of the capacitor is nF level.

4. The power-off timing circuit according to claim 1, characterized in that: The follower loop includes an operational amplifier, a non-inverting input terminal of the operational amplifier is connected to a cutoff terminal of the unidirectional conduction loop, and an inverting input terminal and an output terminal of the operational amplifier are respectively connected to the input terminal of the control chip.

5. The power-off timing circuit according to claim 1, characterized in that: It also includes a current limiting resistor connected between the input end of the timing loop and the following loop.

6. The power-off timing circuit according to claim 1, characterized in that: The unidirectional conduction loop includes a diode, the anode of the diode is connected to the output end of the control chip, and the cathode of the diode is connected to the input end of the follower loop.

7. The power-off timing circuit according to any one of claims 1 to 6, characterized in that: The control chip can execute a power-off timing method, and the power-off timing method includes: a discharge step, wherein after the control chip detects that the power signal at the power end is disconnected, the output end of the control chip sends a discharge signal, and the timing circuit performs discharge; A detection step, after the control chip detects that the power signal at the power supply end is restored, the input end of the control chip detects an input signal; A power-off time determining step is to determine the power-off time of the power supply end of the control chip according to the input signal and a preset power-off timing curve.

8. The power-off timing circuit according to claim 7, characterized in that: The power-off timing method further comprises: Charging and restoring step: after the detection step is completed, the output end of the control chip outputs a charging signal, and the timing circuit is charged until the power is fully charged.

9. The power-off timing circuit according to any one of claims 1 to 6, characterized in that: The control chip can execute a method for generating a power-off timing curve, and the method for generating a power-off timing curve includes: A discharge step, wherein the output end of the control chip sends a discharge signal, and the timing circuit performs discharge; a detection step, in which the control chip counts while the timing circuit is discharging in the discharge step, and the input end of the control chip detects input signals at preset time intervals; The curve generating step generates and stores a power-off timing curve according to the input signal and the timing time of the control chip.

10. An electrical device, characterized in that: The electrical device is equipped with a power-off timing circuit as described in any one of claims 1-9.

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