Instruction processing device, system and method

Abstract

In the embodiment of the present application, an instruction processing device, system and method are provided, and the device includes: an instruction fetch module, a decoding module and an execution module, wherein the instruction fetch module is used to obtain original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data; the decoding module is used to read the target instruction data from the instruction fetch module, perform full decoding processing on the target instruction data, and obtain instruction information; the execution module is used to obtain instruction information from the decoding module, determine the existence result of the data dependency relationship according to the operand information, and determine the execution unit in the execution module according to the instruction type, the existence result and the operand information, and perform operation processing in the execution unit to obtain the execution result. The device can allocate more execution resources for performance-critical instructions, disperse them to various pipeline stages, reduce cavitation, and distribute complex instructions to different pipeline stages, thereby improving the work efficiency of the processor.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular, to an instruction processing device, system and method. Background Art

[0002] With the continuous development of computer equipment, the central processing unit (CPU) is the computing and control core of a computer device. Its main function is to complete the execution of computer instructions and the processing of data. In the process of increasing computing complexity, the performance of the CPU is becoming more and more important. Among them, the essence of the computer program running on the computer device is the execution process of instructions. In order to improve the working efficiency and performance of the CPU in the computer device, the research on how to process computer instructions is particularly important.

[0003] At present, the related technology adopts the classic five-stage pipeline processor architecture, such as a microprocessor (Microprocessor without interlocked pipelined stages, MIPS), in which each pipeline stage in the architecture includes five instruction processing stages, namely, instruction fetch (IF), decode (ID), execute (EX), memory storage (MEM), and write back (WB), and each pipeline stage is used to process different tasks in the execution process of an instruction. However, the processing tasks of the single-stage pipeline in this scheme are heavy, resulting in excessive resource consumption, and the generated electrical signals require a longer path for transmission, thereby limiting the operating frequency of the processor and affecting the performance of the processor. In addition, critical tasks and complex tasks may preempt the execution unit, resulting in resource contention and cavitation, resulting in low processing efficiency of the processor. Summary of the invention

[0004] The embodiments of the present application provide an instruction processing device, system and method.

[0005] According to a first aspect of an embodiment of the present application, there is provided an instruction processing device, including:

[0006] An instruction fetch module, the instruction fetch module is used to obtain original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data;

[0007] A decoding module, the decoding module is connected to the instruction fetch module, and is used to read the target instruction data from the instruction fetch module, perform full decoding processing on the target instruction data, and obtain instruction information; the instruction information includes instruction type and operand information;

[0008] An execution module, the execution module is connected to the decoding module, and is used to obtain the instruction information from the decoding module, determine the existence result of the data dependency relationship according to the operand information, and determine the execution unit in the execution module according to the instruction type, the existence result and the operand information, perform corresponding operation processing in the execution unit to obtain an execution result, each of the execution units corresponds to a pipeline stage.

[0009] In an optional embodiment of the present application, the execution module includes: a first execution unit, a second execution unit and a third execution unit; the second execution unit is connected to the first execution unit and the third execution unit; the execution result includes a first execution result and a second execution result;

[0010] The first execution unit is used to: when the instruction type is a performance-critical instruction and there is a result representation that there is no data dependency, perform operation processing on the performance-critical instruction according to operand information to obtain a first execution result, and when the instruction type is a memory access instruction, calculate the memory address of the memory access instruction according to the operand information; the performance-critical instruction includes at least one of the following: a general computing instruction and a jump instruction;

[0011] The second execution unit is used to: perform a data loading or storing operation according to the memory address;

[0012] The third execution unit is used to: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, perform operation processing on the performance-critical instruction; and when the instruction type is a non-performance-critical instruction, perform corresponding processing according to operand information to obtain a second execution result.

[0013] In an optional embodiment of the present application, the first execution result includes a first operation result and a first prediction result; the first execution unit includes: a first arithmetic logic unit, a first branch prediction unit and an address generation unit;

[0014] The first arithmetic logic unit is used to: when the instruction type of the target instruction data is a performance-critical instruction and there is a result indicating that there is no data dependency, perform operation processing on the performance-critical instruction without data dependency according to the operand information to obtain the first operation result;

[0015] The first branch prediction unit is used to: when the instruction type of the target instruction data is a performance-critical instruction and there is a result representation that there is no data dependency, perform branch prediction processing on the performance-critical instruction without data dependency according to the operand information to obtain the first prediction result;

[0016] The address generating unit is used for: when the instruction type of the target instruction data is a memory access instruction, calculating a memory address for the memory access instruction according to operand information of the memory access instruction.

[0017] In an optional embodiment of the present application, the second execution unit includes: an address access unit; the address access unit is connected to the address generation unit;

[0018] The address access unit is used to perform a data loading operation or a data storage operation according to the memory address and operand information corresponding to the memory access instruction.

[0019] In an optional embodiment of the present application, the second execution result includes: a second operation result and a second prediction result; the third execution unit includes: a second arithmetic logic unit and a second branch prediction unit;

[0020] The second arithmetic logic unit is used to: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, perform a logic operation on the performance-critical instruction without data dependency according to the operand information to obtain the second operation result;

[0021] The second branch prediction unit is used to: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, perform branch prediction processing on the performance-critical instruction without data dependency according to the operand information to obtain the second prediction result.

[0022] In an optional embodiment of the present application, the second execution result includes: a control result, a multiplication result, and a division result; the third execution unit also includes: a control and status register, a multiplication unit, and a division unit;

[0023] The control and status register is used to: perform reading and writing of the control and status register according to the operand information to obtain the control result;

[0024] The multiplication unit is used to: perform multiplication processing according to the operand information to obtain the multiplication result;

[0025] The division unit is used to perform division processing according to the operand information to obtain the division result.

[0026] In an optional embodiment of the present application, the instruction fetch module includes: an instruction fetch unit and a preprocessing unit, wherein the instruction fetch unit is connected to the preprocessing unit;

[0027] The instruction fetch unit is used to: perform length segmentation processing on the original instruction data to obtain complete instruction data, and send the complete instruction data to the preprocessing unit;

[0028] The pre-processing unit is used to: perform pre-decoding processing on the complete instruction data to obtain the target instruction data.

[0029] A second aspect of the embodiments of the present application provides an instruction processing system, including the instruction processing device provided in the above embodiments.

[0030] A third aspect of the embodiments of the present application provides an instruction processing method, the method comprising:

[0031] Acquire original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data;

[0032] Fully decoding the target instruction data to obtain instruction information; the instruction information includes instruction type and operand information;

[0033] Determine the existence result of the data dependency relationship according to the operand information, and determine the execution unit in the execution module according to the instruction type, the existence result and the operand information, perform corresponding operation processing in the execution unit to obtain the execution result; each of the execution units corresponds to a pipeline stage.

[0034] The instruction processing device in the embodiment of the present application includes an instruction fetch module, a decoding module and an execution module. The instruction fetch module is used to obtain original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data. The decoding module is used to read the target instruction data from the instruction fetch module, and perform full decoding processing on the target instruction data to obtain instruction information, which includes instruction type and operand information; the execution module is used to obtain instruction information from the decoding module, determine the existence result of the data dependency relationship according to the operand information, and determine the execution unit in the execution module according to the instruction type, existence result and operand information, and perform corresponding operation processing in the execution unit to obtain an execution result. Compared with the prior art, the instruction processing device of the present application, on the one hand, obtains target instruction data by length-slicing and pre-decoding the original instruction data, and fully decodes the target instruction data through a decoding module, thereby providing data guidance information for subsequent execution modules to perform calculations; on the other hand, according to the instruction type and the existence of data dependencies, more execution resources are allocated to performance-critical instructions, which are dispersed to the pipeline levels corresponding to each execution unit, reducing the cavitation phenomenon caused by data dependencies, and allowing these instructions to be distributedly executed in the pipeline levels, reducing the jams caused by data dependencies, and maximizing the utilization of resources, thereby improving the overall performance of the processor, and distributing complex instruction tasks to different pipeline levels, avoiding overload of a single stage, reducing the load of each stage, and further improving the processing efficiency of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0036] Figure 1 A structural diagram of a classic five-stage pipeline in the prior art provided for one embodiment of the present application;

[0037] Figure 2 A schematic diagram of the structure of an instruction processing device provided by one embodiment of the present application;

[0038] Figure 3 A schematic diagram of the structure of an instruction processing device provided by one embodiment of the present application;

[0039] Figure 4 A flowchart of an instruction processing method provided by an embodiment of the present application;

[0040] Figure 5 A schematic diagram of the structure of an instruction processing device provided for one embodiment of the present application.

[0041] Description of reference numerals:

[0042] Instruction fetch module-10; instruction fetch unit-11; preprocessing unit-12; decoding module-20; execution module-30; first execution unit-31; second execution unit-32; third execution unit-33; first arithmetic logic unit-311; first branch prediction unit-312; address generation unit-313; address access unit-321; second arithmetic logic unit-331; second branch prediction unit-332; control and status register-333; multiplication unit-334; division unit-335. DETAILED DESCRIPTION

[0043] In the process of implementing the present application, the inventors discovered that the current single-stage pipeline processing tasks are heavy, resulting in excessive resource consumption, limiting the operating frequency of the processor, affecting the performance of the processor, and there may be critical tasks and complex tasks preempting the execution unit, resulting in resource contention and cavitation, resulting in low processing efficiency of the processor.

[0044] Understandably, see Figure 1 As shown, the processor CPU of the related technology adopts pipeline technology, such as the classic five-stage pipeline. Each stage of the pipeline includes five instruction processing units, IF, ID, EX, MEM and WB. Among them, the IF unit is responsible for reading instructions from the memory, the ID unit is responsible for decoding and decoding instructions, that is, identifying the instruction type, the EX unit is responsible for executing the instruction and obtaining the operation result, the MEM unit is used for memory access operations, which can be reading data from the internal or external memory, or writing the instruction result into the memory, and the WB unit is used to write the result of the instruction execution into the register stack of the processor for quick access next time.

[0045] Among them, for the processor architecture, different pipelines can be divided into different pipelines according to different pipeline classifications. For different processors, the number of pipeline stages used is limited, and each stage requires a large number of combinational logic circuits to perform operations, especially for the EX pipeline stage. When encountering complex instructions or performance-critical instructions, the single-stage pipeline will face a large computational burden, resulting in a single-stage pipeline processing task that is too heavy. This excessive task volume will cause the signal path in the processor to become longer, increase the delay, thereby limiting the operating frequency that the processor can achieve, and thus affecting the overall performance. In addition, in the classic pipeline design, all operations rely on a shared execution unit to complete. If a time-consuming instruction is currently being processed, other instructions waiting to be executed have to wait in line. In this case, even simple operations that can be completed quickly will be delayed because there are more complex operations in front. This waiting caused by resource competition is called "correlation", which will cause "bubbles" in the pipeline, that is, time periods in which no effective work occurs during the pipeline cycle. These bubbles waste the time window that could have been used to execute other instructions, thereby reducing processor efficiency.

[0046] In response to the above problems, the embodiments of the present application provide instruction processing devices, systems and methods. Compared with the prior art, the instruction processing device of the present application, on the one hand, obtains target instruction data by length segmentation and pre-decoding of the original instruction data, and fully decodes the target instruction data through a decoding module, thereby providing data guidance information for subsequent execution modules to perform calculations; on the other hand, according to the instruction type and the existence of data dependencies, more execution resources are allocated to performance-critical instructions, which are dispersed to the pipeline levels corresponding to each execution unit, reducing the cavitation phenomenon caused by data dependencies, and allowing these instructions to be distributedly executed in the pipeline levels, reducing the jams caused by data dependencies, and maximizing the utilization of resources, thereby improving the overall performance of the processor, and distributing complex instruction tasks to different pipeline levels, avoiding overload of a single stage, reducing the load of each stage, and further improving the processing efficiency of the processor.

[0047] The solutions in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java, interpreted scripting language JavaScript, HDL hardware description languages ​​such as Verilog and System Verilog, etc.

[0048] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0049] See also Figure 2 , Figure 2 The structural diagram of the instruction processing device provided in the embodiment of the present application includes an instruction fetch module 10, a decoding module 20 and an execution module 30. The instruction fetch module 10 is used to obtain original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data; the decoding module 20 is connected to the instruction fetch module 10, and is used to read the target instruction data from the instruction fetch module 10, and perform full decoding processing on the target instruction data to obtain instruction information; the instruction information includes instruction type and operand information; the execution module 30 is connected to the decoding module 20, and is used to obtain instruction information from the decoding module 20, determine the existence result of the data dependency relationship according to the operand information, and determine the execution unit in the execution module 30 according to the instruction type, the existence result and the operand information, and perform corresponding operation processing in the execution unit to obtain the execution result, and each execution unit corresponds to a pipeline stage.

[0050] It should be noted that the above-mentioned original instruction data is the instruction data that needs to be processed. The original instruction data can be the original instruction stream that has not been split and processed, for example, it can be a whole instruction data stream, which includes multiple instruction data. The multiple instruction data can be instruction data of different instruction types or instruction data of the same instruction type.

[0051] Optionally, in the process of acquiring multiple original instruction data, they may be acquired from a memory or other memory units.

[0052] After acquiring the original instruction data, the instruction fetching module 10 can perform length segmentation processing on the original instruction data, specifically, firstly obtain the length information of the original instruction data according to the preset instruction format, and then perform length segmentation processing on the original instruction data according to the length information of the original instruction data to obtain complete instruction data. The preset instruction format is obtained by sorting out the actual instruction data, and can be customized according to actual needs.

[0053] After obtaining the complete instruction data, the complete instruction data can be pre-decoded to extract key features and obtain target instruction data, which are used to provide information for the prediction of branch jump instructions. Among them, branch jump instructions can include conditional branch instructions and unconditional branch instructions. For example, the opcode part of the instruction that may represent a branch jump, or the field related to the jump address calculation is identified. Based on these key features, it is predicted whether the branch is executed and the possible jump target address. Among them, the target instruction data refers to the instruction data after the original instruction data is fully decoded. The above target instruction data is complete instruction data.

[0054] In this embodiment, pre-decoding of complete instruction data is performed to help improve the instruction pipeline efficiency of the processor and reduce pipeline pauses caused by branch prediction errors.

[0055] The decoding module 20 is connected to the instruction fetch module 10. After the decoding module 20 obtains the original instruction data from the instruction fetch module 10, it can perform a comprehensive decoding process on the target instruction data to obtain instruction information. Optionally, the above-mentioned full decoding process may include at least one of the following operations: opcode parsing, register file reading, immediate number processing, dependency detection, exception detection, etc. Among them, opcode analysis can be to perform opcode parsing on the target instruction data to determine the instruction type; register file reading can be to read the corresponding source operand from the register file according to the register number in the target instruction data; when the instruction contains an immediate number, the immediate number processing can be performed, specifically to expand or adjust it to meet the required operation format; dependency detection can be to detect whether the current instruction needs to wait for the result of the previous instruction, that is, whether there is a data dependency. If there is a data dependency, it may be necessary to set a data forwarding path or delay the execution of the instruction; exception detection specifically checks whether the instruction is legal, whether there is an illegal operation or other situations that may cause an exception, etc. In addition, for some complex instructions, it is also necessary to parse out special fields of the instruction, such as the mode bit of the instruction, the privilege level-related bit, etc.

[0056] In this embodiment, by setting a decoding module, instructions can be parsed quickly and accurately, which helps to reduce delays in the pipeline and improve the overall performance of the processor.

[0057] The execution module 30 is connected to the decoding module 20, and the execution module 30 may include a multi-level pipeline, and each level of the pipeline includes an execution unit. After full decoding processing, each target instruction data can correspond to an instruction type and operand information. The instruction type may include, for example, performance-critical instructions, memory access instructions, and non-performance-critical instructions. Performance-critical instructions may include: operation instructions, jump instructions or memory access instructions, storage instructions, etc. The number of the target instruction data may be three, four, or any other number.

[0058] After obtaining the instruction type and operand information from the decoding module, the execution module 30 determines whether there is a data dependency for each target instruction data according to the operand information, and obtains an existence result, which may include whether the target instruction data has a data dependency or not. The performance-critical instruction may include two execution points during the execution process, each execution point corresponds to an execution unit, and different execution points have different conditions to be satisfied when executing operations, for example, the first execution point and the second execution point may be included.

[0059] It can be understood that data dependency refers to the situation in which the result of one instruction is used by another subsequent instruction during the execution of the program. This dependency will affect the execution order of instructions and the scheduling of the pipeline.

[0060] When the instruction type of the target instruction data is a performance-critical instruction, and when there is a result representation that there is a data dependency, the target instruction data is executed in the first execution point of the execution module 30; when the performance-critical indicator is not executed in the first execution point and there is a result representation that there is a data dependency, the target instruction data is executed in the second execution point of the execution module 30.

[0061] For memory access instructions, two execution points may be included, each execution point corresponds to an execution unit. For example, the memory access instruction may be executed at the first execution point first and then at the second execution point, thereby distributing complex instructions to different pipelines, so that the amount of tasks undertaken by each pipeline is more balanced, thereby improving the work efficiency of the processor.

[0062] In the process of performing operation processing on the target instruction data at each execution point, different instruction types may be included, and corresponding operations may be performed to obtain an execution result. After obtaining the execution result, the execution result may be written back to a physical register so as to facilitate subsequent calling of the execution result for data processing.

[0063] The instruction processing device in the embodiment of the present application includes an instruction fetch module, a decoding module and an execution module. The instruction fetch module is used to obtain original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data. The decoding module is used to read the target instruction data from the instruction fetch module, and perform full decoding processing on the target instruction data to obtain instruction information, which includes instruction type and operand information; the execution module is used to obtain instruction information from the decoding module, determine the existence result of the data dependency relationship according to the operand information, and determine the execution unit in the execution module according to the instruction type, existence result and operand information, and perform corresponding operation processing in the execution unit to obtain an execution result. Compared with the prior art, the instruction processing device of the present application, on the one hand, obtains target instruction data by length-slicing and pre-decoding the original instruction data, and fully decodes the target instruction data through a decoding module, thereby providing data guidance information for subsequent execution modules to perform calculations; on the other hand, according to the instruction type and the existence of data dependencies, more execution resources are allocated to performance-critical instructions, which are dispersed to the pipeline levels corresponding to each execution unit, reducing the cavitation phenomenon caused by data dependencies, and allowing these instructions to be distributedly executed in the pipeline levels, reducing the jams caused by data dependencies, and maximizing the utilization of resources, thereby improving the overall performance of the processor, and distributing complex instruction tasks to different pipeline levels, avoiding overload of a single stage, reducing the load of each stage, and further improving the processing efficiency of the processor.

[0064] In an optional embodiment of the present application, please continue to refer to Figure 2 As shown, the execution module 30 includes: a first execution unit 31, a second execution unit 32 and a third execution unit 33; the second execution unit 32 is connected to the first execution unit 31 and the third execution unit 33; and the execution result includes a first execution result and a second execution result.

[0065] The first execution unit 31 is used to: when the instruction type is a performance-critical instruction and there is a result representation that there is no data dependency, perform operation processing on the performance-critical instruction according to the operand information to obtain a first execution result, and when the instruction type is a memory access instruction, calculate the memory address of the memory access instruction according to the operand information; the performance-critical instruction includes at least one of the following: a general computing instruction, a jump instruction;

[0066] The second execution unit 32 is used to: perform data loading or storage operations according to the memory address;

[0067] The third execution unit 33 is used to: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, perform operation processing on the performance-critical instruction, and when the instruction type is a non-performance-critical instruction, perform corresponding processing according to the operand information to obtain a second execution result.

[0068] It should be noted that the above-mentioned performance-critical instructions are general instructions, which may include general computing instructions and jump instructions. The first execution unit is the first execution point of the performance-critical instructions, and the third execution unit is the second execution point of the performance-critical instructions. After obtaining the instruction type and operand information of the target instruction data, it can be determined whether the instruction type is a performance-critical instruction. When it is a performance-critical instruction, it can be determined whether there is a data dependency relationship. It can be determined whether there is a data dependency relationship based on the operand information and preset rules. When there is a data dependency relationship, it represents that the execution condition of the first execution point of the performance-critical instruction is met, and the target instruction data is processed in the first execution unit to obtain a first execution result. When there is a data dependency relationship for the performance-critical instruction, it represents that the execution condition of the first execution point of the performance-critical instruction is not met, and it needs to be executed at the second execution point, and then it is determined whether there is a data dependency relationship. When there is a data dependency relationship, it represents that the execution condition of the second execution point of the performance-critical instruction is met, and the target instruction data is processed in the third execution unit to obtain a second execution result.

[0069] For example, the instruction fetch module is the IF module, the decoding module is the DE module, the first execution unit is EX0, the second execution unit is EX1, and the third execution unit is EX2. After the target instruction data is transmitted to the DE module through the IF module, the target instruction data is fully decoded in the DE module to obtain instruction information, such as determining the current instruction type and determining its operand source, which may include data forwarding or reading register files; if data forwarding is required, each data forwarding source will be detected in the subsequent pipeline stage. When the target instruction data is a performance-critical instruction and there is no data dependency, the performance-critical instruction can be directly executed at the EX0 pipeline stage; if there is a data dependency, it is necessary to continue to the next pipeline level EX2. If the performance-critical instruction is not executed at the EX0 pipeline stage and there is no data dependency, it can be directly executed in the EX2 unit.

[0070] In this embodiment, since the performance-critical instruction has two execution opportunities, when the first execution point obtains execution resources but the instruction itself has data dependencies, the pipeline will not be stuck, but the execution resources will be immediately released and the next pipeline stage will be continued, that is, the second execution point will be entered. The pipeline will be stuck only if the data dependency of the instruction itself is still not resolved when the execution resources are obtained for the second time. Therefore, in this architecture, the pipeline jams caused by data dependencies are greatly reduced. Compared with the jams caused by data dependencies and resource dependencies in the classic pipeline, the jams in this architecture are significantly reduced, and the processor execution efficiency is higher.

[0071] When the instruction type is a memory access instruction, it is sliced ​​reasonably and dispersed to different pipeline stages. When the instruction type is a memory access instruction, the memory address of the memory access instruction is calculated according to the operand information in the first execution unit EX0, and the data loading or storage operation is performed according to the memory address in the second execution unit EX1, so that the amount of tasks undertaken by each pipeline stage is relatively balanced. Compared with the existing classic pipeline stage where the MEM type operation instructions are only in one pipeline stage, it avoids concentrating all tasks in the MEM unit and can increase the operating frequency of the processor.

[0072] It is understood that memory access instructions are a type of instructions used in the processor to interact with the memory, and in some cases are considered to be time-consuming operations. They allow programs to read or load data from the memory or write or store data to the memory. Memory access instructions are one of the basic operations in the execution of computer programs. Optionally, memory access instructions include:

[0073] The Load instruction reads data from the memory and stores it in the register; the Store instruction writes the data in the register to the memory.

[0074] The above-mentioned non-performance-critical instructions may include: multi-cycle instructions and system control instructions ebreak / ecall / fence, etc. For non-performance-critical instructions, corresponding processing may be performed in the third execution unit EX2 to obtain a second execution result.

[0075] In this embodiment, more execution resources are allocated to performance-critical instructions, allowing these instructions to be executed in a distributed manner in the pipeline, reducing the jams caused by data dependencies, thereby improving the overall performance of the processor, and cutting complex memory access instructions into multiple parts, so that fragmented instruction tasks are evenly distributed in different pipeline levels. Compared with the classic architecture that concentrates all execution logic in one pipeline level, the logic circuits between each level of this solution are simpler, and therefore the operating frequency is higher.

[0076] In an optional embodiment of the present application, please continue to refer to Figure 3As shown, the first execution result includes a first operation result and a first prediction result, and the first execution unit 31 includes: a first arithmetic logic unit 311 , a first branch prediction unit 312 and an address generation unit 313 .

[0077] The first arithmetic logic unit 311 is used for: when the instruction type of the target instruction data is a performance-critical instruction and there is a result representation that there is no data dependency, performing operation processing on the performance-critical instruction without data dependency according to the operand information to obtain a first operation result; the first branch prediction unit 312 is used for: when the instruction type of the target instruction data is a performance-critical instruction and there is a result representation that there is no data dependency, performing branch prediction processing on the performance-critical instruction without data dependency according to the operand information to obtain a first prediction result; the address generation unit 313 is used for: when the instruction type of the target instruction data is a memory access instruction, for the memory access instruction, calculating the memory address according to the operand information of the memory access instruction.

[0078] It should be noted that the first arithmetic logic unit (ALU) is ALU1, which is mainly used to perform basic arithmetic and logic operations, such as addition, subtraction, and, or, and negation. When a logic operation needs to be performed, if the instruction type of the target instruction data is a performance-critical instruction and there is no data dependency, the target instruction data without data dependency is operated according to the operand information to obtain a first operation result.

[0079] The first branch prediction unit (Branch Jump Predictor, BJP) is BJP1, which is responsible for predicting the results of branch instructions (such as conditional jumps, unconditional jumps, etc.) during program execution to reduce the delay caused by branches. It can help determine the execution path of the program in advance. When branch prediction needs to be performed, if the instruction type of the target instruction data is a performance-critical instruction and there is no data dependency, branch prediction processing is performed on the target instruction data without data dependency according to the operand information, thereby obtaining a first prediction result.

[0080] The address generation unit (AGU) may be AGU1, which is used to calculate the actual address of the memory access instruction and process complex addressing modes. When the instruction type of the target instruction data is a memory access instruction, the memory address is calculated according to the operand information of the memory access instruction.

[0081] In this embodiment, by setting up the first arithmetic logic unit and the first branch prediction unit, the pipeline efficiency can be improved and the performance loss caused by branches can be reduced. By setting up the address generation unit, some complex tasks can be shared at the pipeline level, the memory access speed can be accelerated, and the execution efficiency of data loading and storage instructions can be improved.

[0082] In an optional embodiment of the present application, please continue to refer to Figure 3 As shown, the second execution unit 32 includes: an address access unit 321; the address access unit 321 is connected to the address generation unit 313; the address access unit 321 is used to: perform a data loading operation or a data storage operation according to the memory address and the operand information corresponding to the memory access instruction.

[0083] It is understandable that the circuit frequency will be affected by single-cycle execution in the prior art, so complex tasks are fragmented and processed separately, that is, memory access instructions are executed in stages and executed in different pipeline stages, which can reduce the task burden of the single-stage pipeline.

[0084] The address access unit can be understood as AGU2. When the instruction type is a memory access instruction and the actual memory address is calculated in the address generation unit in the first execution unit, a data loading operation or a data storage operation can be performed in the address access unit according to the memory address and the operand information corresponding to the memory access instruction. When the memory access instruction is a data loading instruction, a data loading operation is performed in the address access unit according to the memory address; when the memory access instruction is a data storage instruction, a data storage operation is performed in the address access unit according to the memory address.

[0085] In this embodiment, by processing memory access instructions in stages, the task burden of a single-stage pipeline is reduced, which helps to better utilize pipeline resources and reduce jams caused by complex tasks, thereby improving the work efficiency and overall performance of the processor.

[0086] In an optional embodiment of the present application, see Figure 3 As shown, the second execution result includes: a second operation result and a second prediction result; the third execution unit 33 includes: a second arithmetic logic unit 331 and a second branch prediction unit 332.

[0087] The second arithmetic logic unit is used for: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, performing logical operation processing on the performance-critical instruction without data dependency according to the operand information to obtain a second operation result; the second branch prediction unit is used for: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, performing branch prediction processing on the performance-critical instruction without data dependency according to the operand information to obtain a second prediction result.

[0088] It should be noted that, taking the second arithmetic logic unit as ALU2 and the second branch prediction unit as BJP2 as an example, when the performance-critical instruction is not executed in the first execution unit and there is no data dependency, when the performance-critical instruction is a logical arithmetic instruction, logical operations are performed on the performance-critical instruction for which there is no data dependency according to the operand information to obtain a second operation result.

[0089] When the performance-critical instruction is not executed in the first execution unit and no data dependency exists, when the performance-critical instruction is a branch prediction instruction, branch prediction processing is performed on the performance-critical instruction without data dependency according to the operand information to obtain a second prediction result.

[0090] In this embodiment, two execution opportunities (EX0 and EX2) are provided for critical instructions. If data dependency is encountered during the first execution, these instructions will not block the pipeline, but continue to flow downward until the second execution point (EX2) satisfies the conditions and is executed, thereby reducing the cavitation phenomenon caused by data dependency, facilitating effective instruction execution, and improving instruction processing efficiency.

[0091] In an optional embodiment of the present application, the second execution result includes: a control result, a multiplication result and a division result; the third execution unit 33 also includes: a control and status register 333, a multiplication unit 334, and a division unit 335.

[0092] The control and status register 333 is used to read and write the control and status register according to the operand information to obtain the control result; the multiplication unit is used to perform multiplication processing according to the operand information to obtain the multiplication result; the division unit is used to perform division processing according to the operand information to obtain the division result.

[0093] It should be noted that the Control and Status Registers (CSR) are used to store processor status information and control signals, which may include, for example, interrupt enable control signals, exception handling address control signals, etc. Status information may include: processor operating status, configuration information, etc.

[0094] Among them, the above-mentioned control and status registers may include a program counter, a condition code register, an interrupt enable register, an exception program counter, an exception cause register, a privileged mode register, a performance monitoring register, a debug register, a system control register, etc. Different registers correspond to different functions.

[0095] The multiplier unit (MUL) is used to perform a multiplication operation according to operand information to obtain a multiplication result when the instruction type is a non-performance-critical instruction.

[0096] The above-mentioned divider unit (DIV) is used to perform a division operation according to operand information to obtain a division result when the instruction type is a non-performance-critical instruction.

[0097] In this embodiment, by setting control and status registers, the internal state of the processor can be managed and controlled to implement complex control logic, and by setting multiplication units and division units, non-performance-critical instructions can be executed quickly, reducing data jams and reducing hardware resource consumption while achieving performance improvements.

[0098] In one of the embodiments, the present application also provides a specific implementation of the structure of the instruction fetch module. The instruction fetch module 10 includes: an instruction fetch unit 11 and a preprocessing unit 12. The instruction fetch unit 11 and the preprocessing unit 12 are connected.

[0099] The instruction fetch unit 11 is used to perform length segmentation processing on the original instruction data to obtain complete instruction data and send it to the preprocessing unit; the preprocessing unit 12 is used to perform pre-decoding processing on the complete instruction data to obtain target instruction data.

[0100] Specifically, after obtaining the original instruction data, the instruction fetch unit 11 can perform length segmentation processing on the original instruction data. First, the length information of the original instruction data is obtained according to a preset instruction format, and then the original instruction data is segmented according to the length information of the original instruction data to obtain complete instruction data.

[0101] After obtaining the complete instruction data, the preprocessing unit 12 can perform pre-decoding processing on the complete instruction data, extract key features, and obtain target instruction data, which are used to provide information for the prediction of branch jump instructions. Among them, branch jump instructions can include conditional branch instructions and unconditional branch instructions. For example, the opcode part of the instruction that may represent a branch jump, or the field related to the jump address calculation is identified. Based on these key features, it is predicted whether the branch is executed and the possible jump target address. Among them, the target instruction data refers to the instruction data after the original instruction data is fully decoded. The above-mentioned target instruction data is complete instruction data.

[0102] In the embodiment of the present application, by setting up an instruction fetch unit, the original instruction data can be length-sliced ​​into complete instruction data, and a complete instruction can be provided to the subsequent pipeline stage for processing, which helps to improve the efficiency of the pipeline and reduce the delay caused by waiting for complete instructions. By setting up a preprocessing unit, the instruction acquisition and processing speed is improved, the cavitation phenomenon in the pipeline is reduced, and the control flow processing is optimized through early branch prediction, which can better support the needs of high-performance computing while maintaining low power consumption and a small chip area.

[0103] On the other hand, the present application embodiment also provides an instruction processing method, see Figure 4 As shown, the instruction processing method includes the following steps 201 to 203:

[0104] Step 201: Acquire original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data.

[0105] Step 202: Fully decode the target instruction data to obtain instruction information; the instruction information includes instruction type and operand information.

[0106] Step 203, determine the existence result of the data dependency relationship according to the operand information, and determine the execution unit in the execution module according to the instruction type, the existence result and the operand information, perform the corresponding operation processing in the execution unit, and obtain the execution result; each execution unit corresponds to a pipeline stage.

[0107] The execution module includes: a first execution unit, a second execution unit and a third execution unit; the second execution unit is connected to the first execution unit and the third execution unit; and the execution result includes a first execution result and a second execution result.

[0108] Determine the existence result of data dependency according to operand information, and determine the execution unit in the execution module according to the instruction type, the existence result and the operand information, perform corresponding operation processing in the execution unit to obtain the execution result, including: when the instruction type is a performance-critical instruction and the existence result indicates that there is no data dependency, perform operation processing on the performance-critical instruction according to the operand information in the first execution unit to obtain the first execution result, and when the instruction type is a memory access instruction, calculate the memory address of the memory access instruction according to the operand information in the first execution unit; the performance-critical instruction includes at least one of the following: a general computing instruction, a jump instruction; in the second execution unit, perform data loading or storage operations according to the memory address; when the performance-critical instruction is not executed in the first execution unit and the existence result indicates that there is no data dependency, perform operation processing on the performance-critical instruction in the third execution unit, and when the instruction type is a non-performance-critical instruction, perform corresponding processing in the third execution unit according to the operand information to obtain the second execution result.

[0109] Specifically, see Figure 5 The processor includes an instruction fetch module (IF), a decoding module (DE) and an execution module (EX). The instruction fetch module (IFU) includes a six-stage pipeline. The first-stage pipeline step includes a first instruction fetch unit (IF1), and the second-stage pipeline step includes a second instruction fetch unit (IF2). The original instruction data is obtained through the IF1 unit, and the original instruction data is length-segmented to obtain complete instruction data, and sent to the IF2 unit. The complete instruction data is pre-decoded through the IF2 unit to obtain target instruction data, and the target instruction data is sent to the decoding module.

[0110] The third-level pipeline step includes a decoding module (DE), in which the target instruction data is fully decoded to obtain the instruction type and operand information, and transmitted to the execution module (EX). The execution module (EX) includes three pipelines, namely the fourth-level pipeline, the fifth-level pipeline and the sixth-level pipeline. The fourth-level pipeline includes the first execution unit (EX0), the fifth-level pipeline includes the second execution unit (EX1), and the sixth-level pipeline includes the third execution unit (EX2).

[0111] The above-mentioned EX0 unit may include a first arithmetic logic unit (ALU1), a first branch and prediction unit (BJP1), and an address generation unit (AGU1). The EX1 unit may include an address access unit (AGU2). The EX2 unit may include a second arithmetic logic unit (ALU2), a second branch and prediction unit (BJP2), a control and status register (CSR), a multiplication unit (MUL), and a division unit (DIV). When the instruction type is a performance-critical instruction, it is determined whether the target instruction data has a data dependency relationship. When there is no data dependency relationship and a logical operation is required, the ALU1 in the EX0 unit performs an operation process to obtain a first operation result; when there is no data dependency relationship and a branch prediction operation is required, the BJP1 in the EX0 unit performs a branch prediction process to obtain a first prediction result. When the instruction type is a memory access instruction, the memory address is calculated in the AGU1 in the EX0 unit, and then the data load or store operation is performed in the AGU2 unit according to the memory address.

[0112] If the performance-critical instruction is not executed in EX0 and there is no data dependency, when a logical operation is required, the operation processing can be performed in ALU2 in the EX2 unit to obtain the second operation result; if the performance-critical indicator is not executed in EX0 and there is no data dependency, when branch prediction processing is required, branch prediction processing can be performed in BJP2 in the EX2 unit to obtain the second prediction result. For non-performance-critical instructions, control processing can be performed by the CSR unit to obtain a control result, and multiplication processing can be performed by the MUL unit to obtain a multiplication result, and division processing can be performed by the DIV unit to obtain a division result.

[0113] Compared with the prior art, the instruction processing method in this embodiment obtains target instruction data by length segmentation and pre-decoding of the original instruction data, and fully decodes the target instruction data through a decoding module, thereby providing data guidance information for subsequent execution modules to perform calculations. On the other hand, according to the instruction type and the existence of data dependencies, more execution resources are allocated to performance-critical instructions and dispersed to the pipeline levels corresponding to each execution unit, thereby reducing the cavitation phenomenon caused by data dependencies, and allowing these instructions to be executed in a distributed manner in the pipeline levels, thereby reducing the jams caused by data dependencies, maximizing the utilization of resources, and improving the overall performance of the processor. Complex instruction tasks are distributed across different pipeline levels, thereby avoiding overload of a single stage, reducing the load of each stage, and further improving the processing efficiency of the processor.

[0114] On the other hand, an embodiment of the present application further provides a processing system, which includes the instruction processing device provided by the above embodiment.

[0115] Compared with the prior art, the processing system of the present application obtains target instruction data by length segmentation and pre-decoding of original instruction data, and fully decodes the target instruction data through a decoding module, thereby providing data guidance information for subsequent execution modules to perform calculations; on the other hand, according to the instruction type and the existence of data dependencies, more execution resources are allocated to performance-critical instructions, which are dispersed to the pipeline levels corresponding to each execution unit, reducing the cavitation phenomenon caused by data dependencies, and allowing these instructions to be executed in a distributed manner in the pipeline levels, reducing the jams caused by data dependencies, and maximizing the utilization of resources, thereby improving the overall performance of the processor, and distributing complex instruction tasks to different pipeline levels, avoiding overload of a single stage, reducing the load of each stage, and further improving the processing efficiency of the processor.

[0116] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0117] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0118] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0119] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0120] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0121] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0122] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An instruction processing device, characterized in that: The equipment includes: An instruction fetch module, the instruction fetch module is used to obtain original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data; A decoding module, the decoding module is connected to the instruction fetch module, and is used to read the target instruction data from the instruction fetch module, perform full decoding processing on the target instruction data, and obtain instruction information; the instruction information includes instruction type and operand information; An execution module, the execution module is connected to the decoding module, and is used to obtain the instruction information from the decoding module, determine the existence result of the data dependency relationship according to the operand information, and determine the execution unit in the execution module according to the instruction type, the existence result and the operand information, and perform corresponding operation processing in the execution unit to obtain an execution result, each of the execution units corresponds to a pipeline stage; wherein the execution module includes: a first execution unit, a second execution unit and a third execution unit; the second execution unit is connected to the first execution unit and the third execution unit; the execution result includes a first execution result and a second execution result; The first execution unit is used to: when the instruction type is a performance-critical instruction and there is a result representation that there is no data dependency, perform operation processing on the performance-critical instruction according to operand information to obtain a first execution result, and when the instruction type is a memory access instruction, calculate the memory address of the memory access instruction according to the operand information; the performance-critical instruction includes at least one of the following: a general computing instruction and a jump instruction; The second execution unit is used to: perform a data loading or storing operation according to the memory address; The third execution unit is used to: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, perform operation processing on the performance-critical instruction; and when the instruction type is a non-performance-critical instruction, perform corresponding processing according to operand information to obtain a second execution result.

2. The device according to claim 1, characterized in that The first execution result includes a first operation result and a first prediction result; the first execution unit includes: a first arithmetic logic unit, a first branch prediction unit and an address generation unit; The first arithmetic logic unit is used to: when the instruction type of the target instruction data is a performance-critical instruction and there is a result indicating that there is no data dependency, perform operation processing on the performance-critical instruction without data dependency according to the operand information to obtain the first operation result; The first branch prediction unit is used to: when the instruction type of the target instruction data is a performance-critical instruction and there is a result representation that there is no data dependency, perform branch prediction processing on the performance-critical instruction without data dependency according to the operand information to obtain the first prediction result; The address generating unit is used for: when the instruction type of the target instruction data is a memory access instruction, calculating a memory address for the memory access instruction according to operand information of the memory access instruction.

3. The device according to claim 2, characterized in that The second execution unit includes: an address access unit; the address access unit is connected to the address generation unit; The address access unit is used to perform a data loading operation or a data storage operation according to the memory address and operand information corresponding to the memory access instruction.

4. The device according to claim 1, characterized in that The second execution result includes: a second operation result and a second prediction result; the third execution unit includes: a second arithmetic logic unit and a second branch prediction unit; The second arithmetic logic unit is used to: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, perform a logic operation on the performance-critical instruction without data dependency according to the operand information to obtain the second operation result; The second branch prediction unit is used to: when the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, perform branch prediction processing on the performance-critical instruction without data dependency according to the operand information to obtain the second prediction result.

5. The device according to claim 4, characterized in that The second execution result includes: a control result, a multiplication result and a division result; the third execution unit also includes: a control and status register, a multiplication unit, and a division unit; The control and status register is used to: perform reading and writing of the control and status register according to the operand information to obtain the control result; The multiplication unit is used to: perform multiplication processing according to the operand information to obtain the multiplication result; The division unit is used to perform division processing according to the operand information to obtain the division result.

6. The device according to claim 1, characterized in that The instruction fetch module comprises: an instruction fetch unit and a preprocessing unit, wherein the instruction fetch unit is connected to the preprocessing unit; The instruction fetch unit is used to: perform length segmentation processing on the original instruction data to obtain complete instruction data, and send the complete instruction data to the preprocessing unit; The pre-processing unit is used to: perform pre-decoding processing on the complete instruction data to obtain the target instruction data.

7. A processing system, characterized in that: The processing system comprises: an instruction processing device as described in any one of claims 1-6.

8. A command processing method, characterized in that: Applied to the instruction processing device according to any one of claims 1 to 6, the method comprises: Acquire original instruction data, and perform length segmentation and pre-decoding processing on the original instruction data to obtain target instruction data; Fully decoding the target instruction data to obtain instruction information; the instruction information includes instruction type and operand information; Determining the existence result of the data dependency relationship according to the operand information, and determining the execution unit in the execution module according to the instruction type, the existence result and the operand information, performing corresponding operation processing in the execution unit to obtain the execution result; each of the execution units corresponds to a pipeline stage; wherein the execution module includes a first execution unit, a second execution unit and a third execution unit, and the execution result includes a first execution result and a second execution result; determining the existence result of the data dependency relationship according to the operand information, and determining the execution unit in the execution module according to the instruction type, the existence result and the operand information, performing corresponding operation processing in the execution unit to obtain the execution result, including: When the instruction type is a performance-critical instruction and there is a result representation that there is no data dependency, the first execution unit performs a calculation on the performance-critical instruction according to the operand information to obtain a first execution result, and when the instruction type is a memory access instruction, the first execution unit calculates the memory address of the memory access instruction according to the operand information; the performance-critical instruction includes at least one of the following: a general computing instruction, a jump instruction; In the second execution unit, a data loading or storing operation is performed according to the memory address; When the performance-critical instruction is not executed in the first execution unit and there is a result indicating that there is no data dependency, the performance-critical instruction is operated in the third execution unit, and when the instruction type is a non-performance-critical instruction, corresponding processing is performed in the third execution unit according to operand information to obtain a second execution result.

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