A storage access optimization system for parallel computing

Abstract

The present application relates to the field of GPU parallel processing technology, and in particular to a storage access optimization system for parallel computing. The system includes: a GPU, a processor, and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: according to a number of instruction streams corresponding to a parallel computing module, a target instruction sequence for accessing an internal memory is determined; according to an access address corresponding to the target instruction, the target instruction is added to an access sequence of a storage subunit corresponding to the access address, and an access sequence corresponding to each storage subunit is obtained, and then storage access is performed on each storage subunit, thereby realizing parallel access to the internal memory. Compared with the serial access form of the internal memory in the prior art, the access efficiency of the internal memory in the GPU parallel computing scenario is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of GPU parallel processing, and in particular to a storage access optimization system for parallel computing. Background Art

[0002] Since GPU has more Arithmetic And Logic Unit (ALU) for data processing, it is suitable for parallel processing of dense data and is good at large-scale concurrent computing.

[0003] In order to improve parallel efficiency, the instruction streams corresponding to multiple programs can be handed over to a parallel computing module containing several threads for processing. A parallel computing module corresponds to an internal memory. When the amount of data is large, it is usually necessary to move the data from the external memory to the internal memory first, and then different threads move part of the data from the internal memory to their respective private memories in the form of instructions for use.

[0004] However, the internal memory actually receives instruction access requests in serial form, so the internal memory can only perform one read or write operation at a time, and the subsequent instruction needs to wait until the operation corresponding to the previous instruction is completed before it can be executed, resulting in low access efficiency of the internal memory in the GPU parallel computing scenario. Therefore, how to improve the access efficiency of the internal memory in the GPU parallel computing scenario has become an urgent problem to be solved. Summary of the invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is:

[0006] A storage access optimization system for parallel computing, the system comprising: a GPU, a processor and a memory storing a computer program, wherein the GPU comprises a parallel computing module set A={a1, a2, ..., a m , …, a M}, a m is the mth parallel computing module in A, where m is an integer in the range [1, M], and M is the number of parallel computing modules contained in A. m Includes internal memory m , e m It includes N storage subunits {e m 1, e m 2, …, e m n ,…,e m N},e m nThe nth storage subunit contained in the internal memory in the mth parallel computing module, different storage subunits correspond to different access addresses, and when the computer program is executed by the processor, the following steps are implemented:

[0007] S101, according to a m The corresponding instruction streams determine the access e m The target instruction sequence includes K target instructions, and the target instruction is to access e m instruction, K is a positive integer.

[0008] S102, for any target instruction, according to the access address corresponding to the target instruction, add the target instruction to the access sequence of the storage subunit corresponding to the access address, traverse all target instructions, and obtain the access sequences corresponding to N storage subunits respectively.

[0009] S103 , performing storage access on the N storage sub-units according to the access sequences respectively corresponding to the N storage sub-units.

[0010] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, a storage access optimization system for parallel computing provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0011] The present invention provides a storage access optimization system for parallel computing, the system comprising: a GPU, a processor and a memory storing a computer program, wherein the GPU comprises a parallel computing module set A={a1, a2, ..., a m , …, a M}, a m is the mth parallel computing module in A, where m is an integer in the range [1, M], and M is the number of parallel computing modules contained in A. m Includes internal memory m , e m It includes N storage subunits {e m 1, e m 2, …, e m n ,…,e m N},e m n is the nth storage subunit contained in the internal memory of the mth parallel computing module, and different storage subunits have different access addresses. When the computer program is executed by the processor, the following steps are implemented: according to a m The corresponding instruction streams determine the access e mThe target instruction sequence includes K target instructions, and the target instruction is to access e m Instruction, K is a positive integer. For any target instruction, according to the access address corresponding to the target instruction, the target instruction is added to the access sequence of the storage subunit corresponding to the access address, all target instructions are traversed to obtain the access sequences corresponding to N storage subunits respectively, and according to the access sequences corresponding to the N storage subunits respectively, storage access is performed on the N storage subunits.

[0012] It can be seen that a target instruction sequence for accessing the internal memory is determined from several instruction streams corresponding to the parallel computing module, and an access sequence corresponding to each storage sub-unit is formed according to the access address of the target instruction, thereby realizing parallel access to the internal memory. Compared with the serial access form of the internal memory in the prior art, the access efficiency of the internal memory in the GPU parallel computing scenario is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flowchart of a computer program executed by a processor in a storage access optimization system for parallel computing provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] This embodiment provides a storage access optimization system for parallel computing, the system comprising: a GPU, a processor and a memory storing a computer program, wherein the GPU comprises a parallel computing module set A={a1, a2, ..., a m , …, a M}, a m is the mth parallel computing module in A, where m is an integer in the range [1, M], and M is the number of parallel computing modules contained in A. m Includes internal memory m , e mIt includes N storage subunits {e m 1, e m 2, …, e m n ,…,e m N},e m n is the nth storage subunit contained in the internal memory of the mth parallel computing module. Different storage subunits have different access addresses. Figure 1 , is a flow chart of a computer program executed by a processor in a storage access optimization system for parallel computing provided by an embodiment of the present invention. When the computer program is executed by the processor, the following steps are implemented:

[0017] S101, according to a m The corresponding instruction streams determine the access e m The target instruction sequence includes K target instructions, and the target instruction is to access e m Instruction, K is a positive integer;

[0018] S102, for any target instruction, according to the access address corresponding to the target instruction, add the target instruction to the access sequence of the storage subunit corresponding to the access address, traverse all target instructions, and obtain the access sequences corresponding to N storage subunits respectively;

[0019] S103 , performing storage access on the N storage sub-units according to the access sequences respectively corresponding to the N storage sub-units.

[0020] Among them, the above system also includes external memory. When the amount of data required for calculation is large, such as large-size matrix calculation, it is necessary to move the data from the external memory to the internal memory, and then different threads move the data from the internal memory to the corresponding registers for use. The external memory can refer to SDRAM, DDR and other memories, and the internal memory can also be generally referred to as local memory.

[0021] An instruction stream corresponds to a thread. The parallel computing module supports parallel processing of multiple threads. The instruction stream can include computing instructions, data read instructions, data write instructions, etc., and the data read instructions and data write instructions can access different storage devices, such as accessing internal memory, accessing private memory corresponding to the thread, etc.

[0022] It should be noted that a target instruction may include multiple access addresses. Correspondingly, an access sequence may include multiple identical target instructions. For example, the access addresses corresponding to target instruction x1 include address 0, address 1, and address 0, and the access addresses corresponding to target instruction x2 include address 0, address 1, and address 2. For the storage subunit corresponding to address 0, the access sequence is x1, x1, x2; for the storage subunit corresponding to address 1, the access sequence is x0, x1; and for the storage subunit corresponding to address 2, the access sequence is x2.

[0023] Specifically, this embodiment parallelizes the computing module a m Corresponding internal memory m It is divided into N storage sub-units, and the access addresses corresponding to different storage sub-units are different, so that parallel access can be performed according to the storage sub-units. For example, if there are multiple target instructions for accessing different storage sub-units, multiple target instructions can be executed simultaneously to improve the access efficiency of the internal memory.

[0024] In a specific embodiment, the m The corresponding instruction streams determine the access e m The target instruction sequence includes:

[0025] According to the instruction corresponding to the access e m The access order is from a m Determine the first K accesses e from the corresponding several instruction streams m The instructions are respectively used as the target instructions;

[0026] According to the access orders respectively corresponding to all target instructions, the target instruction sequence is formed by all target instruction sequences.

[0027] Among them, the instruction pair e m There is a sequence of accesses, so the first K accesses can be determined according to the access sequence. m The instructions are respectively used as target instructions. In this embodiment, K can be set to 4, and the implementer can adjust the value of K according to actual needs.

[0028] In a specific implementation, the internal memory corresponds to a single port, and the target instruction corresponds to a read instruction or a write instruction.

[0029] Among them, the internal memory corresponds to a single port, which means that the internal memory can only support one of the read operation and the write operation at the same time. In this embodiment, the internal memory is divided into N storage sub-units, and it can be considered that each storage sub-unit can only support one of the read operation and the write operation at the same time. The read instruction corresponds to the read operation of the internal memory, and the write instruction corresponds to the write operation of the internal memory.

[0030] In a specific implementation, step S103 also includes the following steps:

[0031] S1031, when there are i consecutive read instructions in the access sequence corresponding to any storage sub-unit, the i consecutive read instructions are merged into a single read operation on the storage sub-unit, where i is an integer greater than 1.

[0032] Among them, when there are i consecutive read instructions in the access sequence corresponding to a storage subunit, it means that i consecutive read instructions need to read the same data, so a single read operation can be performed on the storage subunit, and the result of the single read operation is provided to the i consecutive read instructions.

[0033] In a specific implementation, step S103 also includes the following steps:

[0034] S1032: When there is a write instruction and a read instruction consecutively in the access sequence corresponding to any storage sub-unit and the write instruction is in front, the write instruction is used as a write operation to the storage sub-unit, and the content of the write instruction is sent to the read instruction.

[0035] Among them, when there is a write instruction and a read instruction consecutively in the access sequence corresponding to a storage sub-unit and the write instruction comes first, the content to be read by the read instruction is the content to be written by the write instruction. Therefore, the write operation on the storage sub-unit is normally retained without the need to perform a read operation on the storage sub-unit. It is only necessary to send the content of the write instruction to the read instruction.

[0036] In a specific implementation, the internal memory corresponds to a dual port, the dual port is used to support the internal memory to perform a read operation and a write operation in parallel, and the target instruction corresponds to a read instruction and a write instruction;

[0037] When the computer program is executed by a processor, after step S101 and before step S102, the following steps are further included:

[0038] S104, forming a first instruction sequence according to all target instructions belonging to the read instruction;

[0039] S105, forming a second instruction sequence according to all target instructions belonging to the write instruction;

[0040] Accordingly, step S102 includes the following steps:

[0041] S1021, for any target instruction in the first instruction sequence, according to the access address corresponding to the target instruction, add the target instruction to the first access sequence of the storage subunit corresponding to the access address, traverse all the target instructions in the first instruction sequence, and obtain the first access sequences corresponding to the N storage subunits respectively;

[0042] S1022, for any target instruction in the second instruction sequence, according to the access address corresponding to the target instruction, add the target instruction to the second access sequence of the storage subunit corresponding to the access address, traverse all target instructions in the second instruction sequence, and obtain second access sequences corresponding to N storage subunits respectively;

[0043] Accordingly, step S103 includes:

[0044] The N storage sub-units are accessed for storage according to the first access sequence and the second access sequence respectively corresponding to the N storage sub-units.

[0045] When the internal memory corresponds to a dual port, it indicates that the internal memory supports read-write parallel operations. Therefore, in this embodiment, on the basis of read-write parallel operations, the storage sub-units perform parallel processing on the read operation and the write operation respectively.

[0046] In a specific embodiment, the a m Corresponding to Q threads, Q is an integer greater than one.

[0047] Wherein, Q is an integer greater than one, that is, the parallel computing module corresponds to at least two threads.

[0048] In a specific implementation, N satisfies the following conditions:

[0049] Q / N=P, N is an integer greater than 1, and P is a positive integer.

[0050] Among them, P is the ratio of Q to N. It can be seen that the maximum value of N is Q and the minimum value is 2. The implementer can adjust the value of N according to the actual situation and only needs to ensure that N meets the above conditions.

[0051] In this embodiment, a target instruction sequence for accessing the internal memory is determined from several instruction streams corresponding to the parallel computing module, and an access sequence corresponding to each storage sub-unit is formed according to the access address of the target instruction, thereby realizing parallel access to the internal memory. Compared with the serial access form of the internal memory in the prior art, the access efficiency of the internal memory in the GPU parallel computing scenario is effectively improved.

[0052] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A storage access optimization system for parallel computing, characterized in that: The system comprises: a GPU, a processor and a memory storing a computer program, wherein the GPU comprises a parallel computing module set A={a1, a2, ..., a m , …, a M }, a m is the mth parallel computing module in A, where m is an integer in the range [1, M], and M is the number of parallel computing modules contained in A. m Includes internal memory m , e m It includes N storage subunits {e m 1, e m 2, …, e m n ,…,e m N },e m n The nth storage subunit contained in the internal memory in the mth parallel computing module, different storage subunits correspond to different access addresses, and when the computer program is executed by the processor, the following steps are implemented: S101, according to a m The corresponding instruction streams determine the access e m The target instruction sequence includes K target instructions, and the target instruction is to access e m Instruction, K is a positive integer; S102, for any target instruction, according to the access address corresponding to the target instruction, add the target instruction to the access sequence of the storage subunit corresponding to the access address, traverse all target instructions, and obtain the access sequences corresponding to N storage subunits respectively; S103, performing storage access on the N storage sub-units according to the access sequences respectively corresponding to the N storage sub-units; Wherein, when the internal memory corresponds to a single port, the target instruction corresponds to a read instruction or a write instruction; Accordingly, step S103 also includes the following steps: S1031, when there are i consecutive read instructions in the access sequence corresponding to any storage subunit, the i consecutive read instructions are merged into a single read operation on the storage subunit, where i is an integer greater than 1; S1032: When there is a write instruction and a read instruction consecutively in the access sequence corresponding to any storage sub-unit and the write instruction is in front, the write instruction is used as a write operation to the storage sub-unit, and the content of the write instruction is sent to the read instruction.

2. The storage access optimization system for parallel computing according to claim 1, characterized in that: According to a m The corresponding instruction streams determine the access e m The target instruction sequence includes: According to the instruction corresponding to the access e m The access order is from a m Determine the first K accesses e from the corresponding several instruction streams m The instructions are respectively used as the target instructions; The target instruction sequence is formed by all target instruction sequences according to the access orders respectively corresponding to all target instructions.

3. The storage access optimization system for parallel computing according to claim 1, characterized in that: When the internal memory corresponds to a dual port, the dual port is used to support the internal memory to perform a read operation and a write operation in parallel, and the target instruction corresponds to a read instruction and a write instruction; Accordingly, when the computer program is executed by a processor, after step S101 and before step S102, the following steps are further included: S104, forming a first instruction sequence according to all target instructions belonging to the read instruction; S105, forming a second instruction sequence according to all target instructions belonging to the write instruction; Accordingly, step S102 includes the following steps: S1021, for any target instruction in the first instruction sequence, according to the access address corresponding to the target instruction, add the target instruction to the first access sequence of the storage subunit corresponding to the access address, traverse all the target instructions in the first instruction sequence, and obtain the first access sequences corresponding to the N storage subunits respectively; S1022, for any target instruction in the second instruction sequence, according to the access address corresponding to the target instruction, add the target instruction to the second access sequence of the storage subunit corresponding to the access address, traverse all target instructions in the second instruction sequence, and obtain second access sequences corresponding to N storage subunits respectively; Accordingly, step S103 includes: The N storage sub-units are accessed for storage according to the first access sequence and the second access sequence respectively corresponding to the N storage sub-units.

4. The storage access optimization system for parallel computing according to claim 1, characterized in that: The a m Corresponding to Q threads, Q is an integer greater than 1.

5. The storage access optimization system for parallel computing according to claim 4, characterized in that: N satisfies the following conditions: Q / N=P, N is an integer greater than 1, and P is a positive integer.

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