Multi-core multi-rate scheduling method and device, storage medium and electronic equipment

Abstract

The invention provides a multi-core multi-rate scheduling method and device, a storage medium and electronic equipment, and is applied to the technical field of computer simulation. Based on a code visualization model reference and parallel execution architecture, a code visualization model is configured through hardware and an operating system configuration file, so that the code visualization model can generate a multi-core multi-rate code suitable for underlying software, and then the code is added to underlying scheduling to generate a final executable file. Therefore, multi-core and multi-rate scheduling in the aspects of cross-core interaction and multi-rate system interaction is realized, and the operation efficiency of the whole platform system is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of computer simulation technology, and in particular to a multi-core multi-rate scheduling method, device, storage medium and electronic equipment. Background Art

[0002] In the development of modern embedded systems, Model-Based Design (MBD) has become a mainstream method. MBD can replace the traditional code writing method by building a control system design process based on mathematical models, such as using tools such as Matlab / Simulink. Multicore technology refers to the integration of two or more complete computing engines (cores) in a processor, which makes the system easier to expand and can provide more powerful processing performance with lower power consumption and less heat. Multirate technology refers to multiple subsystems in a system running at different rates to process signals with different sampling rates.

[0003] Currently, the existing technology mainly adds multiple subsystems to a model, sets it as an atomic system, fills in the corresponding scheduling function name and generated file name and other information, and uses it as a template. After the code is generated, the scheduling of each subsystem is added to the multi-core scheduling of the underlying operating system. This method uses each atomic system as a scheduling unit, that is, each underlying scheduling function only contains the logic within the atomic system. Therefore, this method does not support functions such as cross-core interaction and multi-rate system interaction, because the relevant logic involved in the interaction is usually in the step function of the top-level model, and this function does not belong to any subsystem, so the interaction function between subsystems cannot be completed.

[0004] Therefore, how to achieve multi-core multi-rate scheduling in supporting cross-core interaction and multi-rate system interaction has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] In view of the above problems, the present invention provides a multi-core multi-rate scheduling method, device, storage medium and electronic device that overcome the above problems or at least partially solve the above problems. The technical solution is as follows:

[0006] A multi-core multi-rate scheduling method, comprising:

[0007] Generate a multi-core multi-rate configuration file based on a central processing unit and an operating system of a target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and multi-rate scheduling information supported by the operating system;

[0008] Modify the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain the configured code visualization model;

[0009] Reference at least two pre-built function control models in the configured code visualization model, and respectively set different function control models on different cores of the central processing unit;

[0010] Performing model simulation and code generation on the code visualization model to obtain multi-core multi-rate code;

[0011] Adding the model scheduling interface in the multi-core multi-rate code to the scheduling interface provided by the operating system to obtain the integration code of the multi-core multi-rate code and the operating system;

[0012] The integrated code is compiled and linked to obtain a multi-core multi-rate scheduling executable file.

[0013] Optionally, modifying the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain the configured code visualization model includes:

[0014] Create a new blank code visualization model;

[0015] Modifying model configuration and code generation options of the code visualization model;

[0016] The code visualization model is configured with multiple cores and multiple tasks by using the number of cores and the multi-rate scheduling information to obtain the configured code visualization model.

[0017] Optionally, the modifying of the model configuration and code generation options of the code visualization model includes:

[0018] The code visualization model sets the solver type to fixed step size, allows tasks to be executed concurrently on the target platform, automatically handles rate conversion of data transmission, and sets the code generation system target file to an embedded coder.

[0019] Optionally, performing multi-core multi-task configuration on the code visualization model by using the number of cores and the multi-rate scheduling information to obtain the configured code visualization model includes:

[0020] According to the number of cores, configuring the number of cores of the computing core of the code visualization model;

[0021] According to the multi-rate scheduling information, the computing core is configured to support scheduling of multiple different periods.

[0022] Optionally, before respectively setting the different functional control models on different cores of the central processing unit, the method further includes:

[0023] Add a rate conversion module to the code visualization model.

[0024] Optionally, the multi-core multi-rate code includes scheduling functions corresponding to the contents of each of the functional control models, model interaction logic between different functional control models, and rate interaction logic between different cycles.

[0025] Optionally, the model scheduling interface includes a model initialization scheduling interface and a multi-core multi-rate periodic scheduling interface.

[0026] A multi-core multi-rate scheduling device comprises: a configuration file generating unit, a code visualization model configuring unit, a function control model referencing unit, a multi-core multi-rate code obtaining unit, a model scheduling interface integrating unit and an executable file obtaining unit.

[0027] The configuration file generating unit is used to generate a multi-core multi-rate configuration file based on a central processing unit and an operating system of a target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and multi-rate scheduling information supported by the operating system;

[0028] The code visualization model configuration unit is used to modify the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain the configured code visualization model;

[0029] The function control model referencing unit is used to reference at least two pre-built function control models in the configured code visualization model, and respectively set different function control models on different cores of the central processing unit;

[0030] The multi-core multi-rate code acquisition unit is used to perform model simulation and code generation on the code visualization model to obtain the multi-core multi-rate code;

[0031] The model scheduling interface integration unit is used to add the model scheduling interface in the multi-core multi-rate code to the scheduling interface provided by the operating system to obtain the integration code of the multi-core multi-rate code and the operating system;

[0032] The executable file obtaining unit is used to perform code compiling and linking processing on the integrated code to obtain a multi-core multi-rate scheduling executable file.

[0033] A computer-readable storage medium stores a program, wherein when the program is executed by a processor, the multi-core multi-rate scheduling method described in any one of the above items is implemented.

[0034] An electronic device comprises at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other via the bus; and the processor is used to call program instructions in the memory to execute any of the multi-core multi-rate scheduling methods described above.

[0035] By means of the above technical scheme, the present invention provides a multi-core multi-rate scheduling method, device, storage medium and electronic device, the method comprising: generating a multi-core multi-rate configuration file based on a central processing unit and an operating system of a target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and the multi-rate scheduling information supported by the operating system; modifying the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain a configured code visualization model; referencing at least two pre-built functional control models in the configured code visualization model, and setting different functional control models on different cores of the central processing unit respectively; performing model simulation and code generation on the code visualization model to obtain a multi-core multi-rate code; adding the model scheduling interface in the multi-core multi-rate code to the scheduling interface provided by the operating system to obtain the integrated code of the multi-core multi-rate code and the operating system; performing code compilation and linking processing on the integrated code to obtain a multi-core multi-rate scheduling executable file. The present invention is based on code visualization model reference and parallel execution architecture, and configures the code visualization model through hardware and operating system configuration files, so that it can generate multi-core and multi-rate codes suitable for underlying software, and then adds these codes to the underlying scheduling to generate the final executable file, thereby realizing multi-core and multi-rate scheduling in cross-core interaction and multi-rate system interaction, thereby effectively improving the operating efficiency of the entire platform system.

[0036] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0038] Figure 1 A schematic diagram showing a flow chart of an implementation of a multi-core multi-rate scheduling method provided by an embodiment of the present invention;

[0039] Figure 2 A schematic flow chart of another implementation of the multi-core multi-rate scheduling method provided by an embodiment of the present invention is shown;

[0040] Figure 3 A schematic diagram of the structure of a multi-core multi-rate scheduling device provided by an embodiment of the present invention is shown;

[0041] Figure 4 A schematic structural diagram of an electronic device provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0043] Currently, in the development of modern embedded systems, developers use model-based design (MBD) technology to build system models, perform algorithm design, simulation verification, and automatically generate code, thereby achieving closed-loop software development. This technology is widely used in automotive electronics and other fields. For example, in the development of automotive powertrain controllers, engineers can use MBD to design complex control algorithms and ensure that they run stably in real environments.

[0044] For example: Simulink is a visual simulation tool, a block diagram environment in MATLAB that supports multi-domain simulation and model-based design. Simulink provides system design, simulation, automatic code generation, and continuous testing and verification of embedded systems. With Simulink, developers can build complex control logic models and deploy the automatically generated code from these models to embedded platforms, such as automotive electronic control units (ECUs).

[0045] A complex control model can usually be divided into various functional modules, each of which implements a specific function. Due to the different functions of each module, its running speed is also different. Functional modules that require precise control and real-time response usually require a higher running speed, such as scheduling with a cycle of 1ms or 5ms; while functional modules that do not require high real-time performance can run at a lower rate, such as 500ms or 1000ms. At the same time, modern CPUs mostly use a multi-core architecture, which can assign different tasks to different cores to run, thereby effectively improving CPU utilization.

[0046] Multicore technology refers to the integration of two or more complete computing engines (cores) in one processor, which makes the system easier to expand and provides more powerful processing performance with lower power consumption and less heat. Multirate technology refers to multiple subsystems in a system running at different rates to process signals with different sampling rates.

[0047] However, existing model-based code generation methods have certain limitations and do not support functions such as cross-core interaction and multi-rate system interaction. Therefore, it is particularly important to develop a multi-core multi-rate scheduling method that can effectively support multi-core and multi-rate embedded systems.

[0048] Based on this, in an embodiment of the present invention, a multi-core multi-rate scheduling method is provided. First, a multi-core multi-rate configuration file is generated according to the hardware platform and the operating system. Secondly, the parallel configuration of the code visualization model is modified based on the multi-core multi-rate configuration file to generate multi-core multi-rate code. Finally, the generated scheduling interface is added to the operating system scheduling to realize multi-core multi-rate operation of the system. It can be seen that the embodiment of the present invention is based on the code visualization model reference and parallel execution architecture, and configures the code visualization model through hardware and operating system configuration files, so that it can generate multi-core multi-rate code suitable for the underlying software, and then adds these codes to the underlying scheduling to generate the final executable file, thereby realizing multi-core multi-rate scheduling in cross-core interaction and multi-rate system interaction, thereby effectively improving the operating efficiency of the entire platform system.

[0049] like Figure 1 As shown, a flowchart of an implementation of a multi-core multi-rate scheduling method provided by an embodiment of the present invention is provided. The method may include:

[0050] S100: Generate a multi-core multi-rate configuration file based on a central processing unit and an operating system of a target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and multi-rate scheduling information supported by the operating system.

[0051] The target platform refers to the hardware device or system environment where the control model is ultimately executed, such as embedded control units (ECUs), microcontrollers, microprocessors, real-time operating systems, and industrial control systems in the automotive electronics field.

[0052] The central processing unit (CPU) refers to the core component of the target platform, which is equivalent to the hardware environment in which the target platform runs and is responsible for executing program instructions and processing data.

[0053] Among them, the operating system refers to the software environment in which the target platform runs. It is the system software responsible for managing the computer hardware and software resources of the target platform, providing basic services for application programs, and providing an interface for users to interact with the system.

[0054] The core count refers to the number of independent processing units (cores) contained in the CPU. Each core can perform computing tasks independently.

[0055] The multi-rate scheduling information refers to the execution frequency and scheduling strategy required for different tasks in a multi-core processor and multi-tasking environment. The execution cycle of a task is related to the execution frequency. For example, if a task is executed every 10 milliseconds, the execution cycle is 10 milliseconds.

[0056] The multi-core multi-rate configuration file is a file used to describe and configure specific settings and parameters of the software system. For example, assuming that the target platform is a dual-core CPU and the operating system supports running 1ms, 5ms, 10ms, 20ms, 50ms, 100ms, 200ms and 1000ms schedules on each core, the structure of the generated multi-core multi-rate configuration file can be as follows: Figure 2 shown.

[0057] It can be understood that in addition to the number of cores supported by the CPU and the multi-rate scheduling information supported by the operating system, the multi-core multi-rate configuration file usually also includes the type of CPU, architecture (such as x86, ARM), clock speed and other hardware characteristics and operating system information. The operating system information may include the type of target operating system (such as Windows, Linux, RTOS) and kernel version, etc.

[0058] Optionally, the file format of the multi-core multi-rate configuration file can be XML or MAT for easy reading and use.

[0059] S110 . Modify the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain a configured code visualization model.

[0060] The code visualization model refers to a model that uses graphical methods to represent, design, and analyze code and system behavior. The code visualization model uses graphical interfaces and tools to display complex code logic and system architecture in an easy-to-understand visual form to help developers understand code structure and system behavior more intuitively, thereby simplifying the development, debugging, and maintenance process.

[0061] Parallel configuration refers to the processing operation of modeling and configuring parallel tasks and multi-threaded processing through model-driven development tools.

[0062] Model-driven development tools refer to tools used to design, simulate and verify complex systems by creating system models using graphical interfaces. Model-driven development tools support graphical interfaces, multi-domain modeling, model simulation and verification, automatic code generation, and integrated development environment. Common model-driven development tools include Simulink, LabVIEW, Modelica, Stateflow, MATLAB, Dymola, and Enterprise Architect.

[0063] Specifically, an embodiment of the present invention can use a model-driven development tool to create a code visualization model, and then configure the code visualization model in parallel based on the number of cores and multi-rate scheduling information, so that the configured code visualization model can execute multiple tasks at the same time, thereby improving the processing speed and system efficiency of the code visualization model.

[0064] S120: referencing at least two pre-built function control models in the configured code visualization model, and setting different function control models on different cores of the central processing unit.

[0065] Among them, the functional control model is a model used to design, simulate and verify the control system of a specific function or task. It can be understood that a complete program can be divided into multiple modules according to its different functions, and each module corresponds to a functional control model that can achieve a specific function. For example: a functional control model can be used for a PID controller for motor control, and another functional control model can be used for a temperature control system.

[0066] Specifically, the embodiment of the present invention can integrate or embed at least two functional control models in a configured code visualization model, so as to add these independent functional control models to the code visualization model and implement function calls from functional control model to functional control model.

[0067] Specifically, the embodiment of the present invention can create an independent thread or process for each functional control model, and specify these threads or processes to run on different cores, thereby realizing the binding relationship between the functional control model and the specific core.

[0068] S130 , performing model simulation and code generation on the code visualization model to obtain multi-core multi-rate code.

[0069] Specifically, during the model simulation process, the embodiments of the present invention allow verification in the host computer environment of whether the operating logic and input and output of the code visualization model meet the design expectations without deploying the model to the actual host computer hardware, thereby facilitating the early discovery and correction of potential problems and ensuring the correctness and reliability of the model.

[0070] Specifically, after the model simulation is completed, the embodiment of the present invention can convert the code visualization model verified by the model simulation into a code source file of a high-level computer language (eg, C / C++ code), thereby obtaining a multi-core multi-rate code.

[0071] S140: Add the model scheduling interface in the multi-core multi-rate code to the scheduling interface provided by the operating system to obtain the integration code of the multi-core multi-rate code and the operating system.

[0072] The model scheduling interface refers to the mechanism and tools used to manage and control the execution of different functional control models on the cores of the bound processors at a predetermined rate.

[0073] Optionally, the model scheduling interface includes a model initialization scheduling interface and a multi-core multi-rate periodic scheduling interface.

[0074] The model initialization scheduling interface refers to the function or method used to initialize the model in the embedded system. The model initialization scheduling interface is mainly responsible for initializing the function control model when the system starts, such as allocating memory, setting the initial state, etc.

[0075] Among them, the multi-core multi-rate cycle scheduling interface refers to the interface for scheduling and managing tasks according to different rates (cycles) in a multi-core processor environment. Each core can support multiple different execution cycles (such as 1ms, 5ms, 10ms, etc.), and these multi-core multi-rate cycle scheduling interfaces are responsible for calling the corresponding tasks within the specified time interval.

[0076] The scheduling interface provided by the operating system refers to the system interface or API used for task scheduling in the embedded operating system. The operating system usually provides a set of standard scheduling interfaces to manage the execution of tasks, including task creation, scheduling and management.

[0077] Specifically, the embodiment of the present invention can add the model initialization scheduling interface to the startup sequence of the scheduling interface provided by the operating system, so that when the operating system starts, the model initialization scheduling interface is called to perform initialization operations on the corresponding function control model.

[0078] Specifically, the embodiment of the present invention can register the multi-core multi-rate periodic scheduling interface to the scheduler of the scheduling interface provided by the operating system to ensure that the corresponding function control model can be called within the specified time interval.

[0079] Among them, the integrated code refers to the code after integrating the multi-core multi-rate code into the operating system code, including the code that integrates the model initialization scheduling interface into the initialization process of the operating system, and the code that registers the multi-core multi-rate periodic scheduling interface into the operating system scheduler.

[0080] S150 , compile and link the integrated code to obtain a multi-core multi-rate scheduling executable file.

[0081] Specifically, the embodiments of the present invention can use a compiler suitable for the target platform (for example, GCC and Clang) to compile all source code files including the integrated code, convert all source code files into machine code for the target platform, and then use a linker to link the compiled target files and library files together to generate the final multi-core multi-rate scheduling executable file.

[0082] It is understandable that the source code file may also include the code input by the user and the code generated by the configuration tool. The embodiment of the present invention may select a suitable compiler according to the type of the central processor of the target platform, integrate the integrated code, the user input code and the code generated by the configuration tool into an integrated development environment, and then call the compiler and linker for processing to generate a multi-core multi-rate scheduling executable file.

[0083] The present invention provides a multi-core multi-rate scheduling method, which includes: generating a multi-core multi-rate configuration file based on a central processing unit and an operating system of a target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and the multi-rate scheduling information supported by the operating system; modifying the parallel configuration of a code visualization model based on the number of cores and the multi-rate scheduling information to obtain a configured code visualization model; referencing at least two pre-built function control models in the configured code visualization model, and setting different function control models on different cores of the central processing unit respectively; performing model simulation and code generation on the code visualization model to obtain a multi-core multi-rate code; adding a model scheduling interface in the multi-core multi-rate code to a scheduling interface provided by the operating system to obtain an integrated code of the multi-core multi-rate code and the operating system; performing code compilation and linking processing on the integrated code to obtain a multi-core multi-rate scheduling executable file. The present invention is based on code visualization model reference and parallel execution architecture, and configures the code visualization model through hardware and operating system configuration files, so that it can generate multi-core and multi-rate codes suitable for underlying software, and then adds these codes to the underlying scheduling to generate the final executable file, thereby realizing multi-core and multi-rate scheduling in cross-core interaction and multi-rate system interaction, thereby effectively improving the operating efficiency of the entire platform system.

[0084] Optional, based on Figure 1 The method shown, such as Figure 2 As shown, a flowchart of another implementation of the multi-core multi-rate scheduling method provided by an embodiment of the present invention is shown, and step S110 may specifically include:

[0085] S200. Create a blank code visualization model.

[0086] Specifically, the embodiment of the present invention can create a new code visualization model that does not contain any specific implementation code in a model-driven development tool.

[0087] S210. Modify the model configuration and code generation options of the code visualization model.

[0088] The model configuration is a model parameter used to ensure that the behavior of the code visualization model meets expectations and that the code can be generated correctly. The configuration items of the model configuration may include simulation parameters, solver type and error control, data import / export, hardware configuration, and module parameters.

[0089] The code generation options are used to control how to automatically generate executable code from the code visualization model. The code generation options may include target language, generated code type, task execution, rate conversion, file naming rules, code layering, and interface configuration.

[0090] S220 , using the core number and multi-rate scheduling information, perform multi-core and multi-task configuration on the code visualization model to obtain a configured code visualization model.

[0091] Specifically, an embodiment of the present invention can identify each functional control model that needs to be executed in the code visualization model, configure the number of running cores of the code visualization model according to the number of cores of the central processing unit of the target platform and the number of functional control models, and then select the execution frequency that can meet the needs of the functional control model from the multi-rate scheduling information and configure it to the corresponding computing core.

[0092] The embodiment of the present invention enables the code visualization model to run efficiently in a multi-core processor environment through modification of the code visualization model and multi-core multi-task configuration, which helps to achieve multi-core multi-rate scheduling and improve system performance and resource utilization.

[0093] Optional, in the above Figure 2 On the basis of one or more corresponding embodiments, in another optional embodiment provided by the embodiment of the present invention, modifying the model configuration and code generation options of the code visualization model may specifically include:

[0094] The code visualization model sets the solver type to fixed step, allows tasks to execute concurrently on the target platform, automatically handles rate conversion for data transfer, and sets the code generation system target file to Embedded Coder.

[0095] The embodiment of the present invention uses a fixed-step solver to ensure that each simulation time step is calculated within the same time interval, thereby ensuring the periodic execution of tasks, helping to realize a real-time control system, and making it easier for the scheduler to manage the execution order and time allocation of tasks.

[0096] The embodiment of the present invention allows tasks to be executed concurrently on the target platform so that tasks can be run simultaneously on a multi-core processor, thereby significantly improving the overall performance of the concurrent task execution mechanism, more effectively utilizing multi-core resources, and improving the efficiency of the central processing unit.

[0097] The embodiment of the present invention can ensure that the data sampling rate and the processing rate match when transferring data between different tasks by automatically processing the rate conversion of data transmission, thereby avoiding data loss or delay and ensuring the consistency of data transmission.

[0098] The embodiment of the present invention sets the code generation system target file as an embedded encoder, so that the subsequently generated code will be optimized and encoded for the embedded platform, so that it can run on the embedded device efficiently.

[0099] Optional, in the above Figure 2 On the basis of one or more corresponding embodiments, in another optional embodiment provided by the embodiment of the present invention, the code visualization model is configured with multiple cores and multiple tasks by using the core number and the multi-rate scheduling information to obtain the configured code visualization model, which may specifically include:

[0100] According to the number of cores, configure the number of cores of the computational cores of the code visualization model.

[0101] Specifically, the embodiment of the present invention can configure the same number of computing cores for the code visualization model according to the number of functional control models, so that each functional control model can be bound to a different computing core. It is understandable that the number of computing cores configured for the code visualization model is not greater than the number of cores.

[0102] According to the multi-rate scheduling information, the computing kernel is configured to support scheduling of multiple different cycles.

[0103] Specifically, the embodiment of the present invention can select a task execution frequency suitable for the functional control model in the multi-rate scheduling information, and configure the corresponding computing core according to the task execution frequency.

[0104] To facilitate understanding, an example is given here to illustrate: when the target platform is an autonomous driving system, an embodiment of the present invention can bind the relevant functional control models of sensor data acquisition and processing to a computing core with a high execution frequency, and bind the relevant functional control models of path planning and decision-making to another computing core with a low execution frequency.

[0105] The embodiment of the present invention enables the code visualization model to efficiently implement multi-rate scheduling in a multi-core processor environment through multi-core configuration and multi-rate scheduling, thereby helping to improve system performance and resource utilization.

[0106] Optional, in the above Figure 1 On the basis of one or more corresponding embodiments, in another optional embodiment provided by the embodiment of the present invention, before respectively setting different function control models on different cores of the central processing unit, the method may further include:

[0107] Add rate conversion module to code visualization model.

[0108] Among them, the rate conversion module (Rate Transition Block) is used to process data transmission and interaction between signals of different rates.

[0109] Specifically, the embodiment of the present invention can add a rate conversion module to the code visualization model in the model-driven development tool, and configure the input and output rates, buffer mode and other related parameters of the rate conversion module.

[0110] The embodiment of the present invention can coordinate signals of different rates through the rate conversion module, so that different sensors and actuators can work at different rates, thereby achieving effective data transmission between these devices.

[0111] Optional, in the above Figure 1 Based on the corresponding one or more embodiments, in another optional embodiment provided by the embodiment of the present invention, the multi-core multi-rate code includes scheduling functions corresponding to the contents of each functional control model, model interaction logic between different functional control models, and rate interaction logic between different cycles.

[0112] The scheduling function is responsible for managing and controlling the execution order and timing of each functional control model, ensuring that each functional control model is executed at the correct time and on the correct core.

[0113] Among them, model interaction logic refers to how different functional control models communicate with each other and exchange data, ensuring that different functional control models can correctly share and access data.

[0114] The rate interaction logic refers to the data transfer and processing between tasks of different rates. Since different tasks have different execution cycles, the rate interaction logic needs to handle rate conversion and data buffering to ensure the correct transmission of data between tasks of different cycles.

[0115] The embodiment of the present invention can fully utilize the computing power of the multi-core processor and the collaborative work between tasks of different rates by including the scheduling function of the functional control model and the multi-core multi-rate code of the multi-model multi-rate interaction logic, so that the target platform can run efficiently and reliably.

[0116] In order to facilitate understanding of the overall technical solution of the multi-core multi-rate scheduling method provided by the embodiment of this aspect, the following steps are used as examples to illustrate.

[0117] Step 1: Generate the corresponding configuration file based on the CPU and operating system scheduling to be deployed. The configuration file contains the number of cores supported by the CPU and the multi-rate scheduling information supported by the operating system. For example, for a dual-core CPU platform, the operating system supports running 1ms, 5ms, 10ms, 20ms, 50ms, 100ms, 200ms, and 1000ms scheduling on each core. This configuration file can be saved in XML or MAT format for subsequent reading and use.

[0118] Step 2: Create a new blank Simulink model and name it A.slx. Click the Model Configuration button and modify the following model configuration and code generation options to generate embedded code:

[0119] Solver-Type:Fixed-step

[0120] Solver-Allow tasks to execute concurrently on target:on

[0121] Solver-Automatically handle rate transition for data transfer:on

[0122] Code Generation-System target file:ert.tlc(Embedded Coder)

[0123] Click the Configure Tasks button to configure multi-core and multi-task. At this time, read the previously generated configuration file content and set the configuration to dual-core, with each core supporting 8 scheduling tasks with different periods. Create two new sub-models, B1.slx and B2.slx, and set their running rates to 1000ms and 100ms respectively. Add Model modules to reference B1 and B2 in the A.slx model, and add a rate conversion module. In the multi-core configuration interface, set B1 to run on core1 with a period of 1000ms, and set B2 to run on core2 with a period of 100ms. After completing the above configuration, perform model simulation and code generation. From the generated code, it can be found that the B1 and B2 model contents are generated in the two scheduling functions Core1_Task_1000ms_step and Core2_Task_100ms_step, respectively, and include the interaction logic between the two and the interaction logic at different rates.

[0124] Step 3: Add the model scheduling interface contained in the code generated in step 2 to the scheduling interface provided by the underlying operating system, including the model initialization scheduling interface and the multi-core multi-rate periodic scheduling interface. After completing the above steps, you can compile and link the code to generate the final executable file.

[0125] Through the above steps, the embodiment of the present invention realizes multi-core, multi-rate based code generation and scheduling configuration, fully utilizes the performance of the multi-core processor, ensures that each functional control model runs efficiently and correctly at different rates, realizes multi-core multi-rate scheduling in cross-core interaction and multi-rate system interaction, and thus effectively improves the operating efficiency of the entire platform system.

[0126] Although operations are depicted in a particular order, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order.Multitasking and parallel processing may be advantageous under certain circumstances.

[0127] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0128] Corresponding to the above method embodiment, the embodiment of the present invention also provides a multi-core multi-rate scheduling device, whose structure is as follows: Figure 3 As shown, it may include: a configuration file generating unit 10, a code visualization model configuring unit 20, a function control model referencing unit 30, a multi-core multi-rate code obtaining unit 40, a model scheduling interface integrating unit 50 and an executable file obtaining unit 60.

[0129] The configuration file generating unit 10 is used to generate a multi-core multi-rate configuration file based on the central processing unit and the operating system of the target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and the multi-rate scheduling information supported by the operating system.

[0130] The code visualization model configuration unit 20 is used to modify the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain a configured code visualization model.

[0131] The function control model referencing unit 30 is used to reference at least two pre-built function control models in the configured code visualization model, and respectively set different function control models on different cores of the central processing unit.

[0132] The multi-core multi-rate code obtaining unit 40 is used to perform model simulation and code generation on the code visualization model to obtain the multi-core multi-rate code.

[0133] The model scheduling interface integration unit 50 is used to add the model scheduling interface in the multi-core multi-rate code to the scheduling interface provided by the operating system to obtain the integration code of the multi-core multi-rate code and the operating system.

[0134] The executable file obtaining unit 60 is used to perform code compiling and linking processing on the integrated code to obtain a multi-core multi-rate scheduling executable file.

[0135] Optionally, the code visualization model configuration unit 20 may further include: a model creation subunit, a model modification subunit and a model configuration subunit.

[0136] Model creation subunit, used to create a new blank code visualization model;

[0137] A model modification subunit is used to modify the model configuration and code generation options of the code visualization model;

[0138] The model configuration subunit is used to configure the code visualization model with multiple cores and multiple tasks by using the core number and multi-rate scheduling information to obtain a configured code visualization model.

[0139] Optionally, a model modification subunit can be used to set the solver type of the code visualization model to fixed step size, allow tasks to be executed concurrently on the target platform, automatically handle rate conversion of data transmission, and set the code generation system target file to an embedded coder.

[0140] Optionally, the model configuration subunit can be used to configure the number of cores of the computing core of the code visualization model according to the number of cores; and configure the computing core to support scheduling of multiple different periods according to the multi-rate scheduling information.

[0141] Optionally, the multi-core multi-rate scheduling device may further include: a rate conversion module adding unit.

[0142] The rate conversion module adding unit is used to add a rate conversion module to the code visualization model before the function control model referencing unit 30 sets different function control models on different cores of the central processing unit respectively.

[0143] Optionally, the multi-core multi-rate code includes scheduling functions corresponding to the content of each functional control model, model interaction logic between different functional control models, and rate interaction logic between different cycles.

[0144] Optionally, the model scheduling interface includes a model initialization scheduling interface and a multi-core multi-rate periodic scheduling interface.

[0145] The present invention provides a multi-core multi-rate scheduling device, which is used to: generate a multi-core multi-rate configuration file based on a central processing unit and an operating system of a target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and the multi-rate scheduling information supported by the operating system; modify the parallel configuration of a code visualization model based on the number of cores and the multi-rate scheduling information to obtain a configured code visualization model; reference at least two pre-built function control models in the configured code visualization model, and respectively set different function control models on different cores of the central processing unit; perform model simulation and code generation on the code visualization model to obtain a multi-core multi-rate code; add a model scheduling interface in the multi-core multi-rate code to a scheduling interface provided by the operating system to obtain an integrated code of the multi-core multi-rate code and the operating system; perform code compilation and linking processing on the integrated code to obtain a multi-core multi-rate scheduling executable file. The present invention is based on code visualization model reference and parallel execution architecture, and configures the code visualization model through hardware and operating system configuration files, so that it can generate multi-core and multi-rate codes suitable for underlying software, and then adds these codes to the underlying scheduling to generate the final executable file, thereby realizing multi-core and multi-rate scheduling in cross-core interaction and multi-rate system interaction, thereby effectively improving the operating efficiency of the entire platform system.

[0146] Regarding the device in the above embodiment, the specific manner in which each unit performs the operation has been described in detail in the embodiment of the method, and will not be elaborated here.

[0147] The multi-core multi-rate scheduling device includes a processor and a memory. The above-mentioned configuration file generation unit 10, code visualization model configuration unit 20, function control model reference unit 30, multi-core multi-rate code acquisition unit 40, model scheduling interface integration unit 50 and executable file acquisition unit 60 are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions.

[0148] The processor contains a kernel, which calls the corresponding program unit from the memory. One or more kernels can be set, and the kernel parameters are adjusted to refer to the parallel execution architecture based on the code visualization model. The code visualization model is configured through hardware and operating system configuration files to enable it to generate multi-core multi-rate codes suitable for the underlying software, and then these codes are added to the underlying scheduling to generate the final executable file, thereby realizing multi-core multi-rate scheduling in cross-core interaction and multi-rate system interaction, thereby effectively improving the operating efficiency of the entire platform system.

[0149] An embodiment of the present invention provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the multi-core multi-rate scheduling method is implemented.

[0150] An embodiment of the present invention provides a processor, which is used to run a program, wherein the multi-core multi-rate scheduling method is executed when the program is running.

[0151] like Figure 4 As shown, an embodiment of the present invention provides an electronic device 1000, which includes at least one processor 1001, and at least one memory 1002 and a bus 1003 connected to the processor 1001; wherein the processor 1001 and the memory 1002 communicate with each other through the bus 1003; the processor 1001 is used to call the program instructions in the memory 1002 to execute the above-mentioned multi-core multi-rate scheduling method. The electronic device in this article can be a server, a PC, a PAD, a mobile phone, an ECU (Electronic Control Unit), a VCU (Vehicle Control Unit), an MCU (Micro Controller Unit), an HCU (Hybrid Control Unit), etc.

[0152] The present invention also provides a computer program product, which, when executed on an electronic device, is suitable for executing a program for initializing the steps of the multi-core multi-rate scheduling method.

[0153] The present invention is described with reference to flowcharts and / or block diagrams of methods, apparatuses, electronic devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable device to generate a machine, so that the instructions executed by the processor of the computer or other programmable device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0154] In a typical configuration, an electronic device includes one or more processors (CPU), a memory, and a bus. The electronic device may also include an input / output interface, a network interface, and the like.

[0155] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip. The memory is an example of a computer-readable medium.

[0156] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0157] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0158] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left" and "right" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the positions or elements referred to must have specific directions, be constructed and operate in specific directions. Therefore, they should not be understood as limitations of the present invention.

[0159] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. It should also be noted that the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0160] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0161] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A multi-core multi-rate scheduling method, characterized in that: include: Generate a multi-core multi-rate configuration file based on a central processing unit and an operating system of a target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and multi-rate scheduling information supported by the operating system; Modify the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain the configured code visualization model; Reference at least two pre-built function control models in the configured code visualization model, and respectively set different function control models on different cores of the central processing unit; Performing model simulation and code generation on the code visualization model to obtain multi-core multi-rate code; Adding the model scheduling interface in the multi-core multi-rate code to the scheduling interface provided by the operating system to obtain the integration code of the multi-core multi-rate code and the operating system; The integrated code is compiled and linked to obtain a multi-core multi-rate scheduling executable file.

2. The method according to claim 1, characterized in that The modifying the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain the configured code visualization model includes: Create a new blank code visualization model; Modifying model configuration and code generation options of the code visualization model; The code visualization model is configured with multiple cores and multiple tasks by using the number of cores and the multi-rate scheduling information to obtain the configured code visualization model.

3. The method according to claim 2, characterized in that The modifying of the model configuration and code generation options of the code visualization model includes: The code visualization model sets the solver type to fixed step size, allows tasks to be executed concurrently on the target platform, automatically handles rate conversion of data transmission, and sets the code generation system target file to an embedded coder.

4. The method according to claim 2, characterized in that: The step of configuring the code visualization model for multi-core and multi-task by using the number of cores and the multi-rate scheduling information to obtain the configured code visualization model includes: According to the number of cores, configuring the number of cores of the computing core of the code visualization model; According to the multi-rate scheduling information, the computing core is configured to support scheduling of multiple different periods.

5. The method according to claim 1, characterized in that Before respectively setting the different functional control models on different cores of the central processing unit, the method further includes: Add a rate conversion module to the code visualization model.

6. The method according to any one of claims 1 to 5, characterized in that The multi-core multi-rate code includes scheduling functions corresponding to the contents of each of the functional control models, model interaction logic between different functional control models, and rate interaction logic between different cycles.

7. The method according to claim 6, characterized in that The model scheduling interface includes a model initialization scheduling interface and a multi-core multi-rate periodic scheduling interface.

8. A multi-core multi-rate scheduling device, characterized in that: include: Configuration file generation unit, code visualization model configuration unit, function control model reference unit, multi-core multi-rate code acquisition unit, model scheduling interface integration unit and executable file acquisition unit, The configuration file generating unit is used to generate a multi-core multi-rate configuration file based on a central processing unit and an operating system of a target platform, wherein the multi-core multi-rate configuration file includes the number of cores supported by the central processing unit and multi-rate scheduling information supported by the operating system; The code visualization model configuration unit is used to modify the parallel configuration of the code visualization model based on the number of cores and the multi-rate scheduling information to obtain the configured code visualization model; The function control model referencing unit is used to reference at least two pre-built function control models in the configured code visualization model, and respectively set different function control models on different cores of the central processing unit; The multi-core multi-rate code acquisition unit is used to perform model simulation and code generation on the code visualization model to obtain the multi-core multi-rate code; The model scheduling interface integration unit is used to add the model scheduling interface in the multi-core multi-rate code to the scheduling interface provided by the operating system to obtain the integration code of the multi-core multi-rate code and the operating system; The executable file obtaining unit is used to perform code compiling and linking processing on the integrated code to obtain a multi-core multi-rate scheduling executable file.

9. A computer-readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the multi-core multi-rate scheduling method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: The electronic device includes at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other through the bus; the processor is used to call program instructions in the memory to execute the multi-core multi-rate scheduling method as described in any one of claims 1 to 7.

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