Computing system, data processing method, equipment, device, medium and program product

Abstract

The embodiment of the invention provides a computing system, a data processing method, equipment, a device, a medium and a program product. In the embodiment of the invention, when the data volume of the to-be-exchanged target data between the hardware processing unit and the processor is smaller than or equal to the set data volume threshold value, the target hardware descriptor carrying the target data is generated according to the field definition of the hardware descriptor, so that the elastic change of the field definition of the hardware descriptor is realized. And then, writing the target hardware descriptor into a data queue in a memory. Therefore, a receiver (a hardware processing unit or a processor) of the target data can read the target hardware descriptor from the memory and directly obtain the target data from the target hardware descriptor. According to the embodiment of the invention, a receiver of the target data can obtain the target data only through one-time memory access operation without reading the target data in other memory areas, so that the memory access times of the receiver of the target data can be reduced, and the resource consumption of memory access is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a computing system, a data processing method, a device, a apparatus, a medium and a program product. Background Art

[0002] Domain Specific Architecture (DSA) is a programmable hardware processor customized for a specific domain that can be used to accelerate certain applications. DSA allows optimization within a specific domain to achieve higher performance. By customizing the hardware or architecture, execution efficiency can be significantly improved, latency can be reduced, and energy consumption can be optimized in certain specific tasks.

[0003] DSA hardware can be used as a separate root complex integrated endpoint (RCiEP) device embedded in the socket of the central processing unit (CPU). DSA hardware can achieve hardware acceleration of data processing. However, when the CPU and DSA hardware interact to perform computing tasks, they need to frequently access the memory to exchange data. These frequent memory access operations consume a lot of system resources and affect the overall system performance. Summary of the invention

[0004] Various aspects of the present application provide a computing system, a data processing method, a device, an apparatus, a medium, and a program product, which can reduce the number of memory accesses when exchanging data between a processor and a hardware processing unit.

[0005] The embodiment of the present application provides a computing system, comprising: a processor, a hardware processing unit and a memory; the processor and the hardware processing unit are electrically connected to the memory respectively; the memory stores a data queue for storing a hardware descriptor; the hardware descriptor is a data structure describing information of data exchanged between the hardware processing unit and the processor; The hardware processing unit or the processor is used to generate a target hardware descriptor carrying the target data according to the field definition of the hardware descriptor when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold; and write the target hardware descriptor into the data queue so that the recipient of the target data can read the target hardware descriptor from the data queue and obtain the target data from the target hardware descriptor.

[0006] The embodiment of the present application also provides a data processing method, which is applicable to a processor or a hardware processing unit, wherein the processor and the hardware processing unit are electrically connected to a memory respectively; the memory stores a data queue for storing a hardware descriptor; the hardware descriptor is a data structure that describes information about data exchanged between the hardware processing unit and the processor; The method comprises: When the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, generating a target hardware descriptor carrying the target data according to a field definition of the hardware descriptor; The target hardware descriptor is written into the data queue, so that a receiver of the target data can read the target hardware descriptor from the data queue and obtain the target data from the target hardware descriptor.

[0007] The embodiment of the present application also provides a data processing method, which is applicable to a hardware processing unit or a processor, wherein the processor and the hardware processing unit are electrically connected to a memory respectively; the memory stores a data queue for storing a hardware descriptor; the hardware descriptor is a data structure that describes information about data exchanged between the hardware processing unit and the processor; The method comprises: Reading a target hardware descriptor from the data queue; the target hardware descriptor is a hardware descriptor carrying the target data generated by the provider of the target data according to the field definition of the hardware descriptor when the data amount of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold; The target data is obtained from the target hardware descriptor.

[0008] The embodiment of the present application also provides a hardware processing device, comprising: a memory access engine and a computing engine; the memory computing engine and the computing engine are electrically connected; the hardware processing device is used to be electrically connected to the memory, and the memory is electrically connected to the processor; the memory stores a second data queue, and the hardware descriptor in the second data queue is a data structure that describes information about data provided by the hardware processing device to the processor; The computing engine is configured to generate a target hardware descriptor carrying the target data according to a field definition of the hardware descriptor when the amount of target data to be exchanged between the hardware processing device and the processor is less than or equal to a set data amount threshold; The memory access engine is used to write the target hardware descriptor into the second data queue, so that the processor can read the target hardware descriptor from the second data queue and obtain the target data from the target hardware descriptor.

[0009] On the other hand, the memory further stores a first data queue; the hardware descriptor in the first data queue is a data structure describing information about data obtained by the hardware processing device from the processor; The memory access engine is further used to: read a first hardware descriptor from the first data queue; and obtain the target original data from the first hardware descriptor; the first hardware descriptor is a hardware descriptor carrying the target original data generated by the processor according to the field definition of the hardware descriptor in the first data queue when the data volume of the target original data corresponding to the target computing request is less than or equal to the set first data volume threshold; The computing engine is further used to compute the target original data to obtain a target computing result corresponding to the target computing request.

[0010] The embodiment of the present application also provides an electronic device, comprising: a memory and a processor; the memory comprises a memory and other storage media; the processor is electrically connected to the memory; the memory is used to be electrically connected to a hardware processing unit; the other storage media is used to store computer programs; the memory stores a data queue; the hardware descriptor in the data queue is a data structure that describes information about data to be exchanged between the hardware processing unit and the processor; The processor is coupled to the memory and the other storage media, and is configured to execute the computer program to execute the steps in the data processing method executed by the processor.

[0011] An embodiment of the present application also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the above-mentioned data processing methods.

[0012] An embodiment of the present application also provides a computer program product, including a computer program. When the computer program is executed by one or more processors, the one or more processors are caused to execute the steps in the above-mentioned data processing methods.

[0013] In an embodiment of the present application, when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data amount threshold, a target hardware descriptor carrying the target data is generated according to the field definition of the hardware descriptor, thereby realizing the flexible change of the field definition of the hardware descriptor. Afterwards, the target hardware descriptor is written to the data queue in the memory. In this way, the receiver of the target data (hardware processing unit or processor) can read the target hardware descriptor from the memory and directly obtain the target data from the target hardware descriptor. Among them, the receiver of the target data only needs one memory access operation to obtain the target data, and there is no need to read the target data from other memory areas, which can reduce the number of memory accesses of the receiver of the target data, thereby reducing the resource consumption of memory access. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of the structure of the computing system provided for the traditional solution and a schematic diagram of the interaction process between the CPU and the DSA hardware in the computing system; Figure 2 It is a schematic diagram of the structure of the traditional hardware descriptor; Figure 3 and Figure 4 A schematic diagram of the structure of a computing system provided in an embodiment of the present application and a schematic diagram of the interaction process between a processor and a hardware processing unit in the computing system; Figure 5 A schematic diagram of the interaction process between another processor and a hardware processing unit provided in an embodiment of the present application; Figure 6 A schematic diagram of a detailed interaction process between a processor and a hardware processing unit provided in an embodiment of the present application; Figure 7 and Figure 8 A flowchart of a data processing method provided in an embodiment of the present application; Figure 9a A schematic diagram of the structure of a hardware processing device provided in an embodiment of the present application; Figure 9b A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0016] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0017] Figure 1 A schematic diagram of the computing system and the interaction process between the CPU and DSA hardware in the computing system provided for the traditional solution. Figure 1 As shown, in the traditional solution, the DSA hardware can be an RCiEP device, which is packaged in a system on chip (SoC). Alternatively, the DSA hardware can also be an independent high-speed peripheral component interconnect (PCIe) device, which is connected to the system through a PCIe slot. When the DSA hardware performs computing tasks, the CPU needs to allocate two memory areas for the DSA hardware, one of which is used to store the submission queue and the other is used to store the completion queue. Generally speaking, this type of queue has a minimum unit, which is the minimum unit that the DSA hardware reads or writes. These two queues are a way for the CPU to interact with the DSA hardware for data.

[0018] In practice, the smallest unit in the aforementioned submission queue and completion queue is a hardware descriptor. A hardware descriptor is a data structure defined by the developer of a hardware processing unit. This data structure is used to describe the information of data exchanged between the hardware processing unit and the processor (such as a CPU). The data receiver (hardware processing unit or processor) can read data from memory based on the information of the data described by the hardware descriptor.

[0019] The hardware descriptors currently designed by the industry are generally 64 bytes. Figure 2As shown, the hardware descriptor in the submission queue usually includes: Operation Code field, Source Address field and Destination Address field. Among them, the Operation Code field is used to indicate which calculation operation the DSA hardware performs; the Source Address field is used to indicate the location of the original data of this operation in the memory; the Destination Address field is used to indicate the location in the memory where the DSA hardware stores the calculation result, that is, the memory address of the data provided by the DSA to the CPU. The hardware descriptor in the completion queue includes: Status field and Destination Address field, etc. Among them, the Status field is used to indicate the completion status of the DSA hardware executing the task, and its value can be completion, failure or error, etc. The Destination Address field is used to indicate the location of the calculation result of this operation in the memory, and the CPU can obtain the calculation result from the corresponding memory location according to the Destination Address field.

[0020] like Figure 1 As shown in the figure, the CPU, memory and DSA hardware are connected to each other through the input / output (IO) fabric. The IO fabric is a high-speed interconnect interface that connects different components and is mainly used to transmit data between different devices within the system. The IO fabric provides a unified platform that allows different IO devices to communicate through standard interfaces, improving the flexibility and scalability of the system. Figure 1 The interactive process of CPU and DSA coordinating to execute computing tasks is given as an example. Figure 1 As shown, the interaction process mainly includes the following steps: 1. The CPU fills in the hardware descriptor according to the calculation request, writes the hardware descriptor to the submission queue, and writes the original data corresponding to the calculation request to the memory area pre-allocated for the original data, that is, Figure 1 The "first memory area" in .

[0021] 2. The DSA hardware senses that a new task has been written to the submission queue, and reads the new task into the data cache area (Buffer) inside the DSA hardware according to the minimum unit (that is, the size of the hardware descriptor).

[0022] Specifically, the Direct Memory Access (DMA) engine in the DSA hardware uses DMA to read the hardware descriptor into the data cache area inside the DSA hardware. The DMA engine is a hardware component specifically used to implement data transmission between the kernel and IO devices (such as DSA hardware). By handing over the data transmission task to the DMA engine, the speed and efficiency of data transmission can be significantly improved, reducing the burden on the CPU.

[0023] 3. The DSA hardware parses the read hardware descriptor and parses the source address and destination address from the hardware descriptor.

[0024] 4. Based on the source address, the DSA hardware reads the original data to be calculated from the memory into the data cache area (Buffer) inside the DSA hardware.

[0025] Specifically, the DMA engine in the DSA hardware uses the DMA method to read the original data into the data cache area inside the DSA hardware.

[0026] 5. The DSA hardware calculates the original data according to the operation indicated by the opcode field of the hardware descriptor to obtain the calculation result.

[0027] Specifically, the computing engine in the DSA hardware calculates the raw data according to the operation indicated by the opcode field of the hardware descriptor to obtain the calculation result. The computing engine refers to a hardware module specially designed to accelerate a specific type of computing task. This type of hardware is usually customized to optimize the performance of a specific algorithm or application field.

[0028] 6. The DSA hardware writes the calculation result into the memory area indicated by the destination address, i.e. Figure 1 The "second memory area" in .

[0029] Specifically, the DMA engine in the DSA hardware uses DMA to write the calculation result to the memory area indicated by the destination address.

[0030] 7. The DSA hardware writes the task execution status and destination address to the hardware descriptor corresponding to the completion queue, and writes the hardware descriptor to the completion queue in the memory.

[0031] Specifically, the DMA engine in the DSA hardware writes the hardware descriptor into the completion queue in the memory using the DMA method.

[0032] 8. The DSA hardware notifies the CPU that the calculation is complete. The CPU reads the hardware descriptor from the completion queue in the memory and reads the calculation result from the memory according to the destination address recorded in the hardware descriptor.

[0033] Figure 1 The interaction process between the CPU and DSA hardware when executing computing tasks is only briefly described. Among them, steps 1 and 8 involve the CPU's access operations to the memory, and the CPU needs to perform 4 memory access operations. Steps 2, 4, 6, and 7 all involve the DSA hardware's access operations to the memory, that is, the DSA hardware needs to perform at least 4 memory access operations to execute a computing task. In the actual computing task execution process, a computing task is often divided into multiple small subtasks, each subtask corresponds to a hardware descriptor in the submission queue and a hardware descriptor in the completion queue. Each subtask requires the CPU and DSA hardware to perform 4 memory access operations respectively, which requires frequent and large-scale memory access, consumes a large amount of system resources, and affects the overall performance of the system.

[0034] In order to reduce the number of memory accesses by hardware processing units such as DSA hardware when performing computing tasks, in some embodiments of the present application, when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data amount threshold, a target hardware descriptor carrying the target data is generated according to the field definition of the hardware descriptor, thereby realizing the flexible change of the field definition of the hardware descriptor. Afterwards, the target hardware descriptor is written to the data queue in the memory. In this way, the recipient of the target data (hardware processing unit or processor) can read the target hardware descriptor from the memory and directly obtain the target data from the target hardware descriptor. Among them, the recipient of the target data only needs one memory access operation to obtain the target data, without having to go to other memory areas to read the target data, which can reduce the number of memory accesses of the recipient of the target data, thereby reducing the resource consumption of memory access.

[0035] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0036] It should be noted that the same reference numerals represent the same object or the same step in the following drawings and embodiments, and therefore, once an object or a step is defined in one drawing or embodiment, there is no need to further discuss it in the subsequent drawings and embodiments.

[0037] Figure 3 and Figure 4 This is a schematic diagram of the structure of the computing system provided in the embodiment of the present application. Figure 3 and Figure 4As shown, the computing system mainly includes: a processor 10, a hardware processing unit 20 and a memory 30. Among them, the processor 10 and the hardware processing unit 20 are electrically connected to the memory 30 respectively. The processor 10 and the hardware processing unit 20 can be electrically connected to the memory 30 through a data bus. The data bus can be a serial interface data bus, such as a peripheral component interconnect (PCI) interface, a high-speed peripheral component interconnect (PCIe) interface, a universal serial bus (USB) serial interface, an RS485 interface or an RS232 interface, etc., but not limited to this. Preferably, the processor 10 and the hardware processing unit 20 are electrically connected to the memory 30 through a PCIe interface, which can increase the data transmission speed between the processor 10 and the hardware processing unit 20 and the memory 30.

[0038] Processor 10 is a general-purpose processor that executes program code according to a predetermined instruction set. A program is composed of a series of machine language instructions that tell the processor how to process data. Processor 10 is generally a central processing unit (CPU). Processing data using a computer program is generally called software computing.

[0039] The hardware processing unit 20, which may also be referred to as DSA hardware, refers to a hardware processor that uses a hardware description language (HDL) for data processing. The hardware description language may be a very-high-speed integrated circuit hardware description language (VHDL), Verilog HDL, System Verilog or System C, etc. The hardware processing unit 20 may be a field-programmable gate array (FPGA), a programmable array logic device (PAL), a general array logic device (GAL), a complex programmable logic device (CPLD), etc.; or, the hardware processing unit 20 may also be an application-specific integrated circuit (ASIC).

[0040] The hardware processing unit 20 is a programmable integrated circuit that allows the user to define its functions at the hardware level. The hardware processing unit 20 contains a large number of programmable logic blocks (Logic Blocks), which can be connected through programming to form complex digital circuits. Therefore, data processing performed by the hardware processing unit 20 can be called hardware computing, which can achieve hardware acceleration of data processing.

[0041] According to the aforementioned Figure 1 From the interaction process between the CPU and the DSA hardware shown in the figure, it can be seen that no matter how much data is exchanged between the CPU and the DSA hardware in actual operation, even if it is 1 byte of raw data or calculation results, the CPU core and the DSA hardware need to perform 4 memory access operations respectively. Frequent and large-scale memory access consumes a large amount of system resources and affects the overall performance of the system.

[0042] according to Figure 2 The data structure of the hardware descriptor shown in the figure shows that some fields in the hardware descriptor are still unused, such as the optional fields. Among them, the optional fields refer to other fields other than the necessary basic fields in the hardware descriptor, and the user can choose whether to use these fields. In the embodiment of the present application, the unused fields in the hardware descriptor are defined as target fields, that is, the target fields are free fields in the hardware descriptor. Therefore, when the amount of target data to be exchanged between the processor 10 and the hardware processing unit 20 is large, the target field is still used. Figure 1 The method shown implements data exchange between the processor 10 and the hardware processing unit 20. This hardware descriptor that can dynamically change the definition or meaning of some fields can be called a flexible hardware descriptor. The flexibility means that the definition of some fields of the hardware descriptor is flexible and changeable. The flexible hardware descriptor means that the meaning of the fields in the hardware descriptor is dynamically defined by the hardware processing unit 20 such as DSA hardware.

[0043] For example, when the amount of target data to be exchanged between the processor 10 and the hardware processing unit 20 is relatively small, the target field in the hardware descriptor is used to store the target data to be exchanged; and when the amount of target data to be exchanged between the processor 10 and the hardware processing unit 20 is relatively large, the target field in the hardware descriptor is still used. Figure 1 The method shown implements data exchange between the processor 10 and the hardware processing unit 20, and the target field in the hardware descriptor is used to store other data or is left empty. During use, the meaning or definition of the target field of the hardware descriptor is changeable, so this type of hardware descriptor can be called a flexible hardware descriptor.

[0044] Based on such flexible hardware descriptors defined by the hardware processing unit 20, the embodiment of the present application improves the interaction process between the processor 10 and the hardware processing unit 20. Figure 3 , Figure 4 and Figure 5 The interaction process between the processor 10 and the hardware processing unit 20 provided in the embodiment of the present application is exemplified.

[0045] In the embodiment of the present application, for the convenience of description and distinction, the data to be exchanged between the hardware processing unit 20 and the processor 10 is defined as target data. The target data can be data that the hardware processing unit 20 needs to read from the memory, or data that the hardware processing unit 20 needs to write into the memory.

[0046] In the embodiments of the present application, Figure 3 and Figure 4 As shown, the memory 30 stores a data queue for storing hardware descriptors. The hardware descriptor is the basic unit (also called the minimum unit) of the data queue. The hardware processing unit 20 can read data from the data queue in units of hardware descriptors, or write data to the data queue in units of hardware descriptors. In some embodiments, the target data is the data that the hardware processing unit 20 needs to read from the memory, then the recipient of the target data is the hardware processing unit 20, and the data queue is the aforementioned Figure 2 In some other embodiments, the target data is data that the hardware processing unit 20 needs to write into the memory, then the receiver of the target data is the processor 10, and the data queue is the aforementioned Figure 2 In the embodiment of the present application, for the convenience of description and distinction, the data queue (i.e., submission queue) used when the hardware processing unit 20 needs to read data from the memory is defined as the first data queue; the data queue (i.e., completion queue) used when the hardware processing unit 20 needs to write data to the memory is defined as the second data queue. Figure 3 As shown, the hardware descriptor in the first data queue is a data structure that describes the information of the data obtained by the hardware processing unit from the processor. Figure 4 As shown, the hardware descriptor in the second data queue is a data structure that describes information about data provided by the hardware processing unit to the processor.

[0047] In the embodiment of the present application, the data that the hardware processing unit 20 needs to read from the memory, and the data that the hardware processing unit 20 needs to write to the memory, are collectively referred to as target data to be exchanged between the hardware processing unit 20 and the processor 10.

[0048] Based on the flexible hardware descriptor proposed in the embodiment of the present application, that is, the hardware descriptor with flexible and variable definition of unused fields, in the embodiment of the present application, Figure 3 and Figure 4As shown in step 1, the processor 10 or the hardware processing unit 20 may generate a target hardware descriptor carrying the target data according to the field definition of the hardware descriptor when the amount of target data to be exchanged between the hardware processing unit 20 and the processor 10 is less than or equal to the set data amount threshold. The data amount threshold may be determined by the total length of the hardware descriptor, the length of the basic field in the hardware descriptor, and the opcode. Specifically, the data amount threshold is less than or equal to the amount of data defined by the opcode in the hardware descriptor, and is less than or equal to the data length A obtained by subtracting the length of the basic field from the total length of the hardware descriptor. For example, the data amount value may be the minimum value between the amount of data that can be defined by the opcode and the data length A.

[0049] like Figure 2 As shown, for the hardware descriptor in the first data queue (i.e., submission queue), its basic fields include: operation code field, source address field, and destination address field. For the hardware descriptor in the second data queue (i.e., completion queue), its basic fields include: destination address field and task status field.

[0050] Specifically, when the amount of target data to be exchanged between the hardware processing unit 20 and the processor 10 is less than or equal to a set data amount threshold, the processor 10 or the hardware processing unit 20 may write the target data into an unused field (such as a target field) of the hardware descriptor according to the field definition of the hardware descriptor to obtain a target hardware descriptor carrying the target data.

[0051] Of course, the processor 10 or the hardware processing unit 20 can also determine the values ​​of other fields of the hardware descriptor, and write the values ​​of other fields of the hardware descriptor into corresponding fields according to the field definition of the hardware descriptor, thereby obtaining the target hardware descriptor carrying the target data.

[0052] Further, if Figure 3 and Figure 4 As shown in step 2, the processor 10 or the hardware processing unit 20 may write the target hardware descriptor into the data queue. Figure 3 and Figure 4 As shown in step 3 and step 4, the receiver of the target data can read the target hardware descriptor from the data queue and obtain the target data directly from the target hardware descriptor, that is, the receiver of the target data only needs one memory access operation to obtain the target data, and there is no need to read the target data from other memory areas, which can reduce the number of memory accesses of the receiver of the target data, thereby reducing the resource consumption of memory access.

[0053] On the other hand, the processor 10 or the hardware processing unit 20 only needs to write the target data into the target hardware descriptor and store it in the memory, and there is no need to store the target data in other areas of the memory, which can also save memory resources.

[0054] Of course, if the data volume of the target data is greater than the set data volume threshold, the processor 10 or the hardware processing unit 20 may write the target data into the corresponding target memory area in the memory. The target memory area is the memory area allocated for the target data by the processor 10. In this way, the recipient of the target data can obtain the target data from the target memory area.

[0055] The following is an illustrative description of the process of data exchange between the processor 10 and the hardware processing unit 20 based on the elastic hardware descriptor from the perspectives of the target data being the original data corresponding to the calculation request that the hardware processing unit 20 needs to read from the memory 30, and the target data being the calculation result corresponding to the calculation request that the hardware processing unit 20 needs to write to the memory 30.

[0056] In some embodiments, Figure 3 and Figure 5 As shown, the target data is the data that the hardware processing unit 20 needs to read from the memory 30. The target data may be the original data corresponding to the calculation request, that is, the original data requested to be calculated by the calculation request. For the convenience of description and distinction, the calculation request currently processed by the processor 10 is defined as the target calculation request, and the original data corresponding to the target calculation request is defined as the target original data. In this embodiment, the data queue includes the aforementioned first data queue (i.e., the submission queue). The hardware descriptor in the first data queue is a data structure that describes the information of the data obtained by the hardware processing unit 20 from the processor 10. The recipient of the target data is the hardware processing unit 20.

[0057] In this embodiment, the target hardware descriptor is generated by the processor 10. Specifically, Figure 3 and Figure 5 As shown in step 1, the processor 10 can generate a hardware descriptor carrying the target original data according to the field definition of the hardware descriptor in the first data queue when the data volume of the target original data is less than or equal to the set data volume threshold. The hardware descriptor is the target hardware descriptor.

[0058] Specifically, the processor 10 can respond to the target computing request and obtain the target original data corresponding to the target computing request as the target data; and determine whether the data volume of the target original data is less than or equal to the set data volume threshold; if the judgment result is yes, then according to the field definition of the hardware descriptor in the first data queue, generate a hardware descriptor carrying the target original data, and the hardware descriptor is the target hardware descriptor.

[0059] Specifically, according to Figure 2From the basic structure of the hardware descriptor in the first data queue (i.e., submission queue) shown, it can be seen that the hardware descriptor in the first data queue includes: a source address field and a target field. Among them, the source address field is used to record the memory address information of the original data corresponding to the calculation request; and the target field is an unused field in the hardware descriptor in the first data queue, which can be defined independently by the hardware processing unit. Based on this, when the processor 10 generates a hardware descriptor carrying the target original data, it can write the invalid memory address information into the source address field of the hardware descriptor according to the field definition of the hardware descriptor in the first data queue, and write the target original data into the target field of the hardware descriptor to obtain a hardware descriptor carrying the target original data, i.e., the target hardware descriptor.

[0060] The invalid memory address information may be pre-set memory address information, which does not belong to normal memory address information, such as 0x7f7f7f7f7f7f7f7f, etc. In this way, the hardware processing unit 20 may determine whether to directly obtain the target original data to be calculated from the hardware descriptor according to whether the memory address information stored in the source address field of the hardware descriptor read from the first data queue is invalid memory address information, or to read the target original data from the target memory area in the memory.

[0061] Alternatively, a flag bit may be set in the target field. The flag bit may identify whether the target hardware descriptor carries the target original data. Based on this, the processor 10 may set the flag bit in the target hardware descriptor to the first identifier representing that the target hardware descriptor carries the target original data according to the field definition of the hardware descriptor in the first data queue when the data volume of the target original data is less than or equal to the set data volume threshold, and write the target original data into the target field of the hardware descriptor to obtain the hardware descriptor carrying the target original data, i.e., the target hardware descriptor. In this way, the hardware processing unit 20 may determine whether to directly obtain the target original data to be calculated from the hardware descriptor according to whether the flag bit of the hardware descriptor read from the first data queue is the first identifier; or read the target original data from the target memory area in the memory. If the data volume of the target original data is greater than the set data volume threshold, according to the field definition of the hardware descriptor in the first data queue, the flag bit in the target hardware descriptor is set to the second identifier representing that the target hardware descriptor does not carry the target original data. For example, the first identifier may be binary "1", the second identifier may be binary "0", etc.

[0062] Further, if Figure 5 As shown in step 2, the processor 10 may write the target hardware descriptor into the first data queue. Figure 5As shown in step 3, the hardware processing unit 20 may read the target hardware descriptor from the first data queue. Figure 5 As shown, the DMA engine in the hardware processing unit 20 can read the target hardware descriptor from the first data queue using the DMA method, such as reading the target hardware descriptor from the first data queue to the cache in the hardware processing unit 20 using the DMA method.

[0063] In some embodiments, the processor 10 may maintain a write pointer corresponding to the first data queue; when the target hardware descriptor is written to the first data queue, the processor 10 may add 1 to the write pointer and notify the hardware processing unit 20 that a new hardware descriptor is written to the first data queue. The hardware processing unit 20 may respond to the notification and determine that a new hardware descriptor is written to the first data queue. Further, the hardware processing unit 20 may use the DMA engine to read the target hardware descriptor from the first data queue in a DMA manner when sensing that a new hardware descriptor is written to the first data queue.

[0064] Further, the hardware processing unit 20 may obtain the memory address information stored in the source address field from the target hardware descriptor. Further, if the memory address information stored in the source address field is invalid memory address information, then Figure 5 As shown in step 4, the hardware processing unit 20 obtains the target original data from the target hardware descriptor. Specifically, the DMA engine in the hardware processing unit 20 can obtain the target original data from the target hardware descriptor.

[0065] Specifically, the hardware processing unit 20 can parse the target hardware descriptor to obtain the memory address information stored in the source address field in the target hardware descriptor; and determine whether the memory address information stored in the source address field in the target hardware descriptor is the set invalid memory address information; if the judgment result is yes, the hardware processing unit 20 obtains the target original data from the target hardware descriptor. Specifically, the hardware processing unit 20 can obtain the target original data from the target field of the target hardware descriptor. Alternatively, the hardware processing unit 20 can parse the target hardware descriptor to obtain the value of the flag bit in the target hardware descriptor; and if the value of the flag bit is the first identifier, the hardware processing unit 20 can also obtain the target original data from the target field of the target hardware descriptor.

[0066] Through the above method, when the data volume of the target original data is less than or equal to the set data volume threshold, the hardware processing unit 20 only needs to read the target hardware descriptor from the first data queue in the memory, and can directly obtain the target original data from the target hardware descriptor, without having to read the target original data from the memory according to the memory address information stored in the source address field, which can reduce the number of memory accesses of the hardware processing unit and reduce the resource consumption of memory access.

[0067] On the other hand, when the amount of target original data is less than or equal to the set data amount threshold, the processor only needs to write the target hardware descriptor into the first data queue in the memory, without having to allocate memory space separately for the target original data, which can save memory resources. The processor also does not need to write the target original data into a separate memory space, which can also reduce the number of times the processor accesses the memory and reduce the resource consumption of memory access.

[0068] Further, if Figure 5 As shown in step 5, after obtaining the target original data from the target hardware descriptor, the hardware processing unit 20 may calculate the target original data to obtain the target calculation result. In the embodiment of the present application, the specific implementation of the target original data is not limited. In some embodiments, Figure 2 As shown, the hardware descriptor in the first data queue also includes: an operation code field, which is used to record the operation code corresponding to the calculation request, and the operation code is used to indicate which calculation operation the hardware processing unit performs. Accordingly, when the processor 10 generates a hardware descriptor carrying the target original data, it can also respond to the target calculation request and determine the target operation code corresponding to the target calculation request. Specifically, the processor 10 can parse the target calculation request to determine the calculation method (defined as the target calculation method) of the target calculation request; determine the target operation code corresponding to the target calculation request according to the target calculation method. In the embodiment of the present application, the specific content of the calculation method is not limited. For example, the calculation method can be hash calculation, key exchange or key generation. The operation code corresponding to the calculation method is defined by the manufacturer of the hardware processing unit and pre-configured into the processor and the hardware processing unit. The processor 10 can obtain the operation code corresponding to the target calculation method as the target operation code from the correspondence between the pre-configured calculation method and the operation code according to the target calculation method corresponding to the target calculation request.

[0069] Furthermore, the processor 10 may write the target opcode into the opcode field of the target hardware descriptor. Accordingly, the hardware processing unit 20 may obtain the target opcode from the opcode field of the target hardware descriptor; and calculate the target raw data according to the calculation method corresponding to the target opcode to obtain the target calculation result. Specifically, Figure 5 As shown, the computing engine in the hardware processing unit can obtain the target operation code from the operation code field of the target hardware descriptor; and calculate the target original data according to the calculation method corresponding to the target operation code to obtain the target calculation result.

[0070] To further reduce the number of memory accesses, such as Figure 5As shown in step 5, for the target calculation result, the hardware processing unit 20 may also carry the target calculation result in the hardware descriptor when the target calculation result is less than or equal to the set data volume threshold. In the embodiment of the present application, for the convenience of description and distinction, the data volume threshold used to determine whether the target data (such as the target original data) read from the memory by the hardware processing unit needs to be carried in the hardware descriptor is defined as the first data volume threshold; and the data volume threshold used to determine whether the data written to the memory by the hardware descriptor (such as the target calculation result) needs to be carried in the hardware descriptor is defined as the second data volume threshold. Among them, the first data volume threshold and the second data volume threshold may be the same or different. Among them, the first data volume threshold is specifically determined by the total length of the hardware descriptors in the first data queue (i.e., the submission queue), the length of the basic field in the hardware descriptor, and the operation code in the hardware descriptor. The first data volume threshold may be less than or equal to the maximum amount of data that can be calculated by the operation code in the hardware descriptor in the first data queue, and less than or equal to the data length B obtained by subtracting the length of the basic field from the total length of the hardware descriptor. For example, the first data volume threshold may be a minimum value of a data length B and a maximum data volume that can be calculated by an operation code in the hardware descriptor.

[0071] The second data volume threshold is specifically determined by the total length of the hardware descriptors in the second data queue (i.e., the completion queue), the length of the basic field in the hardware descriptor, and the opcode in the target hardware descriptor read in the first data queue. The first data volume threshold may be less than or equal to the length Y of the calculation result corresponding to the opcode in the target hardware descriptor in the first data queue, and less than or equal to the data length C obtained by subtracting the length of the basic field of the hardware descriptor in the second data queue from the total length of the hardware descriptors in the second data queue. For example, the second data volume threshold may be the minimum value of the data length C and the length Y of the calculation result corresponding to the opcode in the target hardware descriptor in the first data queue, that is, the second quantity threshold may be equal to the minimum value of C and Y.

[0072] Specifically, the hardware processing unit 20 may generate a hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue when the data volume of the target calculation result is less than or equal to the set second data volume threshold. In the embodiment of the present application, for the convenience of description and distinction, the hardware descriptor carrying the target original data generated by the aforementioned processor 10 is defined as the first hardware descriptor; and the hardware descriptor carrying the target calculation result generated by the hardware processing unit 20 is defined as the second hardware descriptor.

[0073] Specifically, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit 20 may write the target calculation result into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue to obtain a hardware descriptor carrying the target calculation result, i.e., the second hardware descriptor.

[0074] In the embodiment of the present application, the specific implementation method of the hardware processing unit 20 determining whether the data volume of the target calculation result is less than or equal to the set second data volume threshold is not limited. In some embodiments, the hardware processing unit 20 can count the data volume of the target calculation result and determine whether the data volume of the target calculation result is less than or equal to the set second data volume threshold.

[0075] In other embodiments, since the length of the calculation results of some computing tasks is fixed, for example, a hash algorithm can convert a series of data into a value of fixed length. For another example, in the key generation algorithm, the length of the generated key is fixed, etc. Based on this, the processor 10 can determine the data volume of the target calculation result, that is, the length of the target calculation result, according to the calculation method corresponding to the target calculation request. Further, if the data volume of the target calculation result is less than or equal to the set second data volume threshold, the processor 10 can write invalid memory address information into the destination address field of the first hardware descriptor when generating the first hardware descriptor carrying the target original data. Among them, the invalid memory address information written into the destination address field of the first hardware descriptor can be the same as or different from the invalid memory address information written into the source address field of the first hardware descriptor. For the convenience of description and distinction, the invalid memory address information written into the source address field of the first hardware descriptor is defined as invalid first memory address information, and the invalid memory address information written into the destination address field of the first hardware descriptor is defined as invalid second memory address information. Among them, the first memory address information and the second memory address information can be the same or different.

[0076] Accordingly, the hardware processing unit 20 can obtain the memory address information stored in the destination address field from the first hardware descriptor; and when the memory address information stored in the destination address field in the first hardware descriptor is invalid second memory address information, it determines that the data volume of the target calculation result is less than or equal to the second data volume threshold, and generates a hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue.

[0077] Further, if Figure 5As shown in step 6, the hardware processing unit 20 may write the second hardware descriptor into the second data queue. In this embodiment, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit carries the target calculation result in the second hardware descriptor and writes it into the second data queue in the memory, without having to write the target calculation result into another separate memory area, which can reduce the number of times the hardware processing unit writes data to the memory, that is, reduce the number of memory accesses of the hardware processing unit, thereby reducing the resource consumption of memory accesses. In addition, since the hardware processing unit no longer needs to write the target calculation result into a separate memory area, there is no need to allocate another separate memory space for the target calculation result, which can save memory resources.

[0078] Accordingly, if Figure 5 As shown in steps 7 and 8, the processor 10 can read the second hardware descriptor from the second data queue and obtain the target calculation result from the second hardware descriptor. The processor only needs to read the second hardware descriptor from the memory to directly obtain the target calculation result from the second hardware descriptor, without having to read the memory separately to obtain the target calculation result, which can reduce the number of memory accesses of the processor, thereby reducing the resource consumption of memory access.

[0079] In the embodiment of the present application, in order to make the processor 10 perceive whether to obtain the target calculation result from the second hardware descriptor or read the target calculation result from the corresponding area of ​​the memory, the hardware processing unit 20 may also write the invalid second memory address information into the destination address field of the second hardware descriptor when generating the second hardware descriptor carrying the target calculation result. The destination address field of the second hardware descriptor is used to record the memory address information of the data provided by the hardware processing unit to the processor.

[0080] Accordingly, the processor 10 can read the second hardware descriptor from the second data queue. In some embodiments, the processor 10 can periodically query whether there is a new hardware operator written to the second data queue according to a set query cycle; if a new hardware operator is found to be written, the processor 10 can obtain the hardware operator newly written in the current query cycle from the second data queue; thereafter, the memory address information stored in the destination address field is obtained from the read hardware operator; and when the memory address information is invalid second memory address information, the target calculation result is obtained from the hardware operator. Similarly, if the hardware operator read from the second data queue is the second hardware operator, the memory address information stored in the destination address field can be obtained from the second hardware descriptor; and when the memory address information stored in the destination address field of the second hardware descriptor is invalid second memory address information, the target calculation result is obtained from the second hardware descriptor. Among them, when the target calculation result is less than or equal to the second data volume threshold, the destination address field of the second hardware descriptor writes invalid second memory address information. The processor 10 can determine where to obtain the target calculation result based on the value of the destination address field, providing guidance information for the processor on where to obtain the target calculation result.

[0081] The data provided by the hardware processing unit to the processor in the above embodiment is the calculation result corresponding to the calculation request of the processor. Of course, the data provided by the hardware processing unit to the processor may also be other data, which is not associated with the calculation request obtained by the processor. Figure 4 The process of providing data from the hardware processing unit to the processor is exemplified.

[0082] exist Figure 4 In the embodiment of the present application, the target data is the data provided by the hardware processing unit to the processor, and the recipient of the target data is the processor 10. In the embodiment of the present application, the hardware processing unit 20 may be the calculation result corresponding to the aforementioned calculation request, or other data, such as data received from other devices. Accordingly, the hardware processing unit 20 may generate a hardware descriptor (defined as a third hardware descriptor) carrying the target data according to the field definition of the hardware descriptor in the second data queue when the data volume of the target data is less than or equal to the set second data volume threshold. The third hardware descriptor is the target hardware descriptor in this embodiment.

[0083] Specifically, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit 20 may write the target data into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue to obtain a third hardware descriptor carrying the target data.

[0084] Further, the hardware processing unit 20 may write the third hardware descriptor into the second data queue. In this embodiment, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit carries the target calculation result in the third hardware descriptor and writes it into the second data queue in the memory, without having to write the target data into another separate memory area, which can reduce the number of times the hardware processing unit writes data to the memory, that is, reduce the number of memory accesses of the hardware processing unit, thereby reducing the resource consumption of memory accesses. In addition, since the hardware processing unit no longer needs to write the target data into a separate memory area, there is no need to allocate another separate memory space for the target data, which can save memory resources.

[0085] Accordingly, the processor 10 can read the third hardware descriptor from the second data queue and obtain the target data from the third hardware descriptor. The processor only needs to read the third hardware descriptor from the memory to directly obtain the target data from the third hardware descriptor without having to read the memory separately to obtain the target data, which can reduce the number of memory accesses of the processor, thereby reducing the resource consumption of memory access.

[0086] In an embodiment of the present application, in order to enable the processor 10 to perceive whether to obtain the target calculation result from the third hardware descriptor or to read the target data from the corresponding area of ​​the memory, the hardware processing unit 20 may also write the invalid second memory address information into the destination address field of the third hardware descriptor when generating the third hardware descriptor carrying the target calculation result.

[0087] Accordingly, the processor 10 can read the third hardware descriptor from the second data queue, and can obtain the memory address information stored in the destination address field from the third hardware descriptor; and obtain the target data from the third hardware descriptor when the memory address information stored in the destination address field of the third hardware descriptor is invalid second memory address information. Wherein, when the target calculation result is less than or equal to the second data volume threshold, the destination address field of the second hardware descriptor writes the invalid second memory address information, and the processor 10 can determine where to obtain the target calculation result according to the value of the destination address field, which provides guidance information for the processor on where to obtain the target data.

[0088] In order to facilitate understanding of the interaction process between the hardware processing unit and the processor provided in the embodiment of the present application, Figure 6 The specific embodiment shown is described in detail. Figure 6 As shown, the interaction process between the hardware processing unit and the processor provided in the embodiment of the present application mainly includes the following steps: Step 1: The processor 10 responds to a target computing request, obtains target original data corresponding to the target computing request, and determines a target computing method of the target computing request; and determines a target operation code corresponding to the target computing request according to the target computing method.

[0089] Step 2: Write the target opcode into the opcode field of the first hardware descriptor.

[0090] Step 3: The processor 10 determines whether the data volume Q1 of the target original data is less than or equal to the set first data volume threshold Q0; and determines whether the data volume P1 of the calculation result corresponding to the target calculation method is less than or equal to the set second data volume threshold P0. If the judgment result is: Q1≤Q0, and P1≤P0, then execute steps 4-6, and then execute step 9; if the judgment result is: Q1≤Q0, P1>P0, then execute steps 4-5 and step 8, and then execute step 9; if the judgment result is: Q1>Q0, P1≤P0, then execute steps 7 and 6, and then execute step 9; if the judgment result is Q1>Q0, P1>P0, then execute steps 7 and 8, and then execute step 9.

[0091] Step 4: Write the target original data into the target field of the first hardware operator.

[0092] Step 5: Write the invalid first memory address information into the source address field of the first hardware descriptor.

[0093] Step 6: Write the invalid second memory address information into the destination address field of the first hardware descriptor.

[0094] Step 7: The processor 10 allocates a first target memory area for the target original data, writes the target original data into the first target memory area, and writes the memory address information of the first target memory area into the source address field of the first hardware descriptor.

[0095] Step 8: The processor 10 allocates a second target memory area for the target calculation result, and writes the memory address information of the second target memory area into the destination address field of the first hardware descriptor.

[0096] Step 9: The processor 10 writes the first hardware descriptor into the first data queue.

[0097] Step 10: The hardware processing unit 20 senses that a new hardware descriptor is written to the first data queue, and uses the DMA engine to read the first hardware descriptor from the first data queue to a cache area within the hardware processing unit.

[0098] Step 11: The hardware processing unit 20 parses the first hardware descriptor to obtain the memory address information stored in the source address field of the first hardware descriptor, the target operation code stored in the operation code field, and the memory address information stored in the destination address field.

[0099] Step 12: The hardware processing unit 20 determines whether the memory address information stored in the source address field of the first hardware descriptor is invalid first memory address information; if so, execute step 13; if not, execute step 14.

[0100] Step 13: Obtain target original data from the first hardware descriptor, and then execute step 15.

[0101] Step 14: Use the DMA engine to read the target original data from the memory area indicated by the memory address information stored in the source address field of the first hardware descriptor, store it in the cache area in the hardware processing unit, and then execute step 15.

[0102] Step 15: Utilize the computing engine in the hardware processing unit 20 to calculate the target original data according to the target computing method corresponding to the target operation code to obtain the target computing result.

[0103] Step 16: The hardware processing unit 20 determines whether the memory address information stored in the destination address field of the first hardware descriptor is invalid second memory address information. If yes, execute step 17; if not, execute step 18.

[0104] Step 17: The hardware processing unit 20 writes the target calculation result into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue; and writes the invalid second memory address information into the destination address field of the second hardware descriptor.

[0105] Step 18: The DMA engine in the hardware processing unit 20 writes the target calculation result into the second target memory area indicated by the memory address information stored in the destination address field of the first hardware descriptor, and writes the memory address information of the second target memory area into the destination address field of the second hardware descriptor.

[0106] Step 19: The DMA engine in the hardware processing unit 20 writes the second hardware descriptor into the second data queue.

[0107] Step 20: The processor 10 reads the second hardware descriptor from the second data queue.

[0108] Step 21: The processor 10 obtains the memory address information stored in the destination address field of the second hardware descriptor from the second hardware descriptor; and determines whether the memory address information stored in the destination address field of the second hardware descriptor is invalid second memory address information; if the judgment result is yes, execute step 22; if the judgment result is no, execute step 23.

[0109] Step 22: Obtain the target calculation result from the second hardware descriptor.

[0110] Step 23: Read the target calculation result from the memory area indicated by the memory address information stored in the destination address field of the second hardware descriptor.

[0111] according to Figure 6 The interaction process between the hardware processing unit and the processor shown in the figure shows that when the data volume of the original data and the calculation result corresponding to the calculation request is small (less than or equal to the corresponding data volume threshold), the processor performs two memory accesses (one is to write the first hardware descriptor to the first data queue in the memory, and the other is to read the second hardware descriptor from the second data queue in the memory), and the hardware processing unit performs two memory accesses (one is to read the first hardware descriptor from the first data queue in the memory, and the other is to write the second hardware descriptor to the second data queue in the memory). Compared with Figure 1 The interaction process between the hardware processing unit and the processor shown in the figure reduces two memory access operations for both the processor and the hardware processing unit, which helps to reduce the resource consumption of memory access. In particular, the hardware processing unit reduces up to two DMA operations, which greatly improves the performance of the hardware processing hardware, and theoretically can achieve a performance improvement of about 50%.

[0112] The execution logic of the hardware processing unit is realized by connecting logic blocks through a hardware programming language to form a digital circuit. Therefore, the execution logic of the hardware processing unit provided in the embodiment of the present application can provide guidance for the hardware design of the hardware processing unit and realize the optimization of the hardware processing unit.

[0113] In addition to the computing system provided in the aforementioned embodiments, the embodiments of the present application also provide a data processing method. The data processing method provided in the embodiments of the present application is exemplarily described below from the perspectives of a processor and a hardware processing unit.

[0114] Figure 7 The flowchart of the data processing method provided in the embodiment of the present application is shown in FIG. 1 . The method is applicable to a processor or a hardware processing unit. Figure 7 As shown, the data processing method mainly includes the following steps: 701. When the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, generate a target hardware descriptor carrying the target data according to a field definition of the hardware descriptor.

[0115] 702. Write the target hardware descriptor into the data queue, so that the receiver of the target data can read the target hardware descriptor from the data queue and obtain the target data from the target hardware descriptor.

[0116] Figure 8 1 is a flow chart of another data processing method provided in an embodiment of the present application. The method is applicable to a hardware processing unit or a processor. Figure 8 As shown, the data processing method mainly includes the following steps: 801. Read a target hardware descriptor from a data queue; the target hardware descriptor is a hardware descriptor carrying the target data generated by a provider of the target data according to a field definition of the hardware descriptor when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold.

[0117] 802. Get target data from the target hardware descriptor.

[0118] In this embodiment, the processor and the hardware processing unit are electrically connected to the memory respectively; the memory stores a data queue for storing hardware descriptors; the hardware descriptor is a data structure that describes information about data exchanged between the hardware processing unit and the processor.

[0119] It should be noted that in Figure 7 When the data processing method shown is executed by a processor, Figure 8 The data processing method shown is executed by a hardware processing unit. Figure 7 When the data processing method shown is executed by a hardware processing unit, Figure 8 The data processing method shown is executed by a processor.

[0120] The data to be exchanged between the hardware processing unit and the processor is defined as target data, wherein the target data may be data that the hardware processing unit needs to read from the memory, or data that the hardware processing unit needs to write into the memory.

[0121] Based on the flexible hardware descriptor proposed in the embodiment of the present application, that is, a hardware descriptor with flexible and variable definitions of unused fields, in the embodiment of the present application, in step 701, when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to the set data amount threshold, a target hardware descriptor carrying the target data can be generated according to the field definition of the hardware descriptor.

[0122] Specifically, when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, the target data is written into an unused field (such as a target field) of the hardware descriptor according to the field definition of the hardware descriptor to obtain a target hardware descriptor carrying the target data.

[0123] Of course, the values ​​of other fields of the hardware descriptor may also be determined, and according to the field definition of the hardware descriptor, the values ​​of other fields of the hardware descriptor are written into corresponding fields, thereby obtaining a target hardware descriptor carrying target data.

[0124] Furthermore, in step 702, the target hardware descriptor may be written into the data queue. Thus, for the receiver of the target data, in step 801, the target hardware descriptor may be read from the data queue, and in step 802, the target data may be directly obtained from the target hardware descriptor, that is, the receiver of the target data only needs one memory access operation to obtain the target data, and does not need to read the target data from other memory areas, which can reduce the number of memory accesses of the receiver of the target data, thereby reducing the resource consumption of memory access.

[0125] On the other hand, the processor or hardware processing only needs to write the target data into the target hardware descriptor and store it in the memory. There is no need to store the target data in other areas of the memory, which can also save memory resources.

[0126] Of course, if the amount of target data is greater than the set data amount threshold, the target data can be written to the corresponding target memory area in the memory. The target memory area is the memory area allocated by the processor for the target data. In this way, the receiver of the target data can obtain the target data from the target memory area.

[0127] In some embodiments, the target data is data that the hardware processing unit needs to read from the memory. The target data may be the original data corresponding to the computing request, that is, the original data requested to be calculated by the computing request. For the convenience of description and distinction, the processor and the computing request currently being processed are defined as the target computing request, and the original data corresponding to the target computing request is defined as the target original data. In this embodiment, the data queue includes the aforementioned first data queue (i.e., the submission queue). The recipient of the target data is the hardware processing unit.

[0128] In this embodiment, the target hardware descriptor is generated by the processor. Specifically, when the amount of the target original data is less than or equal to the set data amount threshold, a hardware descriptor carrying the target original data is generated according to the field definition of the hardware descriptor in the first data queue, and the hardware descriptor is the target hardware descriptor.

[0129] Specifically, in response to a target computing request, the target original data corresponding to the target computing request can be obtained as the target data; and it is determined whether the data volume of the target original data is less than or equal to the set data volume threshold; if the judgment result is yes, a hardware descriptor carrying the target original data is generated according to the field definition of the hardware descriptor in the first data queue, and the hardware descriptor is the target hardware descriptor.

[0130] Specifically, the hardware descriptor in the first data queue includes: a source address field and a target field. The source address field is used to record the memory address information of the original data corresponding to the calculation request; and the target field is an unused field (i.e., an idle field) in the hardware descriptor in the first data queue, which can be defined independently by the hardware processing unit. Based on this, when generating a hardware descriptor carrying the target original data, the invalid memory address information can be written into the source address field of the hardware descriptor according to the field definition of the hardware descriptor in the first data queue, and the target original data can be written into the target field of the hardware descriptor to obtain a hardware descriptor carrying the target original data, i.e., the target hardware descriptor.

[0131] The invalid memory address information may be pre-set memory address information, which is not normal memory address information. In this way, the hardware processing unit may determine whether to directly obtain the target original data to be calculated from the hardware descriptor or read the target original data from the target memory area in the memory according to whether the memory address information stored in the source address field of the hardware descriptor read from the first data queue is invalid memory address information.

[0132] Further, the target hardware descriptor can be written into the first data queue. Accordingly, the hardware processing unit can read the target hardware descriptor from the first data queue. Specifically, the target hardware descriptor can be read from the first data queue using DMA, such as using DMA to read the target hardware descriptor from the first data queue into a cache in the hardware processing unit.

[0133] Further, the hardware processing unit may obtain the memory address information stored in the source address field from the target hardware descriptor. Further, if the memory address information stored in the source address field is invalid memory address information, the hardware processing unit obtains the target original data from the target hardware descriptor.

[0134] Specifically, the target hardware descriptor can be parsed to obtain the memory address information stored in the source address field in the target hardware descriptor; and it is determined whether the memory address information stored in the source address field in the target hardware descriptor is the set invalid memory address information; if the judgment result is yes, the hardware processing unit obtains the target original data from the target hardware descriptor. Specifically, the hardware processing unit can obtain the target original data from the target field of the target hardware descriptor. In this way, when the data volume of the target original data is less than or equal to the set data volume threshold, the hardware processing unit only needs to read the target hardware descriptor from the first data queue in the memory, and can directly obtain the target original data from the target hardware descriptor, without having to read the target original data from the memory according to the memory address information stored in the source address field, which can reduce the number of memory accesses of the hardware processing unit and reduce the resource consumption of memory access.

[0135] On the other hand, when the amount of target original data is less than or equal to the set data amount threshold, the processor only needs to write the target hardware descriptor into the first data queue in the memory, without having to allocate memory space separately for the target original data, which can save memory resources. The processor also needs to write the target original data into a separate memory space, which can also reduce the number of times the processor accesses the memory and reduce the resource consumption of memory access.

[0136] After obtaining the target original data from the target hardware descriptor, the hardware processing unit can calculate the target original data to obtain the target calculation result. In the embodiment of the present application, the specific implementation method of the target original data is not limited. In some embodiments, the hardware descriptor in the first data queue also includes: an operation code field, which is used to record the operation code corresponding to the calculation request, and the operation code is used to indicate which calculation operation the hardware processing unit performs. Accordingly, when the processor generates a hardware descriptor carrying the target original data, it can also respond to the target calculation request and determine the target operation code corresponding to the target calculation request. Further, the target operation code can be written into the operation code field of the target hardware descriptor.

[0137] Correspondingly, the hardware processing unit can obtain the target opcode from the opcode field of the target hardware descriptor; and calculate the target raw data according to the calculation method corresponding to the target opcode to obtain the target calculation result. Specifically, the calculation engine in the hardware processing unit can obtain the target opcode from the opcode field of the target hardware descriptor; and calculate the target raw data according to the calculation method corresponding to the target opcode to obtain the target calculation result.

[0138] In order to further reduce the number of memory accesses, for the target calculation result, the hardware processing unit may also carry the target calculation result in the hardware descriptor when the target calculation result is less than or equal to the set data volume threshold. In the embodiment of the present application, for the convenience of description and distinction, the data volume threshold used to determine whether the target data (such as the target original data) read from the memory by the hardware processing unit needs to be carried in the hardware descriptor is defined as the first data volume threshold; and the data volume threshold used to determine whether the data (such as the target calculation result) written to the memory by the hardware descriptor needs to be carried in the hardware descriptor is defined as the second data volume threshold.

[0139] Specifically, the hardware processing unit may generate a hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue when the data volume of the target calculation result is less than or equal to the set second data volume threshold. In the embodiment of the present application, for the convenience of description and distinction, the hardware descriptor carrying the target original data generated by the aforementioned processor is defined as the first hardware descriptor; and the hardware descriptor carrying the target calculation result generated by the hardware processing unit is defined as the second hardware descriptor.

[0140] Specifically, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit may write the target calculation result into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue to obtain a hardware descriptor carrying the target calculation result, i.e., the second hardware descriptor.

[0141] In some embodiments, the hardware processing unit may count the data volume of the target calculation result, and determine whether the data volume of the target calculation result is less than or equal to a set second data volume threshold.

[0142] In other embodiments, the length of the calculation results of some computing tasks is fixed. Based on this, the processor can determine the data volume of the target calculation result, that is, the length of the target calculation result, according to the calculation method corresponding to the target calculation request. Further, if the data volume of the target calculation result is less than or equal to the set second data volume threshold, the processor may write invalid memory address information into the destination address field of the first hardware descriptor when generating a first hardware descriptor carrying the target original data. For ease of description and distinction, the invalid memory address information written into the source address field of the first hardware descriptor is defined as invalid first memory address information, and the invalid memory address information written into the destination address field of the first hardware descriptor is defined as invalid second memory address information. Among them, the first memory address information and the second memory address information may be the same or different.

[0143] Accordingly, the hardware processing unit can obtain the memory address information stored in the destination address field from the first hardware descriptor; and when the memory address information stored in the destination address field in the first hardware descriptor is invalid second memory address information, it determines that the data volume of the target calculation result is less than or equal to the second data volume threshold, and generates a hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue.

[0144] Further, the hardware processing unit may write the second hardware descriptor into the second data queue. In this embodiment, when the data volume of the target calculation result is less than or equal to the set second data volume threshold, the hardware processing unit carries the target calculation result in the second hardware descriptor and writes it into the second data queue in the memory, without having to write the target calculation result into another separate memory area, which can reduce the number of times the hardware processing unit writes data to the memory, that is, reduce the number of memory accesses of the hardware processing unit, thereby reducing the resource consumption of memory accesses. In addition, since the hardware processing unit no longer needs to write the target calculation result into a separate memory area, there is no need to allocate another separate memory space for the target calculation result, which can save memory resources.

[0145] Accordingly, the processor can read the second hardware descriptor from the second data queue and obtain the target calculation result from the second hardware descriptor. The processor only needs to read the second hardware descriptor from the memory to directly obtain the target calculation result from the second hardware descriptor, without having to read the memory separately to obtain the target calculation result, which can reduce the number of memory accesses of the processor, thereby reducing the resource consumption of memory access.

[0146] In the embodiment of the present application, in order to make the processor aware of whether to obtain the target calculation result from the second hardware descriptor or read the target calculation result from the corresponding area of ​​the memory, the hardware processing unit may also write the invalid second memory address information into the destination address field of the second hardware descriptor when generating the second hardware descriptor carrying the target calculation result. The destination address field of the second hardware descriptor is used to record the memory address information of the data provided by the hardware processing unit to the processor.

[0147] Accordingly, the processor can read the second hardware descriptor from the second data queue. Further, the memory address information stored in the destination address field can be obtained from the second hardware descriptor; and when the memory address information stored in the destination address field of the second hardware descriptor is invalid second memory address information, the target calculation result is obtained from the second hardware descriptor. Wherein, when the target calculation result is less than or equal to the second data volume threshold, the destination address field of the second hardware descriptor writes invalid second memory address information, and the processor can determine where to obtain the target calculation result based on the value of the destination address field, which provides guidance information for the processor on where to obtain the target calculation result.

[0148] The data provided by the hardware processing unit to the processor in the aforementioned embodiment is the calculation result corresponding to the calculation request of the processor. Of course, the data provided by the hardware processing unit to the processor may also be other data, which is not associated with the calculation request obtained by the processor.

[0149] In other embodiments, the target data is data provided by the hardware processing unit to the processor, and the recipient of the target data is the processor. In the embodiment of the present application, the hardware processing unit may be the calculation result corresponding to the aforementioned calculation request, or other data, such as data received from other devices. Accordingly, the hardware processing unit may generate a hardware descriptor (defined as a third hardware descriptor) carrying the target data according to the field definition of the hardware descriptor in the second data queue when the data volume of the target data is less than or equal to the set second data volume threshold. The third hardware descriptor is the target hardware descriptor in this embodiment.

[0150] Specifically, when the data volume of the target data is less than or equal to a set second data volume threshold, the hardware processing unit may write the target data into the target field of the second hardware descriptor according to the field definition of the hardware descriptor in the second data queue to obtain a third hardware descriptor carrying the target data.

[0151] Furthermore, the hardware processing unit may write the third hardware descriptor into the second data queue. In this embodiment, when the data volume of the target data is less than or equal to the set second data volume threshold, the hardware processing unit carries the target calculation result in the third hardware descriptor and writes it into the second data queue in the memory, without having to write the target data into another separate memory area, which can reduce the number of times the hardware processing unit writes data to the memory, that is, reduce the number of memory accesses of the hardware processing unit, thereby reducing the resource consumption of memory accesses. In addition, since the hardware processing unit no longer needs to write the target data into a separate memory area, there is no need to allocate another separate memory space for the target data, which can save memory resources.

[0152] Accordingly, the processor can read the third hardware descriptor from the second data queue and obtain the target data from the third hardware descriptor. The processor only needs to read the third hardware descriptor from the memory to directly obtain the target data from the third hardware descriptor without having to read the memory separately to obtain the target data, which can reduce the number of memory accesses of the processor, thereby reducing the resource consumption of memory access.

[0153] In an embodiment of the present application, in order to enable the processor to perceive whether to obtain the target calculation result from the third hardware descriptor or to read the target data from the corresponding area of ​​the memory, the hardware processing unit may also write the invalid second memory address information into the destination address field of the third hardware descriptor when generating the third hardware descriptor carrying the target calculation result.

[0154] Accordingly, the processor can read the third hardware descriptor from the second data queue, and can obtain the memory address information stored in the destination address field from the third hardware descriptor; and when the memory address information stored in the destination address field of the third hardware descriptor is invalid second memory address information, the target data is obtained from the third hardware descriptor. Wherein, when the target calculation result is less than or equal to the second data volume threshold, the destination address field of the second hardware descriptor writes the invalid second memory address information, and the processor can determine where to obtain the target calculation result according to the value of the destination address field, which provides guidance information for the processor on where to obtain the target data.

[0155] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 801 and 802 can be device A; for another example, the execution subject of step 801 can be device A, and the execution subject of step 802 can be device B; and so on.

[0156] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations appearing in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel, and the sequence numbers of the operations, such as 801, 802, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel.

[0157] Accordingly, an embodiment of the present application also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the data processing method provided in the aforementioned embodiments.

[0158] The embodiment of the present application also provides a computer program product, including a computer program. When the computer program is executed by one or more processors, the one or more processors are caused to execute the steps of the data processing method provided in the aforementioned embodiments.

[0159] In the embodiments of the present application, the specific implementation form of the computer program product is not limited. In some embodiments, the computer program product can be implemented as an application (Application, APP), a small program, a computer-side client, a program module, a plug-in, an installation package, a software development kit (Software Development Kit, SDK), an image file of a disc (such as an ISO file), a plug-in or software as a service (Software as a Service, SaaS) software, etc., but is not limited thereto.

[0160] Figure 9a This is a schematic diagram of the structure of the hardware processing device provided in the embodiment of the present application. Figure 9a As shown, the hardware processing device mainly includes: a memory access engine 901 and a computing engine 902. The memory access engine 901 and the computing engine 902 are electrically connected. Among them, the memory access engine 901 can be a DMA engine.

[0161] The hardware processing device is used to be electrically connected to the memory; the memory is electrically connected to the processor; the memory stores a second data queue, and the hardware descriptor in the second data queue is a data structure that describes information about data provided by the hardware processing device to the processor.

[0162] In some embodiments of the present application, the memory further stores a first data queue; the hardware descriptor in the first data queue is a data structure that describes information about data obtained by the hardware processing device from the processor.

[0163] The memory access engine 901 is used to read the first hardware descriptor from the first data queue; and obtain the target original data from the first hardware descriptor; the first hardware descriptor is a hardware descriptor carrying the target original data generated by the processor according to the field definition of the hardware descriptor in the first data queue when the data volume of the target original data corresponding to the target computing request is less than or equal to the set first data volume threshold.

[0164] The calculation engine 902 is used to calculate the target original data to obtain the target calculation result corresponding to the target calculation request.

[0165] In some embodiments, the memory access engine 901 uses DMA to read the first hardware descriptor from the first data queue to the cache 903.

[0166] In some embodiments, the hardware descriptor in the first data queue includes: a source address field and a target field, the source address field is used to record the memory address information of the data obtained by the hardware processing device from the processor; when the data volume of the target original data is less than or equal to the set first data volume threshold, the processor writes the invalid first memory address information into the source address field of the first hardware descriptor according to the field definition of the hardware descriptor in the first data queue, and writes the target original data into the target field of the first hardware descriptor to obtain the first hardware descriptor.

[0167] When the memory access engine 901 obtains the target original data from the first hardware descriptor, it is specifically used to: obtain the memory address information stored in the source address field of the first hardware descriptor from the first hardware descriptor; when the memory address information stored in the source address field of the first hardware descriptor is invalid first memory address information, obtain the target original data from the first hardware descriptor.

[0168] In some other embodiments, the memory further stores a second data queue; the hardware descriptor in the second data queue is a data structure that describes information about data provided by the hardware processing device to the processor. The computing engine 902 is also used to: when the data volume of the target computing result is less than or equal to the set second data volume threshold, generate a second hardware descriptor carrying the target computing result according to the field definition of the hardware descriptor in the second data queue. Accordingly, the memory access engine 901 is used to write the second hardware descriptor into the second data queue so that the processor can read the second hardware descriptor from the second data queue and obtain the target computing result from the second hardware descriptor.

[0169] Furthermore, the hardware descriptor in the first data queue includes: a destination address field for recording the memory address information of the data provided by the hardware processing device to the processor; when the data volume of the target calculation result is less than or equal to the second data volume threshold, the processor writes the invalid second memory address information into the destination address field of the first hardware descriptor. Accordingly, the calculation engine 902 is also used to: obtain the memory address information stored in the destination address field of the first hardware descriptor from the first hardware descriptor; and, when the memory address information stored in the destination address field of the first hardware descriptor is the invalid second memory address information, determine that the data volume of the target calculation result is less than or equal to the second data volume threshold.

[0170] In some embodiments, the hardware descriptor in the first data queue further includes: an opcode field for recording the opcode corresponding to the calculation request. The processor determines the target opcode corresponding to the target calculation request in response to the target calculation request, and writes the target opcode into the opcode field in the first hardware descriptor. Accordingly, when the calculation engine 902 calculates the target raw data, it is specifically used to: obtain the target opcode from the opcode field of the first hardware descriptor; calculate the target raw data according to the calculation method corresponding to the target opcode to obtain the target calculation result.

[0171] In some embodiments of the present application, the computing engine 901 is used to generate a target hardware descriptor carrying the target data according to the field definition of the hardware descriptor when the amount of target data to be exchanged between the hardware processing device and the processor is less than or equal to a set data amount threshold.

[0172] Accordingly, the memory access engine 902 is used to write the target hardware descriptor into the second data queue, so that the processor can read the target hardware descriptor from the second data queue and obtain the target data from the target hardware descriptor.

[0173] In some embodiments, when generating a target hardware descriptor carrying target data, the computing engine 901 is specifically used to: write invalid second memory address information into the destination address field of the third hardware descriptor according to the field definition of the hardware descriptor in the second data queue, and write the target data into the target field of the third hardware descriptor, so that the processor can obtain the target calculation result from the third hardware descriptor when the memory address information stored in the destination address field of the third hardware descriptor is invalid second memory address information.

[0174] Figure 9b This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 9b As shown, the electronic device includes: a memory 90a and a processor 90b. Among them, the memory 90a includes a memory 90a1 and other storage media 90a2. The memory 90a1 can store a data queue. The hardware descriptor in the data queue is a data structure that describes the information of the data to be exchanged between the processor 90a and the hardware processing unit. In this embodiment, the other storage media in the memory 90a is used to store computer programs. The processor 90a can be connected to the hardware processing unit for communication.

[0175] When the processor 90a is in communication connection with the hardware processing unit, the processor 90b is coupled to the memory 90a for executing a computer program for executing the steps of the data processing method performed by the processor provided in the above embodiments. The specific implementation of each step can be referred to the relevant description of the above embodiments, which will not be repeated here.

[0176] In some optional embodiments, such as Figure 9b As shown, the electronic device may also include optional components such as a communication component 90c, a power component 90d, a display component 90e and an audio component 90f. Figure 9b Some components are shown schematically, and it does not mean that electronic devices must include Figure 9b The components shown do not necessarily mean that the electronic device can only include Figure 9b Components shown.

[0177] in addition, Figure 9b The components in the dashed box are optional components, not mandatory components, and may depend on the product form of the electronic device. The electronic device of this embodiment may be implemented as a terminal device such as a desktop computer, a laptop computer, a mobile phone, or an IoT device; or it may be various server devices such as a traditional server, a cloud server, or a server cluster.

[0178] In an embodiment of the present application, the memory is used to store a computer program and can be configured to store various other data to support operations on the device where it is located. Among them, the processor can execute the computer program stored in the memory to implement the corresponding control logic. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random-Access Memory, SRAM), electrically erasable programmable read only memory (Electrically Erasable Programmable Read Only Memory, EEPROM), erasable programmable read only memory (Electrical Programmable Read Only Memory, EPROM), programmable read only memory (Programmable Read Only Memory, PROM), read only memory (Read Only Memory, ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0179] In the embodiment of the present application, the processor may be any hardware processing device that can execute the logic of the above method. Optionally, the processor may be a central processing unit (CPU), a graphics processing unit (GPU) or a microcontroller unit (MCU); it may also be a field programmable gate array (FPGA), a programmable array logic device (PAL), a general array logic device (GAL), a complex programmable logic device (CPLD) or other programmable devices; or it may be an advanced reduced instruction set (RISC) processor (Advanced RISC Machines, ARM) or a system on chip (System on Chip, SoC), etc., but not limited thereto.

[0180] In an embodiment of the present application, the communication component is configured to facilitate wired or wireless communication between the device in which it is located and other devices. The device in which the communication component is located can access a wireless network based on a communication standard, such as Wireless Fidelity (WiFi), 2G or 3G, 4G, 5G or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component can also be implemented based on Near Field Communication (NFC) technology, Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology or other technologies.

[0181] In an embodiment of the present application, the display component may include a liquid crystal display (LCD) and a touch panel (TP). If the display component includes a touch panel, the display component may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0182] In an embodiment of the present application, a power supply component is configured to provide power to various components of the device in which it is located. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply component is located.

[0183] In an embodiment of the present application, the audio component may be configured to output and / or input audio signals. For example, the audio component includes a microphone (Microphone, MIC), and when the device where the audio component is located is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal may be further stored in a memory or sent via a communication component. In some embodiments, the audio component also includes a speaker for outputting an audio signal. For example, for a device with a language interaction function, voice interaction with a user may be achieved through an audio component.

[0184] It should be noted that the descriptions such as “first” and “second” in this article are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do they limit “first” and “second” to different types.

[0185] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) containing computer-usable program codes.

[0186] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0187] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0188] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0189] In a typical configuration, a computing device includes one or more processors (CPU, etc.), input / output interfaces, network interfaces, and memory.

[0190] Memory may include non-permanent storage in a computer-readable medium, in the form of random-access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0191] Computer storage media is readable storage media, also known as readable media. Readable storage media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0192] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the above elements.

[0193] The above contents are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A computing system, characterized in that: include: Processors, hardware processing units and memory; The processor and the hardware processing unit are electrically connected to the memory respectively; The memory stores a data queue for storing hardware descriptors; the hardware descriptors are data structures that describe information about data exchanged between the hardware processing unit and the processor; The hardware processing unit or the processor is configured to generate a target hardware descriptor carrying the target data according to a field definition of the hardware descriptor when the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold; The target hardware descriptor is written into the data queue, so that the receiver of the target data can read the target hardware descriptor from the data queue and obtain the target data from the target hardware descriptor.

2. A data processing method, applicable to a processor or a hardware processing unit, characterized in that: The processor and the hardware processing unit are electrically connected to a memory respectively; the memory stores a data queue for storing hardware descriptors; The hardware descriptor is a data structure that describes information about data exchanged between the hardware processing unit and the processor; The method comprises: When the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, generating a target hardware descriptor carrying the target data according to a field definition of the hardware descriptor; The target hardware descriptor is written into the data queue, so that a receiver of the target data can read the target hardware descriptor from the data queue and obtain the target data from the target hardware descriptor.

3. The method according to claim 2, characterized in that The method is applicable to the processor; the data queue includes a first data queue, the hardware descriptor in the first data queue is a data structure describing information about data obtained by the hardware processing unit from the processor; the target data is target original data corresponding to a target computing request; the receiver of the target data is the hardware processing unit; When the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, generating a target hardware descriptor carrying the target data according to the field definition of the hardware descriptor includes: When the data volume of the target original data is less than or equal to a set first data volume threshold, generating a first hardware descriptor carrying the target original data as the target hardware descriptor according to the field definition of the hardware descriptor in the first data queue; Writing the target hardware descriptor into the data queue comprises: The first hardware descriptor is written into the first data queue, so that the hardware processing unit reads the first hardware descriptor from the first data queue, obtains the target original data from the first hardware descriptor, and calculates the target original data to obtain a target calculation result.

4. The method according to claim 3, characterized in that The hardware descriptor in the first data queue includes: a source address field and a target field, the source address field is used to record the memory address information of the data obtained by the hardware processing unit from the processor; the target field is a free field in the hardware descriptor in the first data queue; The step of generating a first hardware descriptor carrying the target original data according to the field definition of the hardware descriptor in the first data queue includes: According to the field definition of the hardware descriptor in the first data queue, the invalid first memory address information is written into the source address field of the first hardware descriptor, and the target original data is written into the target field of the first hardware descriptor to obtain the first hardware descriptor, so that the hardware processing unit can obtain the target original data from the first hardware descriptor when the memory address information stored in the source address information field of the first hardware descriptor is the invalid first memory address information.

5. The method according to claim 3 or 4, characterized in that: The data queue further includes: a second data queue; the hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing unit to the processor; the hardware processing unit generates a second hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue when the data volume of the target calculation result is less than or equal to the set second data volume threshold; and writes the second hardware descriptor into the second data queue; The method further comprises: The second hardware descriptor is read from the second data queue, and the target calculation result is obtained from the second hardware descriptor.

6. The method according to claim 5, characterized in that The hardware descriptor in the first data queue includes: a destination address field for recording memory address information of data provided by the hardware processing unit to the processor; The step of writing the invalid first memory address information into the source address field of the first hardware descriptor and writing the target original data into the target field of the first hardware descriptor according to the field definition of the hardware descriptor in the first data queue to obtain the first hardware descriptor comprises: According to the field definition of the hardware descriptor in the first data queue, writing the invalid first memory address information into the source address field of the first hardware descriptor, and writing the target original data into the target field of the first hardware descriptor; and When the data volume of the target calculation result is less than or equal to the second data volume threshold, invalid second memory address information is written into the destination address field of the first hardware descriptor to obtain the first hardware descriptor, so that the hardware processing unit can determine that the data volume of the target calculation result is less than or equal to the second data volume threshold when the memory address information stored in the destination address field of the first hardware descriptor is the invalid second memory address information.

7. The method according to claim 5, characterized in that The hardware descriptor in the second data queue further includes: a destination address field, which is used to record the memory address information of the data provided by the hardware processing unit to the processor; the hardware processing unit, when the data amount of the target calculation result is less than or equal to the second data amount threshold, writes the invalid second memory address information into the destination address field of the second hardware descriptor; The obtaining the target calculation result from the second hardware descriptor includes: When the memory address information stored in the destination address field of the second hardware descriptor is the invalid second memory address information, the target calculation result is obtained from the second hardware descriptor.

8. The method according to claim 3 or 4, characterized in that: The hardware descriptor in the first data queue further includes: an operation code field, which is used to record the operation code corresponding to the calculation request; the method further includes: In response to the target computing request, determining a target operation code corresponding to the target computing request; The step of generating a first hardware descriptor carrying the target original data according to the field definition of the hardware descriptor in the first data queue includes: According to the field definition of the hardware descriptor in the first data queue, the target opcode is written into the opcode field in the first hardware descriptor, and the target original data is written into the target field in the first hardware descriptor to obtain the first hardware operator, so that the hardware processing unit can obtain the target opcode from the opcode field of the first hardware descriptor; and the target original data is calculated according to the calculation method corresponding to the target opcode to obtain the target calculation result.

9. The method according to claim 2, characterized in that: The method is applicable to the hardware processing unit; the data queue includes: a second data queue; the hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing unit to the processor; the target data is data to be provided by the hardware processing unit to the processor; When the amount of target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold, generating a target hardware descriptor carrying the target data according to the field definition of the hardware descriptor includes: When the data volume of the target data is less than or equal to a set second data volume threshold, generating a third hardware descriptor carrying the target data as the target hardware descriptor according to the field definition of the hardware descriptor in the second data queue; Writing the target hardware descriptor into the data queue comprises: The third hardware descriptor is written into the second data queue, so that the processor reads the third hardware descriptor from the second data queue and obtains the target data from the third hardware descriptor.

10. The method according to claim 9, characterized in that The step of generating, according to the field definition of the hardware descriptor in the second data queue, a third hardware descriptor carrying the target calculation result as the target hardware descriptor comprises: According to the field definition of the hardware descriptor in the second data queue, the invalid second memory address information is written into the destination address field of the third hardware descriptor, and the target data is written into the target field of the third hardware descriptor, so that the processor can obtain the target data from the third hardware descriptor when the memory address information stored in the destination address field of the third hardware descriptor is the invalid second memory address information.

11. A data processing method, applicable to a hardware processing unit or processor, characterized in that: The processor and the hardware processing unit are electrically connected to a memory respectively; the memory stores a data queue for storing a hardware descriptor; the hardware descriptor is a data structure describing information of data exchanged between the hardware processing unit and the processor; The method comprises: Reading a target hardware descriptor from the data queue; the target hardware descriptor is a hardware descriptor carrying the target data generated by the provider of the target data according to the field definition of the hardware descriptor when the data amount of the target data to be exchanged between the hardware processing unit and the processor is less than or equal to a set data amount threshold; The target data is obtained from the target hardware descriptor.

12. The method according to claim 11, characterized in that: The method is applicable to a hardware processing unit, the data queue includes a first data queue; the hardware descriptor in the first data queue is a data structure describing information about data obtained by the hardware processing unit from the processor; the target data is target original data corresponding to a target computing request; The provider of the target data is the processor; The step of reading a target hardware descriptor from the data queue comprises: Reading a first hardware descriptor from the first data queue; the first hardware descriptor is a hardware descriptor carrying the target original data generated by the processor according to the field definition of the hardware descriptor in the first data queue when the data amount of the target original data corresponding to the target computing request is less than or equal to the set first data amount threshold; The method further comprises: The target original data is calculated to obtain a target calculation result corresponding to the target calculation request.

13. The method according to claim 12, characterized in that The hardware descriptor in the first data queue includes: a source address field and a target field, the source address field is used to record the memory address information of the data obtained by the hardware processing unit from the processor; when the data volume of the target original data is less than or equal to the set first data volume threshold, the processor writes the invalid first memory address information into the source address field of the first hardware descriptor according to the field definition of the hardware descriptor in the first data queue, and writes the target original data into the target field of the first hardware descriptor, so as to obtain the first hardware descriptor; The acquiring the target original data from the first hardware descriptor comprises: Acquire, from the first hardware descriptor, memory address information stored in a source address field of the first hardware descriptor; When the memory address information stored in the source address field of the first hardware descriptor is the invalid first memory address information, the target original data is obtained from the first hardware descriptor.

14. The method according to claim 12 or 13, characterized in that The memory further stores a second data queue; the hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing unit to the processor; the method further includes: When the data volume of the target calculation result is less than or equal to a set second data volume threshold, generating a second hardware descriptor carrying the target calculation result according to the field definition of the hardware descriptor in the second data queue; The second hardware descriptor is written into the second data queue, so that the processor reads the second hardware descriptor from the second data queue and obtains the target calculation result from the second hardware descriptor.

15. The method according to claim 14, characterized in that The hardware descriptor in the first data queue includes: a destination address field, which is used to record the memory address information of the data provided by the hardware processing unit to the processor; the processor writes the invalid second memory address information into the destination address field of the first hardware descriptor when the data amount of the target calculation result is less than or equal to the second data amount threshold; The method further comprises: Acquire, from the first hardware descriptor, memory address information stored in a destination address field of the first hardware descriptor; When the memory address information stored in the destination address field of the first hardware descriptor is the invalid second memory address information, it is determined that the data amount of the target calculation result is less than or equal to the second data amount threshold.

16. A hardware processing device, characterized in that: include: Memory access engine and calculation engine; The memory computing engine and the computing engine are electrically connected; The hardware processing device is used to be electrically connected to the memory, and the memory is electrically connected to the processor; The memory stores a second data queue, wherein the hardware descriptor in the second data queue is a data structure describing information of data provided by the hardware processing device to the processor; The computing engine is configured to generate a target hardware descriptor carrying the target data according to a field definition of the hardware descriptor when the amount of target data to be exchanged between the hardware processing device and the processor is less than or equal to a set data amount threshold; The memory access engine is used to write the target hardware descriptor into the second data queue, so that the processor can read the target hardware descriptor from the second data queue and obtain the target data from the target hardware descriptor.

17. The device according to claim 16, characterized in that The memory also stores a first data queue; the hardware descriptor in the first data queue is a data structure describing information of data obtained by the hardware processing device from the processor; The memory access engine is further used to: read a first hardware descriptor from the first data queue; and obtaining target original data corresponding to the target calculation result from the first hardware descriptor; The first hardware descriptor is a hardware descriptor carrying the target original data, generated by the processor according to the field definition of the hardware descriptor in the first data queue when the data volume of the target original data is less than or equal to the set first data volume threshold; The computing engine is further configured to compute the target original data to obtain a target computing result corresponding to the target computing request.

18. An electronic device, characterized in that: include: A memory and a processor; the memory includes a memory and other storage media; the processor is electrically connected to the memory; The memory is used to be electrically connected to the hardware processing unit; The other storage medium is used to store the computer program; The memory stores a data queue; the hardware descriptor in the data queue is a data structure describing information about data to be exchanged between the hardware processing unit and the processor; The processor is coupled to the memory and the other storage media, and is configured to execute the computer program for executing the steps in the method of any one of claims 2-8 and 11.

19. A computer-readable storage medium storing computer instructions, characterized in that: When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the method according to any one of claims 2 to 15.

20. A computer program product, characterized in that The method comprises a computer program which, when executed by one or more processors, causes the one or more processors to execute the steps of the method according to any one of claims 2 to 15.

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