Computation graph execution method and device, equipment, storage medium and program product

Abstract

The invention relates to a calculation graph execution method and device, computer equipment, a computer readable storage medium and a computer program product. The method is applied to the computer equipment, the equipment comprises a reconfigurable processor and a memory, the reconfigurable processor comprises a plurality of computing units, the memory comprises a plurality of storage units, and the method comprises the steps that a preset computing graph is obtained, and the computing graph comprises a plurality of nodes and side information corresponding to the nodes; for each node, determining a target calculation unit and a target storage unit corresponding to the node according to node information corresponding to the node and the side information; according to the target calculation units and the target storage unit, operation instructions corresponding to the nodes are generated, and all the operation instructions are operated through all the target calculation units. By adopting the method, the access overhead of the memory can be reduced.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a computational graph execution method, apparatus, computer device, computer-readable storage medium, and computer program product. Background Art

[0002] A reconfigurable processor is a flexible and programmable processor architecture that can flexibly configure hardware resources according to different application requirements and algorithm characteristics. In a reconfigurable processor, memory and data access directly affect the execution efficiency of the algorithm and the performance of the system.

[0003] In traditional technology, the memory structure is optimized to improve the memory access efficiency. However, in large-scale data processing scenarios, the reconfigurable processor still has the problem of high memory access overhead when executing the computation graph. Summary of the invention

[0004] Based on this, it is necessary to provide a computational graph execution method, apparatus, computer device, computer-readable storage medium and computer program product that can reduce memory access overhead in order to address the above technical problems.

[0005] In a first aspect, the present application provides a computational graph execution method. For a computer device, the device includes a reconfigurable processor and a memory, the reconfigurable processor includes a plurality of computing units, the memory includes a plurality of storage units, and the method includes:

[0006] Obtain a preset computational graph, the computational graph comprising a plurality of nodes and edge information corresponding to each of the nodes;

[0007] For each of the nodes, determining a target computing unit and a target storage unit corresponding to the node according to the node information corresponding to the node and the edge information;

[0008] According to the target computing unit and the target storage unit, a computing instruction corresponding to the node is generated, and each of the computing instructions is executed through each of the target computing units.

[0009] In one embodiment, the node information includes a computing requirement corresponding to the node, and determining a target computing unit and a target storage unit corresponding to the node according to the node information corresponding to the node and the edge information includes:

[0010] According to the computing requirement, determining the target computing unit from the computing units;

[0011] The target storage unit is determined from the storage units according to the side information.

[0012] In one embodiment, determining the target storage unit from each of the storage units according to the side information includes:

[0013] Determine a candidate storage unit from each of the storage units according to the side information;

[0014] Determining the access type of the node according to the historical access times of the node;

[0015] The target storage unit is determined from each of the candidate storage units according to the access type.

[0016] In one embodiment, the method further comprises:

[0017] According to each of the edge information, a plurality of associated nodes having an associated relationship are determined from each of the nodes;

[0018] If the storage position of the target storage unit corresponding to each of the associated nodes does not meet the preset conditions, the associated storage units corresponding to each of the associated nodes are re-determined from each of the storage units based on the edge information, and the associated storage units meet the preset conditions, and the preset conditions are that the difference between the storage addresses of the target storage units corresponding to each of the associated nodes is less than a preset threshold.

[0019] In one embodiment, the executing each of the operation instructions through each of the target computing units includes:

[0020] Obtaining the execution priority of each of the nodes, and determining the execution order of each of the nodes according to the priority and the computing requirement;

[0021] According to the execution order, each of the operation instructions is executed by each of the target computing units.

[0022] In one embodiment, the operation instruction includes a calculation operation instruction and a data transfer instruction, and generating the operation instruction according to the target computing unit and the target storage unit includes:

[0023] generating the computing operation instruction according to the computing requirement of the target computing unit;

[0024] The data transfer instruction is generated according to the side information and the storage location of the target storage unit.

[0025] In a second aspect, the present application also provides a computational graph execution device. For use in a computer device, the device includes a reconfigurable processor and a memory, the reconfigurable processor includes a plurality of computing units, the memory includes a plurality of storage units, and the device includes:

[0026] An acquisition module is used to acquire a preset computational graph, wherein the computational graph includes a plurality of nodes and edge information corresponding to each of the nodes;

[0027] A first determination module is used to determine, for each of the nodes, a target computing unit and a target storage unit corresponding to the node according to the node information corresponding to the node and the edge information;

[0028] An operation module is used to generate a computing instruction corresponding to the node according to the target computing unit and the target storage unit, and to execute each of the computing instructions through each of the target computing units.

[0029] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in the first aspect are implemented.

[0030] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0031] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0032] The above-mentioned calculation graph execution method, device, computer equipment, computer-readable storage medium and computer program product, the computer equipment obtains a preset calculation graph, the calculation graph includes multiple nodes and edge information corresponding to each node, then, for each node, according to the node information and edge information corresponding to the node, the target computing unit and target storage unit corresponding to the node are determined, and then, according to the target computing unit and the target storage unit, the operation instruction corresponding to the node is generated, and each operation instruction is executed through each target computing unit. Since the target computing unit is determined according to the node information, the determined target computing unit can satisfy the node information of each node, and the target storage unit is determined according to the edge information, so that the determined target storage unit can satisfy the data dependency corresponding to the edge information, so that in the process of running each operation instruction, the storage unit accessed during the data transmission process can be quickly and accurately determined, thereby reducing the number of accesses to the memory and reducing the access overhead of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] FIG1 is a diagram of an application environment of a computation graph execution method in one embodiment;

[0035] FIG2 is a schematic diagram of a flow chart of a method for executing a computational graph in one embodiment;

[0036] FIG3 is a schematic diagram of a flow chart of a method for executing a computational graph in another embodiment;

[0037] FIG4 is a schematic diagram of a flow chart of a method for executing a computational graph in another embodiment;

[0038] FIG5 is a schematic diagram of a flow chart of S203 in another embodiment;

[0039] FIG6 is a schematic diagram of the flow chart of S203 in another embodiment;

[0040] FIG7 is a block diagram of a computation graph execution device in one embodiment;

[0041] FIG. 8 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] In traditional technology, there are several methods to optimize the performance of processors and memories. The first is to optimize the memory hierarchy, for example, data cache optimization, locality optimization, and memory prefetch optimization. The second is direct memory access technology, which is used to achieve high-speed data transmission between host memory and peripherals, reduce CPU load and improve system parallelism. In reconfigurable processors, DMA technology is often used to achieve data exchange with external memory. The third is to design on-chip memory and memory controller. This method is used to improve the efficiency and bandwidth of memory access, for example, optimization of cache, local memory and memory channel, and memory controller that supports high-bandwidth data transmission and parallel computing. The fourth is compilation optimization technology. In reconfigurable processors, compilers play a vital role. Compiler optimization technology can significantly affect the performance and execution efficiency of programs. Compilation optimization technology can include instruction scheduling, data rearrangement, loop unrolling and vectorization optimization to improve the parallelism and data locality of programs. The fifth is to optimize memory technology. New memory technologies such as non-volatile memory, 3D stacked memory and memory storage level memory are constantly emerging. These new memory technologies are of great significance for memory and data access of reconfigurable processors, and can improve memory capacity, bandwidth and energy efficiency.

[0044] However, in the hardware architecture of reconfigurable processors, if the computing scenario is large-scale and requires high parallelism for data processing, traditional memory access technology often cannot meet the high performance requirements of the processor; moreover, in data transmission, additional delays and energy consumption overhead are usually introduced, especially for data exchange with external memory. Memory access scheduling is also a complex issue. In the memory access scheduling algorithm, factors such as data dependency, load balancing, and hardware resource allocation need to be considered. However, existing memory access scheduling algorithms often cannot make full use of hardware resources, resulting in performance loss and resource waste. In addition, in the memory and data management methods of reconfigurable processors, there is a lack of direct control methods under the programming model, which makes it impossible for developers to effectively customize and optimize the memory and data management of the processor. At the same time, the abstraction level provided by the classic programming language is too high and cannot meet the refined requirements for memory and data management in certain application scenarios.

[0045] Therefore, in the conventional technology, in the large-scale data processing scenario, when the reconfigurable processor executes the computation graph, the memory access overhead is large. Based on this, the present application proposes a computation graph execution method to reduce the memory access overhead.

[0046] The calculation graph execution method provided in the embodiment of the present application can be applied to the application environment shown in Figure 1. Figure 1 includes a computer device, which includes a reconfigurable processor 102 and a memory 104, wherein the reconfigurable processor 102 includes multiple computing units, and the memory 104 includes multiple storage units. The computer device can obtain a preset calculation graph, which includes multiple nodes and edge information corresponding to each node. For each node, the computer device determines the target computing unit and target storage unit corresponding to the node according to the node information and edge information corresponding to the node. The computer device generates the operation instructions corresponding to the node according to the target computing unit and the target storage unit, and runs each operation instruction through each target computing unit. Among them, the memory 104 is used to store data that the reconfigurable processor 102 needs to process. The memory 104 may include an external memory and an on-chip memory.

[0047] In an exemplary embodiment, as shown in FIG2 , a computation graph execution method is provided, which is described by taking the method applied to the computer device in FIG1 as an example, and includes the following steps:

[0048] S201, obtaining a preset computational graph, where the computational graph includes multiple nodes and edge information corresponding to each node.

[0049] Among them, a computational graph is a data structure used to represent a computational process. A computational graph is a set of graphs consisting of nodes and edges, wherein a node identifier represents a basic operation or computational unit in a computational task, such as addition, multiplication, logical operation, etc. Each node usually has input and output ports for receiving and sending data. An edge represents the transmission relationship of data in a computational task, and an edge connects the input and output ports between different nodes, indicating the path of data flow. In this embodiment, the node connected by each edge is determined as edge information.

[0050] The data flow corresponding to the computational graph describes the data dependency in the computational task, that is, the computation result of a node may be used as the input data of another node, thus forming a data flow path. Among them, data dependency refers to the dependency between related nodes. For example, if the computation result of node A affects the computation process of node B, it means that node B depends on the data of node A. Data dependency can be divided into control dependency and data dependency. Control dependency refers to the control flow dependency in the computational task, and data dependency refers to the data transmission dependency in the computational task.

[0051] It should be noted that in the embodiment of the present application, in order to solve the problem that there is a lack of direct control methods under the programming model during the execution of the calculation graph by the reconfigurable processor, which makes it impossible for developers to effectively customize and optimize the memory and data management of the processor, and at the same time, the abstract level provided by the classic programming language is too high to meet the refined requirements for memory and data management in certain application scenarios. A domain specific language (DSL) is used to program the calculation graph, so that the programming results of the DSL language are heterogeneously programmed in the reconfigurable processor. Therefore, in this embodiment, the preset calculation graph is the calculation graph corresponding to the DSL language. Among them,

[0052] In this embodiment, the computer device can obtain the calculation graph to be run from the calculation graph database in advance, wherein the obtained operation graph includes multiple nodes and edges for connecting each node. By obtaining the calculation graph, the multiple nodes included in the calculation graph and the edge information corresponding to each node can be obtained.

[0053] S202, for each node, determine the target computing unit and the target storage unit corresponding to the node according to the node information and edge information corresponding to the node.

[0054] Node information refers to the data, data type, operation type, input node, output node, etc. corresponding to each node. Edge information refers to the nodes connected by each edge, as well as the data flow path information between the input data node and the output data node.

[0055] The computing unit is a component in the processor for performing arithmetic operations or logical operations, and the storage unit is a storage space in the memory for storing data to realize data reading and data writing functions. In this embodiment, the target storage unit is a storage unit that can satisfy the edge information. It can be understood that before the computer device executes the calculation graph, it needs to map the calculation graph to the computer device, that is, map the nodes in the calculation graph to the computing units in the processor, and map the data to be processed to the storage unit of the processor. Therefore, in this embodiment, the target computing unit refers to the computing unit that can satisfy the node information of the node, and the target storage unit refers to the storage unit that will satisfy the edge information.

[0056] In this embodiment, the computer device can determine, based on the node information corresponding to the node, a computing unit that satisfies the node information from multiple computing units as a target computing unit, and determine a storage unit that satisfies the edge information from multiple storage units as a target storage unit. It can be understood that one target computing unit can correspond to multiple target storage units, and multiple target storage units can be used to store input data and output data corresponding to the target computing unit.

[0057] S203, generating operation instructions corresponding to the node according to the target computing unit and the target storage unit, and executing each operation instruction through each target computing unit.

[0058] The operation instruction refers to a computer program that instructs the target computing unit to perform data processing operations. It can be understood that since the target computing unit is determined according to the node, the operation instruction generated according to the target computing unit is the operation instruction corresponding to the node.

[0059] In this embodiment, the computer device can generate operation instructions according to the data processing type and processing requirements corresponding to each target computing unit, and then compile the operation instructions by controlling the compiler to execute each operation instruction through each target computing unit. It can be understood that in this embodiment, if the node information indicates that the node can be processed in parallel, the target computing unit corresponding to the node can execute the operation instruction in parallel with the target computing unit that can also be processed in parallel.

[0060] As an optional implementation, if multiple nodes correspond to one target computing unit, the generated operation instructions can be used as the operation instructions corresponding to the multiple nodes.

[0061] In the above-mentioned calculation graph execution method, the computer device obtains a preset calculation graph, which includes multiple nodes and edge information corresponding to each node. Then, for each node, the target computing unit and target storage unit corresponding to the node are determined according to the node information and edge information corresponding to the node. Then, according to the target computing unit and the target storage unit, the operation instruction corresponding to the node is generated, and each operation instruction is executed through each target computing unit. Since the target computing unit is determined according to the node information, the determined target computing unit can satisfy the node information of each node, and the target storage unit is determined according to the edge information, so that the determined target storage unit can satisfy the data dependency corresponding to the edge information, so that in the process of running each operation instruction, the storage unit accessed during the data transmission process can be quickly and accurately determined, thereby reducing the number of accesses to the memory and reducing the access overhead of the memory.

[0062] In the process of determining the target computing unit and the target storage unit, the computer device may determine the target computing unit according to the computing requirements corresponding to the node, and determine the target storage unit according to the edge information. In an exemplary embodiment, the node information includes the computing requirements corresponding to the node, and the specific process of S202 may include:

[0063] In a possible implementation, a target computing unit is determined from various computing units according to computing requirements.

[0064] The computing demand refers to the computing resources required to run the corresponding computer program when processing the to-be-processed data corresponding to each node, for example, CPU resources, memory resources, network resources such as bandwidth, hard disk resources, parallel requirements, etc. It should be noted that the processing performance of different computing units in the processor may be different. Therefore, it is necessary to select a computing unit that can meet the computing demand of the node from the multiple computing units included in the processor as the corresponding target computing unit.

[0065] In this embodiment, the computer device may screen computing units that meet the computing requirements of each node from various computing units according to the computing requirements of each node, thereby determining the computing units that meet the computing requirements as target computing units.

[0066] In another possible implementation, the target storage unit is determined from the storage units according to the side information.

[0067] The edge information represents the data dependency between nodes in the computation graph, that is, the edge information can represent the flow path of the data transmitted between nodes. During the data transmission process, it may involve which storage unit the data is read from and which storage unit the data is written to. Therefore, the target storage unit can be determined based on the edge information.

[0068] In this embodiment, the computer device can determine the data dependency relationship between the nodes based on the side information, and then determine the storage unit corresponding to the input data and output data of each node based on the data dependency relationship, thereby determining the corresponding storage unit as the target storage unit.

[0069] In the above “determining the target storage unit from each storage unit according to the side information”, as shown in FIG3 , the process may include:

[0070] S301, determining a candidate storage unit from each storage unit according to the side information.

[0071] Among them, the candidate storage unit refers to a computing unit that can meet the storage requirements of the input data and output data of each node. For example, if the input data of node A includes 100 bytes, the storage capacity of storage unit 1 is 256 bytes, the storage capacity of storage unit 2 is 20 bytes, and the storage capacity of storage unit 3 is 120 bytes, then storage unit 1 and storage unit 3 can both be candidate storage units of node A.

[0072] In this embodiment, the computer device may determine the data dependency relationship between the nodes according to the side information, and then determine the computing units that satisfy the data dependency relationship and the data storage requirements as candidate storage units.

[0073] S302: Determine the access type of the node according to the historical access times of the node.

[0074] The historical number of visits to a node refers to the number of visits to the node within a historical time period. The historical number of visits can be used to determine whether each node is frequently visited, thereby determining the access type of each node, wherein the access type may include frequent visits or infrequent visits.

[0075] In this embodiment, a threshold of the number of visits can be set in advance. If the number of historical visits to a node is greater than or equal to the threshold, the access type of the node can be determined to be frequent visits. If the number of historical visits to a node is less than the threshold, the access type of the node can be determined to be infrequent visits.

[0076] S303: Determine a target storage unit from each candidate storage unit according to the access type.

[0077] It is understandable that the storage medium of the storage unit is different, and the corresponding access speed is also different. In the embodiment of the present application, in order to improve the overall access efficiency and improve the utilization rate of storage resources, the data corresponding to the node can be stored in storage units with different access speeds according to the access frequency of the node. It should be noted that the memory can be divided into memories with different access speeds, for example, external memories or on-chip memories, wherein the on-chip memory refers to memories directly integrated inside the integrated circuit chip, which are usually located inside the CPU, such as the first-level cache (Level 1 Cache) and the second-level cache (Level 2 Cache), which are used to improve data processing speed and efficiency. The types of on-chip memories include static random access memory and dynamic random access memory, wherein static random access memory is usually used for high-speed caching due to its faster speed, and dynamic random access memory is used for main memory due to its lower cost and larger capacity. External memory refers to storage other than computer memory and CPU cache. This type of storage can generally still save data after power failure. Common external storage includes hard disks, floppy disks, CDs, USB flash drives, etc. The access speed of external storage is lower than that of on-chip memory.

[0078] Optionally, in this embodiment, if the access type of the node is frequent access, the data corresponding to the node can be stored in a storage unit with a faster access speed, thereby determining the storage unit with a faster access speed among the candidate storage units as the target storage unit; if the access type of the node is infrequent access, the data corresponding to the node can be stored in a storage unit with a slower access speed, thereby determining the storage unit with a slower access speed among the candidate storage units as the target storage unit.

[0079] In this embodiment, the computer device determines a candidate storage unit from each storage unit based on the edge information, and then determines the access type of the node based on the historical number of accesses to the node, and determines the target storage unit from each candidate storage unit based on the access type. The data corresponding to nodes of different access types can be stored in the corresponding target storage unit, thereby improving the matching degree between the target storage unit and the data corresponding to the node. For example, the data of frequently accessed nodes is stored in a storage unit with a higher access speed, and the data of infrequently accessed nodes is stored in a storage unit with a lower access speed. This can improve the reading speed and writing speed of data in the process of running operation instructions, while improving the utilization of memory resources and maximizing the performance and efficiency of the computer system.

[0080] In this embodiment, the computer device determines the target computing unit from each computing unit according to the computing requirements, and determines the target storage unit from each storage unit according to the side information, so that the determined target computing unit can meet the computing requirements of the node, and the determined target storage unit can meet the data dependency corresponding to the side information, thereby improving the data access speed and reducing the memory access delay and data transmission time in the process of running the operation instructions, thereby effectively utilizing the computing resources inside the processor and the storage units in the memory.

[0081] After determining the target computing unit and the target storage unit, in order to further improve the speed of data access, a data reorganization method can also be used to store data with associated relationships in storage units with similar physical locations. In an exemplary embodiment, as shown in FIG4 , the method includes:

[0082] S401, determining a plurality of associated nodes having an associated relationship from among the nodes according to each edge information.

[0083] Among them, associated nodes refer to multiple nodes with data dependency relationships. For example, if the processing data of node A comes from node B, then node A and node B are associated nodes with an associated relationship; or, if the calculation result of node A is output to node C, then node A and node C are associated nodes with an associated relationship.

[0084] In this embodiment, the computer device may determine the data dependency relationship corresponding to each edge information according to each edge information, and then determine the associated node corresponding to each node according to the data dependency relationship. For example, if the computer device determines that node A has data dependency relationships with node B and node C respectively according to the edge information, node B and node C may be determined as the associated nodes of node A.

[0085] S402, if the storage location of the target storage unit corresponding to each associated node does not meet the preset condition, then the associated storage unit corresponding to each associated node is re-determined from each storage unit according to the edge information, and the associated storage unit meets the preset condition, and the preset condition is that the difference between the storage addresses of the target storage units corresponding to each associated node is less than a preset threshold.

[0086] It is understandable that when the computing unit in the computer device runs the operation instruction, it needs to read data from the storage unit 1, calculate the data to obtain the data result, and then write the data result into the storage unit 2. During the data transmission process, if the physical positions of the storage unit 1 and the storage unit 2 are close, the time spent on the data transmission process is relatively short. If the physical positions of the storage unit 1 and the storage unit 2 are relatively far, the time spent on the data transmission process is relatively long. Therefore, the storage address of the target storage unit corresponding to the associated node can be calculated, so as to determine whether the physical positions of the target storage units corresponding to the associated nodes are close according to the calculation result. In this embodiment, the difference between the storage addresses of the target storage units corresponding to each associated node can be determined as a preset condition that is less than a preset threshold. If the associated node does not meet the preset condition, the associated storage unit corresponding to each associated node is re-determined.

[0087] The associated storage unit corresponding to each associated node refers to a storage unit that satisfies both the data dependency relationship corresponding to the edge information and the preset conditions.

[0088] In this embodiment, the computer device can obtain the storage address according to the storage position of the target storage unit corresponding to each associated node, and then calculate the difference between each storage address, and then determine whether the difference is less than a preset threshold value. If the difference is less than the preset threshold value, it can be determined that the storage position of the target storage unit corresponding to each associated node meets the preset condition; if the difference is greater than the preset threshold value, it can be determined that the storage position of the target storage unit corresponding to each associated node does not meet the preset condition. Then, the computer device can redetermine the storage unit that meets the side information from each storage unit according to the side information, and when the redetermined storage unit that meets the side information meets the preset condition, the redetermined storage unit that meets the side information is determined as the associated storage unit.

[0089] Optionally, the associated storage unit may be a storage unit that satisfies the side information and is continuous; or, the associated storage unit may be a storage unit that satisfies the side information and is discontinuous. If the associated storage unit may be a storage unit that satisfies the side information and is continuous, the locality and continuity of data access may be optimized, and the randomness and fragmentation of memory access may be reduced.

[0090] In this embodiment, the computer device can determine multiple associated nodes with an associated relationship from each node based on each edge information, so that when the storage position of the target storage unit corresponding to each associated node does not meet the preset condition, the associated storage unit corresponding to each associated node can be re-determined from each storage unit. Since the associated storage unit satisfies the preset condition that the difference between the storage addresses of the target storage units corresponding to each associated node is less than the preset threshold, when the storage position of the target storage unit corresponding to each associated node does not meet the preset condition, the associated storage unit corresponding to each associated node can be re-determined to obtain the associated storage unit that satisfies both the edge information and the preset condition, thereby reducing the time for accessing the storage unit and improving the data access efficiency and the running speed of the operation instructions.

[0091] In the above scenario where each of the target computing units executes each of the operation instructions, the computer device may also adjust the execution order of the operation instructions according to the execution priority of each node. In an exemplary embodiment, as shown in FIG5 , the above S203 includes:

[0092] S501, obtaining the execution priority of each node, and determining the execution order of each node according to the priority and computing requirements.

[0093] The execution priority is a parameter that determines the priority of each operating program to receive system resources when the computer time-sharing operating system processes multiple operating programs. The higher priority is executed first, and the lower priority is executed later. In this embodiment, in order to improve the overall efficiency of executing the calculation graph, the execution order of each node can be adjusted according to the execution priority of each node.

[0094] In this embodiment, the computer device can obtain the execution priority from the node information of each node, and then determine whether the computing resources in the computer device can meet the high-priority computing requirements. If so, the execution order of the high-priority nodes can be advanced and the execution order of the low-priority nodes can be postponed.

[0095] S502, executing each operation instruction through each target computing unit according to the execution order.

[0096] In this embodiment, after determining the execution order of each node, the computer device can control the target computing unit corresponding to each node to execute each operation instruction in turn according to the execution order.

[0097] In this embodiment, the computer device can determine the execution order of each node according to the priority and computing requirements by obtaining the execution priority of each node, so that each operation instruction can be run through each target computing unit according to the execution order. Since the order and priority of memory access are adjusted by adjusting the execution order, the bandwidth and parallelism of data transmission can be maximized and the delay of memory access can be reduced.

[0098] In the above scenario where each of the target computing units executes each of the operation instructions, the computer device may generate a computing operation instruction according to the computing requirements, and according to an exemplary embodiment, as shown in FIG6 , the above S203 includes:

[0099] S601, generating a computing operation instruction according to the computing requirements of the target computing unit.

[0100] The computing operation instruction refers to a computer program that instructs the computing unit to perform data operations. For example, the computing operation instruction may be an addition operation, a multiplication operation, a logical AND operation, a logical OR operation, etc. It is understandable that the computing requirements corresponding to each target computing unit are different, and the computing operation instructions corresponding to each target computing unit are also different.

[0101] In this embodiment, the computer device can generate a computing operation instruction corresponding to each target computing unit according to the computing requirements corresponding to each target computing unit. For example, if the computing requirement of the target computing unit is to perform an addition operation, the computing operation instruction can be to instruct the target computing unit to perform the addition operation.

[0102] S602, generating a data transmission instruction according to the side information and the storage location of the target storage unit.

[0103] The data transfer instruction is a computer program that instructs the target computing unit to read data from the target storage unit and / or write data to the target storage unit.

[0104] In this embodiment, the computer device can determine the flow path of data during the operation instruction execution according to the side information, and then generate the data transmission instruction corresponding to each target storage unit according to the storage position and flow path of the target storage unit. Exemplarily, if the data flow path is target storage unit 1-target storage unit 2, the data transmission instruction can be to instruct the target computing unit to obtain data from target storage unit 1, and after data processing, instruct the target computing unit to write the data processing result into target storage unit 2.

[0105] In this embodiment, since the computing operation instructions are generated according to the computing requirements of the target computing unit, and the data transfer instructions are generated according to the side information and the storage location of the target storage unit, the target computing unit can efficiently and accurately execute the computing instructions according to the generated computing operation instructions and data transfer instructions, thereby improving the efficiency of running the computing instructions.

[0106] To facilitate understanding by those skilled in the art, the following is a detailed introduction to the computational graph execution method provided by the present application. The method is used in a computer device, the device includes a reconfigurable processor and a memory, the reconfigurable processor includes a plurality of computing units, the memory includes a plurality of storage units, and the method may include:

[0107] S1, obtain the preset calculation graph.

[0108] S2: Determine the target computing unit from each computing unit according to the computing requirements of the node.

[0109] S3, determining a candidate storage unit from each storage unit according to the side information.

[0110] S4, determining the access type of the node according to the historical access times of the node, and determining the target storage unit from each storage unit according to the access type.

[0111] S5, determining a plurality of associated nodes having an associated relationship from each node according to each edge information.

[0112] S6: If the storage location of the target storage unit corresponding to each associated node does not meet the preset condition, then re-determine the associated storage unit corresponding to each associated node from each storage unit according to the side information.

[0113] S7, generating a computing operation instruction according to the computing requirements of the target computing unit.

[0114] S8, generating a data transmission instruction according to the side information and the storage location of the target storage unit.

[0115] S9, obtaining the execution priority of each node, and determining the execution order of each node according to the priority and computing requirements.

[0116] S10, executing each operation instruction through each target computing unit according to the execution order.

[0117] It should be noted that for the description in the above S1-S10, reference may be made to the relevant description in the above embodiment, and the effects are similar, which will not be repeated in this embodiment.

[0118] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0119] Based on the same inventive concept, the embodiment of the present application also provides a computational graph execution device for implementing the computational graph execution method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more computational graph execution device embodiments provided below can refer to the limitations on the computational graph execution method above, and will not be repeated here.

[0120] In one embodiment, as shown in FIG. 7 , a computation graph execution device is provided, including: an acquisition module 701, a first determination module 702, and an operation module 703, wherein:

[0121] The acquisition module 701 is used to acquire a preset computation graph, where the computation graph includes multiple nodes and edge information corresponding to each node;

[0122] A first determination module 702 is used to determine, for each node, a target computing unit and a target storage unit corresponding to the node according to the node information and edge information corresponding to the node;

[0123] The running module 703 is used to generate a computing instruction corresponding to the node according to the target computing unit and the target storage unit, and run each computing instruction through each target computing unit.

[0124] The computation graph execution device provided in this embodiment can execute the above method embodiments, and its implementation principles and technical effects are similar, which will not be repeated here.

[0125] In one embodiment, the node information includes the computing requirements corresponding to the node. The first determining module 802 includes: a first determining unit and a second determining unit, wherein:

[0126] A first determining unit, configured to determine a target computing unit from among the computing units according to a computing requirement;

[0127] The second determining unit is used to determine a target storage unit from each storage unit according to the side information.

[0128] The computation graph execution device provided in this embodiment can execute the above method embodiments, and its implementation principles and technical effects are similar, which will not be repeated here.

[0129] In one embodiment, the second determining unit is specifically configured to:

[0130] Determine a candidate storage unit from each storage unit according to the side information;

[0131] Determine the access type of the node based on the historical access times of the node;

[0132] According to the access type, a target storage unit is determined from each candidate storage unit.

[0133] The computation graph execution device provided in this embodiment can execute the above method embodiments, and its implementation principles and technical effects are similar, which will not be repeated here.

[0134] In one embodiment, the above device further comprises:

[0135] A second determination module is used to determine a plurality of associated nodes having an associated relationship from each node according to each edge information;

[0136] The third determination module is used to redetermine the associated storage units corresponding to each associated node from each storage unit based on the side information if the storage position of the target storage unit corresponding to each associated node does not meet the preset condition, and the associated storage unit meets the preset condition, and the preset condition is that the difference between the storage addresses of the target storage units corresponding to each associated node is less than a preset threshold.

[0137] The computation graph execution device provided in this embodiment can execute the above method embodiments, and its implementation principles and technical effects are similar, which will not be repeated here.

[0138] In one embodiment, the operation module 803 includes:

[0139] A third determination unit is used to obtain the execution priority of each node and determine the execution order of each node according to the priority and computing requirements;

[0140] The execution unit is used to execute each operation instruction through each target computing unit according to the execution order.

[0141] The computation graph execution device provided in this embodiment can execute the above method embodiments, and its implementation principles and technical effects are similar, which will not be repeated here.

[0142] In one embodiment, the operation instruction includes a calculation operation instruction and a data transmission instruction, and the operation module 803 includes:

[0143] A first generating unit, used for generating a computing operation instruction according to a computing requirement of a target computing unit;

[0144] The second generating unit is used to generate a data transmission instruction according to the side information and the storage location of the target storage unit.

[0145] The computation graph execution device provided in this embodiment can execute the above method embodiments, and its implementation principles and technical effects are similar, which will not be repeated here.

[0146] Each module in the above-mentioned computation graph execution device can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each of the above modules.

[0147] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in FIG8. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store node data and edge data corresponding to the calculation graph. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a calculation graph execution method is implemented.

[0148] Those skilled in the art will understand that the structure shown in FIG. 8 is merely a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0149] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0150] Get a preset computational graph, which includes multiple nodes and edge information corresponding to each node;

[0151] For each node, determine the target computing unit and target storage unit corresponding to the node according to the node information and edge information corresponding to the node;

[0152] According to the target computing unit and the target storage unit, a computing instruction corresponding to the node is generated, and each computing instruction is executed through each target computing unit.

[0153] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0154] According to the computing requirements, a target computing unit is determined from among the computing units;

[0155] According to the side information, a target storage unit is determined from each storage unit.

[0156] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0157] Determine a candidate storage unit from each storage unit according to the side information;

[0158] Determine the access type of the node based on the historical access times of the node;

[0159] According to the access type, a target storage unit is determined from each candidate storage unit.

[0160] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0161] According to each edge information, multiple associated nodes having an associated relationship are determined from each node;

[0162] If the storage position of the target storage unit corresponding to each associated node does not meet the preset conditions, the associated storage unit corresponding to each associated node is re-determined from each storage unit based on the edge information, and the associated storage unit meets the preset conditions, and the preset condition is that the difference between the storage addresses of the target storage units corresponding to each associated node is less than the preset threshold.

[0163] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0164] Obtain the execution priority of each node, and determine the execution order of each node based on the priority and computing requirements;

[0165] Each operation instruction is executed by each target computing unit in the execution order.

[0166] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0167] Generate computing operation instructions according to the computing requirements of the target computing unit;

[0168] Generate data transfer instructions based on the side information and the storage location of the target storage unit.

[0169] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0170] Get a preset computational graph, which includes multiple nodes and edge information corresponding to each node;

[0171] For each node, determine the target computing unit and target storage unit corresponding to the node according to the node information and edge information corresponding to the node;

[0172] According to the target computing unit and the target storage unit, a computing instruction corresponding to the node is generated, and each computing instruction is executed through each target computing unit.

[0173] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0174] According to the computing requirements, a target computing unit is determined from among the computing units;

[0175] According to the side information, a target storage unit is determined from each storage unit.

[0176] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0177] Determine a candidate storage unit from each storage unit according to the side information;

[0178] Determine the access type of the node based on the historical access times of the node;

[0179] According to the access type, a target storage unit is determined from each candidate storage unit.

[0180] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0181] According to each edge information, multiple associated nodes having an associated relationship are determined from each node;

[0182] If the storage position of the target storage unit corresponding to each associated node does not meet the preset conditions, the associated storage unit corresponding to each associated node is re-determined from each storage unit based on the edge information, and the associated storage unit meets the preset conditions, and the preset condition is that the difference between the storage addresses of the target storage units corresponding to each associated node is less than the preset threshold.

[0183] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0184] Obtain the execution priority of each node, and determine the execution order of each node based on the priority and computing requirements;

[0185] Each operation instruction is executed by each target computing unit in the execution order.

[0186] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0187] Generate computing operation instructions according to the computing requirements of the target computing unit;

[0188] Generate data transfer instructions based on the side information and the storage location of the target storage unit.

[0189] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0190] Get a preset computational graph, which includes multiple nodes and edge information corresponding to each node;

[0191] For each node, determine the target computing unit and target storage unit corresponding to the node according to the node information and edge information corresponding to the node;

[0192] According to the target computing unit and the target storage unit, a computing instruction corresponding to the node is generated, and each computing instruction is executed through each target computing unit.

[0193] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0194] According to the computing requirements, a target computing unit is determined from among the computing units;

[0195] According to the side information, a target storage unit is determined from each storage unit.

[0196] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0197] Determine a candidate storage unit from each storage unit according to the side information;

[0198] Determine the access type of the node based on the historical access times of the node;

[0199] A target storage unit is determined from each candidate storage unit according to the access type.

[0200] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0201] According to each edge information, multiple associated nodes having an associated relationship are determined from each node;

[0202] If the storage position of the target storage unit corresponding to each associated node does not meet the preset conditions, the associated storage unit corresponding to each associated node is re-determined from each storage unit based on the edge information, and the associated storage unit meets the preset conditions, and the preset condition is that the difference between the storage addresses of the target storage units corresponding to each associated node is less than the preset threshold.

[0203] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0204] Obtain the execution priority of each node, and determine the execution order of each node based on the priority and computing requirements;

[0205] Each operation instruction is executed by each target computing unit in the execution order.

[0206] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0207] Generate computing operation instructions according to the computing requirements of the target computing unit;

[0208] Generate data transfer instructions based on the side information and the storage location of the target storage unit.

[0209] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0210] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0211] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A computational graph execution method, characterized in that: For a computer device, the device comprises a reconfigurable processor and a memory, the reconfigurable processor comprises a plurality of computing units, the memory comprises a plurality of storage units, the method comprises: Obtain a preset computational graph, the computational graph comprising a plurality of nodes and edge information corresponding to each of the nodes; For each of the nodes, determining a target computing unit and a target storage unit corresponding to the node according to the node information corresponding to the node and the edge information; According to the target computing unit and the target storage unit, a computing instruction corresponding to the node is generated, and each of the computing instructions is executed through each of the target computing units.

2. The method according to claim 1, characterized in that The node information includes a computing requirement corresponding to the node, and determining a target computing unit and a target storage unit corresponding to the node according to the node information corresponding to the node and the edge information includes: According to the computing requirement, determining the target computing unit from the computing units; The target storage unit is determined from the storage units according to the side information.

3. The method according to claim 2, characterized in that The step of determining the target storage unit from each of the storage units according to the side information includes: Determine a candidate storage unit from each of the storage units according to the side information; Determining the access type of the node according to the historical access times of the node; The target storage unit is determined from each of the candidate storage units according to the access type.

4. The method according to claim 2 or 3, characterized in that: The method further comprises: According to each of the edge information, a plurality of associated nodes having an associated relationship are determined from each of the nodes; If the storage position of the target storage unit corresponding to each of the associated nodes does not meet the preset conditions, the associated storage units corresponding to each of the associated nodes are re-determined from each of the storage units based on the edge information, and the associated storage units meet the preset conditions, and the preset conditions are that the difference between the storage addresses of the target storage units corresponding to each of the associated nodes is less than a preset threshold.

5. The method according to claim 2, characterized in that: The executing each of the operation instructions by each of the target computing units includes: Obtaining the execution priority of each of the nodes, and determining the execution order of each of the nodes according to the priority and the computing requirement; According to the execution order, each of the operation instructions is executed by each of the target computing units.

6. The method according to claim 1, characterized in that The operation instruction includes a calculation operation instruction and a data transmission instruction, and the generating of the operation instruction according to the target computing unit and the target storage unit includes: generating the computing operation instruction according to the computing requirement of the target computing unit; The data transfer instruction is generated according to the side information and the storage location of the target storage unit.

7. A computation graph execution device, characterized in that: For a computer device, the device comprises a reconfigurable processor and a memory, the reconfigurable processor comprises a plurality of computing units, the memory comprises a plurality of storage units, and the apparatus comprises: An acquisition module is used to acquire a preset computational graph, wherein the computational graph includes a plurality of nodes and edge information corresponding to each of the nodes; A first determination module is used to determine, for each of the nodes, a target computing unit and a target storage unit corresponding to the node according to the node information corresponding to the node and the edge information; An operation module is used to generate a computing instruction corresponding to the node according to the target computing unit and the target storage unit, and to execute each of the computing instructions through each of the target computing units.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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