Parasitic parameter determination method and device of integrated chip and storage medium

Abstract

The invention provides a parasitic parameter determination method and device for an integrated chip and a storage medium, and relates to but not limited to the technical field of electronic circuits, and the method comprises the steps: determining a conductor region and a boundary region based on a plurality of contour coordinates of each conductor in a preset calculation region; constructing a Gaussian surface on a to-be-predicted conductor in the conductor area, and uniformly sampling on the Gaussian surface according to a preset sampling interval to obtain a plurality of sampling points; acquiring a physical information neural network model; the physical information neural network model is obtained by performing model training on sample sampling points obtained by sampling a conductor region and a boundary region, and the sampling density of the sample conductor region is greater than the sampling density of the sample boundary region; and performing parasitic parameter prediction on the sampling points on the Gaussian surface through the physical information neural network model to obtain parasitic parameter prediction data of the conductor to be predicted. According to the embodiment of the invention, the calculation efficiency is ensured while the parasitic parameter precision requirement is met.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of electronic circuit technology, and in particular to a method, device, and storage medium for determining parasitic parameters of an integrated chip. Background Art

[0002] With the advancement of processes and technologies, the interconnect structure in integrated circuit chips has become more complex, and the circuit density has increased, resulting in increasingly serious parasitic effects of interconnects. How to accurately and quickly extract parasitic parameters such as parasitic capacitance is crucial to ensuring chip design quality, meeting stringent PPA index requirements, and shortening the design cycle. In related technologies, the parasitic parameters of integrated circuit chips can be calculated using field solver technology, where field solvers such as finite element methods and finite difference methods obtain accurate field distributions by discretely approximating electromagnetic field equations, thereby accurately calculating parasitic parameters. However, the higher the accuracy of the field solver, the lower the calculation efficiency. Therefore, how to ensure calculation efficiency while meeting the accuracy requirements of parasitic parameters is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The embodiments of the present application provide a method, device and storage medium for determining parasitic parameters of an integrated chip, aiming to meet the requirements for parasitic parameter accuracy while ensuring calculation efficiency.

[0004] In a first aspect, an embodiment of the present application provides a method for determining parasitic parameters of an integrated chip, which is applied to a cloud platform. The method for determining parasitic parameters of an integrated chip includes:

[0005] Based on a plurality of contour coordinates of each conductor in the calculation area of ​​the integrated chip, a conductor area and a boundary area are determined; wherein the boundary area is an area in the calculation area excluding the conductor area and the conductor;

[0006] Constructing a Gaussian surface of the conductor to be predicted in the conductor region, and performing uniform sampling on the Gaussian surface according to a preset sampling interval to obtain a plurality of sampling points;

[0007] Acquire a physical information neural network model; the physical information neural network model is obtained by training the sample sampling points obtained by sampling the conductor area and the boundary area, and the sampling density of the conductor area is greater than the sampling density of the boundary area;

[0008] The parasitic parameters of the sampling points are predicted by using the physical information neural network model to obtain parasitic parameter prediction data of the conductor to be predicted.

[0009] In a second aspect, an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for determining the parasitic parameters of an integrated chip as described in any one of the first aspects is implemented.

[0010] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, comprising computer-executable instructions stored therein, wherein the computer-executable instructions are used by a processor to execute the method for determining parasitic parameters of an integrated chip as described in any one of the first aspects.

[0011] The above-mentioned embodiments of the present application have at least the following beneficial effects: by dividing the calculation area according to the contour coordinates of each conductor, determining the conductor area and the boundary area, and obtaining the physical information neural network model, since the physical information neural network model is obtained by training the sample sampling points obtained by sampling the conductor area and the boundary area respectively based on different sampling densities, the physical information neural network model can realize multi-scale feature learning of the sampling points, thereby ensuring the accuracy of the prediction of the physical information neural network model, and therefore, the accuracy of the parasitic parameter prediction data of the conductor to be predicted by the physical information neural network model is higher. And compared with the existing method, before the actual calculation, there is no need to provide more computing resources or time for pre-calculation preparation, and the Gaussian surface is constructed and sampled for the conductor to be predicted, and the parasitic parameter prediction data can be obtained based on the physical information neural network model, and the calculation efficiency is higher. Therefore, the embodiment of the present application can ensure the calculation efficiency while meeting the parasitic parameter accuracy requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1a It is a calculation area after meshing when solving parasitic parameters in the prior art;

[0013] Figure 1b It is a schematic diagram of random walk in the prior art;

[0014] Figure 2 A schematic flow chart of a method for determining parasitic parameters of an integrated chip according to an embodiment of the present application;

[0015] Figure 3 A schematic diagram of conductors and conductor regions in an embodiment of a method for determining parasitic parameters of an integrated chip according to an embodiment of the present application;

[0016] Figure 4 A schematic diagram of a boundary area, a calculation area, and a conductor area in an embodiment of a method for determining parasitic parameters of an integrated chip according to an embodiment of the present application;

[0017] Figure 5A schematic diagram of the minimum reference spacing in an embodiment of a method for determining parasitic parameters of an integrated chip according to an embodiment of the present application;

[0018] Figure 6a A schematic diagram of conductor area sampling in an embodiment of a method for determining parasitic parameters of an integrated chip according to an embodiment of the present application;

[0019] Figure 6b A schematic diagram of sampling of a boundary area in an embodiment of a method for determining parasitic parameters of an integrated chip according to an embodiment of the present application;

[0020] Figure 7 It is an architecture diagram of a physical information neural network model in a parasitic parameter determination method of an integrated chip according to an embodiment of the present application;

[0021] Figure 8 It is an architecture diagram of a fully connected network module in a physical information neural network model in a parasitic parameter determination method of an integrated chip according to an embodiment of the present application;

[0022] Fig. 9 A schematic diagram of Gaussian sampling points in an application embodiment of a method for determining parasitic parameters of an integrated chip of an application embodiment;

[0023] Fig.10 It is a schematic diagram of the hardware structure corresponding to the method for determining parasitic parameters of an integrated chip according to an embodiment of the application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art belonging to the technical field of the present application. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application. The terms "first", "second", "third", "fourth", etc. (if present) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order.

[0026] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0027] With the advancement of process and technology, the interconnection structure in integrated circuit chips has become more complex, and the circuit density has increased, resulting in increasingly serious parasitic effects of interconnection lines. How to accurately and quickly extract parasitic parameters such as parasitic capacitance is crucial to ensuring the design quality of integrated circuit chips, meeting the stringent PPA index requirements, and shortening the design cycle. On the other hand, as the size of integrated circuit chips is further reduced, the manufacturing process of integrated circuit chips has evolved from a planar device process to a non-planar device process, and the 3D structure of the fin field effect transistor (FinField-EffectTransistor, FinFET) makes the parasitic capacitance and parasitic resistance around it increasingly important, and the parasitic effects are becoming more and more complex and will also become very sensitive to the influence of the process structure. For example, at the 7nm process node, the proportion of parasitic resistance in the total resistance can reach nearly 50%. The reduction in the area of ​​​​the integrated circuit chip will increase the parasitic capacitance, and will also greatly reduce the system speed, increase power consumption, and cause the parasitic effects of the interconnection lines to become more and more serious. Therefore, for integrated circuit chips, accurate modeling is required to consider the parasitic effects of the interconnection lines, that is, accurate parasitic parameter extraction is required, and the interconnection geometric parameter deviation caused by the nano process is also required. In the related art, the parasitic parameters of the integrated circuit chip can be calculated by the field solver (FieldSolver) technology, wherein the field solver, such as the finite element method, the finite difference method, etc., obtains the accurate field distribution by discretely approximating the electromagnetic field equation, thereby accurately calculating the parasitic parameters. However, the field solver needs to perform operations such as meshing according to the structure of the conductor on the integrated circuit chip, which takes a lot of time. It is difficult to balance accuracy and efficiency when processing the calculation of the actual large-scale interconnection structure. Therefore, it is still impractical to implement the parasitic parameter solution of the whole chip based on the field solver. Although some fast field solvers can also be combined with pattern matching technology to solve the parasitic parameter extraction problem of the whole chip, the accuracy of the parasitic parameters of this method is not high. Therefore, in the prior art, the extraction of parasitic parameters in the integrated chip cannot balance efficiency and accuracy.

[0028] Among them, the finite difference method is taken as an example. The finite difference method is one of the most basic methods for capacitance calculation. It is simple in form and easy to implement. This method first divides the calculation area of ​​the integrated circuit chip into grids and obtains Figure 1a The gridded calculation area shown in the figure is then discretized using grid point differences instead of differentials to discretize the electric field equations. Corresponding boundary conditions are applied to the grid points that fall on the main conductor, the ambient conductor, or the boundary of the solution area, thereby establishing a matrix equation for the grid points of the entire solution area, and then solving the matrix equation by direct or iterative methods. After obtaining the electric potential of all grid points in the calculation area, the Gaussian surface sum is performed to obtain the charge on the conductor, thereby obtaining the capacitance value. Since the differentials of each order involved in the equation need to be approximately expressed by the difference of the point and the adjacent grid points, the solution area needs to be divided into horizontal and vertical grids. This method has poor adaptability to complex multi-media structures and boundary conditions, that is, the accuracy of parasitic parameters is low.

[0029] Among them, taking the finite element method as an example, the solution of capacitance in the finite element method can be reduced to the problem of solving the electric field equation for the spatial potential distribution under given boundary conditions. This method first discretizes the calculation area to be solved into a finite number of connected but non-overlapping (irregular triangles or quadrilaterals, polygons) sub-areas, and expresses the unknown functions in the solution area by function interpolation in the sub-areas. Then, the linear equation system is constructed using the variational method to solve the potential distribution of the calculation area. After the potential distribution is calculated, the Gaussian formula can be used to integrate on the closed surface of the conductor to calculate the capacitance, or the electrostatic field energy method can be used to calculate. Since the finite element method cannot directly consider the open domain problem, the calculation area needs to be truncated, which produces a certain truncation error, but it can be improved by a hybrid method of the finite element method combined with the integral method. Finite elements can achieve high-precision interconnect capacitance parameter extraction, but when dealing with large-scale extraction problems, it is necessary to use acceleration technologies such as parallel computing. At present, for full-chip, large-scale interconnect line structures, the parasitic parameter extraction method directly based on finite elements will be affected by the grid size. When the mesh size is too large, the calculation results will be distorted; when the mesh size is too small, the calculation cost will increase. Therefore, in finite element analysis, it is very important to find a suitable mesh size, but this is not easy to achieve, especially for complex conductor structures and electric field distributions. It is necessary to generate adaptive meshes according to conditions such as the conductor structure, and the computing time, memory, disk space and other computing resources consumed are quite amazing. In addition, finite elements do not have a good way to deal with infinite solution domain problems.

[0030] Among them, taking the boundary element method as an example, the boundary element method mainly includes the indirect boundary element method and the direct boundary element method. The indirect boundary element method can be regarded as a special moment method. Because its coefficient matrix is ​​completely dense, it brings great difficulties to the solution of the equation. Therefore, a variety of acceleration algorithms such as the multipole acceleration algorithm and the singular value decomposition algorithm have been proposed, which has made the indirect boundary element method have a great development and become one of the main methods for three-dimensional capacitance parasitic extraction. The direct boundary element method is based on the direct boundary integral equation. The electric field equation for solving the mixed boundary conditions of the region is converted into a discrete integral equation on the conductor surface and the dielectric interface by using the same discrete method as the indirect boundary element method through the weighted residual method and applying the Green's formula. A linear equation system can be obtained, and then the normal electric field intensity on the conductor surface is obtained. Finally, it is integrated to obtain the parasitic capacitance. With the development of ultra-large-scale integrated circuit technology, the integral equation method faces many challenges. Generally, the interconnection structure contains multiple layers of dielectrics, each of which is different, which makes the interconnection capacitance extraction need to consider the problem of inhomogeneous dielectrics. The direct boundary element method must discretize the dielectric interface and introduce additional unknowns, which greatly increases the amount of calculation and has low calculation efficiency. Its application scope is based on the existence of the basic solution of the corresponding differential operator. It is difficult to apply to problems such as inhomogeneous media, so its application scope is far less universal than that of the finite element method. In addition, the coefficient matrix for solving the algebraic equations created by it is generally asymmetric and full, which greatly limits the scale of problem solving. For common nonlinear problems, because the domain integral term will appear in the equation, the advantage of the boundary element method that only the boundary needs to be discretized is partially offset.

[0031] Among them, the random walk capacitance extraction method is taken as an example. The random walk capacitance extraction method is the application of the Monte Carlo method in the calculation of electrostatic field capacitance. Figure 1b As shown in the figure, the coupling capacitance between the main conductor and other conductors is calculated by establishing a closed Gaussian surface surrounding the main conductor: first, a point r is uniformly sampled on the Gaussian surface, and then a point r is uniformly sampled on the first transfer cube. (1) , and then repeat the above sampling process. Sampling continues in this way until the result of a certain sampling falls on a point with a known potential. A sampling chain formed in this way is called a suspended random walk. Assuming that the main conductor is numbered i, and the conductor numbered j is the conductor that the suspended random walk ends, then the coupling capacitor C at the end of this random walk is ij Cumulative increase, this increment is C ij A sampling estimate of C ij The estimated accumulation of divided by the number of suspended random walks falling on conductor j is averaged to obtain C ij. In recent years, the suspended random walk method has made great progress in dealing with complex shapes, complex multilayer dielectrics, and large-scale conductor structures. Coupled with its natural advantages in parallel computing, it has become the most unique and promising method in the field of parasitic parameter extraction. However, the calculation speed of capacitance extraction when used for layout needs to be further improved; it is difficult to adapt to complex geometric shapes and complex materials, and the processing efficiency of non-Manhattan structures is not high.

[0032] Among them, taking the pattern matching method as an example, a pattern library is established in advance based on geometric structures and geometric parameters. When extracting, the actual layout is compared with the pattern library to obtain the resistance and capacitance values. This method is more suitable for large-scale circuits, but errors often occur due to pattern matching errors, and the establishment of the pattern library is time-consuming and laborious. With the development of technology and the increasingly high accuracy requirements for parasitic parameter extraction, the traditional layout capacitance extraction technology using the pattern matching method cannot meet the accuracy requirements, especially for the next generation of analog circuits with high precision requirements.

[0033] In summary, in the prior art, how to ensure computational efficiency while meeting parasitic parameter accuracy requirements is a technical problem that needs to be solved urgently. Based on this, the present application provides a parasitic parameter determination method, device and storage medium for an integrated chip, aiming to meet parasitic parameter accuracy requirements while ensuring computational efficiency.

[0034] An embodiment of the present application provides a parasitic parameter determination device, including a data reading module, a region segmentation and sampling module, a physical information neural network electric field equation solving module, and a parasitic parameter calculation module.

[0035] The data reading module is used to obtain the conductor-related data in the calculation area, wherein the conductor-related data includes boundary data, dielectric constant, and contour coordinates of the conductor. The contour coordinates may be coordinates selected on the conductor contour line. For regular graphics, such as square conductors, the coordinates of the two corner points on the diagonal line of the two-dimensional graphics formed by projecting the conductor on the calculation area may be used as the contour coordinates.

[0036] The region segmentation and sampling module is used to divide the calculation region into the conductor region and the boundary region and to sample the conductor region and the boundary region respectively, wherein the conductor region encompasses all the conductors in the calculation region and does not contain any conductors, and the boundary region is the region excluding the conductor region and the conductors in the calculation region. The sampling of the conductor region and the boundary region includes both the sampling inside the region and the sampling of the boundaries of each region.

[0037] The physical information neural network electric field equation solving module is used to output parasitic parameter prediction data of the conductor to be predicted based on sampling points on the Gaussian surface of the conductor to be predicted.

[0038] The parasitic parameter calculation module is used to calculate the parasitic capacitance of the conductor to be predicted based on the parasitic parameter prediction data.

[0039] Understandably, referring to Figure 2 As shown, an embodiment of the present application provides a method for determining parasitic parameters of an integrated chip, and the method for determining parasitic parameters of an integrated chip includes:

[0040] Step S100, determining a conductor region and a boundary region based on multiple contour coordinates of each conductor in a calculation region of the integrated chip; wherein the boundary region is a region other than the conductor region and the conductor in the calculation region;

[0041] Step S200: constructing a Gaussian surface of the conductor to be predicted in the conductor region, and performing uniform sampling on the Gaussian surface according to a preset sampling interval to obtain a plurality of sampling points;

[0042] Step S300, obtaining a physical information neural network model; the physical information neural network model is obtained by training the sample sampling points obtained by sampling the conductor area and the boundary area, and the sampling density of the conductor area is greater than the sampling density of the boundary area;

[0043] Step S400: predicting parasitic parameters of sampling points by using a physical information neural network model to obtain parasitic parameter prediction data of the conductor to be predicted.

[0044] Therefore, by dividing the calculation area according to the contour coordinates of each conductor, determining the conductor area and the boundary area, and obtaining the physical information neural network model, since the physical information neural network model is obtained by training the sample sampling points obtained by sampling the conductor area and the boundary area at different sampling densities, the physical information neural network model can realize multi-scale feature learning of the sampling points, thereby ensuring the accuracy of the prediction of the physical information neural network model, and therefore, the accuracy of the parasitic parameter prediction data of the conductor to be predicted by the physical information neural network model is higher. And compared with the existing method, before the actual calculation, there is no need to provide more computing resources or time for pre-calculation preparation, and the Gaussian surface is constructed and sampled for the conductor to be predicted, and the parasitic parameter prediction data can be obtained based on the physical information neural network model, and the calculation efficiency is higher. Therefore, the embodiment of the present application can ensure the calculation efficiency while meeting the parasitic parameter accuracy requirements.

[0045] It is understandable that the physical information neural network model essentially adopts a meshless algorithm, which can be applied to the calculation of complex conductor structures and complex media, and no mesh needs to be generated during the calculation process, thus avoiding the computing resources and time required for mesh generation.

[0046] It is understandable that the sample sampling points for training the physical information neural network model may include sample sampling points within the region and at the region boundary. For example, the sample sampling points of the conductor region include sampling the contour of the conductor, the conductor region, and the outer boundary of the conductor region. For example, the sample sampling points of the boundary region include sampling the boundary region and the outer boundary of the boundary region. For the same region, the sampling density within the region and the boundary of the region may be the same or different. Therefore, the sampling density of the conductor region is greater than the sampling density of the boundary region, which can be understood as the sampling density within the conductor region is greater than the sampling density within the boundary region, and the sampling density on the boundary of the conductor region is greater than the sampling density of the outer boundary of the boundary region (that is, the boundary of the calculation region). In some embodiments, the sample sampling points also include sampling points on the conductor contour. The sampling point density on the conductor contour is greater than the sampling density on the boundary of the conductor region. In this way, multi-dimensional feature learning can be achieved, while improving calculation accuracy and reducing sample sampling points.

[0047] It can be understood that the conductor area is a closed area formed between a closed contour line enclosing all conductors in the calculation area and the contours of each conductor.

[0048] In some embodiments, the parasitic parameter prediction data of the conductor to be predicted is the potential (ie, electric potential) of each sampling point corresponding to the conductor with prediction, and according to Gauss's theorem ∫ S kE·dA=Q, which can determine the charge value of a certain area Among them, E i is the electric field on the Gaussian surface, k i is the dielectric constant, d Si is the area of ​​change on the Gaussian surface, U θ,i is the potential on the Gaussian surface. n is the external normal vector of the sampling point. Therefore, after obtaining the parasitic parameter prediction data of the conductor to be predicted, the potential of each sampling point is substituted into The parasitic parameter Q can be determined. Among them, The sampling interval of the Gaussian surface is set. In some embodiments, the sampling interval may be set to a minimum reference interval between the contour coordinates of each conductor in the conductor region.

[0049] It is understandable that in the process of solving the capacitance, it is usually necessary to solve the infinite domain problem of the electric field equation, that is, the normal electric field strength at infinity is 0. Therefore, the calculation area determined based on this principle is usually much larger than the area of ​​the conductor area. At least one calculation area can be divided in an integrated chip, and the embodiment of the present application does not limit the calculation area that can be divided on the integrated chip.

[0050] For a trained physical information network model, it can also be applied to a conductor area and a calculation area with the same outer boundary size as that during training to predict the parasitic parameters of the conductor.

[0051] The embodiments of the present application do not limit the shape of the outer boundary of the boundary area and the conductor area. In some embodiments, the outer boundary of the conductor area can be a closed curve that wraps the conductors in the calculation area, or it can be a rectangle. The outer boundary of the boundary area can be set to a rectangle or a closed curve. The contour coordinates of the conductor can characterize the contour of the conductor. For example, for a rectangular contour, two coordinate points on the diagonal line are used as contour coordinates to reflect the rectangular contour. For special-shaped conductors, sampling can be performed based on the contour of the conductor to ensure that the deviation between the closed curve formed by the contour coordinates and the actual contour line of the conductor is within a preset tolerance threshold.

[0052] By setting the sampling density of the conductor area to be greater than the sampling density of the boundary area, the number of sampling points of the sample sampling points in the conductor area and the sample sampling points in the boundary area are different, so that the physical information neural network model learns different feature scales for the conductor area and the boundary area, thereby realizing the parasitic parameter solution of the multi-scale physical information neural network model.

[0053] It can be understood that the sampling density represents the ratio between the number of sample sampling points and the area of ​​the sampled region.

[0054] It is understandable that the loss function of the physical information neural network model in the embodiment of the present application is determined based on the electric field residual equation, the conductor boundary condition, the calculation area boundary condition and the interface constraint condition. Among them, the electric field residual equation characterizes the relationship between the partial derivative value obtained by taking the second-order partial derivative of the electric potential at the same sampling point with respect to the x-coordinate and the partial derivative value obtained by taking the second-order partial derivative of the electric potential at the y-coordinate, the conductor boundary condition is used to characterize the relationship between the predicted value and the actual value of the electric potential of the sampling point on the outer boundary of the conductor area, and the calculation area boundary condition characterizes the relationship between the predicted value and the actual value of the electric field strength of the sampling point on the boundary of the calculation area. The interface constraint condition is used to characterize the relationship between the electric potential and the partial derivative of the electric potential of the sample sampling point at the junction of the conductor area and the boundary area. In some embodiments, the conductor boundary condition is generally a Dirichlet boundary condition, and the calculation area boundary condition can be divided into different situations, which can include both the Dirichlet boundary condition and the Neumann boundary condition, or either of the two conditions.

[0055] For example, if the outline of the conductor area is a rectangle and the shape of the conductor is a rectangle, then refer to Figure 3As shown in the figure, net0, net1, and net2 represent the three conductors in the area. Conductor net0 contains only one sub-conductor, which is a rectangle. Conductor net1 and conductor net2 are both polygons formed by stacking four sub-conductors (each sub-conductor is a rectangle). The lower left corner coordinates (X1, Y1) and upper right corner coordinates (X2, Y2) of each conductor are used as contour coordinates, and the data related to the conductor can be obtained as shown in Table 1 below:

[0056]

[0057] Table 1

[0058] Then, the conductor area and the calculation area can be determined by combining the contour coordinates in Table 1. At this time, the relative positions of the conductor area, the boundary area, and the calculation area are as follows: Figure 4 As shown. Fig. 9 , assuming that net0 is the conductor to be predicted, then Gaussian surface 1 is constructed based on net0 as follows Fig. 9 As shown, Gaussian surface 1 is uniformly sampled with reference to step S200 to obtain multiple sampling points. At this time, the parasitic capacitance of net0 is obtained based on the multiple sampling points. Similarly, net1 and net2 can also be predicted separately, which will not be described in detail in the embodiments of the present application.

[0059] Therefore, compared with traditional numerical algorithms, the physical information neural network model can be applied to the capacitance calculation of complex conductor structures and complex media, solving the problem that traditional methods are difficult to adapt to complex geometric shapes and complex materials. And there is no need to generate a grid, only to generate sampling points for training in the calculation area, avoiding the large amount of time and computing resources required to generate and debug the grid. It can be used to parameterize the solution of partial differential equations to achieve the purpose of accelerating the solution.

[0060] Understandably, referring to Figure 7 As shown, the physical information neural network model includes a first fully connected network module and a second fully connected network module. The physical information neural network model is used to predict the parasitic parameters of the sampling points to obtain the parasitic parameter prediction data of the conductor to be predicted, including:

[0061] The electric potential of the sampling point is predicted by the first fully connected network module to obtain the first parasitic parameter prediction data; the first fully connected network module is used to predict the electric potential of the conductor area;

[0062] The electric potential of the sampling point is predicted by the second fully connected network module to obtain second parasitic parameter prediction data; the second fully connected network module is used to predict the electric potential of the boundary area;

[0063] According to a preset level set function, first parasitic parameter prediction data and second parasitic parameter prediction data, parasitic parameter prediction data of a conductor to be predicted is obtained; wherein the level set function characterizes the relationship between a sampling point and the center coordinates of a conductor region and size information of the conductor region.

[0064] It is understandable that the first fully connected network module is trained based on the sample sampling points in the conductor area during training, and the second fully connected network module is trained based on the sample sampling points in the boundary area during training, so that the same physical information neural network can achieve feature learning of different scales for sampling points in different areas.

[0065] The level set function is a function constructed based on the level set method, which can realize the identification of the area where the sampling point is located, so that the output of the physical information neural network model can be determined based on the output of the first fully connected network module and the second fully connected network module. θ Set to U θ =φU θ,c +(1-φ)U θ,b ; where φ is the level set function, U θ,c For the sub-neural network fitting the conductor region potential (i.e., the first fully connected network module), U θ,b It is a sub-neural network (i.e., the second fully connected network module) that fits the potential of the boundary region. φ can be calculated in real time based on the conductor region.

[0066] The size information of the conductor region may include the width and length of the conductor region.

[0067] For example, the parasitic parameter prediction data is taken as the potential (ie, electric potential) of the sampling point; the contours of the calculation area and the conductor area are both rectangular; refer to Figure 7 As shown, based on the first fully connected network module U θ,c and the second fully connected network module U θ,b Construct an initial physical information neural network, and set a partial derivative counting layer and a constraint layer to assist in constructing the loss function of the initial physical information neural network through the partial derivative counting layer and the constraint layer, where θ represents a parameter composed of weight W and bias b. Figure 7 As shown, U θ,c Used to predict the potential at the sampling point of the conductor area, U θ,b It is used to predict the potential of the sampling points in the boundary area. At this time, the initial physical information neural network U can be obtained based on the level set method. θ =φU θ,c +(1-φ)U θ,b; where φ is the level set function. In some embodiments, φ is calculated using a symbolic function. In some embodiments, the formula Calculate; where (x c ,y c ) is the center coordinate of the conductor area; a is the length of the conductor area, b is the width of the conductor area, 0.5 is a coefficient, and 0.5 can be adaptively adjusted according to actual conditions; (x, y) is the input data of the physical information network model, then the initial physical information neural network can be trained to obtain a trained physical information neural network. At this time, for the trained physical information neural network, it is connected through the first fully connected network module U θ,c , the second fully connected network module U θ,b The potential U of the sampling point is determined by the level set function θ .

[0068] Understandably, referring to Figure 8 As shown, the first fully connected network module and the second fully connected network module are both provided with three branch sub-networks, wherein the two branch sub-networks each include a first input layer and a first hidden layer connected in sequence, and the other branch sub-network includes a second input layer, a plurality of second hidden layers and an output layer connected in sequence, and the first hidden layer is connected to the input of each second hidden layer other than the first layer, and the parasitic parameter prediction data of the conductor area and the parasitic parameter prediction data of the boundary area are obtained by the following steps:

[0069] Inputting the sampling points into the first input layer and the second input layer of the first fully connected network module and the second fully connected network module at the same time;

[0070] For each first hidden layer, obtaining first output data according to the first input layer corresponding to the first hidden layer;

[0071] For the second hidden layer of the first layer, second output data is obtained according to the second input layer correspondingly connected to the second hidden layer;

[0072] For each second hidden layer outside the first layer, third output data is obtained according to the second output data of the previous correspondingly connected second hidden layer and the two first output data;

[0073] For each output layer, prediction is performed according to the third output data output by the second hidden layer correspondingly connected to the output layer to obtain parasitic parameter prediction data.

[0074] By setting the first fully connected network module and the second fully connected network module with three branch sub-networks, and using one of the branch sub-networks as the main path and the other two branch sub-networks as auxiliary paths, the outputs of the three hidden layers can be summarized at the same time after the first hidden layer of the main path, thereby improving the prediction accuracy of the fully connected network module.

[0075] The embodiment of the present application does not limit the number of layers of the second hidden layer, and those skilled in the art can selectively set it according to actual needs.

[0076] Reference Figure 8 As shown, the second hidden layer is provided with L layers, and the two first hidden layers can be respectively expressed as M = φ (XW 1 +b 1 ) and N=φ(XW 2 +b 2 ), where X represents the input data of the model, W 1 represents the weight of the first hidden layer M, b 1 represents the bias of the first hidden layer M. W 2 represents the weight of the first hidden layer N, b 2 represents the bias of the first hidden layer N. The first second hidden layer H 1 =φ(XW z,1 +b z,1 ), where W z,1 Represents the second hidden layer H 1 The weight of b z,1 Represents the second hidden layer H 1 For the second hidden layer H other than the first second hidden layer k+1 =(1-Z k )⊙M+Z k ⊙N,k=1,...,L; where Z k =φ(H k W z,k +b z,k ),k=1,...,L; then for the output layer U θ,* (x) = H L+1 W+b, that is, the sampling point is input into the first fully connected network module, and the output of the first fully connected network module can be expressed as U θ,c (x) = H L+1 W+b; the sampling point is input into the second fully connected network module, and the output of the second fully connected network module can be expressed as U θ,b (x) = H L+1 W+b.

[0077] It is understandable that the physical information neural network model is trained through the following steps:

[0078] Configure the residual loss function, boundary loss function and continuity constraint loss function; wherein the residual loss function represents the mean square sum of the equation residuals of the sample sampling points in the conductor region and the boundary region; the boundary loss function represents the sum of the mean square error of the potential of the sample sampling points on the outer boundary of the conductor region and the mean square error of the electric field of the sample sampling points on the outer boundary of the boundary region; the continuity constraint loss function represents the mean square error of the sample sampling points at the junction of the conductor region and the boundary region;

[0079] Determine the target loss function according to the residual loss function, the boundary loss function and the continuity constraint loss function;

[0080] Obtain a sample point set of the conductor area and the boundary area;

[0081] Based on the target loss function and the sample sampling point set, the initial physical information neural network model is trained to obtain a trained physical information neural network model.

[0082] It is understandable that for each sample sampling point in the conductor area and the boundary area, the output U of the mode can be used. θ To approximate the actual electric potential U(x,y), where the electric field equation is Therefore, the residual formula can be constructed based on the electric field equation to obtain the residual of the equation Therefore, we can respectively calculate the r of each sample point in the conductor area. θ (x, y) calculates the mean square of the potential; based on the r of each sample sampling point in the boundary area θ (x, y) calculates the mean square of the potential; and then the mean square sum of the potentials of the sample sampling points in the conductor area and the sample sampling points in the boundary area can be calculated.

[0083] The boundary loss function and the continuity constraint loss function can be determined based on the conductor boundary conditions and the calculation area boundary conditions. The conductor boundary conditions can be used to characterize the relationship between the actual potential value and the predicted potential value of the sample sampling points on the outer boundary of the conductor area, and the calculation area boundary conditions can be used to characterize the relationship between the actual normal electric field strength and the predicted normal electric field strength of the sample sampling points on the outer boundary of the boundary area. Among them, the normal electric field strength on the outer boundary can be expressed as Therefore, the boundary loss function constructed based on the conductor boundary condition and the calculation area boundary condition can be used to count the mean square error of the potential of the sampling points on the outer boundary of the conductor area and the sum of the mean square error of the electric field of the sampling points on the outer boundary of the boundary area.

[0084] In some embodiments, the objective loss function can be set to be a superposition of a residual loss function, a boundary loss function, and a continuity constraint loss function, such as Among them, L totalrepresents the target loss function, L r is the residual loss function; is the boundary loss function; is the continuity constraint loss function.

[0085] It is understandable that the residual loss function is set as:

[0086]

[0087] Among them, L r Represents the residual loss value, N c Represents the number of sample points in the conductor area, N b Indicates the number of sample points in the boundary area, (x i,c ,y i,c ) represents the sample sampling point in the conductor area, (x i,b ,y i,b ) represents the sample sampling point within the boundary area; in, is the second-order partial derivative of the potential at the sample sampling point (x, y) with respect to x, is the second-order partial derivative of the potential at the sample sampling point (x, y) with respect to y; k is the dielectric constant;

[0088] The boundary loss function is set as:

[0089]

[0090] in, represents the boundary loss value, is the number of sample points on the conductor boundary in the conductor region, is the number of sample points on the outer boundary of the boundary area, U(x i,d ,y i,d ) represents the sample sampling point (x i,d ,y i,d )’s potential, Based on the conductor boundary condition, the sampling point (x i,d ,y i,d ) is the potential value assigned; q θ (x i,n ,y i,n ) represents the sample sampling point (x i,n ,y i,n )’s electric field strength; The sampling point (x i,n ,y i,n ) is the value of the electric field strength assigned; h n is the sampling spacing uniformly sampled on the outer boundary of the boundary region;

[0091] The continuity constraint loss function is set as:

[0092]

[0093] in, is the continuity loss value, (x i,I ,y i,I ) is the sampling point at the junction of the conductor area and the boundary area; U θ,c (x i,I ,y i,I ) is the output of the first fully connected network module (x i,I ,y i,I ) potential, U θ,b (x i,I ,y i,I ) represents the output of the second fully connected network module (x i,I ,y i,I )’s potential; The number of sampling points for sampling at the junction of the conductor area and the boundary area; Indicates the sample sampling point (x i,I ,y i,I ) θ,c Taking the first-order partial derivative of x, Indicates the sample sampling point (x i,I ,y i,I ) θ,b Taking the first-order partial derivative of x, Indicates the sample sampling point (x i,I ,y i,I ) θ,c Taking the first-order partial derivative of y, Indicates the sample sampling point (x i,I ,y i,I ) θ,b Take the first partial derivative of y.

[0094] Therefore, by calculating the loss values ​​at the outer boundary, junction and within the region respectively, the accuracy of the physical information neural network model can be further improved.

[0095] It is understandable that during the training process, reference Figure 7 As shown, the sample sampling points at the outer boundary of the conductor area will be input into the first fully connected network module and the second fully connected network module for feature learning respectively, the sample sampling points in the conductor area will enter the first fully connected network module for feature learning, and the sample sampling points in the boundary area and on the outer boundary of the boundary area will enter the second fully connected network module for feature learning.

[0096] It can be understood that obtaining the sample sampling point set of the conductor area and the boundary area includes:

[0097] Determine the minimum reference spacing of the calculation area according to the multiple contour coordinates;

[0098] According to the preset sample sampling point number strategy, random sampling is performed in the conductor area and the boundary area;

[0099] Obtaining the calculation area boundary sampling spacing, the intersection sampling spacing and the conductor boundary sampling spacing, wherein the calculation area boundary sampling spacing, the intersection sampling spacing and the conductor boundary sampling spacing are all determined based on the minimum reference spacing, and the conductor boundary sampling spacing is smaller than the intersection sampling spacing; the intersection sampling spacing is smaller than the calculation area boundary sampling spacing;

[0100] According to the sampling interval of the boundary of the calculation area, the sampling interval of the intersection and the sampling interval of the conductor boundary, the outer boundary of the boundary area, the intersection of the calculation area and the conductor area, and the contour of the conductor are uniformly sampled respectively;

[0101] The sample sampling points obtained by uniform sampling and the sample sampling points obtained by random sampling are combined to obtain a sample sampling point set.

[0102] The sample sampling point number strategy is used to determine the number of random sampling in the conductor area and the number of random sampling in the boundary area, wherein the number of random sampling in the conductor area is greater than the number of random sampling in the boundary area.

[0103] By setting a variety of different sampling intervals, the diversity of samples can be improved, thereby further improving the accuracy of the model.

[0104] It is understood that the minimum reference spacing is determined by the following steps:

[0105] According to the coordinates of each contour, the X-axis spacing and Y-axis spacing with the smallest coordinate spacing are calculated respectively;

[0106] Determine, according to each contour coordinate, a first minimum side length of each conductor projection in the X-axis direction and a second minimum side length in the Y-axis direction;

[0107] A minimum reference spacing is determined according to the first minimum side length, the second minimum side length, the X-axis spacing, and the Y-axis spacing.

[0108] It is understandable that the above-mentioned X-axis and Y-axis are both coordinate axes based on the plane where the calculation area is located. The first minimum side length can be considered as the length of the shortest line segment among the line segments obtained by projecting each conductor along the X-axis. The second minimum side length can be considered as the length of the shortest line segment among the line segments obtained by projecting each conductor along the Y-axis. The X-axis spacing is the minimum spacing between two x-coordinates of each contour coordinate projected on the X-axis. The Y-axis spacing is the minimum spacing between two y-coordinates of each contour coordinate projected on the Y-axis.

[0109] In some embodiments, different or partially identical weight coefficients may be set for the first minimum side length, the second minimum side length, the X-axis spacing, and the Y-axis spacing, respectively. After the first minimum side length, the second minimum side length, the X-axis spacing, and the Y-axis spacing are multiplied by their respective corresponding weight coefficients, the smallest value is selected from the multiplied values ​​as the minimum reference spacing. For example, the minimum reference spacing h=min(n x / 8,d x / 2,n y / 8,d y / 2); where n x is the first minimum side length, n y is the second smallest side length, 1 / 8 is n x 、n y The weight coefficient of x is the minimum X-axis spacing, 1 / 2 is d x ,d y The weight coefficient of .

[0110] It is understandable that the physical information neural network model is trained through the following steps:

[0111] The initial physical information neural network model is trained based on a preset learning rate adaptive adjustment strategy;

[0112] When the number of training iterations of the initial physical information neural network model meets the preset number of iterations, the training of the initial physical information neural network model is stopped to obtain an intermediate physical information neural network model;

[0113] The intermediate physical information neural network model is trained by the memory-constrained quasi-Newton method;

[0114] When the output result of the intermediate physical information neural network model meets the preset convergence condition, the training of the intermediate physical information neural network model is stopped to obtain the physical information neural network model.

[0115] It is understandable that the initial physical information neural network model can be trained based on a preset learning rate adaptive adjustment strategy through the Adam optimizer. The memory-limited quasi-Newton method can be set to the L-BFGS-B (limited-memory BroydenFletcherGoldfarbShanno algorithm with bound constraints) optimizer.

[0116] Therefore, a two-step optimization method is used to train the initial physical information neural network model, which can improve the convenience of training while improving the training efficiency and calculation accuracy.

[0117] The embodiment of the present application does not impose any restrictions on the convergence conditions, which can be set to, for example, a loss value less than a preset threshold or the number of iterations meeting a preset number.

[0118] Exemplarily, an embodiment of the present application is described with reference to the accompanying drawings. Taking the conductor as a rectangular body, and the conductor area and the calculation area as rectangular bodies as an example, the specific steps are as follows:

[0119] Step S1, obtaining conductor-related data of each conductor in the calculation area to be calculated, wherein the conductor-related data includes information such as the boundary position of the calculation area, dielectric constant, the name of the conductor in the calculation area and the sub-conductor contained in the conductor, and the position coordinates (i.e., contour coordinates). Figure 3 Taking the example shown in Table 1, the calculation area and conductor related data shown in Table 1 can be obtained. Among them, net0, net1, and net2 represent the three conductors in the area. Conductor net0 contains only one sub-conductor, which is a rectangle. Conductor net1 and conductor net2 are both polygons formed by stacking four sub-conductors (each of which is a rectangle). The multiple contour coordinates of each sub-conductor are the x-coordinate and y-coordinate of the lower left corner of the conductor and the x-coordinate and y-coordinate of the upper right corner of the conductor.

[0120] Step S2: Figure 4 As shown in the figure, the calculation area is divided into two parts: one is the small-scale area containing the conductor, that is, the conductor area, and the other is the large-scale area outside the conductor area to the boundary of the calculation area, that is, the boundary area. Then, sample sampling points are sampled for each area, conductor boundary, area boundary, etc.; the sample sampling point set is obtained; the specific calculation steps are as follows:

[0121] Step S2.1, calculate the minimum reference spacing h. First, calculate the minimum side lengths of all rectangular sub-conductors in the x-direction and the y-direction and record them as n x (As attached Figure 5 As shown, x1~x18 are projections of the outline coordinates of the sub-conductor on the x-axis, y1~y5 are projections of the outline coordinates of the sub-conductor on the y-axis, x is the distance between x4 and x5) and n y (the distance between y4 and y5), and then project the outline coordinates of all rectangular sub-conductors onto the x-axis and y-axis respectively, and calculate the minimum spacing d between adjacent coordinates on the x-axis and y-axis x (the distance between x1 and x2) and d y (The distance between y4 and y5). Minimum reference spacing h = min (n x / 8,d x / 2,n y / 8,d y / 2).

[0122] Step S2.2: Set the boundary coordinates of the conductor region to Here x i ,y i The x- and y-coordinates of the body are shown respectively. Used to calculate the minimum x-coordinate value of all conductors in the calculation area. Used to calculate the maximum x-coordinate value of all conductors in the calculation area. Used to calculate the minimum y coordinate value of all conductors in the calculation area. Used to calculate the maximum y coordinate value of all conductors in the calculation area. Among them, 1000 is the adjustment coefficient, which can be adjusted according to the actual situation to ensure that the area of ​​the boundary area is larger than the area of ​​the conductor area. At this time, the boundary area is the remaining part of the entire area minus the small-scale area Ω b =(-L,L,0,L) / Ω d .

[0123] Step S2.3, perform random uniform sampling in the conductor area and the boundary area, respectively. The number of sample sampling points is 10000 and 5000 respectively. Sampling is performed at the boundary of the conductor, the interface between the conductor area and the boundary area, and the boundary of the calculation area. The reference distance for sampling the boundary of the conductor can be set to h (that is, the sampling spacing of the conductor boundary is h); the reference distance for sampling the interface between the conductor area and the boundary area is 10*h (that is, the sampling spacing of the intersection is 10h), and the reference distance for the boundary of the calculation area is 100*h (that is, the sampling spacing of the boundary of the calculation area is 100*h). The number of random uniform sampling can be adjusted according to the actual situation, and the coefficient of the minimum reference spacing adopted for each boundary can be adaptively adjusted. At this time, it can be obtained Figure 6a , Figure 6b Schematic diagram of the sample sampling points shown.

[0124] S3, construct the initial physical information neural network, such as Figure 7 As shown, the initial physical information neural network U θ The construction is as follows: Initialize the first fully connected network module U θ,c and the second fully connected network module U θ,b , the first fully connected network module U θ,c For the potential prediction of the conductor area, the second fully connected network module U θ,b Used to predict the electric potential of the boundary area; based on the center coordinates of the conductor area and the size information of the conductor area, the level set function of the calculation area is obtained, and the first fully connected network module U is connected to the first fully connected network module U by the level set function. θ,c and the second fully connected network module U θ,b coupled into an initial physical information neural network; at this time, the initial physical information neural network U θ =φUθ,c +(1-φ)U θ,b . Among them, the level set function φ=sign(max( x,y max x,y (|xx c |-0.5a,|yy c |-0.5b),0)).

[0125] Further, the first fully connected network module U θ,c and the second fully connected network module U θ,b All adopt Figure 8 The structure shown is used to improve the accuracy of parasitic parameters.

[0126] Furthermore, the partial derivative calculation layer and constraint layer are set for the initial physical information neural network, as follows:

[0127] Among them, the partial derivative calculation layer: the partial derivative calculation layer is used to calculate the first-order partial derivative of the electric potential with respect to x, the first-order partial derivative with respect to y, the second-order partial derivative with respect to x, and the second-order partial derivative with respect to y. Among them, the above partial derivatives can use the automatic differentiation technology in the back-propagation algorithm to solve the partial derivatives of the neural network.

[0128] Among them, the first-order partial derivative of the potential with respect to x is Find the first-order partial derivative of the potential with respect to y Find the second-order partial derivative of the electric potential with respect to x The second-order partial derivative of the potential with respect to y is

[0129] Constraint layer: Equations and solution conditions The constraint layer is determined according to the electric field equations and their boundary conditions in the calculation area. The electric field equations and their boundary conditions are as follows:

[0130]

[0131] Among them, U represents the electric potential, q represents the normal electric field strength, and k represents the dielectric constant. It should be emphasized that k can be a constant as given in Table 1, or it can be a function that varies with the solution area. U represents the conductor boundary condition, which can be the Dirichlet boundary condition, is the potential value on the outer boundary of the conductor, Υ q To calculate the boundary conditions of the region, you can use the Neumann boundary conditions. is the normal boundary strength, which can also be used Indicates that n is the boundary normal vector.

[0132] At this point, the loss function L can be defined total =L r +L ud +L uI ,in, N c , N b are the number of sample points in the conductor area and the boundary area respectively. Different boundary conditions correspond to different characteristic scales. To ensure the accuracy of the calculation, the error term corresponding to the boundary conditions of the calculation area is multiplied by h n -2 ,h n is the reference length of the corresponding boundary. in, is the number of sample points corresponding to the regional interface. correspond Figure 7 Intermediate interface constraints. I is the reference length of the corresponding boundary (such as the sampling spacing at the junction of the conductor area and the boundary area).

[0133] S4, input the sample sampling points in step S2 into the initial physical information neural network model for training. Among them, the sample sampling points in the conductor area, the sample sampling points on the outline of the conductor, and the sample sampling points at the junction of the conductor area and the boundary area can all be used to train the first fully connected network module, and the sample sampling points in the boundary area, the sample sampling points on the outer boundary of the boundary area, and the sample sampling points at the junction of the conductor area and the boundary area can all be used to train the second fully connected network module. The specific steps are as follows:

[0134] First, the Adam optimizer is used with an adaptive learning rate to train iteratively for 5000 steps to reduce the loss function to a smaller value and obtain the intermediate physical information neural network. Then the L-BFGS-B (limited-memory Broyden Fletcher Goldfarb Shanno algorithm with bound constraints) optimizer is used to optimize and fine-tune the physical information neural network to further improve the calculation accuracy. L-BFGS-B will automatically stop training according to the pre-set incremental tolerance (1e-3) to obtain a trained physical information neural network model.

[0135] At this time, the parasitic parameters of the conductor can be predicted based on the trained physical information neural network model.

[0136] S5. Construct the Gaussian surface of each conductor in the calculation area to be calculated for parasitic parameters, and obtain Fig. 9 The conductor area shown. Fig. 9As shown, the largest rectangular box corresponds to the conductor area, and conductor 1, conductor 2, and conductor 3 correspond to Gaussian surface 1, Gaussian surface 2, and Gaussian surface respectively. Fig. 9 The Gaussian surface of each conductor is sampled separately to obtain the sampling points corresponding to the Gaussian surface.

[0137] S6. Use the trained physical information neural network to predict the electric potential of the sampling point and obtain the electric field on each Gaussian surface. Obtain the charge value of the Gaussian surface area of ​​each conductor.

[0138] Reference Fig.10 As shown, an embodiment of the present application further provides an electronic device, including:

[0139] One or more processors 801;

[0140] The memory 802 stores one or more programs. When the one or more programs are executed by the one or more processors 801, the one or more processors 801 implement the method provided in any embodiment of the present application.

[0141] The memory 802 is a non-transient network system that can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory 802 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory 802 may optionally include a memory 802 remotely arranged relative to the processor 801, and these remote memories 802 may be connected to the processor 801 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0142] The memory 802 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 802, and the processor 801 calls and executes the methods of the embodiments of this application.

[0143] The processor 801 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in the embodiment of the present application.

[0144] In some embodiments, the electronic device further comprises:

[0145] Input / output interface, used to realize information input and output;

[0146] Communication interface, used to realize communication interaction between this device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);

[0147] A bus that transmits information between various components of the device (e.g., processor 801, memory 802, input / output interface, and communication interface);

[0148] The processor 801 , the memory 802 , the input / output interface and the communication interface can be connected to each other in communication within the device via a bus.

[0149] An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute a method provided in any embodiment of the present application.

[0150] An embodiment of the present application also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, so that the computer device executes a method provided in any embodiment of the present application.

[0151] The system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0152] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0153] In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0154] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process or an execution thread, and a component may be located on a computer or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may communicate, for example, through local or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, or a network, such as the Internet interacting with other systems through signals).

[0155] The above describes some embodiments of the present application with reference to the accompanying drawings, but does not limit the scope of the present invention. Any modification, equivalent substitution and improvement made by those skilled in the art without departing from the scope and essence of the present invention shall be within the scope of the present application.

Claims

1. A method for determining parasitic parameters of an integrated chip, characterized in that: The method comprises: Based on a plurality of contour coordinates of each conductor in the calculation area of ​​the integrated chip, a conductor area and a boundary area are determined; wherein the boundary area is an area in the calculation area excluding the conductor area and the conductor; Constructing a Gaussian surface of the conductor to be predicted in the conductor region, and performing uniform sampling on the Gaussian surface according to a preset sampling interval to obtain a plurality of sampling points; Acquire a physical information neural network model; the physical information neural network model is obtained by training the sample sampling points obtained by sampling the conductor area and the boundary area, and the sampling density of the conductor area is greater than the sampling density of the boundary area; The parasitic parameters of the sampling points are predicted by using the physical information neural network model to obtain parasitic parameter prediction data of the conductor to be predicted.

2. The method for determining parasitic parameters of an integrated chip according to claim 1, characterized in that: The physical information neural network model includes a first fully connected network module and a second fully connected network module. The parasitic parameter prediction of the sampling point is performed by the physical information neural network model to obtain the parasitic parameter prediction data of the conductor to be predicted, including: Predicting the potential of the sampling point through the first fully connected network module to obtain first parasitic parameter prediction data; the first fully connected network module is used to predict the potential of the conductor area; The second fully connected network module is used to predict the electric potential of the sampling point to obtain second parasitic parameter prediction data; the second fully connected network module is used to predict the electric potential of the boundary area; According to a preset level set function, the first parasitic parameter prediction data and the second parasitic parameter prediction data, the parasitic parameter prediction data of the conductor to be predicted is obtained; wherein the level set function characterizes the relationship between the sampling point and the center coordinates of the conductor area and the size information of the conductor area.

3. The method for determining parasitic parameters of an integrated chip according to claim 2, characterized in that: The first fully connected network module and the second fully connected network module are both provided with three branch sub-networks, wherein two branch sub-networks each include a first input layer and a first hidden layer connected in sequence, and another branch sub-network includes a second input layer, a plurality of second hidden layers and an output layer connected in sequence, and the first hidden layers are all connected to the input of each of the second hidden layers other than the first layer, and the parasitic parameter prediction data of the conductor area and the parasitic parameter prediction data of the boundary area are both obtained by the following steps: Inputting the sampling points into the first input layer and the second input layer of the first fully connected network module and the second fully connected network module at the same time; For each of the first hidden layers, obtaining first output data according to the first input layer corresponding to the first hidden layer; For the second hidden layer of the first layer, obtaining second output data according to the second input layer connected to the second hidden layer; For each second hidden layer outside the first layer, obtaining third output data according to the second output data of the second hidden layer connected to the previous corresponding layer and the two first output data; For each of the output layers, prediction is performed according to the third output data output by the second hidden layer correspondingly connected to the output layer to obtain the parasitic parameter prediction data.

4. The method for determining parasitic parameters of an integrated chip according to claim 1, characterized in that: The physical information neural network model is trained through the following steps: A residual loss function, a boundary loss function and a continuity constraint loss function are configured; wherein the residual loss function represents the mean square sum of the equation residuals of the sample sampling points in the conductor region and in the boundary region; the boundary loss function represents the sum of the mean square error of the potential of the sample sampling points on the outer boundary of the conductor in the conductor region and the mean square error of the electric field of the sample sampling points on the outer boundary of the boundary region; the continuity constraint loss function represents the mean square error of the potential and the partial derivative of the potential of the sample sampling points at the junction of the conductor region and the boundary region; Determine a target loss function according to the residual loss function, the boundary loss function and the continuity constraint loss function; Acquire a sample point set of the conductor area and the boundary area; Based on the target loss function and the sample sampling point set, the initial physical information neural network model is trained to obtain a trained physical information neural network model.

5. The method for determining parasitic parameters of an integrated chip according to claim 4, characterized in that: The physical information neural network model includes a first fully connected network module and a second fully connected network module; The residual loss function is set to: Among them, the L r Represents the residual loss value, the N c represents the number of sample points in the conductor area, and the N b represents the number of sample points in the boundary area, and the (x i，c ,y i，c ) represents the sample sampling point in the conductor area, and the (x i，b ,y i，b ) represents the sample sampling point in the boundary area; the residual of the equation ;in, is the second-order partial derivative of the potential at the sample sampling point (x, y) with respect to x, is the sample sampling point ( x， y) is the second-order partial derivative of the potential with respect to y; k is the dielectric constant; The boundary loss function is set to: Among them, the represents the boundary loss value, is the number of sample points on the conductor boundary in the conductor region, is the number of sample points on the outer boundary of the boundary area, U(x i，d ,y i，d ) represents the sample sampling point (x i，d ,y i，d )’s potential, Based on the conductor boundary condition, the sample sampling point (x i，d ,y i，d ) is the potential value assigned; q θ (x i，n ,y i，n ) represents the sample sampling point (x i，n ,y i，n )’s normal electric field strength; The sample sampling point (x i，n ,y i，n ) is the normal electric field strength value assigned; h n is a sampling interval uniformly sampled on the outer boundary of the boundary area; The continuity constraint loss function is set as: in, is the continuity loss value, (x i，I ,y i，I ) is a sampling point at the junction of the conductor area and the boundary area; U θ，c (x i，I ,y i，I ) is the output of the first fully connected network module (x i，I ,y i，I ) potential, U θ，b (x i，I ,y i，I ) represents the output of the second fully connected network module (x i，I ,y i，I )’s potential; is the number of sample points at the junction of the conductor area and the boundary area.

6. The method for determining parasitic parameters of an integrated chip according to claim 4, characterized in that: The obtaining of the sample sampling point set of the conductor area and the boundary area comprises: Determining a minimum reference spacing of the calculation area according to the plurality of contour coordinates; According to a preset sample sampling point number strategy, random sampling is performed in the conductor area and the boundary area; Obtaining a calculation region boundary sampling spacing, a junction sampling spacing, and a conductor boundary sampling spacing, wherein the calculation region boundary sampling spacing, the junction sampling spacing, and the conductor boundary sampling spacing are all determined based on the minimum reference spacing, and the conductor boundary sampling spacing is smaller than the junction sampling spacing; the junction sampling spacing is smaller than the calculation region boundary sampling spacing; Uniformly sampling the outer boundary of the boundary area, the boundary between the calculation area and the conductor area, and the contour of the conductor according to the calculation area boundary sampling spacing, the junction sampling spacing, and the conductor boundary sampling spacing; The sample sampling points obtained by uniform sampling and the sample sampling points obtained by random sampling are combined to obtain the sample sampling point set.

7. The method for determining parasitic parameters of an integrated chip according to claim 6, characterized in that: The minimum reference spacing is determined by the following steps: According to the coordinates of each contour, the X-axis spacing and Y-axis spacing with the smallest coordinate spacing are calculated respectively; Determine, according to each contour coordinate, a first minimum side length of each conductor projection in the X-axis direction and a second minimum side length in the Y-axis direction; A minimum reference spacing is determined according to the first minimum side length, the second minimum side length, the X-axis spacing, and the Y-axis spacing.

8. The method for determining parasitic parameters of an integrated chip according to claim 1, characterized in that: The physical information neural network model is trained through the following steps: The initial physical information neural network model is trained based on a preset learning rate adaptive adjustment strategy; When the number of training iterations of the initial physical information neural network model meets a preset number of iterations, the training of the initial physical information neural network model is stopped to obtain an intermediate physical information neural network model; Training the intermediate physical information neural network model by a memory-constrained quasi-Newton method; When the output result of the intermediate physical information neural network model meets the preset convergence condition, the training of the intermediate physical information neural network model is stopped to obtain the physical information neural network model.

9. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the parasitic parameter determination method of the integrated chip as described in any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The method comprises storing computer executable instructions, wherein the computer executable instructions are used to be executed by a processor to implement the parasitic parameter determination method of the integrated chip as claimed in any one of claims 1 to 9.

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