Chip design inspection method and device, electronic equipment, storage medium and chip

Abstract

The embodiment of the invention provides an inspection method and device for chip design, electronic equipment, a storage medium and a chip, and relates to the technical field of chip design, and the inspection method comprises the steps: reading the arrangement information of a function module, and displaying a first bounding box coordinate of the function module on the top layer of the chip in the top layer inspection of the chip, the top layer inspection comprises design rule inspection of the chip, the arrangement information comprises a second bounding box coordinate of the function module in the bottom layer of the chip, and the first bounding box coordinate and the second bounding box coordinate have a preset mapping relation; obtaining a third bounding box coordinate of the violation information marked by the design rule check; according to a preset mapping relation, the third bounding box coordinates are reversely marked into a design file of the corresponding function module. According to the method, the technical problem of operation separation between the current independent DRC and the Full Chip DRC can be solved, so that the number of iterations between the independent DRC and the Full Chip DRC can be reduced, and the chip design efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a chip design inspection method, device, electronic device, storage medium and chip. Background Art

[0002] In order to adapt to the current development trend of lightweight smart devices, the degree of integration of chips is getting higher and higher. Tens of thousands of transistors are integrated on a silicon wafer. In particular, VLSI (Very-Large-Scale Integration) can even integrate more than hundreds of thousands of transistors.

[0003] For high-integration chip design, the chip is currently divided into many sub-modules for easy management and optimization, thereby improving the design convergence efficiency of the entire chip. In actual production, each sub-module of the chip is usually first subjected to a separate DRC (Design Rule Check) and then integrated into the top layer for Full Chip DRC (Full Chip Design Rule Check). During this process, the separate DRC and Full Chip DRC will be iterated several times to meet the design rule requirements of the process factory.

[0004] However, due to the operational separation problem between the current individual DRC and Full Chip DRC, the iteration time between the individual DRC and Full Chip DRC increases and the labor cost increases during the chip design process. Summary of the invention

[0005] The embodiments of the present application provide a chip design inspection method, device, electronic device, storage medium and chip, which can solve the current technical problem of operational separation between individual DRC and Full Chip DRC, thereby reducing the number of iterations between individual DRC and Full Chip DRC and improving the efficiency of chip design.

[0006] In a first aspect, an embodiment of the present application provides a method for inspecting a chip design, wherein the chip includes a plurality of functional modules, and the method includes:

[0007] In a top-level inspection of the chip, layout information of the functional module is read, and first bounding box coordinates of the functional module are displayed on a top-level of the chip, the top-level inspection includes a design rule check of the chip, the layout information includes second bounding box coordinates of the functional module in a bottom-level of the chip, and the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship;

[0008] Obtaining a third bounding box coordinate of the violation information indicated by the design rule check;

[0009] According to the preset mapping relationship, the coordinates of the third boundary box are reversed into the design file of the corresponding functional module.

[0010] The chip design inspection method proposed in the first aspect of the embodiment of the present application, in the top-level inspection of the chip, reads the second bounding box coordinates that can reflect the position and size of the functional module in the chip at the bottom layer of the chip, and the first bounding box coordinates of the corresponding functional module at the top layer of the chip. In this way, the violation information of the Full Chip DRC in the top-level inspection can be transferred to the first bounding box coordinates through the electronic design automation software, and then based on the preset mapping relationship between the first bounding box coordinates and the second bounding box coordinates, the third bounding box coordinates of the above violation information are reversed to the second bounding box coordinates, thereby being able to solve the technical problem of operational fragmentation caused by different functional modes of the design software at different levels in chip design, thereby reducing the duration of each iteration of the top-level design and bottom-level design of the chip, and there is no need to manually perform separate DRC annotations on the functional modules based on the results of the Full Chip DRC, thereby reducing labor costs and improving the efficiency of the entire chip design.

[0011] In some embodiments, the inspection method further includes:

[0012] converting the arrangement information into a library exchange format file;

[0013] In the top-level inspection of the chip, reading the layout information of the functional modules includes:

[0014] In the top-level inspection of the chip, the library exchange format file corresponding to the functional module is read.

[0015] In some implementations, the back-labeling of the third bounding box coordinates to the design file of the corresponding functional module includes:

[0016] converting the third bounding box coordinates into a script sequence;

[0017] The script sequence is stored in the design file of the corresponding functional module.

[0018] In some implementations, the arrangement information further includes an arrangement orientation of the functional module in the bottom layer of the chip;

[0019] The preset mapping relationship includes:

[0020] In a case where the arrangement orientation of the functional module is the same as the reference orientation of the top layer of the chip, the first bounding box coordinate vector and the second bounding box coordinate vector are parallel;

[0021] In the case where the arrangement orientation of the functional module is different from the reference orientation of the top layer of the chip, the preset mapping relationship is determined based on the angular relationship between the arrangement orientation and the reference orientation.

[0022] In a second aspect, an embodiment of the present application provides another inspection method for chip design, wherein the chip includes a plurality of functional modules, and the functional modules include a plurality of hard core units. The inspection method includes:

[0023] In a top-level inspection of the chip, the layout information of the functional module is read, and the first bounding box coordinates and the layout orientation of the functional module are displayed on the top level of the chip, wherein the layout information includes the second bounding box coordinates and the layout orientation of the functional module in the bottom level of the chip, and the fourth bounding box coordinates and the layout orientation of at least one target hard core unit among the plurality of hard core units under the second bounding box coordinates, wherein the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship;

[0024] According to the preset mapping relationship, converting the fourth bounding box coordinates of the target hard core unit into the top layer of the chip to obtain the fifth bounding box coordinates of the target hard core unit in the top layer of the chip;

[0025] Based on the first bounding box coordinates and layout orientation of the functional module and the fifth bounding box coordinates and layout orientation of the target hard core unit, the distribution state of the top layer of the chip is checked to determine whether the chip meets the process standard.

[0026] The inspection method proposed in the second aspect of the embodiment of the present application converts the hard-core units that need to be inspected to the top layer of the chip through the mapping relationship between the corresponding functional modules at the bottom layer and the top layer of the chip, thereby enabling chip designers to directly observe the distribution status of each hard-core unit in the top-level chip design, so that designers can promptly discover problems such as missing or unreasonable distribution of hard-core units that need to be inspected, reduce rework, and thereby improve the efficiency of the entire chip design.

[0027] In some embodiments, the inspection method further includes:

[0028] generating a virtual library exchange format file based on the arrangement information;

[0029] In the top-level inspection of the chip, reading the layout information of the functional modules includes:

[0030] In the top-level inspection of the chip, the virtual library exchange format file corresponding to the functional module is read.

[0031] In some implementations, inspecting the distribution state of the top layer of the chip based on the first bounding box coordinates and the arrangement orientation of the functional module and the fifth bounding box coordinates and the arrangement orientation of the target hard core unit includes:

[0032] Based on the first bounding box coordinates and arrangement orientation of the functional module and the fifth bounding box coordinates and arrangement orientation of the target hard core unit, construct a plurality of virtual instances of the functional modules and the target hard core units at the top layer of the chip;

[0033] The distribution status of the virtual instances in the top layer of the chip is checked to determine whether the chip meets the process standard.

[0034] In some implementations, the target hardware core unit includes a clamp device unit, and the top-level inspection includes a design rule check of the chip;

[0035] The checking the distribution state of the virtual instances in the top layer of the chip to determine whether the chip meets the process standard includes:

[0036] Determining a maximum interval between two adjacent clamping device units based on a process standard of the design rule check;

[0037] Based on the maximum spacing, a functional module missing the clamping device unit is identified in the top layer of the chip.

[0038] In some implementations, the preset mapping relationship includes:

[0039] In a case where the arrangement orientation of the functional module is the same as the reference orientation of the top layer of the chip, the first bounding box coordinate vector and the second bounding box coordinate vector are parallel;

[0040] In the case where the arrangement orientation of the functional module is different from the reference orientation of the top layer of the chip, the preset mapping relationship is determined based on the angular relationship between the arrangement orientation and the reference orientation.

[0041] In a third aspect, an embodiment of the present application provides a chip design inspection device, wherein the chip includes a plurality of functional modules, and the inspection device includes:

[0042] a first reading unit, configured to read the arrangement information of the functional module in a top-level inspection of the chip, and display the first bounding box coordinates of the functional module on the top-level of the chip, wherein the top-level inspection includes a design rule check of the chip, the arrangement information includes the second bounding box coordinates of the functional module in the bottom-level of the chip, and the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship;

[0043] an acquiring unit, configured to acquire a third bounding box coordinate of the violation information indicated by the design rule check;

[0044] The back-marking unit is used to back-mark the third boundary box coordinates into the design file of the corresponding functional module according to the preset mapping relationship.

[0045] In a fourth aspect, an embodiment of the present application provides another inspection device for chip design, wherein the chip includes a plurality of functional modules, the functional modules include a plurality of hard core units, and the inspection device includes:

[0046] a second reading unit, configured to read the arrangement information of the functional module in the top-level inspection of the chip, and to display the first bounding box coordinates and the arrangement orientation of the functional module on the top-level of the chip, wherein the arrangement information includes the second bounding box coordinates and the arrangement orientation of the functional module in the bottom-level of the chip, and the fourth bounding box coordinates and the arrangement orientation of at least one target hard core unit among the plurality of hard core units under the second bounding box coordinates, wherein the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship;

[0047] a conversion unit, configured to convert the fourth bounding box coordinates of the target hard core unit into the top layer of the chip according to the preset mapping relationship, so as to obtain the fifth bounding box coordinates of the target hard core unit in the top layer of the chip;

[0048] The inspection unit is used to inspect the distribution status of the top layer of the chip based on the first bounding box coordinates and layout orientation of the functional module and the fifth bounding box coordinates and layout orientation of the target hard core unit to determine whether the chip meets the process standards.

[0049] In a fifth aspect, an embodiment of the present application provides an electronic device, including:

[0050] Memory for storing computer programs;

[0051] A memory is used to execute the computer program to implement the steps of the inspection method described in any one of the first aspects and / or to implement the steps of the inspection method described in any one of the second aspects.

[0052] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program runs on a computer or a processor, the computer or the processor executes the steps of the inspection method described in any one of the first aspects, and / or executes the steps of the inspection method described in any one of the first aspects.

[0053] In a seventh aspect, an embodiment of the present application provides a chip, wherein the chip adopts the inspection method as described in any one of the first aspect and / or the inspection method as described in any one of the second aspect.

[0054] The technical effects obtained in the above-mentioned third to seventh aspects are similar to the technical effects obtained by the corresponding technical means in the first and second aspects, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] Figure 1 A schematic diagram of a chip design optimization method provided in an embodiment of the present application;

[0057] Figure 2 A schematic diagram of a chip functional module arrangement provided in an embodiment of the present application;

[0058] Figure 3 A schematic diagram of the location of Full Chip DRC violation information at the top layer of a chip provided in an embodiment of the present application;

[0059] Figure 4 A schematic diagram of the location of Full Chip DRC violation information at the bottom layer of a chip provided in an embodiment of the present application;

[0060] Figure 5 A schematic flow chart of another chip design inspection method provided in an embodiment of the present application;

[0061] Figure 6 A schematic diagram of another chip functional module arrangement provided in an embodiment of the present application;

[0062] FIG. 7A to FIG. 7D A schematic diagram of text information of a chip function module provided in an embodiment of the present application;

[0063] Figure 8 A schematic diagram of another chip functional module arrangement proposed in an embodiment of the present application;

[0064] Fig. 9 A schematic diagram of another chip functional module arrangement provided in an embodiment of the present application;

[0065] Fig.10 A schematic diagram of another chip functional module arrangement provided in an embodiment of the present application;

[0066] Fig.11A schematic diagram of the structure of an inspection device provided in an embodiment of the present application;

[0067] Fig.12 A schematic diagram of the structure of another inspection device provided in an embodiment of the present application;

[0068] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0070] It should be understood that the "multiple" mentioned herein refers to two or more. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish between the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0071] In addition, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, product, or apparatus.

[0072] First, some terms and concepts that may be involved in the embodiments of this application are explained and described as follows:

[0073] Chip design: The entire production and manufacturing of a chip generally includes three stages, namely front-end design, back-end design and packaging. The back-end design is the process of converting the logic circuit design into a physical layout. In the later stages of the back-end design, there is a physical verification process, which includes design rule checking and layout comparison. The inspection method proposed in this application is also used in this process.

[0074] Chip bottom-level design and chip top-level design: Chip bottom-level design refers to the basic architecture and circuit design that constitute the entire chip, including instruction set architecture, IP core (Intellectual Property Core), etc. These are the raw materials and foundation of chip design, which determine the basic functions and performance of the chip.

[0075] Chip top-level design refers to the integration and coordination of various modules of the entire chip in chip design to achieve the expected functions of the chip. This usually involves complex system integration, including interface design, signal integrity, power management, etc. between different modules.

[0076] In the embodiments of the present application, the chip bottom layer design and the chip top layer design are respectively referred to as the chip bottom layer and the chip top layer.

[0077] In the inspection method proposed in the example of this application, the bottom-level chip design is aimed at individual inspections of each module in the chip and the hard-core devices under each module, such as the individual DRC mentioned above; the top-level chip design is to perform Full Chip DRC inspections and layout distribution inspections on each module and its subordinate hard-core devices from the perspective of the chip as a whole.

[0078] In the embodiments of the present application, the chip bottom layer design and the chip top layer design are respectively referred to as the chip bottom layer and the chip top layer.

[0079] The modules mentioned above refer to the modules arranged in the chip floorplan in the embodiment of the present application. A chip may include multiple modules, each of which has complete logical function attributes. Each module also includes multiple hard-core devices, which are pre-designed and verified circuit modules with specific functions, such as MEMORY (memory circuit core), IP (intellectual property core), CLAMP (clamp device), etc.

[0080] DRC: Also known as design rule checking, it is a very important part in the field of semiconductor and electronic engineering. It is mainly used to verify whether the design meets the manufacturing requirements of a specific process node. DRC checking is usually performed at the back end of chip design, especially in the physical verification stage. It includes checking the geometry of the layout to ensure that all design rules are met.

[0081] Full Chip DRC: Also known as full chip design rule check, it is a check on whether the entire chip layout design meets specific process manufacturing rules. In the embodiment of the present application, it is performed in the chip top-level design, which is called top-level inspection.

[0082] Density DRC (density design rule check): It is one aspect of Full Chip DRC, which ensures that the design density of some electronic circuit devices (such as transistors, wires, pads, etc.) in the IC (Integrated Circuit) meets specific process requirements.

[0083] EDA (Electronic Design Automation) tools: Computer-aided design tools used to design, verify and manufacture electronic systems. They have a wide range of functions, including circuit simulation, hardware language description, circuit layout, design rule checking, etc.

[0084] ESD (Electrostatic Discharge): Electrostatic discharge refers to the charge transfer phenomenon caused by objects with different electrostatic potentials approaching or directly contacting each other. In the field of electronics, ESD may cause serious damage to electronic equipment and integrated circuits.

[0085] As mentioned above, in the chip design process, the chip bottom design and the chip top design need to go through multiple iterations, and at different design levels, it is necessary to use different functions of the same electronic design automation tool, or different electronic design automation tools to perform design rule checks, layout distribution rationality checks, etc. Therefore, there is a separation between the operation of the electronic design automation tool in the chip bottom design and the chip top design, that is, the operation or application mode of the tool software used in the chip top design is not applicable to the chip bottom design, and because the chip bottom design and the chip top design need to go through multiple iterations, the problems found in the chip top design (such as DRC violations in a module in the chip) cannot be directly (for example, with the help of EDA tools, etc.) fed back to the chip bottom design. Therefore, in the related art, for the problems in the chip bottom design found in the chip top design, they all need to be manually fed back separately, which increases the labor cost, and also increases the iteration time, which in turn affects the duration of the entire chip design cycle.

[0086] In view of this, an embodiment of the present application proposes a chip design inspection method to at least solve the above technical defects.

[0087] The chip design inspection method proposed in the embodiment of the present application can be implemented by electronic design automation software (such as EDA tools) in chip design. Figure 1 , Figure 1 A schematic flow chart of a chip design optimization method provided in an embodiment of the present application includes: S110 to S130.

[0088] S110. In the top-level inspection of the chip, the layout information of the functional module can be read through the EDA tool, and the first bounding box coordinates of the functional module can be displayed on the top level of the chip. The top-level inspection includes a design rule check on the chip. The layout information includes the second bounding box coordinates of the functional module in the bottom level of the chip. The first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship.

[0089] It should be noted that in the embodiments of the present application, the chip mentioned can be understood as an integrated circuit that has not yet been packaged unless otherwise specified, and is divided into multiple functional modules, each of which has complete logical functional attributes.

[0090] As mentioned above, the method provided by the embodiment of the present application can be applied to the physical verification process in chip design. In this process, it is divided into chip top-level design and bottom-level design. In the chip top-level design, each functional module of the chip is targeted for a separate DRC, and in the chip top-level design, the top-level inspection is performed with the entire chip as the target, and the top-level inspection includes a DRC targeting the entire chip, i.e., Full Chip DRC.

[0091] It should be noted that the bounding box coordinates proposed in the embodiment of the present application can be expressed in a diagonal point representation or in a coordinate point combined with width and height.

[0092] The second bounding box coordinates in the layout information of the functional module are read in the chip top-level design, and the second bounding box coordinates represent the position and size of the functional module in the chip bottom layer, and the first bounding box coordinates of the same functional module are displayed in the top-level design, and the first bounding box coordinates represent the position and size of the functional module in the chip top layer, and the two have a preset mapping relationship, and the preset mapping relationship can reflect the projection relationship between the chip top layer and the chip bottom layer, that is, there is a mapping relationship between the coordinate points in the first bounding box coordinates and the coordinate points in the second bounding box coordinates.

[0093] In some examples, the above-mentioned arrangement information also includes the arrangement orientation of the functional modules in the bottom layer of the chip;

[0094] The above preset mapping relationships include:

[0095] When the arrangement orientation of the functional module is the same as the reference orientation of the top layer of the chip, the first bounding box coordinate vector and the second bounding box coordinate vector are parallel;

[0096] In the case where the arrangement orientation of the functional module is different from the reference orientation of the top layer of the chip, the preset mapping relationship is determined based on the angular relationship between the arrangement orientation and the reference orientation.

[0097] It should be noted that the reference orientation of the chip top layer can be understood as the prescribed layout orientation of each circuit module and circuit device in the chip design. Due to the operational separation between the chip bottom layer design and the chip top layer design, the layout orientation of the functional modules is not necessarily exactly the same as the reference orientation. Therefore, the orientation problem needs to be considered when determining the preset mapping relationship.

[0098] Exemplarily, when the arrangement orientation of the functional module is the same as the reference orientation of the top layer of the chip, the first bounding box coordinate vectors are parallel to the second bounding box coordinate vectors, that is, the coordinates in the two boxes have a multiple relationship, such as:

[0099]

[0100] in, represents the vector within the first bounding box coordinates, Represents the vector within the coordinates of the second bounding box, where k is a non-zero constant.

[0101] When the arrangement orientation of the functional module is different from the reference orientation of the top layer of the chip, the rotation formula of the two-dimensional coordinate system can be used to transform the vectors into parallel situations based on the angular relationship between the arrangement orientation of the functional module and the reference orientation, thereby determining the preset mapping relationship between the first bounding box coordinates and the second bounding box coordinates.

[0102] Exemplarily, the clockwise angle difference between the above arrangement orientation and the above reference orientation is θ, that is, the above first bounding box coordinates are rotated clockwise by θ to obtain the above second bounding box coordinates (without considering the translation problem). The coordinates of a certain coordinate point in the above first bounding box coordinates are (x, y), and the coordinates of the point in the first bounding box coordinates are (x', y'), which can be calculated by the following formula:

[0103] xcos(θ)-ysin(θ)=x' (2)

[0104] xsin(θ)+ycos(θ)=y' (3)

[0105] It should be noted that the above coordinate transformation method is not unique, and those skilled in the art should select a suitable transformation method according to the specific situation. The method proposed in the embodiment of the present application is only used as an example or reference.

[0106] S120 , obtaining the third bounding box coordinates of the violation information indicated by the design rule check.

[0107] It should be noted that the above-mentioned design rule check refers to the Full Chip DRC mentioned above. The violation information indicated by the Full Chip DRC will be listed in detail through the EDA tool, including the type, location, severity and other information of the violation. The location of the violation is expressed in the form of the third bounding box coordinates.

[0108] Exemplarily, taking the functional module IP in the chip as an example, when the Full Chip DRC detects that the IP module has a violation, the third bounding box coordinates of the violation information are obtained through the EDA tool.

[0109] S130 . According to a preset mapping relationship, reverse-label the coordinates of the third bounding box into a design file of a corresponding functional module.

[0110] Exemplarily, after obtaining the third bounding box coordinates of the violation information of the Full Chip DRC corresponding to the IP module from step S120, the third bounding box coordinates are converted to the first bounding box coordinates of the IP module, that is, the violation information is represented in the first bounding box coordinates. After obtaining the represented third bounding box coordinates, based on the preset mapping relationship between the first bounding box coordinates and the second bounding box coordinates, the represented third bounding box coordinates are converted to the second bounding box coordinates, and the converted third bounding box coordinates are directly fed back to the design file of the IP module through the EDA tool to complete the back-labeling.

[0111] In order to better understand the technical solution proposed in the embodiment of the present application, a specific example is given below for illustration. It should be noted that, unless otherwise specified, Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 8 , Fig. 9 as well as Fig.10 The shaded structure in the middle represents the perspective of the corresponding functional module or hard core unit at the top layer of the chip, and the blank structure represents the perspective of the corresponding functional module or hard core unit at the bottom layer of the chip.

[0112] Figure 2 A schematic diagram of a chip functional module arrangement provided in an embodiment of the present application, such as Figure 2 As shown, Figure 2In the figure, ddr (dynamic random access memory) represents the bottom layer of the chip, ddr_sys represents a functional module in the ddr with violation information, and its position in the top layer of the chip is indicated by shadow. The first bounding box coordinate of ddr_sys in the top layer of the chip is represented by a coordinate point with width and height, in the form of {coordinate-x, coordinate-y, width, height} corresponding to {x-axis coordinate of point C, y-axis coordinate of point C, width, height}, respectively. Figure 2 The first bounding box coordinates of ddr_sys are {767.52, 3028.992, 3700.32, 999.168}. The second bounding box coordinates are read. The layout orientation of ddr_sys is set to R0, which is the same as the reference orientation of the top layer of the chip. Assuming that there is no relative translation between the two, it can be understood that k in the above formula (1) is 1, and the bounding box coordinates of ddr_sys on the top layer and the bottom layer of the chip are the same.

[0113] Perform Full Chip DRC on the chip, such as Figure 3 As shown, Figure 3 A schematic diagram of the FullChip DRC violation information at the top level of the chip provided in the embodiment of the present application, taking the Density DRC in the Full Chip DRC as an example, obtaining Figure 3 The third bounding box coordinates of the Density DRC at the top layer of the chip are expressed in the form of {coordinate-x1, coordinate-y1, coordinate-x2, coordinate-y2}, corresponding to {x-axis coordinate of point A, y-axis coordinate of point A, x-axis coordinate of point B, y-axis coordinate of point B}, respectively. Figure 3 The third bounding box coordinates of the Density DRC Marker (i.e., the violation information of the Full Chip DRC mentioned above) are {2900.0, 3300, 3100, 3600}, which indicates the position of the Density DRC Marker on the top layer of the chip when Density DRC is performed on the chip.

[0114] The position of the Density DRC Marker is obtained in the top layer of the chip, and the violation information is determined to be in the functional module ddr_sys. The EDA tool is used to learn that the third bounding box coordinates of the top layer of the chip are {2900.0, 3300, 3100, 3600}, and the first bounding box coordinates of ddr_sys in the top layer of the chip are {767.52, 3028.992, 3700.32, 999.168}.

[0115] Figure 4A schematic diagram of the location of Full Chip DRC violation information at the bottom layer of the chip provided in an embodiment of the present application. Figure 4 As shown, based on the preset mapping relationship between the first bounding box coordinates and the second bounding box coordinates in this example, by subtracting the coordinates, the representation of the Density DRC Marker in the second bounding box coordinates is obtained as {2132.48, 271.008, 2332.48, 571.008}, that is, Figure 4 The bounding box coordinates corresponding to A' and B' are fed back to the design file of ddr_sys to complete the back-labeling.

[0116] The process of converting the third bounding box coordinates to the first bounding box coordinates can be performed through EDA tool commands, for example:

[0117] dbTransform-inst$inst-globalPt{29003300}

[0118] Based on this command, 2132.48271.008 is generated, that is Figure 4 The coordinates of point A'.

[0119] dbTransform-inst$inst-globalPt{31003600}

[0120] Based on this command, 2332.48571.008 is generated, that is Figure 4 The coordinates of point B'.

[0121] In summary, the chip design inspection method proposed in the embodiment of the present application, in the top-level inspection of the chip, reads the second bounding box coordinates that can reflect the position and size of the functional module in the chip at the bottom layer of the chip, and the first bounding box coordinates of the corresponding functional module at the top layer of the chip. In this way, the violation information of FullChip DRC in the top-level inspection can be transferred to the first bounding box coordinates through the electronic design automation software, and then based on the preset mapping relationship between the first bounding box coordinates and the second bounding box coordinates, the third bounding box coordinates of the above violation information are reversed to the second bounding box coordinates, thereby being able to solve the technical problem of operational fragmentation caused by different functional modes of the design software at different levels in chip design, thereby reducing the duration of each iteration of the top-level design and bottom-level design of the chip, and there is no need to manually perform separate DRC annotations on the functional modules based on the results of Full ChipDRC, thereby reducing labor costs and improving the efficiency of the entire chip design.

[0122] According to some embodiments, the inspection method further includes:

[0123] Converting layout information into a library exchange format file;

[0124] The above step S110 includes: in the top-level inspection of the chip, reading the library exchange format file corresponding to the functional module.

[0125] It should be noted that LEF (Library Exchange Format) is a standard file format for describing the physical properties of an integrated circuit library unit, which includes various functional information of a functional module.

[0126] Exemplarily, after the bottom-layer design of the chip is completed, the name, position, orientation, length, width and other information of the functional module are converted into an LEF file and stored in the local design file of the functional module. In this way, the local design file can be directly read through EDA tools or other electronic design automation software to obtain the layout information of the corresponding functional module in the bottom layer of the chip.

[0127] In some examples, the above step S130 includes:

[0128] Convert the third bounding box coordinates into a script sequence;

[0129] Store the script sequence in the design file of the corresponding function module.

[0130] It should be noted that the above script sequence can be understood as a script sequence file, which is a text file containing a series of commands or operation steps. By reading it, the corresponding steps can be automatically executed.

[0131] For example, the third bounding box coordinates that have been converted into the second bounding box coordinates can be converted into a script sequence file by an EDA tool. Figures 2 to 4 For example, the coordinates of the third bounding box after conversion are {2132.48, 271.008, 2332.48, 571.008}. The following command: createMarker-type Density_DRC_1-bbox{2132.48271.0082332.48571.008} can be stored in the ddr_sys.drc.tcl script file of the function module ddr_sys. In this way, the command "source ddr_sys.drc.tcl" is executed in the function module ddr_sys to display the DRC violation information in the top layer of the chip, such as Figure 4 As shown in the Density DRC Marker.

[0132] In the relevant technologies of chip design, since each module inside the chip is in a similar packaging state, the designers at the top level of the chip cannot directly see the distribution status of the hard-core devices inside each module at the top level, which increases the time and difficulty of chip design review.

[0133] In view of this problem and the same inventive concept, the embodiment of the present application provides another chip design inspection method to at least solve the above technical defects. Similarly, the chip design inspection method proposed in the embodiment of the present application can also be implemented by electronic design automation software (such as EDA tools) in chip design, such as Figure 5 As shown, Figure 5 A schematic flow chart of another chip design inspection method provided in an embodiment of the present application includes: S210 to S2130.

[0134] S210. In the top-level inspection of the chip, the layout information of the functional module is read, and the first bounding box coordinates and layout orientation of the functional module are displayed on the top level of the chip. The layout information includes the second bounding box coordinates and layout orientation of the functional module in the bottom level of the chip, and the fourth bounding box coordinates and layout orientation of at least one target hard core unit among the multiple hard core units under the second bounding box coordinates. The first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship.

[0135] It should be noted that, among the multiple functional modules of the above chip, each functional module includes multiple hard core units, and the hard core units may be MEMORY, IP, CLAMP, etc. Moreover, the chip includes a large number of transistors, forming a large number of circuit units, namely hard core units. In the top-level inspection, it is not necessary to inspect all types of hard core units. Therefore, in the embodiment of the present application, it is only necessary to obtain the layout information of the hard core unit type (target hard core unit) that needs to be inspected.

[0136] For example, in the top-level inspection of the chip, the layout information of the functional module can be read through the EDA tool. The layout information includes the second bounding box coordinates and layout orientation of the entire functional module at the bottom layer of the chip. The layout information also includes the fourth bounding box coordinates and layout orientation of the hard core unit that needs to be inspected in the functional module under the second bounding box coordinates.

[0137] In some examples, the above preset mapping relationship includes:

[0138] When the arrangement orientation of the functional module is the same as the reference orientation of the top layer of the chip, the first bounding box coordinate vector and the second bounding box coordinate vector are parallel;

[0139] In the case where the arrangement orientation of the functional module is different from the reference orientation of the top layer of the chip, the preset mapping relationship is determined based on the angular relationship between the arrangement orientation and the reference orientation.

[0140] It can be understood that the explanation and elaboration of the technical solutions of the embodiments of the present application have been described in detail in the first aspect of the present application and will not be repeated here.

[0141] S220 . According to a preset mapping relationship, convert the fourth bounding box coordinates of the target hard core unit into the top layer of the chip to obtain the fifth bounding box coordinates of the target hard core unit in the top layer of the chip.

[0142] It should be noted that, through the preset mapping relationship between the first bounding box coordinates and the second bounding box coordinates of the functional module to which the target hard core unit belongs, the fourth bounding box coordinates under the second bounding box coordinates can be converted to the first bounding box coordinates. The first bounding box coordinates belong to the top layer of the chip design, that is, the target hard core unit is converted from the bottom layer perspective of the chip to the functional module perspective of the top layer of the chip, and then further converted from the functional module perspective of the top layer of the chip to the top layer perspective of the chip, thereby obtaining the above-mentioned fifth bounding box coordinates.

[0143] Exemplarily, step S220 may be completed by executing a scripting language through an EDA tool.

[0144] S230 , based on the first bounding box coordinates and layout orientation of the functional module and the fifth bounding box coordinates and layout orientation of the target hard core unit, inspect the distribution state of the top layer of the chip to determine whether the chip meets the process standard.

[0145] It should be noted that the above process standards can determine whether the distribution of each hard-core component is reasonable and whether the spacing is appropriate.

[0146] For example, in the top-level chip design, the first bounding box coordinates and layout orientation of the acquired functional modules, as well as the fifth bounding box coordinates and layout orientation of the target hard core units in the top level of the chip are displayed, and designers can intuitively identify the distribution status of each functional module and the subordinate hard core units in the top level of the chip.

[0147] According to some embodiments, the inspection method further includes:

[0148] generating a virtual library interchange format file based on the arrangement information;

[0149] The above step S210 includes: in the top-level inspection of the chip, reading the virtual library exchange format file corresponding to the functional module.

[0150] It should be noted that, compared with the LEF file, the Dummy LEF (Dummy Library Exchange Format file) is a temporary, virtual standard file format for describing the physical properties of the integrated circuit library unit.

[0151] For example, Figures 2 to 4 Taking the functional module ddr_sys in the chip as an example, after the chip bottom layer design is completed, a dummy LEF file is generated based on the name, position, orientation, length, width and other information of the functional module and its subordinate hard core units, and saved in the text file ddr_sys.macro.loc.info. In this way, ddr_sys.macro.loc.info can be directly read through EDA tools or other electronic design automation software to obtain the layout information of the corresponding functional module and its subordinate hard core units in the chip bottom layer.

[0152] In some examples, the above step S230 includes: constructing virtual instances of multiple functional modules and multiple target hard core units at the top layer of the chip based on the first bounding box coordinates and arrangement orientation of the functional module and the fifth bounding box coordinates and arrangement orientation of the target hard core unit;

[0153] Check the distribution of virtual instances in the top layer of the chip to determine whether the chip meets the process standards.

[0154] Exemplarily, an EDA tool is used to read the first bounding box coordinates and layout orientation of the functional module at the top layer of the chip, as well as the fifth bounding box coordinates and layout orientation corresponding to the target hard core unit at the chip layer, to construct a dummy instance (Dummy Instance) of the corresponding functional module and hard core unit at the top layer of the chip, thereby presenting the position and orientation of each functional module and its internal hard core device at the top layer of the chip.

[0155] In the chip Full Chip DRC, the ESD requirements of the chip need to be met, and a CLAMP needs to be added at a suitable position in the chip design. Based on this, the embodiment of the present application proposes a technical solution to determine the appropriate position of the CLAMP. The above-mentioned step of inspecting the distribution status of the virtual instance in the top layer of the chip to determine whether the chip meets the process standard can be performed in the following manner:

[0156] Based on the process standard of the design rule check, the maximum interval between two adjacent clamping device units is determined;

[0157] Based on the maximum spacing, functional blocks with missing clamping device units are identified in the top layer of the chip.

[0158] It should be noted that the process standard of the Full Chip DRC may be related to the ESD requirement. Based on the process standard, the maximum interval between any two adjacent CLAMPs is determined. It can be understood that for a CLAMP, there must be at least another CLAMP within the radius of the maximum interval.

[0159] For example, based on the virtual instances of the functional modules and the CLAMPs corresponding to the functional modules constructed previously on the top layer of the chip, designers can intuitively observe the positions of the CLAMPs and the functional modules corresponding to the bottom layer of the chip on the top layer of the chip, and based on the above-mentioned maximum interval, designers can directly identify which functional modules have missing CLAMPs, or further identify CLAMP position offset problems based on process requirements, thereby avoiding rework due to problems with the CLAMPs in the functional modules, avoiding risks in advance, and reducing the review time and difficulty of chip design.

[0160] In order to better understand the technical solution proposed in the embodiment of the present application, a specific example is given below for illustration.

[0161] Figure 6 A schematic diagram of another chip functional module arrangement provided in an embodiment of the present application, Figure 6 The schematic diagram of the layout of each hard core unit at the bottom layer of the chip is shown, where the functional module ddr_sys includes hard core units ddrphy, PLL, and CLAMP, where ddrphy and PLL correspond to IP cores, and CLAMP corresponds to clamp devices. The EDA tool captures the layout information of ddr_sys at the bottom layer of the chip (the above second bounding box coordinates, layout direction) and the layout information of ddrphy, PLL, and CLAMP in ddr_sys (the above fourth bounding box coordinates, layout direction), and generates ddr_sys and the DummyLEFs of ddrphy, PLL, and CLAMP, as shown in the figure. FIG. 7A to FIG. 7D As shown, Fig. 7A , Figure 7B , Figure 7C as well as Fig.7D The text information of the functional module ddr_sys, the clamp device CLAMP, the IP core PLL, and the Dummy LEF of the IP core ddrphy are displayed respectively.

[0162] In the chip top-level design, the EDA tool command loadLefFile is used to read the above Dummy LEF file, and based on the read information, a Dummy Instance is created for ddr_sys and its internal ddrphy, PLL, and CLAMP at the chip top level, so that the position and orientation of ddr_sys and its internal ddrphy, PLL, and CLAMP can be presented at the chip top level. Figure 8 As shown, Figure 8 This is a schematic diagram of another chip functional module arrangement proposed in an embodiment of the present application. Figure 8 It shows the position and orientation of the functional module ddr_sys and its internal hard core units ddrphy, PLL, and CLAMP from the top-level perspective of the chip ddr.

[0163] To implement this step specifically, take the hard core unit CLAMP as an example. Figures 2 to 4 Based on the example, the coordinates of the functional module ddr_sys at the top layer of the chip, that is, the first bounding box coordinates mentioned above, are {767.52, 3028.992, 3700.32, 999.168}, the orientation is R0, and the second bounding box coordinates of ddr_sys and the first bounding box coordinates are equal in vector.

[0164] EDA tools read CLAMP's Dumm LEF file ( Figure 7B As shown in the figure, it is known that it is at R90 on the bottom layer of the chip. Since the orientation of ddr_sys on the top layer and the bottom layer of the chip is R0, the orientation of CLAMP on the top layer of the chip is still R90. The EDA tool then grabs the fourth bounding box coordinates of CLAMP under the second bounding box coordinates of ddr_sys, and based on the preset mapping relationship that the second bounding box coordinates of ddr_sys and the first bounding box coordinates are equal in vector, combined with the arrangement orientation of CLAMP on the top layer of the chip, the bounding box coordinates of CLAMP under the first bounding box coordinates of ddr_sys are {1757.286, 440.448, 104.544, 21.984}, which can be regarded as the coordinates of CLAMP in the ddr_sys frame from the perspective of the top layer of the chip. This process can be implemented through TCL (Tool Command Language, a scripting language).

[0165] Further, based on the first bounding box coordinates of ddr_sys being {767.52, 3028.992, 3700.32, 999.168} and the bounding box coordinates of CLAMP under the first bounding box coordinates of ddr_sys being {1757.286, 440.448, 104.544, 21.984}, the two are added together to obtain the fifth bounding box coordinates of CLAMP on the top layer of the chip being {2524.806, 3469.44, 104.544, 21.984}.

[0166] It should be noted that the bounding box coordinates of the aforementioned CLAMP are expressed in the form of coordinate points combined with width and height.

[0167] Fig. 9 Based on the fifth bounding box coordinates and arrangement orientation R90 of CLAMP, a corresponding virtual instance is established on the top layer of the chip through the EDA tool, and the position of CLAMP in ddr_sys can be observed on the top layer of the chip, such as Fig. 9 As shown, Fig. 9 A schematic diagram of another chip functional module arrangement provided in an embodiment of the present application, Fig. 9 The black solid box in the middle represents the CLAMP from the perspective of the top layer of the chip. The situations of other hard core units are similar and will not be described in detail.

[0168] By adopting the above method for each functional module and internal hard-core unit in the chip, the top-level chip designer can directly observe the distribution status of each hard-core unit in each functional module at the bottom of the chip from a top-level perspective, thereby reducing rework caused by problems with each hard-core unit and avoiding risks in advance.

[0169] Furthermore, as a test device that meets ESD requirements, designers need to observe the distribution of CLAMP on the entire chip. Through the previous method, all current virtual instances of CLAMP can be represented at the top level of the chip, such as Fig.10 As shown, Fig.10 A schematic diagram of another chip functional module arrangement provided in an embodiment of the present application is provided. Fig.10 The black solid boxes in the figure represent the distribution of CLAMP. The interval between any two adjacent parallel dashed lines is the same, which is the maximum interval mentioned above. Fig.10 Which part of the area is identified (such as Fig.10 The functional module corresponding to the area D) surrounded by the dotted box needs to add CLAMP.

[0170] It should be noted that the inspection method of the first aspect and the inspection method of the second aspect proposed in the embodiments of the present application can be used separately or simultaneously in chip design. When used simultaneously, there is no requirement for the execution order.

[0171] The method embodiments according to the present application are described above by way of example. Based on the inspection method provided by the embodiments of the present application in the first aspect, the embodiments of the present application provide an inspection device. Fig.11 This is a schematic diagram of the structure of an inspection device provided in an embodiment of the present application. Fig.11 , the inspection device includes the following units.

[0172] A first reading unit 110 is used to read the layout information of the functional module in the top-level inspection of the chip, and to display the first bounding box coordinates of the functional module on the top-level of the chip, the top-level inspection includes a design rule check of the chip, the layout information includes the second bounding box coordinates of the functional module in the bottom-level of the chip, and the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship;

[0173] An acquisition unit 120, configured to acquire the third bounding box coordinates of the violation information indicated by the design rule check;

[0174] The reverse labeling unit 130 is used to reverse label the third boundary box coordinates into the design file of the corresponding functional module according to a preset mapping relationship.

[0175] Based on the inspection method provided in the embodiment of the present application in the second aspect, the embodiment of the present application provides another inspection device. Fig.12 This is a schematic diagram of the structure of another inspection device provided in an embodiment of the present application. Fig.12 , the inspection device includes the following units.

[0176] A second reading unit 210 is used to read the layout information of the functional module in the top-level inspection of the chip, and display the first bounding box coordinates and layout orientation of the functional module on the top-level of the chip, wherein the layout information includes the second bounding box coordinates and layout orientation of the functional module in the bottom-level of the chip, and the fourth bounding box coordinates and layout orientation of at least one target hard core unit among the plurality of hard core units under the second bounding box coordinates, wherein the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship;

[0177] A conversion unit 220, configured to convert the fourth bounding box coordinates of the target hard core unit to the top layer of the chip according to the preset mapping relationship, so as to obtain the fifth bounding box coordinates of the target hard core unit in the top layer of the chip;

[0178] The inspection unit 230 is used to inspect the distribution status of the top layer of the chip based on the first bounding box coordinates and layout orientation of the functional module and the fifth bounding box coordinates and layout orientation of the target hard core unit to determine whether the chip meets the process standards.

[0179] The above describes the device embodiments of the present application. For detailed descriptions of the specific execution processes of data, terms, nouns, steps, technical issues and effects, alternative methods and combinations, please refer to the descriptions in the method embodiments, which will not be repeated here.

[0180] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a computer or a processor, the computer or the processor executes the steps of the inspection method described in any one of the first aspects, and / or executes the steps of the inspection method described in any one of the first aspects.

[0181] An embodiment of the present application also provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program of the inspection method described in any one of the first aspects and / or the inspection method described in any one of the second aspects, and the processor is used to use the computer program when executing the inspection method.

[0182] For example, Fig.13 As shown, the electronic device includes a processor 300, at least one communication bus 400, a user interface 500, at least one external communication interface 600 and a memory 700. The communication bus 400 is configured to realize the connection and communication between these components. The user interface 500 may include a display screen, and the external communication interface 600 may include a standard wired interface and a wireless interface. The memory 700 stores a computer program. The processor 300 is used to execute the computer program stored in the memory 700.

[0183] The description of the above computer program product, computer-readable storage medium, and electronic device is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the computer program product, computer-readable storage medium, and electronic device of this application, please refer to the description of the method embodiment of this application for understanding.

[0184] An embodiment of the present application further provides a chip, which adopts the inspection method as described in any one of the first aspects and / or the inspection method as described in any one of the second aspects.

[0185] The sequence of serial numbers or introduction of the embodiments of the present application is for description only and does not represent the superiority or inferiority of the embodiments.

[0186] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0187] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0188] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0189] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disc (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)). It is worth noting that the computer-readable storage medium mentioned in the embodiment of the present application may be a non-volatile storage medium, in other words, a non-transient storage medium.

[0190] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the embodiments of this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the scene data of the current frame in the three-dimensional virtual scene, the device information of the client, and the scene interaction information involved in the embodiments of this application are all obtained with full authorization.

Claims

1. A chip design inspection method, characterized in that: The chip includes multiple functional modules, and the inspection method includes: In a top-level inspection of the chip, layout information of the functional module is read, and first bounding box coordinates of the functional module are displayed on a top-level of the chip, the top-level inspection includes a design rule check of the chip, the layout information includes second bounding box coordinates of the functional module in a bottom-level of the chip, and the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship; Obtaining a third bounding box coordinate of the violation information indicated by the design rule check; According to the preset mapping relationship, the coordinates of the third boundary box are reversed into the design file of the corresponding functional module.

2. The inspection method according to claim 1, characterized in that: Also includes: converting the arrangement information into a library exchange format file; In the top-level inspection of the chip, reading the layout information of the functional modules includes: In the top-level inspection of the chip, the library exchange format file corresponding to the functional module is read.

3. The inspection method according to claim 2, characterized in that: The step of back-marking the coordinates of the third boundary box to the design file of the corresponding functional module includes: converting the third bounding box coordinates into a script sequence; The script sequence is stored in the design file of the corresponding functional module.

4. The inspection method according to any one of claims 1 to 3, characterized in that: The arrangement information also includes the arrangement orientation of the functional modules in the bottom layer of the chip; The preset mapping relationship includes: In a case where the arrangement orientation of the functional module is the same as the reference orientation of the top layer of the chip, the first bounding box coordinate vector and the second bounding box coordinate vector are parallel; In the case where the arrangement orientation of the functional module is different from the reference orientation of the top layer of the chip, the preset mapping relationship is determined based on the angular relationship between the arrangement orientation and the reference orientation.

5. A chip design inspection method, characterized in that: The chip includes a plurality of functional modules, each of which includes a plurality of hard core units, and the inspection method includes: In a top-level inspection of the chip, the layout information of the functional module is read, and the first bounding box coordinates and the layout orientation of the functional module are displayed on the top level of the chip, wherein the layout information includes the second bounding box coordinates and the layout orientation of the functional module in the bottom level of the chip, and the fourth bounding box coordinates and the layout orientation of at least one target hard core unit among the plurality of hard core units under the second bounding box coordinates, wherein the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship; According to the preset mapping relationship, converting the fourth bounding box coordinates of the target hard core unit into the top layer of the chip to obtain the fifth bounding box coordinates of the target hard core unit in the top layer of the chip; Based on the first bounding box coordinates and layout orientation of the functional module and the fifth bounding box coordinates and layout orientation of the target hard core unit, the distribution state of the top layer of the chip is checked to determine whether the chip meets the process standard.

6. The inspection method according to claim 5, characterized in that: Also includes: generating a virtual library exchange format file based on the arrangement information; In the top-level inspection of the chip, reading the layout information of the functional modules includes: In the top-level inspection of the chip, the virtual library exchange format file corresponding to the functional module is read.

7. The inspection method according to claim 6, characterized in that: The checking the distribution state of the top layer of the chip based on the first bounding box coordinates and the arrangement orientation of the functional module and the fifth bounding box coordinates and the arrangement orientation of the target hard core unit includes: Based on the first bounding box coordinates and arrangement orientation of the functional module and the fifth bounding box coordinates and arrangement orientation of the target hard core unit, construct a plurality of virtual instances of the functional modules and the target hard core units at the top layer of the chip; The distribution status of the virtual instances in the top layer of the chip is checked to determine whether the chip meets the process standard.

8. The inspection method according to claim 7, characterized in that: The target hardware core unit includes a clamp device unit, and the top-level inspection includes a design rule check on the chip; The checking the distribution state of the virtual instances in the top layer of the chip to determine whether the chip meets the process standard includes: Determining a maximum interval between two adjacent clamping device units based on a process standard of the design rule check; Based on the maximum spacing, a functional module missing the clamping device unit is identified in the top layer of the chip.

9. The inspection method according to any one of claims 5 to 8, characterized in that: The preset mapping relationship includes: In a case where the arrangement orientation of the functional module is the same as the reference orientation of the top layer of the chip, the first bounding box coordinate vector and the second bounding box coordinate vector are parallel; In the case where the arrangement orientation of the functional module is different from the reference orientation of the top layer of the chip, the preset mapping relationship is determined based on the angular relationship between the arrangement orientation and the reference orientation.

10. A chip design inspection device, characterized in that: The chip includes multiple functional modules, and the inspection device includes: a first reading unit, configured to read the arrangement information of the functional module in a top-level inspection of the chip, and display the first bounding box coordinates of the functional module on the top-level of the chip, wherein the top-level inspection includes a design rule check of the chip, the arrangement information includes the second bounding box coordinates of the functional module in the bottom-level of the chip, and the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship; an acquiring unit, configured to acquire a third bounding box coordinate of the violation information indicated by the design rule check; The back-labeling unit is used to back-label the third boundary box coordinates into the design file of the corresponding functional module according to the preset mapping relationship.

11. A chip design inspection device, characterized in that: The chip includes a plurality of functional modules, the functional modules include a plurality of hard core units, and the inspection device includes: a second reading unit, configured to read the arrangement information of the functional module in the top-level inspection of the chip, and to display the first bounding box coordinates and the arrangement orientation of the functional module on the top-level of the chip, wherein the arrangement information includes the second bounding box coordinates and the arrangement orientation of the functional module in the bottom-level of the chip, and the fourth bounding box coordinates and the arrangement orientation of at least one target hard core unit among the plurality of hard core units under the second bounding box coordinates, wherein the first bounding box coordinates and the second bounding box coordinates have a preset mapping relationship; a conversion unit, configured to convert the fourth bounding box coordinates of the target hard core unit into the top layer of the chip according to the preset mapping relationship, so as to obtain the fifth bounding box coordinates of the target hard core unit in the top layer of the chip; The inspection unit is used to inspect the distribution status of the top layer of the chip based on the first bounding box coordinates and layout orientation of the functional module and the fifth bounding box coordinates and layout orientation of the target hard core unit to determine whether the chip meets the process standards.

12. An electronic device, characterized in that: include: Memory for storing computer programs; A memory for executing the computer program to implement the steps of the inspection method according to any one of claims 1 to 4, and / or to implement the steps of the inspection method according to any one of claims 5 to 9.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program runs on a computer or a processor, the computer or the processor executes the steps of the inspection method described in any one of claims 1 to 4, and / or executes the steps of the inspection method described in any one of claims 5 to 9.

14. A chip, characterized in that: The chip adopts the inspection method according to any one of claims 1 to 4 and / or the inspection method according to any one of claims 5 to 9.

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