Chip x-state propagation root cause analysis method, electronic device and medium

Abstract

The present invention relates to the field of chip technology, and in particular to a chip x-state propagation root cause analysis method, electronic device and medium. The method comprises: S1, obtaining chip IP information in a chip design to be tested; S2, performing simulation based on the chip design to be tested, and recording the output ports of all minimum component units that output x-states during the simulation process and the corresponding time when the x-state first appears in the first list; S3, determining the earliest minimum component unit that first appears the x-state as a first target minimum component unit, and determining other minimum component units in the first list as second target minimum component units; S4, recording the IP containing the second target minimum component unit. n Determine the target IP n ; S5, parallel acquisition of the first target minimum component unit and each target IP n The invention improves the chip x-state propagation root cause analysis speed, thereby improving the chip verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip x-state propagation root cause analysis method, electronic equipment and medium. Background Art

[0002] During the chip verification process, what is usually transmitted in the chip is usually 0 or 1, and in some cases it may also be a high-impedance state z. The above three states are all normal states. When the chip transmits the x state, it is an abnormal state. The transmission of the x state may be caused by the internal structure of the chip component module itself, or it may be transmitted from other chip component modules, so it is necessary to analyze the root cause of the x state propagation. In the prior art, it is necessary to obtain all signal waveforms, and then combine all signal waveforms and the chip RTL (Register Transfer Level) code to analyze the root cause of the x state propagation. However, due to the large scale of the chip, the existing chip x state propagation root cause analysis method takes a lot of time and is very slow, resulting in low efficiency of chip verification. It can be seen from this that how to improve the speed of chip x state propagation root cause analysis, and then improve the chip verification efficiency has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The object of the present invention is to provide a chip x-state propagation root cause analysis method, electronic equipment and medium, which improves the chip x-state propagation root cause analysis speed and thus improves chip verification efficiency.

[0004] According to a first aspect of the present invention, a chip x-state propagation root cause analysis method is provided, comprising:

[0005] Step S1, obtain the chip IP information {IP1, IP2, ..., IP n ,...,IP N}, IP n is the nth IP information in the chip design to be tested. The value range of n is 1 to N. N is the total number of chip IPs in the chip design to be tested. n =(AU1 n ,AU2 n ,...,Au i n ,...,AU f(n) n ), Au i n IP n The i-th smallest component in the system, i ranges from 1 to f(n), f(n) is IP nThe number of minimum components contained in the chip IP is composed of the minimum components and / or the chip components composed of the minimum components. The chip IP contains the minimum components or the chip components composed of the minimum components. The level setting of the minimum components;

[0006] Step S2, performing simulation based on the chip design to be tested, and recording the output ports of all the smallest constituent units that output the x state and the corresponding time when the x state first appears in the simulation process in a preset first list;

[0007] Step S3, determining the minimum component unit corresponding to the output port of the minimum component unit in which the x state first appears in the preset first list as the first target minimum component unit, and determining the minimum component units corresponding to the output ports of other minimum component units in the preset first list except the output port of the first target minimum component unit as the second target minimum component unit;

[0008] Step S4: {IP1, IP2, ..., IP n ,...,IP N} contains the IP of the second target minimum component unit n Determine the target IP n ;

[0009] Step S5: Acquire the first target minimum component unit and each target IP in parallel n The waveform information is used to perform root cause analysis of x-state propagation.

[0010] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0011] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0012] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the chip x-state propagation root cause analysis method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0013] The present invention establishes a corresponding relationship between the minimum unit and the chip IP in advance, records the output ports of the minimum component units of all output x states and the corresponding time of the first appearance of the x state in each simulation process, determines the target for which the waveform needs to be acquired through the output ports of the minimum component units of all output x states and the corresponding time of the first appearance of the x state in the simulation process, and only needs to acquire the waveform corresponding to the target to perform the x-state propagation root cause analysis, thereby reducing the number of waveforms that need to be acquired, improving the speed of the chip x-state propagation root cause analysis, and further improving the chip verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A flow chart of a chip x-state propagation root cause analysis method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0017] The embodiment of the present invention provides a chip x-state propagation root cause analysis method, such as Figure 1 As shown, including:

[0018] Step S1, obtain the chip IP information {IP1, IP2, ..., IP n ,...,IP N}, IP n The nth IP (Intellectual Property) information in the chip design to be tested. The value range of n is 1 to N, and N is the total number of chip IPs in the chip design to be tested. Chip IP is the chip intellectual property core, which refers to a circuit module with specific functions that is pre-designed in the integrated circuit design. IP n =(AU1 n ,AU2 n ,...,Au i n ,...,AU f(n) n ), Aui n IP n The i-th smallest component in the system, i ranges from 1 to f(n), f(n) is IP n The number of minimum components included in the chip IP is composed of the minimum components and / or the chip components composed of the minimum components. The chip IP contains the minimum components or the chip components composed of the minimum components. The level setting of the module.

[0019] It should be noted that different values ​​of n may also lead to different values ​​of f(n), that is, the number of minimum components of different chip IPs may also be different. The chip IP contains the minimum component unit or the chip component module level setting composed of the minimum component unit. Except for the top level of the chip design to be tested, all minimum component units and chip component modules have parent modules, the minimum component unit has no sub-modules, and the chip component modules have sub-modules. IP n Defines the mapping relationship between the nth IP and the smallest component unit contained in the nth IP.

[0020] Step S2: Simulate based on the chip design to be tested, and record in a preset first list the output ports of all minimum constituent units that output the x state during the simulation process and the corresponding time when the x state first appears.

[0021] It should be noted that the preset first list only needs to record the time when the x-state first appears corresponding to the output port of each minimum component unit. On the premise of meeting the subsequent chip x-state propagation root cause analysis, the amount of information acquired is greatly reduced and the efficiency of the chip x-state propagation root cause analysis is improved.

[0022] Step S3, determine the minimum component unit corresponding to the output port of the minimum component unit in which the x state first appears in the preset first list as the first target minimum component unit, and determine the minimum component unit corresponding to the output port of other minimum component units in the preset first list except the output port of the first target minimum component unit as the second target minimum component unit.

[0023] It should be noted that the minimum component unit corresponding to the output port of the minimum component unit where the x state first appears must be the minimum component unit where the x state propagation root cause exists. Therefore, the corresponding minimum component unit can be directly located based on the output port of the minimum component unit where the x state first appears, and the corresponding minimum component unit is determined as the first target minimum component unit. The first target minimum component unit is the minimum component unit where the x state propagation root cause exists in the first target minimum component unit. The x state appears in the output port of the second target minimum component unit, which may be due to the x state propagation root cause inside the second target minimum component unit, or it may be due to factors such as the interconnection between the component modules in the IP where the second target minimum component unit is located. Therefore, it is necessary to determine the IP corresponding to each second target minimum component unit through step S4.

[0024] Step S4: {IP1, IP2, ..., IP n ,...,IP N} contains the IP of the second target minimum component unit n Determine the target IP n .

[0025] It should be noted that through steps S3 and S4, the root cause of x-state propagation is initially located to the first target minimum component unit and the target IP n , then you only need to obtain the first target minimum component unit and target IP n The waveform can be analyzed without acquiring all waveforms, which greatly reduces the amount of waveform information acquired and the amount of subsequent data analysis, and improves the speed of chip x-state propagation root cause analysis.

[0026] Step S5: Acquire the first target minimum component unit and each target IP in parallel n The waveform information is used to perform root cause analysis of x-state propagation.

[0027] It should be noted that the embodiment of the present invention can realize parallel processing of the first target minimum component unit and each target IP n The waveform information is analyzed to further improve the root cause analysis speed of chip x-state propagation.

[0028] In order to further improve the speed of root cause analysis of x-state propagation, factors that will definitely lead to the occurrence of x-state may be corrected before simulation. As an embodiment, before step S2, the following is further included:

[0029] Step S10, traverse the chip design to be tested, obtain each preselected input port information of each minimum component unit in the chip design to be tested, and store each preselected input port information in a preset second list, the preselected input port information includes a preselected input port identifier and a preselected input port type, the preselected input port is an input port that may cause an x ​​state, the input port type includes a fixed value type, a floating type and a multi-drive type, the fixed value type input port is an input port with a fixed input value set, the floating type input port is an input port set to a floating state, and the multi-drive type input port is an input port connected to multiple input sources.

[0030] It should be noted that fixed value input ports will be set to fixed input values ​​0 or 1. Fixed value input ports themselves will not input x state, but when entering the smallest unit, x state may be generated due to the interconnection inside the smallest unit. Therefore, fixed value input ports are the root cause of x state. Floating input ports will definitely appear in x state during the simulation process, so they need to be processed in advance before simulation. Multi-drive input ports pre-set according to the design of the chip under test can appear in the design of the chip under test. Multi-drive input ports that are not pre-set will definitely appear in x state during the simulation process, so they need to be processed in advance before simulation.

[0031] Step S20, determine whether the currently preset second list only contains fixed value type input ports and / or multi-drive type input ports belonging to the preset multi-drive type port list; if so, execute step S2; otherwise, execute step S30, wherein the preset multi-drive type port list is used to store pre-set multi-drive type ports that can exist.

[0032] It should be noted that if the currently preset second list only contains fixed value type input ports and / or multi-drive type input ports in the preset multi-drive type port list, it means that there is no input port in the current chip design to be tested that will definitely lead to the root cause of the x state, and simulation can be entered.

[0033] Step S30, updating the dangling type ports in the currently preset second list in the chip design under test and the multi-drive type interfaces that do not exist in the preset multi-drive type port list, and returning to execute step S10.

[0034] It should be noted that if the currently preset second list contains not only fixed value type input ports and / or multi-drive type input ports belonging to the preset multi-drive type port list, it means that there are input ports that will definitely appear in the x state during the simulation process, and it is necessary to adjust the design of the chip to be tested and pre-process the input ports that will definitely appear in the x state to reduce the subsequent analysis of the root cause of the x state.

[0035] In order to further improve the efficiency of analyzing the root cause of the x state, the information of the first occurrence of the x state at the minimum component unit input port may be recorded, and the step S2 includes:

[0036] Step S21 : recording the input ports of the smallest constituent units of all input x-states during the simulation process and the corresponding time when the x-state first appears in the preset first list.

[0037] As an embodiment, the step S2 further includes:

[0038] Step S22, when the output port of the minimum component unit that currently outputs the x state for the first time is obtained, determine whether there is an input port of the minimum component unit corresponding to the output port of the minimum component unit that currently outputs the x state for the first time in the currently preset first list; if not, record the minimum component unit corresponding to the output port of the minimum component unit that currently outputs the x state for the first time in the preset pre-selected component unit list.

[0039] It should be noted that, through step S22, the information of the input port and output port of the minimum component unit appearing in the x state can also be combined. When the output port information of the minimum component unit appears in the x state for the first time, and the input port has not appeared in the x state, it means that there must be a root cause of the x state inside the minimum unit. Therefore, this type of minimum component unit can be recorded in the preset pre-selected component unit list.

[0040] On the basis of generating the pre-selected component list, in step S3, the first target minimum component can be further determined in combination with the pre-selected component list, and the second target minimum component can be reduced, thereby more accurately narrowing the scope of subsequent waveform analysis.

[0041] As an embodiment, step S3 includes:

[0042] Step S31: Determine the minimum component unit corresponding to the output port of the minimum component unit in which the x state appears earliest in the preset first list as the first target minimum component unit.

[0043] Step S32: Determine the minimum component unit corresponding to the output port of the minimum component unit in the preset first list in the preset pre-selected component unit list as the first target minimum component unit.

[0044] It should be noted that there must be a root cause of the x state inside the minimum component unit in the preset pre-selected component unit list. Therefore, for the minimum component unit corresponding to the output port of the minimum component unit in the preset first list, if it exists in the preset pre-selected component unit list, it can be directly determined as the first target minimum component unit without analyzing the entire IP in which it is located, further narrowing the scope of analysis.

[0045] Step S33: Determine the minimum component units corresponding to the output ports of other minimum component units except the output port of the first target minimum component unit in the preset first list as the second target minimum component unit.

[0046] As an embodiment, step S5 includes:

[0047] Step S51, parallelly obtain the waveform information of each target module, the target module is the first target minimum component unit or target IP n .

[0048] Step S52, performing x-state propagation root cause analysis based on the waveform information of each target module and the output port of the minimum component unit of the output x-state and / or the input port of the minimum component unit of the input x-state corresponding to each target module in the preset first list, and the pre-selected input port information in the preset second list.

[0049] It should be noted that the output port of the minimum component unit of the output x state, the input port of the minimum component unit of the input x state corresponding to the first list, and the pre-selected input port information in the preset second list can provide analysis direction for the root cause analysis of the x-state propagation of the target module, further speeding up the speed of the root cause analysis of the x-state propagation.

[0050] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0051] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0052] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0053] The embodiment of the present invention pre-establishes a corresponding relationship between the minimum unit and the chip IP, records the output ports of the minimum component units of all output x states and the corresponding time of the first appearance of the x state in each simulation process, determines the target for which a waveform needs to be acquired through the output ports of the minimum component units of all output x states and the corresponding time of the first appearance of the x state in the simulation process, and only needs to acquire the waveform corresponding to the target for x-state propagation root cause analysis, thereby reducing the number of waveforms that need to be acquired, improving the speed of chip x-state propagation root cause analysis, and thereby improving chip verification efficiency.

[0054] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A root cause analysis method for chip x-state propagation, characterized in that: include: Step S1, obtain the chip IP information {IP1, IP2, ..., IP n ,...,IP N }, IP n is the nth IP information in the chip design to be tested. The value range of n is 1 to N. N is the total number of chip IPs in the chip design to be tested. n =(AU1 n ,AU2 n ,...,Au i n ,...,AU f(n) n ), Au i n IP n The i-th smallest component in the system, i ranges from 1 to f(n), f(n) is IP n The number of minimum components contained in the chip IP is composed of the minimum components and / or the chip components composed of the minimum components. The chip IP contains the minimum components or the chip components composed of the minimum components. The level setting of the module; Step S2, performing simulation based on the chip design to be tested, and recording the output ports of all the smallest constituent units that output the x state and the corresponding time when the x state first appears in the simulation process in a preset first list; Step S3, determining the minimum component unit corresponding to the output port of the minimum component unit in which the x state first appears in the preset first list as the first target minimum component unit, and determining the minimum component units corresponding to the output ports of other minimum component units in the preset first list except the output port of the first target minimum component unit as the second target minimum component unit; Step S4: {IP1, IP2, ..., IP n ,...,IP N } contains the IP of the second target minimum component unit n Determine the target IP n ; Step S5: Acquire the first target minimum component unit and each target IP in parallel n The waveform information is used to perform root cause analysis of x-state propagation.

2. The method according to claim 1, characterized in that Before step S2, the following steps are also included: Step S10, traverse the chip design to be tested, obtain each pre-selected input port information of each minimum component unit in the chip design to be tested, and store each pre-selected input port information in a preset second list, the pre-selected input port information includes a pre-selected input port identifier and a pre-selected input port type, the pre-selected input port is an input port that may cause an x ​​state, the input port type includes a fixed value type, a floating type and a multi-drive type, the fixed value type input port is an input port with a fixed input value, the floating type input port is an input port set to a floating state, and the multi-drive type input port is an input port connected to multiple input sources; Step S20, determining whether the currently preset second list contains only fixed value type input ports and / or multi-drive type input ports in the preset multi-drive type port list, if so, executing step S2, otherwise, executing step S30, wherein the preset multi-drive type port list is used to store the preset multi-drive type ports that can exist; Step S30, updating the dangling type ports in the currently preset second list in the chip design under test and the multi-drive type interfaces that do not exist in the preset multi-drive type port list, and returning to execute step S10.

3. The method according to claim 1 or 2, characterized in that: Step S21 : recording the input ports of the smallest constituent units of all input x-states during the simulation process and the corresponding time when the x-state first appears in the preset first list.

4. The method according to claim 3, characterized in that The step S2 further comprises: Step S22, when the output port of the minimum component unit that currently outputs the x state for the first time is obtained, determine whether there is an input port of the minimum component unit corresponding to the output port of the minimum component unit that currently outputs the x state for the first time in the currently preset first list; if not, record the minimum component unit corresponding to the output port of the minimum component unit that currently outputs the x state for the first time in the preset pre-selected component unit list.

5. The method according to claim 4, characterized in that The step S3 comprises: Step S31, determining the minimum component unit corresponding to the output port of the minimum component unit that appears the x state earliest in the preset first list as the first target minimum component unit; Step S32, determining the minimum component unit corresponding to the output port of the minimum component unit in the preset first list in the preset pre-selected component unit list as the first target minimum component unit; Step S33: Determine the minimum component units corresponding to the output ports of other minimum component units except the output port of the first target minimum component unit in the preset first list as the second target minimum component unit.

6. The method according to claim 2, characterized in that The step S5 comprises: Step S51, parallel acquisition of waveform information of each target module, the target module being the first target minimum component unit or target IP n ; Step S52, performing x-state propagation root cause analysis based on the waveform information of each target module and the output port of the minimum component unit of the output x-state and / or the input port of the minimum component unit of the input x-state corresponding to each target module in the preset first list, and the pre-selected input port information in the preset second list.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.

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