Chip layout method, chip, equipment and storage medium
By obtaining chip power bump information and determining and independently powered voltage coverage areas, the chip layout dispersed and power network incomplete problems are solved, reducing power consumption and improving reliability and thermal management performance.
Patent Information
- Application Number
- CN202411366047.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2024-12-27
AI Technical Summary
In the prior art, the dispersed chip layout leads to failure of power analysis simulation, which requires re-planning of layout and wiring, affecting the design progress, and the timing-driven layout of the dual-track SRAM leads to incomplete power network, which easily leads to local overheating and signal integrity problems.
By obtaining the power bump information of the chip, the first voltage coverage area and the second voltage coverage area of the target SRAM are determined and powered independently, avoiding the additional voltage conversion unit, saving area and trace resources, optimizing voltage drop, and according to the application Scenario adjustment of the power supply voltage.
It reduces the power consumption of the macro module, improves the reliability and thermal management performance of the chip, avoids local overheating problems caused by uneven distribution of power bumps, and simplifies the power network design.
Smart Images
Figure CN119203906A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip design technology, and in particular to a chip layout method, chip, device and storage medium. Background Art
[0002] As the scale of semiconductor chips and the complexity of chip systems increase, the impact of chip power consumption is becoming increasingly greater. How to achieve low-power chips has always been a key issue for the industry. Static Random-Acess Memory (SRAM) is widely used in chip design as a macro module. How to reduce chip power consumption, especially how to reduce the power consumption of macro modules, is a key issue that the industry needs to solve urgently.
[0003] In the prior art, dual-track SRAM can be used as a macro module in a low-power chip. Generally, only timing-driven layout is performed on the dual-track SRAM layout, that is, only the critical path in the timing information is identified, and the layout process is driven and guided based on the critical path in the timing information.
[0004] However, the chip layout obtained by adopting this layout method will be relatively scattered, which will cause the power analysis simulation (Power Analysis, PA for short) to fail. In serious cases, the layout and wiring need to be re-planned, affecting the design progress. Summary of the invention
[0005] The purpose of this application is to provide a chip layout method, chip, device and storage medium to address the deficiencies in the above-mentioned prior art, so as to solve the problem that the chip layout obtained in the prior art is relatively scattered, and in severe cases, the layout and wiring need to be re-planned, which affects the design progress.
[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
[0007] In a first aspect, an embodiment of the present application provides a chip layout method, the method comprising:
[0008] Acquire power bump information of a chip, wherein the power bump information includes: a position of the power bump of the chip in the chip;
[0009] Determine a first voltage coverage area and a second voltage coverage area of a target static random access memory to be laid out on the chip according to the power bump information and preset constraint information, wherein the constraint information includes: the first voltage coverage area is located in a boundary area of the chip;
[0010] Arranging the storage unit of the target static random access memory in the first voltage coverage area, and arranging the peripheral unit of the target static random access memory in the second voltage coverage area;
[0011] A first power supply network of the storage unit is arranged according to the arrangement position of the storage unit, and a second power supply network of the peripheral unit is arranged according to the arrangement position of the peripheral unit, and the first power supply network and the second power supply network are independently powered.
[0012] As a possible implementation, determining the first voltage coverage area and the second voltage coverage area of the target static random access memory to be laid out on the chip according to the power bump information and the preset constraint information includes:
[0013] Determining the coverage of each of the power bumps according to the power bump information;
[0014] Determining the first voltage coverage area according to the coverage range of each of the power bumps and the constraint information;
[0015] The second voltage coverage area is determined according to the first voltage coverage area.
[0016] As a possible implementation manner, determining the first voltage coverage area according to the coverage range of each of the power bumps and the constraint information includes:
[0017] Determine at least one target power bump that satisfies the constraint information according to the coverage of each of the power bumps and the constraint information;
[0018] An area formed by the coverage range of the at least one target power bump is used as the first voltage coverage area.
[0019] As a possible implementation manner, the step of arranging the storage unit of the target static random access memory in the first voltage coverage area and arranging the peripheral unit of the target static random access memory in the second voltage coverage area includes:
[0020] Arranging the storage unit of the target static random access memory in the first voltage coverage area, and arranging the peripheral unit of the target static random access memory in the second voltage coverage area;
[0021] A soft placement blocking area is arranged between the storage unit and the peripheral unit.
[0022] As a possible implementation manner, the step of arranging the first power supply network of the storage unit according to the arrangement position of the storage unit includes:
[0023] Arranging a first power line and a second power line for the storage unit at the input and output interface position of the target static random access memory;
[0024] The buffer unit on the first power line is arranged according to the position of the storage unit and the power access position on the chip.
[0025] As a possible implementation, arranging the buffer unit on the first power line according to the position of the storage unit and the power access position on the chip includes:
[0026] Determining a distance between the power access position and the storage unit according to the position of the storage unit and the power access position;
[0027] Determining the number of buffer units to be arranged according to the distance between the power access position and the storage unit;
[0028] The buffer units are arranged in sequence between the power access position and the storage unit according to a preset arrangement interval.
[0029] In a second aspect, another embodiment of the present application provides a chip, the chip comprising: a static random access memory;
[0030] The chip is laid out based on the method steps described in any one of the first aspects.
[0031] As a possible implementation manner, the static random access memory is a dual-track static random access memory.
[0032] In the third aspect, another embodiment of the present application provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to perform the steps of any method described in the first aspect above.
[0033] In a fourth aspect, another embodiment of the present application provides a storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any method described in the first aspect are executed.
[0034] The beneficial effects of the present application are: by acquiring the power bump information of the chip; according to the power bump information and the preset constraint information, determining the first voltage coverage area and the second voltage coverage area of the target SRAM to be laid out on the chip; laying out the storage unit of the target SRAM in the first voltage coverage area, and laying out the peripheral unit of the target SRAM in the second voltage coverage area; and laying out the first power supply network of the storage unit according to the layout position of the storage unit, and laying out the second power supply network of the peripheral unit according to the layout position of the peripheral unit, so that two independent voltages can be used to power the first voltage coverage area and the second voltage coverage area respectively, so that there is no need to add an additional voltage conversion unit, thereby avoiding the timing delay caused by setting the voltage conversion unit, and at the same time, saving the chip area and routing resources, optimizing the voltage drop of the target SRAM to be laid out, and because the first voltage coverage area and the second voltage coverage area are powered by different independent voltages, the power supply of the first voltage coverage area and the second voltage coverage area can be adjusted according to the application scenario of the chip, thereby reducing the power consumption of the macro module in the chip and improving the reliability of the chip. In addition, since the first voltage coverage area and the second voltage coverage area are determined by the power bump information, the problem of local overheating of the chip can be avoided, thereby ensuring the thermal management performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0036] Figure 1 A schematic diagram of a structure when a single-track SRAM is used as a chip memory in the prior art;
[0037] Figure 2 A schematic diagram of a structure of a single-track SRAM in the prior art;
[0038] Figure 3 A schematic diagram of a dual-track SRAM structure in the prior art;
[0039] Figure 4 A schematic diagram of a flow chart of a chip layout method provided in an embodiment of the present application;
[0040] Figure 5 A schematic diagram of a first voltage coverage area and a second voltage coverage area in a chip layout method provided in an embodiment of the present application;
[0041] Figure 6Another schematic diagram of the first voltage coverage area and the second voltage coverage area in the chip layout method provided in an embodiment of the present application;
[0042] Figure 7 A schematic diagram of a chip in the chip layout method provided in an embodiment of the present application;
[0043] Figure 8 A schematic diagram of a process for determining a first voltage coverage area and a second voltage coverage area in a chip layout method provided in an embodiment of the present application;
[0044] Fig. 9 A schematic diagram of a process for determining a first voltage coverage area in a chip layout method provided in an embodiment of the present application;
[0045] Fig.10 Another schematic diagram of a chip layout method provided in an embodiment of the present application;
[0046] Fig.11 A schematic diagram of a process for laying out a first power supply network of a storage unit in a chip layout method provided in an embodiment of the present application;
[0047] Fig.12 A partial structural schematic diagram of a first power supply network and a second power supply network of a target SRAM in a chip layout method provided in an embodiment of the present application;
[0048] Fig.13 A schematic diagram of a process for laying out a first power supply network of a storage unit in a chip layout method provided in an embodiment of the present application;
[0049] Fig.14 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0050] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of order, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.
[0051] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0052] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.
[0053] How to reduce chip power consumption, especially how to reduce the power consumption of macro modules, is a key issue that the industry needs to solve urgently.
[0054] In the prior art, a multi-voltage domain design mode can be adopted in a chip, a single-track static random access memory (SRAM) is used as a memory in the chip, and a power network is wired, thereby realizing chip design. For example, Figure 1 A schematic diagram of a structure when a single-track SRAM is used as a chip memory in the prior art, referring to Figure 1 As shown, two power domains (referred to as Power Domain) are divided in the chip, including a main power domain Domain_0 and a storage power domain Domain_1, and the power supply voltage of the main power domain Domain_0 is higher than the power supply voltage of the storage power domain Domain_1. Figure 2 A schematic diagram of a single-track SRAM in the prior art is shown in FIG. Figure 1 as well as Figure 2 As shown, the single-rail SRAM and the power module of the single-rail SRAM are connected through a power line.
[0055] However, in this design mode, since the calculation program is stored in the single-rail SRAM, there will inevitably be a large number of signals and data interactions between different voltage domains. In order to ensure the stable transmission of signals and data, a large number of voltage conversion units need to be introduced. The area of the voltage conversion unit is generally large, and the resulting timing delay is also long, making the overall performance and power consumption of the chip unfriendly. At the same time, the single-rail SRAM cannot achieve autonomous shutdown and generally uses the rated voltage. When the single-rail SRAM is not needed to work, power consumption will be wasted, which greatly reduces the reliability of the chip.
[0056] In the prior art, dual-track SRAM can also be used as a macro module in a low-power chip. For example, Figure 3 A schematic diagram of a dual-track SRAM in the prior art is shown in FIG. Figure 3 As shown, the dual-rail SRAM includes a control circuit, a first power module, a second power module, an SRAM storage unit circuit and an SRAM peripheral circuit. The power design of this structure is relatively complex and can independently realize power control, but the impact of voltage drop needs to be fully considered, and the layout will be relatively limited.
[0057] Continue to refer to Figure 3 As shown, the dual-track SRAM in the prior art generally only performs timing-driven layout during layout, that is, only the critical path in the timing information is identified, and based on the critical path in the timing information, the layout process is driven and guided, which makes the resulting layout relatively scattered. In addition, since the dual-track SRAM includes two power modules, the scattered layout will destroy the integrity of the chip power network, and the power lines of the same metal layer with the same voltage are difficult to connect together. The overall impedance is high, and the resistance value on the local power network will also be uneven, which is easy to cause voltage drop problems. At the same time, the scattered layout is easy to cause the problem of uneven distribution of power bumps (referred to as bump points). It can be understood that in the heat-sensitive area of the chip, when the distribution of the power bump points is uneven, the resistance will increase, which is easy to cause local overheating, thereby causing the problem of chip thermal management out of control.
[0058] In addition, when the chip packaging process is flip chip (referred to as flipchip) packaging, the spacing (referred to as pitch) of the power supply end, that is, the bump point, is generally above 130 microns, while the size of the dual-track SRAM is usually in the range of tens to hundreds of microns. Under the timing-driven layout, the main power domain (referred to as domain) will not be able to obtain effective power supply support from the bump point where the dual-track SRAM is located, resulting in insufficient power supply. This will cause the power analysis simulation (Power Analysis, referred to as PA) to fail, and in severe cases, the layout and wiring need to be replanned, affecting the design progress. At the same time, insufficient power supply will also bring signal integrity problems, and when the voltage is reduced, the on-resistance in the circuit increases, resulting in a decrease in current, thereby increasing the delay of signal transmission. At the same time, insufficient power supply may also increase the uncertainty of the clock signal, further affecting the timing. In extreme cases, when the voltage fluctuates greatly, the oscillator period inside the chip may change significantly, leading to chip failure.
[0059] Moreover, when the dual-track SRAM in the prior art is only laid out for timing-driven layout, the scattered layout is not conducive to laying out the signal lines that control the voltage of the dual-track SRAM, and is even ignored in some designs, or is controlled by the normally-open buffer added automatically by the tool. Specifically, since the position of the dual-track SRAM is difficult to determine under the timing-driven layout, the length and direction of the signal line will be uncertain when the signal line is laid out. Although the software wiring tool will add a normally-open buffer according to the routing of the signal line in the actual application process, the two power pins of the normally-open buffer are connected to the first power line and the second power line, respectively, wherein the voltage of the second power line is the same as the voltage of the first power module of the dual-track SRAM. However, when the software wiring tool places a normally-open buffer far away from the position of the dual-track SRAM, the power line connected to the second power pin of the normally-open buffer will be very long, which is very likely to cause voltage drop problems, and may eventually cause signal distortion and chip failure.
[0060] In summary, there are more or less problems in the design of macro modules in the prior art, making it difficult to reduce the power consumption of the macro modules.
[0061] Based on the above problems, an embodiment of the present application proposes a chip layout method, which obtains the power bump information of the chip; determines the first voltage coverage area and the second voltage coverage area of the target SRAM to be laid out on the chip according to the power bump information and preset constraint information; arranges the storage cells of the target SRAM in the first voltage coverage area, and arranges the peripheral cells of the target SRAM in the second voltage coverage area; and arranges the first power network of the storage cells according to the layout position of the storage cells, and arranges the second power network of the peripheral cells according to the layout position of the peripheral cells, so that two independent voltages can be used to power the first voltage coverage area and the second voltage coverage area respectively, thereby eliminating the need to add an additional voltage conversion unit, thereby avoiding the timing delay caused by setting the voltage conversion unit, and at the same time, saving the chip area and routing resources, optimizing the voltage drop of the target SRAM, and at the same time, because the first voltage coverage area and the second voltage coverage area are powered by different independent voltages, the power supply of the first voltage coverage area and the second voltage coverage area can be adjusted according to the application scenario of the chip, thereby reducing the power consumption of the macro module in the chip and improving the reliability of the chip. In addition, since the first voltage coverage area and the second voltage coverage area are determined by the power bump information, the problem of local overheating of the chip can be avoided, thereby ensuring the thermal management performance of the chip.
[0062] The chip layout method provided in the embodiments of the present application is described in detail below in combination with multiple embodiments.
[0063] Figure 4A schematic diagram of a chip layout method provided in an embodiment of the present application, referring to Figure 4 As shown, the execution subject of the method can be any electronic device with processing capability, and the method includes:
[0064] S401, obtaining power bump information of the chip.
[0065] Optionally, the power bump information of all power bumps (bump points for short) of the chip can be obtained before the chip layout planning is performed to characterize the existing structure on the chip package. Specifically, the power bump information of the chip can be obtained by processing the chip packaging process document. The power bump information includes: the position of the power bump of the chip in the chip and the coverage of the power bump.
[0066] Optionally, the power bump of the chip (bump point for short) can be a raised metal structure on the chip, which is used to achieve electrical connection between the chip and an external power supply or ground, and can provide a stable power supply and grounding path for the chip to ensure the normal operation and performance stability of the chip.
[0067] Exemplarily, the power bump information of a chip obtained can be [(0, 100), LB, VDD, 100], where (0, 100) indicates that the coordinates of the power bump are (0, 100), and the unit is um, LB indicates that the metal layer where the power bump is located is the LB layer, VDD indicates that the supply voltage of the power bump is VDD, and 100 indicates that the voltage drop (IR) of the power bump can cover a circle with a diameter of 100um.
[0068] S402: Determine a first voltage coverage area and a second voltage coverage area of a target SRAM to be laid out on the chip according to the power bump information and preset constraint information.
[0069] It can be understood that after obtaining the power bump information, the electrical connection point between the chip and the external power supply or ground is determined. Therefore, the first voltage coverage area and the second voltage coverage area of the target SRAM to be laid out on the chip can be determined according to the position in the power bump information and the preset constraints. After obtaining the first voltage coverage area and the second voltage coverage area, the devices arranged in the first voltage coverage area and the second voltage coverage area can be connected to the outside through the bumps. In addition, it can also avoid arranging a voltage conversion unit in the chip, saving the chip area and routing resources. At the same time, it can also enable the same independent voltage to be used for power supply in the same voltage coverage area, and it can enable the first voltage coverage area and the second voltage coverage area to be used for power supply through different independent voltages, so that the size of the independent voltage can be flexibly adjusted according to different actual application scenarios, thereby reducing the power consumption of the chip.
[0070] Optionally, after obtaining the power bump information, the area on the chip can be planned according to the position of each power bump and the preset constraint information based on the position in the power bump information and the preset constraint information, and the first voltage coverage area and the second voltage coverage area of the target SRAM to be laid out on the chip are determined.
[0071] The constraint information is used to constrain the first voltage coverage area, including: the first voltage coverage area is located in the boundary area of the chip.
[0072] Optionally, in addition to constraining the first voltage coverage area, the constraint information may also constrain the second voltage coverage area. Specifically, the constraint information also includes: a minimum coverage range threshold of the first voltage coverage area and the second voltage coverage area is a whole area.
[0073] Exemplarily, after obtaining the power bump information of the chip, in order to better meet the winding requirements, multiple power bumps located at the chip boundary are selected from the power bump information of the chip, and the set of coverage ranges of these power bumps is used as the first voltage coverage area, and the remaining entire area on the chip is used as the second voltage coverage area.
[0074] Exemplarily, after obtaining the power bump information of the chip, in order to better meet the winding requirements, multiple power bumps that do not exceed 100um from the chip boundary are selected from the power bump information of the chip, and the set of coverage ranges of these power bumps is used as the first voltage coverage area, and the remaining entire area on the chip is used as the second voltage coverage area.
[0075] For example, Figure 5A schematic diagram of a first voltage coverage area and a second voltage coverage area in a chip layout method provided in an embodiment of the present application, referring to Figure 5 As shown, according to the different power bump information of the chip, Figure 5 The diagram shows a layout diagram of a first voltage coverage area and a second voltage coverage area that may be obtained after this step is completed.
[0076] For example, Figure 6 Another schematic diagram of the first voltage coverage area and the second voltage coverage area in the chip layout method provided in the embodiment of the present application, referring to Figure 6 As shown, according to the different power bump information of the chip, Figure 6 The figure shows a schematic layout of a first voltage coverage area and a second voltage coverage area that can be obtained after this step is completed.
[0077] Among them, the supply voltage of the first voltage coverage area and the supply voltage of the second voltage coverage area can be adjusted according to different actual application scenarios, and the supply voltage of the first voltage coverage area can be the same as or different from the supply voltage of the second voltage coverage area.
[0078] Exemplarily, in the high-speed and high-performance working mode of the chip, that is, when writing and reading at high speed, the power supply voltage of the first voltage coverage area can be the same as the power supply voltage of the second voltage coverage area, for example: the power supply voltages of the first voltage coverage area and the second voltage coverage area are both the rated voltage of the chip; in the low-power and low-speed working mode of the chip, that is, when writing and reading at low speed, the power supply voltage of the first voltage coverage area can be less than the power supply voltage of the second voltage coverage area, for example: the power supply voltage of the first voltage coverage area is less than the rated voltage, and the power supply voltage of the second voltage coverage area is the rated voltage of the chip; in the sleep mode of the chip, that is, when not writing and reading, the power supply voltage of the first voltage coverage area can be the rated voltage, and the power supply voltage of the second voltage coverage area can be zero, that is, the second voltage coverage area can be turned off. Specifically, the rated voltage can be 0.75V.
[0079] S403 , arranging the memory cells of the target SRAM in the first voltage coverage area, and arranging the peripheral cells of the target SRAM in the second voltage coverage area.
[0080] It can be understood that after determining the first voltage coverage area and the second voltage coverage area, the target SRAM to be laid out can be laid out. Specifically, the storage cells of the target SRAM can be laid out in the first voltage coverage area, and the peripheral cells of the target SRAM can be laid out in the second voltage coverage area.
[0081] Optionally, the storage cells of the target SRAM may be arranged at positions avoiding power bumps in the first voltage coverage area, and the peripheral cells of the target SRAM may be arranged at positions close to access power input points in the second voltage coverage area.
[0082] Optionally, the storage cells of the target SRAM may be arranged at a position away from the power bump in the first voltage coverage area, and the peripheral cells of the target SRAM may be arranged at a central position of the second voltage coverage area.
[0083] Among them, the storage unit of the target SRAM may include Figure 3 The SRAM storage unit circuit in the target target SRAM may include a cross-coupled inverter pair, an access transistor, and a sub-line. Figure 3 The SRAM peripheral circuit and the processor standard unit in the embodiment of the present invention may include an address decoding circuit, a read / write control circuit, a timing control circuit and an input / output circuit.
[0084] S404 , laying out a first power supply network of the storage unit according to the layout position of the storage unit, and laying out a second power supply network of the peripheral unit according to the layout position of the peripheral unit.
[0085] It can be understood that after the storage cells and peripheral units of the target SRAM are arranged, the first power supply network of the storage cells and the second power supply network of the peripheral units can be planned and wired according to the arrangement positions of the storage cells and peripheral units of the target SRAM in combination with the power access positions. Therefore, after the first power supply network and the second power supply network are arranged, the input access power can be processed through the first power supply network and the second power supply network, and the voltages of the first voltage coverage area and the second voltage coverage area can be adjusted to realize power supply to the storage cells and the peripheral units.
[0086] That is to say, since the storage unit is arranged in the first voltage coverage area, the peripheral unit is arranged in the second voltage coverage area, and the first voltage coverage area and the second voltage coverage area are different voltage coverage areas, the first power supply network of the storage unit and the second power supply network of the peripheral power supply can be independently connected to the supply voltage, that is, the first power supply network and the second power supply network are independently powered. Specifically, in different chip operating modes, the supply voltages of the first power supply network and the second power supply network are independent of each other, and the values may be the same or different.
[0087] Optionally, based on the location of the storage unit and the power access position, the distance between the storage unit and the access power source can be calculated, and signal lines and normally-open buffers can be arranged to generate a first power supply network for the storage unit. Based on the location of the peripheral unit and the power access position, the distance between the peripheral unit and the access power source can be calculated, and signals and normally-open buffers can be arranged to generate a second power supply network for the peripheral unit.
[0088] Among them, when laying out signal lines and normally-open buffers, they can be laid out according to preset laying rules, including: signal line laying spacing, signal line laying length, signal line laying type, normally-open buffer laying spacing, and normally-open buffer laying quantity, etc.
[0089] For example, Figure 7 A schematic diagram of a chip in the chip layout method provided in an embodiment of the present application, referring to Figure 7 As shown, in Figure 6 Based on this, taking the first power supply network as an example, after this step is completed, a first power supply network consisting of multiple normally open buffers and black solid connecting wires can be obtained.
[0090] In this embodiment, the power bump information of the chip is obtained; according to the power bump information and the preset constraint information, the first voltage coverage area and the second voltage coverage area of the target SRAM to be laid out on the chip are determined; the storage cells of the target SRAM are laid out in the first voltage coverage area, and the peripheral cells of the target SRAM are laid out in the second voltage coverage area; and the first power supply network of the storage cells is laid out according to the layout position of the storage cells, and the second power supply network of the peripheral cells is laid out according to the layout position of the peripheral cells, so that two independent voltages can be used to power the first voltage coverage area and the second voltage coverage area respectively, so that there is no need to add an additional voltage conversion unit, thereby avoiding the timing delay caused by setting the voltage conversion unit, and at the same time, saving the chip area and routing resources, optimizing the voltage drop of the target SRAM to be laid out, and because the first voltage coverage area and the second voltage coverage area are powered by different independent voltages, the power supply of the first voltage coverage area and the second voltage coverage area can be adjusted according to the application scenario of the chip, thereby reducing the power consumption of the macro module in the chip and improving the reliability of the chip. In addition, since the first voltage coverage area and the second voltage coverage area are determined by the power bump information, the problem of local overheating of the chip can be avoided, thereby ensuring the thermal management performance of the chip.
[0091] As a possible implementation, an exemplary description is given of a process of determining a first voltage coverage area and a second voltage coverage area of a target SRAM to be laid out on a chip according to power bump information and preset constraint information. Figure 8 A schematic diagram of a process for determining a first voltage coverage area and a second voltage coverage area in a chip layout method provided in an embodiment of the present application, referring to Figure 8 As shown, the above step S402 includes:
[0092] S801. Determine the coverage of each power bump according to the power bump information.
[0093] Optionally, after the power bump information is obtained, the coverage of each power bump can be determined according to the power bump information.
[0094] Exemplarily, when the acquired information of a power bump of a chip is [(0, 100), LB, VDD, 100], it can be read that the coverage range of the power bump is a circle with a diameter of 100 um.
[0095] S802: Determine a first voltage coverage area according to the coverage range and constraint information of each power bump.
[0096] Optionally, after obtaining the coverage of each power bump, planning can be performed according to the coverage of each power bump and preset constraint information to determine the first voltage coverage area of the target SRAM to be laid out on the chip.
[0097] For example, after the coverage of each power bump is obtained, in order to better meet the winding requirements, a chip boundary area with a width smaller than the bump coverage radius of 120 um may be selected as the first voltage coverage area.
[0098] S803: Determine a second voltage coverage area according to the first voltage coverage area.
[0099] Optionally, after the first voltage coverage area is determined, an entire area may be determined from the remaining area on the chip as the second voltage coverage area, which helps to ensure the integrity of the second power supply network of the voltage in the second voltage coverage area.
[0100] The coverage of each power bump is determined through the power bump information, and the first voltage coverage area is determined according to the coverage of each power bump and the constraint information, and the second voltage coverage area is determined according to the first voltage coverage area, so that the first voltage coverage area and the second voltage coverage area that are convenient for winding can be generated, so that two independent voltages can be used to power the first voltage coverage area and the second voltage coverage area respectively, thereby eliminating the need to add an additional voltage conversion unit, thereby avoiding the timing delay caused by setting the voltage conversion unit. At the same time, the chip area and routing resources are saved, and the voltage drop of the target SRAM to be laid out is optimized.
[0101] As a possible implementation, the process of determining the first voltage coverage area according to the coverage range and constraint information of each power bump is exemplarily described. Fig. 9 A schematic diagram of a process for determining a first voltage coverage area in a chip layout method provided in an embodiment of the present application, referring to Fig. 9 As shown, the above step S802 includes:
[0102] S901. Determine at least one target power bump that satisfies the constraint information according to the coverage of each power bump and the constraint information.
[0103] Optionally, the coverage of each power bump can be screened based on the two conditions of the minimum coverage range threshold of the first voltage coverage area in the constraint information and the first voltage coverage area being located in the boundary area of the chip to obtain at least one target power bump that meets the constraint information.
[0104] S902: Use an area formed by the coverage range of at least one target power bump as a first voltage coverage area.
[0105] Optionally, the coverage range of at least one target power bump obtained through screening is combined into a first voltage coverage area.
[0106] Through the coverage range and constraint information of each power bump, at least one target power bump that meets the constraint information is determined, and the area formed by the coverage range of at least one target power bump is used as the first voltage coverage area, which helps to modularize the design of the first voltage coverage area, thereby simplifying the design of the first power network and reducing the complexity of the power network. At the same time, it can also reduce unnecessary power loss and facilitate thermal management.
[0107] As a possible implementation, the process of arranging the storage cells of the target SRAM in the first voltage coverage area and arranging the peripheral cells of the target SRAM in the second voltage coverage area is exemplarily described. Fig.10 Another schematic diagram of a chip layout method provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, the above step S403 includes:
[0108] S1001 , arranging storage cells of a target SRAM in a first voltage coverage area, and arranging peripheral cells of the target SRAM in a second voltage coverage area.
[0109] Optionally, the storage cells of the target SRAM can be arranged in the first voltage coverage area close to the chip boundary and away from the power bump, and the peripheral cells of the target SRAM can be arranged in the second voltage coverage area close to the power input point.
[0110] Optionally, the storage cells of the target SRAM may be arranged in the first voltage coverage area at a position close to the chip boundary and away from the power bump, and the peripheral cells of the target SRAM may be arranged in the center of the second voltage coverage area.
[0111] S1002. Arrange a soft placement blocking area between the storage unit and the peripheral unit.
[0112] It can be understood that the storage unit of the target SRAM and the peripheral unit can communicate through two independent data transmission paths, which are the physical paths (referred to as Channels) connecting the storage unit of the target SRAM and the peripheral unit. During the chip layout process, the state of the physical paths connecting the storage unit of the target SRAM and the peripheral unit can be set to ensure that signals and data can be transmitted smoothly.
[0113] Optionally, a soft placement blocking area (soft placement blockage for short) can be covered on the channel, so as to avoid in advance the problem of insufficient voltage drop of some processor standard cells scattered in the channel, and to improve the flexibility of chip layout. At the same time, it can reduce the risk of congestion between storage cells and peripheral units, ensuring that signals and data can be transmitted smoothly.
[0114] As a possible implementation manner, the processing of arranging the first power supply network of the storage unit according to the arrangement position of the storage unit is exemplarily described. Fig.11 A schematic diagram of a process for laying out a first power supply network of a storage unit in a chip layout method provided in an embodiment of the present application, referring to Fig.11 As shown, the above step S404 includes:
[0115] S1101 , laying out a first power line and a second power line for a storage unit at an input / output interface position of a target SRAM.
[0116] Optionally, a power line can be laid out in the metal layer above the power supply (power) and group pins of the target SRAM, so as to reduce the influence of power noise on the target SRAM, improve the flexibility of the first power network wiring, and help optimize the layout of the first power network. The laid power line can control all SRAMs.
[0117] Optionally, Fig.12 A schematic diagram of a part of the structure of the first power supply network and the second power supply network of the target SRAM in the chip layout method provided in an embodiment of the present application, referring to Fig.12As shown, in the metal layer, at the position of the input and output interface (IO interface or IO pin for short) of the target SRAM, the first power line and the second power line can be arranged in pairs for the storage unit according to the preset interval and width. The first power line is a positive (VDD) power line, and the second power line is a negative (VSS) power line.
[0118] For example, continue to refer to Fig.12 As shown, the target SRAM is a second voltage coverage area at the IO pin, and the VDD power line and the VSS power line can be arranged in pairs according to the preset interval and width, wherein the width of the VDD power line and the VSS power line can be 0.04-4, for example: the width can be 0.4, and the interval between the VDD power line and the VSS power line can be determined by the metal layer, for example: when the width of the metal layer is less than 0.08, the interval between the VDD power line and the VSS power line is not less than 0.04, and when the width of the metal layer is greater than 0.08, the interval between the VDD power line and the VSS power line is not less than 0.1, and illustratively, it can be 0.3.
[0119] For example, continue to refer to Fig.12 As shown, the positive (VDDS) power line and the negative (VSS) power line can be arranged in pairs in the first voltage coverage area of the target SRAM, wherein the width of the VDDS power line and the VSS power line can be 0.4, and the interval between the VDD power line and the VSS power line can be 0.3.
[0120] For example, continue to refer to Fig.12 As shown, after the VDDS power line, the VDD power line and the VSS power line are laid out, two independent voltages can be used to supply power to the first voltage coverage area and the second voltage coverage area through different IO pins.
[0121] S1102 , arranging a buffer unit on a first power line according to a position of a storage unit and a power access position on a chip.
[0122] Optionally, the distance between the storage unit and the power supply connection position can be calculated according to the position of the storage unit and the power supply connection position, and a buffer unit can be arranged on the first power line, wherein the buffer unit can be a normally open buffer.
[0123] By arranging a first power line and a second power line for a storage unit at the input and output interface position of a target SRAM, and arranging a buffer unit on the first power line according to the position of the storage unit and the power access position on the chip, it is possible to reduce voltage fluctuations caused by current mutations or external power fluctuations, optimize power distribution, reduce unnecessary power loss, and improve power utilization efficiency.
[0124] As a possible implementation, the process of arranging the buffer unit on the first power line according to the position of the storage unit and the power access position on the chip is exemplarily described. Fig.13 A schematic diagram of a process for laying out a first power supply network of a storage unit in a chip layout method provided in an embodiment of the present application, referring to Fig.13 As shown, the above step S1102 includes:
[0125] S1301. Determine the distance between the power access position and the storage unit according to the position of the storage unit and the power access position.
[0126] It can be understood that when arranging each buffer unit, each buffer unit should be placed according to a certain routing distance to reduce the attenuation and distortion of the signal during the transmission process, while being able to reduce the voltage drop and improve the reliability of the chip.
[0127] Optionally, the shortest distance between the power access location and the storage unit can be calculated based on the location of the storage unit and the power access location (PDW), wherein the shortest distance is the shortest distance between the location of the storage unit and the power access location, which can be calculated by a point-to-point distance algorithm.
[0128] S1302: Determine the number of buffer units to be deployed according to the distance between the power supply access position and the storage unit.
[0129] Optionally, the number of buffer units to be arranged may be determined based on the shortest distance between the power supply access position and the storage unit and in combination with the buffer unit arrangement principle, wherein the arrangement principle may be the routing distance between the buffers.
[0130] S1303 , arranging the buffer units in sequence between the power supply access position and the storage unit according to a preset arrangement interval.
[0131] Optionally, after determining the distance between the power access position and the storage unit and the number of buffer units to be arranged, the buffer units can be arranged horizontally and vertically in sequence between the power access position and the storage unit according to a preset arrangement interval.
[0132] Exemplarily, the layout interval may be 100um. The input port of the first buffer unit is connected to the power access position, the output port of the last buffer unit is connected to the position of the storage unit, and after the layout is completed, the mobile properties of each buffer unit are set to be immovable.
[0133] Exemplarily, the first power line routing uses a high-level low-resistance metal wire to connect through a level-by-level buffer unit. Specifically, the metal layer of the high-level low-resistance metal wire is generally the highest winding metal layer of the power line. In one embodiment, the processing process of this step can be implemented through wiring software, and the highest winding metal layer of the first power line is set to vertical (M12), and the first power line routing metal layer is set to horizontal (M11), vertical (M12) and non-default winding rule (nonedefault rule, referred to as NDR). Specifically, it is set to increase the line width by one times the spacing, that is, 2 times the width and 2 times the spacing (referred to as 2w2s), so that the routing distance of the first power line can be the shortest, the anti-interference ability is strong, and the delay is low, ensuring that the power circuit of the chip is stable and controllable.
[0134] Exemplarily, after each buffer unit is arranged, it is also necessary to connect to the positive (VDDS) power line arranged in the first voltage coverage area of the target SRAM. Specifically, one or more high-level VDDS power lines are drawn from the first voltage coverage area of the target SRAM, and are routed along the placement positions of each buffer unit, and the winding properties of the VDDS power lines of each buffer unit are set from the default power line winding to the power line winding, and NDR winding is adopted, specifically, it is set to increase the line width by one times the spacing, that is, 2 times the width and 2 times the spacing (abbreviated as 2w2s), so as to avoid the problem of insufficient voltage drop of the VDDS power lines of each buffer unit in advance.
[0135] Based on the same inventive concept, a chip is also provided in an embodiment of the present application, and the chip at least includes: SRAM, and the chip is laid out based on the above-mentioned chip layout method.
[0136] As a possible implementation manner, the SRAM may be a dual-track SRAM.
[0137] The present application embodiment also provides an electronic device 1400, such as Fig.14 As shown, Fig.14 A structural diagram of an electronic device provided in an embodiment of the present application includes: a processor 1401, a memory 1402, and optionally, a bus 1403. The memory 1402 stores machine-readable instructions executable by the processor 1401. When the electronic device 1400 is running, the processor 1401 communicates with the memory 1402 through the bus 1403. When the machine-readable instructions are executed by the processor 1401, the steps of the above-mentioned chip layout method are performed.
[0138] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned chip layout method are executed.
[0139] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0140] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or part of the technical solution that contributes to the prior art or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program code.
[0141] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.
Claims
1. A chip layout method, characterized in that: include: Acquire power bump information of a chip, wherein the power bump information includes: a position of the power bump of the chip in the chip; Determine a first voltage coverage area and a second voltage coverage area of a target static random access memory to be laid out on the chip according to the power bump information and preset constraint information, wherein the constraint information includes: the first voltage coverage area is located in a boundary area of the chip; Arranging the storage unit of the target static random access memory in the first voltage coverage area, and arranging the peripheral unit of the target static random access memory in the second voltage coverage area; A first power supply network of the storage unit is arranged according to the arrangement position of the storage unit, and a second power supply network of the peripheral unit is arranged according to the arrangement position of the peripheral unit, and the first power supply network and the second power supply network are independently powered.
2. The chip layout method according to claim 1, characterized in that: The method of determining a first voltage coverage area and a second voltage coverage area of a target static random access memory to be laid out on the chip according to the power bump information and preset constraint information includes: Determining the coverage of each of the power bumps according to the power bump information; Determining the first voltage coverage area according to the coverage range of each of the power bumps and the constraint information; The second voltage coverage area is determined according to the first voltage coverage area.
3. The chip layout method according to claim 2, characterized in that: The determining the first voltage coverage area according to the coverage range of each of the power bumps and the constraint information includes: Determine at least one target power bump that satisfies the constraint information according to the coverage of each of the power bumps and the constraint information; An area formed by the coverage range of the at least one target power bump is used as the first voltage coverage area.
4. The chip layout method according to claim 1, characterized in that: The step of arranging the storage unit of the target static random access memory in the first voltage coverage area and arranging the peripheral unit of the target static random access memory in the second voltage coverage area comprises: Arranging the storage unit of the target static random access memory in the first voltage coverage area, and arranging the peripheral unit of the target static random access memory in the second voltage coverage area; A soft placement blocking area is arranged between the storage unit and the peripheral unit.
5. The chip layout method according to claim 1, characterized in that: The step of arranging the first power supply network of the storage unit according to the arrangement position of the storage unit comprises: Arranging a first power line and a second power line for the storage unit at the input and output interface position of the target static random access memory; The buffer unit on the first power line is arranged according to the position of the storage unit and the power access position on the chip.
6. The chip layout method according to claim 5, characterized in that: The step of arranging a buffer unit on the first power line according to the position of the storage unit and the power access position on the chip includes: Determining a distance between the power access position and the storage unit according to the position of the storage unit and the power access position; Determining the number of buffer units to be arranged according to the distance between the power access position and the storage unit; The buffer units are arranged in sequence between the power access position and the storage unit according to a preset arrangement interval.
7. A chip, characterized in that: The chip at least includes: a static random access memory; The chip is laid out based on the method steps described in any one of claims 1-6.
8. The chip according to claim 7, characterized in that: The static random access memory is a dual-track static random access memory.
9. An electronic device, characterized in that: include: A processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor executes the machine-readable instructions to perform the steps of the chip layout method according to any one of claims 1 to 6.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip layout method according to any one of claims 1 to 6 are executed.