Logic synthesis method, device and equipment, readable storage medium and program product

Abstract

The invention relates to a logic synthesis method, device and equipment, a readable storage medium and a program product. The method comprises the following steps: firstly, performing module division on a target chip to obtain a plurality of sub-modules, then, obtaining a logic synthesis file for performing logic synthesis on the target chip, determining a target logic synthesis file corresponding to each sub-module according to the logic synthesis file, and finally, creating a sub-thread for each sub-module, and performing logic comprehensive processing on each sub-module through the sub-threads and the target logic comprehensive file corresponding to each sub-module, wherein each sub-thread is executed in parallel. By adopting the method, the logic synthesis time of the target chip can be shortened, and the logic synthesis efficiency of the target chip is improved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a logic synthesis method, device, equipment, readable storage medium and program product. Background Art

[0002] Chip logic synthesis is the process of converting the logic structure described by the hardware description language at the register transfer level into gate-level circuits. It is an important technical field in chip design and plays an important role in the design of large-scale chips.

[0003] At present, in the process of logic synthesis, EDA (Electronic Design Automation) tools are generally used to optimize chip circuits according to certain constraints. However, the current logic synthesis process takes a long time and has low efficiency due to the large amount of calculation when the chip scale is large. Summary of the invention

[0004] Based on this, it is necessary to provide a logic synthesis method, device, equipment, readable storage medium and program product that can improve the logic synthesis efficiency of the chip in response to the above technical problems.

[0005] In a first aspect, the present application provides a logic synthesis method, comprising:

[0006] Divide the target chip into modules and determine multiple sub-modules;

[0007] Obtaining a logic synthesis file for logic synthesis of a target chip;

[0008] Determine the target logic synthesis file corresponding to each submodule according to the logic synthesis file;

[0009] A sub-thread is created for each sub-module, and logic synthesis processing is performed on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and each sub-thread is executed in parallel.

[0010] In one embodiment, the target chip is divided into modules to determine a plurality of sub-modules, including:

[0011] According to the function of the target chip, the target chip is divided into a plurality of first modules, each first module corresponding to a function of the target chip;

[0012] If the size of the first module exceeds a preset threshold, the first module is divided according to the number of pins of the target chip to obtain a plurality of second modules;

[0013] The first module and each second module whose size does not exceed the preset threshold are determined as submodules.

[0014] In one embodiment, determining the target logic synthesis file corresponding to each sub-module according to the logic synthesis file includes:

[0015] Determine the target devices included in each submodule;

[0016] Determine the target logic synthesis file corresponding to each sub-module according to the target device and the logic synthesis file.

[0017] In one embodiment, determining the target logic synthesis file corresponding to each sub-module according to the target device and the logic synthesis file includes:

[0018] Create a corresponding target folder for each submodule according to the module identifier of each submodule;

[0019] According to the logic synthesis file corresponding to the target device in the logic synthesis file, a target logic synthesis file corresponding to each sub-module is generated in the target folder.

[0020] In one embodiment, the logic synthesis file includes at least one of a register transfer level RTL file, a design constraint file, an environment configuration file, and an engineering library file.

[0021] In one embodiment, the method further comprises:

[0022] If the logic synthesis of all sub-threads is successful, it is determined that the logic synthesis of the target chip is successful, and the logic synthesis result of the target chip is output;

[0023] If there is a sub-thread logic synthesis failure, the module identifier of the sub-module corresponding to the sub-thread that failed the logic synthesis is recorded, and the corresponding failure prompt information is output.

[0024] In a second aspect, the present application further provides a logic synthesis device, the device comprising:

[0025] A partitioning module is used to partition the target chip into modules and determine multiple sub-modules;

[0026] An acquisition module, used to acquire a logic synthesis file used for logic synthesis of a target chip;

[0027] A determination module, used to determine a target logic synthesis file corresponding to each submodule according to the logic synthesis file;

[0028] A creation module is used to create a sub-thread for each sub-module, perform logic synthesis processing on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and each sub-thread is executed in parallel.

[0029] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements any logic synthesis method described in the first aspect when executing the computer program.

[0030] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the logic synthesis method described in any one of the first aspects above.

[0031] In a fifth aspect, the present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the logic synthesis method described in any one of the first aspects above.

[0032] The above-mentioned logic synthesis method, device, equipment, readable storage medium and program product first divide the target chip into modules to obtain multiple sub-modules, then obtain the logic synthesis file used for logic synthesis of the target chip, determine the target logic synthesis file corresponding to each sub-module according to the logic synthesis file, and finally create a sub-thread for each sub-module, perform logic synthesis processing on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and each sub-thread executes in parallel. In this way, when the scale of the target chip is large, by dividing the target chip into multiple sub-modules, creating a sub-thread for each sub-module to perform logic synthesis, and each sub-thread executes in parallel, multi-threaded logic synthesis is realized, the time for logic synthesis of the target chip is reduced, and the efficiency of logic synthesis of the target chip is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] FIG1 is a flow chart of a logic synthesis method in one embodiment;

[0035] FIG2 is a schematic diagram of module division of a logic synthesis method in one embodiment;

[0036] FIG3 is a flow chart of a logic synthesis method in another embodiment;

[0037] FIG4 is a flow chart of a logic synthesis method in another embodiment;

[0038] FIG5 is a flow chart of a logic synthesis method in another embodiment;

[0039] FIG6 is a flow chart of a logic synthesis method in another embodiment;

[0040] FIG7 is a flow chart of a logic synthesis method in another embodiment;

[0041] FIG8 is a schematic diagram of software modules of a logic synthesis method in another embodiment;

[0042] FIG9 is a block diagram of a logic synthesis device in one embodiment;

[0043] FIG. 10 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] Generally, logic synthesis of large-scale GPU (Graphics Processing Unit) chips takes a lot of time because it involves a large number of calculations and optimization steps. At the same time, the goals of chip logic synthesis usually involve multiple aspects, such as performance, power consumption, and area. There may be trade-offs between multiple goals, and multi-objective optimization is required. Multi-objective optimization will further increase the complexity of calculations, thereby extending the time of chip logic synthesis.

[0046] In view of this, when the target chip is large in scale, the present application divides the target chip into multiple sub-modules, creates a sub-thread for each sub-module to perform logic synthesis, and each sub-thread executes in parallel, thereby realizing multi-threaded logic synthesis, reducing the time for logic synthesis of the target chip and improving the efficiency of logic synthesis of the target chip.

[0047] In an exemplary embodiment, as shown in FIG1 , a logic synthesis method is provided, and the method is described by taking the method applied to a terminal as an example. It can be understood that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server, and includes the following steps:

[0048] Step 101, divide the target chip into modules and determine a plurality of sub-modules.

[0049] In order to reduce the time of logic synthesis of the target chip, the target chip can be divided into modules according to functions to obtain multiple sub-modules, each of which can correspond to different functions and each of which includes multiple devices. Optionally, as shown in FIG2 , the target chip can be divided into 200 sub-modules, including sub-module 1 to sub-module 200.

[0050] Step 102, obtaining a logic synthesis file for performing logic synthesis on a target chip.

[0051] Among them, the logic synthesis file of the target chip may include register transfer level RTL files, design constraint files, environment configuration files, and engineering library files. The design constraint file is the constraint condition for the logic synthesis of the target chip. Optionally, the constraint condition may include timing, area, and power consumption constraints. Timing is the most complex and critical constraint in the logic synthesis process, which determines the performance of the entire chip. During the logic synthesis process, the EDA tool will optimize the circuit according to the constraint conditions. The environment configuration file and engineering library file may include the environment files needed in the logic synthesis process, such as temperature and voltage configuration files.

[0052] Step 103: determining the target logic synthesis file corresponding to each submodule according to the logic synthesis file.

[0053] Among them, the target logic synthesis file is the logic synthesis file needed to be used when each sub-module performs logic synthesis. Optionally, according to the devices contained in each sub-module, the files related to the devices of each sub-module can be determined from the logic synthesis file of the target chip to obtain the target logic synthesis file corresponding to each sub-module.

[0054] Step 104, creating a sub-thread for each sub-module, performing logic synthesis processing on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and each sub-thread is executed in parallel.

[0055] Optionally, a sub-thread is created for each sub-module, and each sub-thread is executed independently in parallel. The logic synthesis of each sub-module does not need to wait for the logic synthesis of other sub-modules. In this way, the logic synthesis time of the target chip is the time of the logic synthesis of the sub-module that takes the longest time, which is less than the logic synthesis time of each sub-module executed in series, thereby improving the efficiency of logic synthesis. Optionally, the process of logic synthesis of multiple sub-modules can be shown in FIG3. In each sub-thread, logic synthesis is processed for each sub-module according to the target logic synthesis file corresponding to each sub-module. The target logic synthesis file can include multiple folders, such as a configuration folder, a Flow folder for storing intermediate files of logic synthesis operation, a log folder for storing the logic synthesis operation status, and a report folder for storing the operation results.

[0056] In the above embodiment, first, the target chip is divided into modules to obtain multiple sub-modules, then the logic synthesis file used for logic synthesis of the target chip is obtained, and the target logic synthesis file corresponding to each sub-module is determined according to the logic synthesis file. Finally, a sub-thread is created for each sub-module, and each sub-module is subjected to logic synthesis processing through the sub-thread and the target logic synthesis file corresponding to each sub-module, and each sub-thread is executed in parallel. In this way, when the scale of the target chip is large, by dividing the target chip into multiple sub-modules, creating a sub-thread for each sub-module to perform logic synthesis, and each sub-thread is executed in parallel, multi-threaded logic synthesis is realized, the time for the target chip to perform logic synthesis is reduced, and the efficiency of the target chip logic synthesis is improved.

[0057] In the embodiment of the present application, the above step 101 divides the target chip into modules, and the step of determining multiple sub-modules is shown in FIG. 4, including:

[0058] Step 401: Divide the target chip into a plurality of first modules according to the functions of the target chip.

[0059] Each first module may correspond to a function of the target chip respectively. For example, the target chip may be divided into a plurality of first modules according to the storage function, communication function or computing function of the target chip.

[0060] Step 402: if the size of the first module exceeds a preset threshold, the first module is divided according to the number of pins of the target chip to obtain a plurality of second modules.

[0061] The size of the first module is the size of the devices included in the first module. After the target chip is divided into multiple first modules according to the functions, the size of the first module devices corresponding to some complex functions is larger, and the size of the first module devices corresponding to some simple functions is smaller. When the sizes of multiple first modules differ greatly, the time for logic synthesis of different first modules may differ greatly during logic synthesis, because the logic synthesis time of the target chip is the logic synthesis time of the first module with the largest size. Therefore, in order to reduce the logic synthesis time of the target chip, the first module can be further divided to obtain multiple sub-modules of substantially the same size.

[0062] Optionally, the size of the first module is judged. If the size of the first module exceeds a preset threshold, the first module is further divided according to the number of pins of the target chip to obtain multiple second modules. The preset threshold can be determined according to the number of pins of the target chip. For example, when the number of pins of the target chip is 1 million, if the target chip is to be divided into 200 sub-modules, the average number of pins of each sub-module can be 5000. The preset threshold can be set to a positive integer greater than 2 times of 5000. When the first module is greater than the preset threshold, that is, the first module can be split into at least 2 sub-modules of average size, so the first module can be further split according to the average number of pins of the sub-modules to determine multiple second modules, so that the difference in the size of each second module is less than the preset difference, that is, the scale of the devices contained in each second module is basically the same.

[0063] Step 403: determine the first module and each second module whose size does not exceed the preset threshold as submodules.

[0064] The first module whose size does not exceed the preset threshold after the first division of the target chip, and the multiple second modules obtained after the second division of the first module whose size exceeds the preset threshold, are used as the sub-modules finally obtained by dividing the target chip. Then, the logic synthesis result of the target chip can be obtained by performing logic synthesis on each sub-module respectively.

[0065] In the above embodiment, the target chip is divided into modules and the sizes of the multiple sub-modules obtained by the division are controlled to be basically the same during the division process, so that the time required for the logic synthesis of each sub-module is almost the same, which can reduce the time required for the logic synthesis of the target chip.

[0066] In one embodiment, the above step 103 determines the target logic synthesis file corresponding to each submodule according to the logic synthesis file, as shown in FIG5 , and includes:

[0067] Step 501, determining the target devices included in each sub-module.

[0068] Step 502: Determine the target logic synthesis file corresponding to each sub-module according to the target device and the logic synthesis file.

[0069] Optionally, the logic synthesis file of the target chip includes all device-related files of the target chip. The steps of step 502 are shown in FIG. 6 and may include:

[0070] Step 601: Create a corresponding target folder for each submodule according to the module identifier of each submodule.

[0071] Optionally, under a preset path, a corresponding target folder is created for each submodule using the module identifier of each submodule as the folder name, and the target logic synthesis file corresponding to each submodule can be placed in the target folder corresponding to each submodule.

[0072] Step 602 , generating a target logic synthesis file corresponding to each sub-module in a target folder according to the logic synthesis file corresponding to the target device in the logic synthesis file.

[0073] Among them, a target logic synthesis file corresponding to each sub-module is generated in the target folder. Optionally, the logic synthesis file corresponding to the target device in the logic synthesis file can be copied to the target folder, or a configuration file can be generated according to the path of the logic synthesis file corresponding to the target device in the logic synthesis file, and the configuration file is saved as the target logic synthesis file in the target folder. In this way, during the logic synthesis process of the sub-module, the corresponding logic synthesis file can be directly found through the path in the configuration file, saving copying time and memory usage.

[0074] In one embodiment, the script program may create a sub-thread for each sub-module, and then execute multi-threaded concurrent execution of logic synthesis of each sub-module. The logic synthesis process includes the following two situations.

[0075] In the first case, if the logic synthesis of all sub-threads is successful, it is determined that the logic synthesis of the target chip is successful, and the logic synthesis result of the target chip is output.

[0076] After confirming that the logic synthesis of the target chip is successful, the logic synthesis results can be recorded, including area data, timing-related data, etc., or the logic synthesis results can be analyzed through a script program.

[0077] In the second case, if there is a sub-thread logic synthesis failure, the module identifier of the sub-module corresponding to the sub-thread that fails in logic synthesis is recorded, and the corresponding failure prompt information is output.

[0078] Optionally, in order to facilitate the user to locate and modify the sub-module that failed the logic synthesis, the module identifier of the sub-module that failed the logic synthesis, as well as the failure information, process files and logs during the logic synthesis process, are recorded as failure prompt information, and the corresponding failure prompt information is output. The user can locate and modify the sub-module that failed the logic synthesis according to the failure prompt information, and after the modification is successful, the logic synthesis of the sub-module is performed separately, without repeating the logic synthesis of other sub-modules of the target chip. Therefore, in the process of multiple optimizations and analysis, it can be quickly iterated to reduce the loss of design cycle and time.

[0079] In the above embodiment, the logic synthesis result of each sub-module is executed concurrently by multiple threads. If the logic synthesis of an individual sub-module fails, the corresponding sub-module can be fault located and modified through the output failure prompt information without affecting the logic synthesis process of other sub-modules.

[0080] In an embodiment of the present application, please refer to FIG. 7 , which shows a flow chart of a logic synthesis method provided in an embodiment of the present application. The logic synthesis method includes the following steps:

[0081] Step 701, divide the target chip into modules and determine a plurality of sub-modules.

[0082] Step 702: Obtain a logic synthesis file for performing logic synthesis on the target chip.

[0083] Step 703: determine the target devices included in each sub-module.

[0084] Step 704: Create a corresponding target folder for each sub-module according to the module identifier of each sub-module.

[0085] Step 705 , generating a target logic synthesis file corresponding to each sub-module in a target folder according to the logic synthesis file corresponding to the target device in the logic synthesis file.

[0086] Step 706, creating a sub-thread for each sub-module, performing logic synthesis processing on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and each sub-thread is executed in parallel.

[0087] Step 707: If the logic synthesis of all sub-threads is successful, it is determined that the logic synthesis of the target chip is successful, and the logic synthesis result of the target chip is output.

[0088] Step 708: If there is a sub-thread that fails in logic synthesis, the module identifier of the sub-module corresponding to the sub-thread that fails in logic synthesis is recorded, and the corresponding failure prompt information is output.

[0089] In one embodiment, the above logic synthesis method can be implemented by Python, and implemented by the built-in module multiprocessing in Python for supporting multi-process programming. Multiprocessing allows tasks to be executed in parallel in multiple processes, thereby making full use of multi-core processors and improving program performance. Optionally, taking a large GPU chip as an example, the process of each submodule determining the corresponding target logic synthesis file and creating a logic synthesis environment at the same time can be shown in Figure 8. The logic synthesis method in Figure 8 can include 3 software modules, such as a constraint collection module, a submodule file generation module, and a logic synthesis file generation module.

[0090] S801, the constraint condition collection module is used to collect the file list files and constraint files of each submodule, and create a total comprehensive folder directory.

[0091] S802, then, the submodule file generation module is used to collect the module identification of each submodule and the path of the target logic synthesis file, and create a logic synthesis folder of each submodule under the total synthesis folder directory according to the module identification of each submodule.

[0092] S803, the logic synthesis file generation module is used to generate the target logic synthesis file corresponding to each sub-module according to the logic synthesis file. Optionally, the synthesis folder corresponding to each sub-module may include a configuration folder, a flow folder, a log folder and a report folder for storing different files. The configuration file may include the path of the logic synthesis file, including the path pointing to the tool file of the logic synthesis, the path pointing to the file list file, the path pointing to the code file, the library file for logic synthesis, and the temperature voltage and other settings.

[0093] S804, searching for the module identifier of each submodule, and copying the path of the code file of each submodule to the folder corresponding to the submodule.

[0094] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0095] Based on the same inventive concept, the embodiment of the present application also provides a logic synthesis device for implementing the logic synthesis method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more logic synthesis device embodiments provided below can refer to the limitations on the logic synthesis method above, and will not be repeated here.

[0096] In an exemplary embodiment, as shown in FIG9 , a logic synthesis device is provided, including: a partitioning module, an acquisition module, a determination module and a creation module, wherein:

[0097] A partitioning module is used to partition the target chip into modules and determine multiple sub-modules;

[0098] An acquisition module, used to acquire a logic synthesis file used for logic synthesis of a target chip;

[0099] A determination module, used to determine a target logic synthesis file corresponding to each submodule according to the logic synthesis file;

[0100] A creation module is used to create a sub-thread for each sub-module, perform logic synthesis processing on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and each sub-thread is executed in parallel.

[0101] In one of the embodiments, the division module is specifically used to divide the target chip into multiple first modules according to the function of the target chip, and each first module corresponds to a function of the target chip; if the size of the first module exceeds a preset threshold, the first module is divided according to the number of pins of the target chip to obtain multiple second modules; the first module whose size does not exceed the preset threshold and each second module are determined as sub-modules.

[0102] In one embodiment, the determination module is specifically used to determine the target device included in each sub-module; and determine the target logic synthesis file corresponding to each sub-module according to the target device and the logic synthesis file.

[0103] In one of the embodiments, the determination module is specifically used to establish a corresponding target folder for each sub-module according to the module identifier of each sub-module; and generate a target logic synthesis file corresponding to each sub-module in the target folder according to the logic synthesis file corresponding to the target device in the logic synthesis file.

[0104] In one embodiment, the logic synthesis file includes at least one of a register transfer level RTL file, a design constraint file, an environment configuration file, and an engineering library file.

[0105] In one of the embodiments, an output module is also included, which is used to determine that the logic synthesis of the target chip is successful if all sub-threads are successfully synthesized, and output the logic synthesis result of the target chip; if there is a sub-thread logic synthesis failure, record the module identifier of the sub-module corresponding to the sub-thread that failed the logic synthesis, and output the corresponding failure prompt information.

[0106] Each module in the above logic synthesis device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0107] In an exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be shown in FIG10. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected via a system bus, and the communication interface, the display unit, and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner may be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a logic synthesis method is implemented. The display unit of the computer device is used to form a visually visible picture, which may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0108] Those skilled in the art will understand that the structure shown in FIG. 10 is merely a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0109] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the following steps when executing the computer program: dividing a target chip into modules to determine a plurality of sub-modules; obtaining a logic synthesis file for logic synthesis of the target chip; determining a target logic synthesis file corresponding to each sub-module according to the logic synthesis file; creating a sub-thread for each sub-module, performing logic synthesis processing on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and executing each sub-thread in parallel.

[0110] In one embodiment, when the processor executes the computer program, the following steps are also implemented: according to the function of the target chip, the target chip is divided into multiple first modules, and each first module corresponds to a function of the target chip; if the size of the first module exceeds a preset threshold, the first module is divided according to the number of pins of the target chip to obtain multiple second modules; the first module and each second module whose size does not exceed the preset threshold are determined as sub-modules.

[0111] In one embodiment, when the processor executes the computer program, the following steps are also implemented: determining the target device included in each sub-module; and determining the target logic synthesis file corresponding to each sub-module according to the target device and the logic synthesis file.

[0112] In one embodiment, when the processor executes the computer program, the following steps are also implemented: a corresponding target folder is established for each sub-module according to the module identifier of each sub-module; and a target logic synthesis file corresponding to each sub-module is generated in the target folder according to the logic synthesis file corresponding to the target device in the logic synthesis file.

[0113] In one embodiment, the logic synthesis file includes at least one of a register transfer level RTL file, a design constraint file, an environment configuration file, and an engineering library file.

[0114] In one embodiment, the processor also implements the following steps when executing the computer program: if the logic synthesis of all sub-threads is successful, it is determined that the logic synthesis of the target chip is successful, and the logic synthesis result of the target chip is output; if there is a sub-thread logic synthesis failure, the module identifier of the sub-module corresponding to the sub-thread that failed the logic synthesis is recorded, and the corresponding failure prompt information is output.

[0115] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: dividing a target chip into modules to determine a plurality of sub-modules; obtaining a logic synthesis file for logic synthesis of the target chip; determining a target logic synthesis file corresponding to each sub-module based on the logic synthesis file; creating a sub-thread for each sub-module, performing logic synthesis processing on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and executing each sub-thread in parallel.

[0116] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to the function of the target chip, the target chip is divided into multiple first modules, each first module corresponds to a function of the target chip; if the size of the first module exceeds a preset threshold, the first module is divided according to the number of pins of the target chip to obtain multiple second modules; the first module and each second module whose size does not exceed the preset threshold are determined as sub-modules.

[0117] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: determining the target device included in each sub-module; and determining the target logic synthesis file corresponding to each sub-module according to the target device and the logic synthesis file.

[0118] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: a corresponding target folder is established for each sub-module according to the module identifier of each sub-module; and a target logic synthesis file corresponding to each sub-module is generated in the target folder according to the logic synthesis file corresponding to the target device in the logic synthesis file.

[0119] In one embodiment, the logic synthesis file includes at least one of a register transfer level RTL file, a design constraint file, an environment configuration file, and an engineering library file.

[0120] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: if the logic synthesis of all sub-threads is successful, it is determined that the logic synthesis of the target chip is successful, and the logic synthesis result of the target chip is output; if there is a sub-thread logic synthesis failure, the module identifier of the sub-module corresponding to the sub-thread that failed the logic synthesis is recorded, and the corresponding failure prompt information is output.

[0121] In one embodiment, a computer program product is provided, including a computer program, which implements the following steps when executed by a processor: dividing a target chip into modules to determine a plurality of sub-modules; obtaining a logic synthesis file for logic synthesis of the target chip; determining a target logic synthesis file corresponding to each sub-module based on the logic synthesis file; creating a sub-thread for each sub-module, performing logic synthesis processing on each sub-module through the sub-thread and the target logic synthesis file corresponding to each sub-module, and executing each sub-thread in parallel.

[0122] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to the function of the target chip, the target chip is divided into multiple first modules, each first module corresponds to a function of the target chip; if the size of the first module exceeds a preset threshold, the first module is divided according to the number of pins of the target chip to obtain multiple second modules; the first module and each second module whose size does not exceed the preset threshold are determined as sub-modules.

[0123] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: determining the target device included in each sub-module; and determining the target logic synthesis file corresponding to each sub-module according to the target device and the logic synthesis file.

[0124] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: a corresponding target folder is established for each sub-module according to the module identifier of each sub-module; and a target logic synthesis file corresponding to each sub-module is generated in the target folder according to the logic synthesis file corresponding to the target device in the logic synthesis file.

[0125] In one embodiment, the logic synthesis file includes at least one of a register transfer level RTL file, a design constraint file, an environment configuration file, and an engineering library file.

[0126] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: if the logic synthesis of all sub-threads is successful, it is determined that the logic synthesis of the target chip is successful, and the logic synthesis result of the target chip is output; if there is a sub-thread logic synthesis failure, the module identifier of the sub-module corresponding to the sub-thread that failed the logic synthesis is recorded, and the corresponding failure prompt information is output.

[0127] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0128] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0129] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0130] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A logic synthesis method, characterized in that: The method comprises: Divide the target chip into modules and determine multiple sub-modules; Obtaining a logic synthesis file for performing logic synthesis on the target chip; Determine the target logic synthesis file corresponding to each of the sub-modules according to the logic synthesis file; A sub-thread is created for each of the sub-modules, and logic synthesis processing is performed on each of the sub-modules through the sub-thread and the target logic synthesis file corresponding to each of the sub-modules, and each of the sub-threads is executed in parallel.

2. The method according to claim 1, characterized in that The target chip is divided into modules to determine a plurality of sub-modules, including: According to the function of the target chip, the target chip is divided into a plurality of first modules, each of the first modules corresponds to a function of the target chip; If the size of the first module exceeds a preset threshold, dividing the first module according to the number of pins of the target chip to obtain a plurality of second modules; The first module and each of the second modules whose size does not exceed the preset threshold are determined as the submodules.

3. The method according to claim 1, characterized in that The step of determining the target logic synthesis file corresponding to each of the sub-modules according to the logic synthesis file comprises: Determining the target device included in each of the sub-modules; The target logic synthesis file corresponding to each of the sub-modules is determined according to the target device and the logic synthesis file.

4. The method according to claim 3, characterized in that Determining a target logic synthesis file corresponding to each of the sub-modules according to the target device and the logic synthesis file includes: Establishing a corresponding target folder for each submodule according to the module identifier of each submodule; According to the logic synthesis file corresponding to the target device in the logic synthesis file, a target logic synthesis file corresponding to each of the sub-modules is generated in the target folder.

5. The method according to claim 1, characterized in that: The logic synthesis file includes at least one of a register transfer level RTL file, a design constraint file, an environment configuration file, and an engineering library file.

6. The method according to claim 1, characterized in that The method further comprises: If the logic synthesis of all the sub-threads is successful, it is determined that the logic synthesis of the target chip is successful, and the logic synthesis result of the target chip is output; If any of the sub-threads fails in logic synthesis, the module identifier of the sub-module corresponding to the sub-thread that fails in logic synthesis is recorded, and corresponding failure prompt information is output.

7. A logic synthesis device, characterized in that: The device comprises: A partitioning module is used to partition the target chip into modules and determine multiple sub-modules; An acquisition module, used for acquiring a logic synthesis file used for logic synthesis of the target chip; A determination module, used for determining a target logic synthesis file corresponding to each of the sub-modules according to the logic synthesis file; A creation module is used to create a sub-thread for each of the sub-modules, perform logic synthesis processing on each of the sub-modules through the sub-thread and the target logic synthesis file corresponding to each of the sub-modules, and each of the sub-threads is executed in parallel.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

Images