Storage and calculation method based on flash memory and artificial intelligence integrated memory

Abstract

The invention relates to a storage and calculation method based on a flash memory and an artificial intelligence integrated memory. A memory in the form of flash memory is provided and includes a memory transistor array. A storage transistor array is used as a carrier of a weight matrix of a neural network, input data of the neural network is set to be transmitted to a series of bit lines of the storage transistor array, output data of the neural network is set to be captured from a series of source lines of the storage transistor array, and storage calculation based on a flash memory is achieved. Each weight in a weight matrix of the neural network is represented by a difference between threshold voltages of a pair of corresponding complementary transistors which are located in the same column but are respectively arranged in two rows in the storage transistor array; the gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled on the same bit line.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of data storage, and more specifically, to a flash memory-based storage and calculation method and an artificial intelligence integrated memory in the field of data storage. Background Art

[0002] In previous electronic devices, computing and storage were separated. The computing part, such as the processor, and the storage part, such as the hard disk or memory, each focused on their own tasks, and computing and storage basically did not interfere with each other. Storage and computing integrate storage and computing, but there are also doubts: artificial intelligence based on neural networks involves a large number of matrix operations and requires the use of larger operators such as operation matrices and weight matrices to match large computing power and faster computing speeds. However, the memory is limited by the semiconductor manufacturing process and cannot be flexibly expanded to adapt operators without limits. For example, the larger the weight matrix, the more columns or rows of the many transistor arrays involved in the weight matrix must be synchronized. The larger the array, the larger the network parasitic parameters will be, and the participation of parasitic parameters in matrix operations will lead to the deviation of the calculation results of the neural network. Summary of the invention

[0003] The present application relates to a storage and calculation method based on flash memory, which is characterized by comprising:

[0004] A memory based on a flash memory format (such as NOR-Flash) is provided, which has a storage transistor array;

[0005] Using a storage transistor array as a carrier of a weight matrix of a neural network, setting the input data of the neural network to be transmitted to a series of bit lines of the storage transistor array, setting the output data of the neural network to be captured from a series of source lines of the storage transistor array, so as to realize storage and calculation integrated based on flash memory;

[0006] In which each weight in the weight matrix of the neural network is represented by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the storage transistor array, the gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled on the same bit line.

[0007] In the above method, the original input data of the neural network (such as an artificial neural network) is converted into an input quantity in the format of a voltage value, so as to be transmitted to a series of bit lines of a storage transistor array based on the input quantity sorted into a vector; any pair of complementary transistors receives the voltage value on the bit line of their column, so that the difference between the drain-source voltages of the any pair of complementary transistors is the same.

[0008] In the above method, an output data of the neural network is represented by the ratio of the difference between the output currents at the source lines of the two rows of transistors corresponding to a row of weights divided by a preset coefficient, and any two transistors in the two rows of transistors located in the same column and sharing the same bit line are regarded as a pair of complementary transistors; and the multiple ratios provided by a series of source lines of the storage transistor array are regarded as the output quantities arranged into vectors provided by the storage transistor array.

[0009] In the above method, the manner of adjusting any weight in the weight matrix includes: changing the floating gate injection charge of each of the pair of complementary transistors selected by the any weight, adjusting the difference in threshold voltages of the selected pair of complementary transistors by the relative change of the floating gate injection charge of the two complementary transistors, and further adjusting the size of the weight value at the position of the selected pair of complementary transistors.

[0010] In the above method, a digital-to-analog converter such as a DAC is configured at the bit line of the storage transistor array, which is used to convert the input data of the neural network (for example, a digital quantity usually relative to an analog quantity) into a voltage value that satisfies the format requirements of the input signal quantity (for example, an analog signal quantity) of the bit line of the storage transistor array.

[0011] In the above method, an analog-to-digital converter such as an ADC is configured at the source line of the storage transistor array, which is used to convert the output signal in the form of an output current at the source line (such as an analog quantity usually relative to a digital quantity) into output data that meets the format requirements of the digital output quantity (such as a digital signal quantity) of the neural network.

[0012] In the above method, a combination of every two rows of transistors is used in a storage transistor array to define a row of weights in a weight matrix (e.g., every two rows of transistors (i.e., a combination) determines a row of weight values), and multiple rows of transistors in the storage transistor array provide multiple combinations accordingly; a multiplexer (MUX) is used to time-switched a group of output currents at the source lines of different combinations to a current subtractor, and the current subtractor performs the current difference calculation of the output currents at the source lines of the two rows of transistors corresponding to each combination.

[0013] In the above method, the address code of the multiplexer is controlled or manipulated to determine whether any combination is selected, and only a group of output currents at the two source lines of the selected combination are delivered to the current subtractor, and a group of output currents at the two source lines of the other unselected combinations are not allowed to be delivered to the current subtractor.

[0014] In the above method, when any combination is selected, the value of the address code is switched to the only enable code value that can activate the combination to be valid, and a code element with a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to the combination are transiently coupled (or coupled) once through the coupling capacitor.

[0015] The present application relates to an artificial intelligence integrated memory, characterized in that it includes:

[0016] Memory in the form of flash memory with arrays of memory transistors used to build implementations of neural networks;

[0017] Using a memory transistor array as a carrier of a weight matrix of a neural network, setting the input data of the neural network to be transmitted to a series of bit lines of the memory transistor array, and setting the output data of the neural network to be captured from a series of source lines of the memory transistor array, so that the memory integrates an artificial intelligence computing function based on a neural network;

[0018] Each weight in the weight matrix of the neural network is characterized by the difference in threshold voltages of a corresponding pair of complementary transistors in the same column but arranged in two rows in the storage transistor array, the gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled to the same bit line;

[0019] Among them, the original input data of the neural network is converted into input quantities in voltage value format and then transmitted to the bit lines of the storage transistor array. The difference in output current at the source lines of each two rows of transistors in the storage transistor array divided by the ratio of a preset coefficient is used as an output data of the neural network.

[0020] In the above-mentioned artificial intelligence integrated memory, the original input data of the neural network is converted into input quantities in the format of voltage values, and is transmitted to a series of bit lines of the storage transistor array based on the input quantities sorted into vectors; any pair of complementary transistors receives the voltage value on the bit line of their column, so that the difference between the drain-source voltages of the any pair of complementary transistors is the same.

[0021] In the above-mentioned artificial intelligence integrated memory, a single output data of the neural network is represented by the ratio of the difference between the output currents at the source lines of the two rows of transistors corresponding to a row of weights divided by a preset coefficient, and any two transistors in the two rows of transistors that are located in the same column and share the same bit line are regarded as a pair of complementary transistors; the many ratios provided by a series of source lines of the storage transistor array are regarded as the output quantities sorted into vectors provided by the storage transistor array.

[0022] In the above-mentioned artificial intelligence integrated memory, the method of adjusting any weight in the weight matrix includes: changing the floating gate injection charge of each of the pair of complementary transistors selected by the any weight, adjusting the difference in threshold voltages of the selected pair of complementary transistors by the relative change of the floating gate injection charge of the two complementary transistors, and further adjusting the size of the weight value at the position of the selected pair of complementary crystals.

[0023] The above-mentioned artificial intelligence integrated memory has a digital-to-analog converter configured at the bit line of the storage transistor array, which is used to convert the input data of the neural network (such as a digital quantity usually relative to an analog quantity) into a voltage value that satisfies the format requirements of the input signal quantity (such as an analog signal quantity) of the bit line of the storage transistor array.

[0024] In the above-mentioned artificial intelligence integrated memory, an analog-to-digital converter is configured at the source line of the storage transistor array, which is used to convert the output signal in the form of an output current at the source line (such as an analog quantity usually relative to a digital quantity) into output data that meets the format requirements of the digital output quantity (such as a digital signal quantity) of the neural network.

[0025] In the above-mentioned artificial intelligence integrated memory, a combination of every two rows of transistors in the storage transistor array is used to define a row of weights in the weight matrix (every two rows of transistors (i.e., one combination) determine a row of weight values), and multiple rows of transistors in the storage transistor array provide multiple combinations accordingly; a multiplexer (MUX) is used to time-switch a group of output currents at the source lines of different combinations to a current subtractor, and the current subtractor performs the current difference calculation of the output currents at the source lines of the two rows of transistors corresponding to each combination.

[0026] The above-mentioned artificial intelligence integrated memory controls the address code or selection signal of the multiplexer to determine whether any combination is selected, and only a group of output currents at the two source lines of the selected combination are delivered to the current subtractor, and a group of output currents at the two source lines of other unselected combinations are not allowed to be delivered to the current subtractor.

[0027] In the above-mentioned artificial intelligence integrated memory, when any combination is selected, the value of the address code at this time is switched to the only enabling code value that can activate the any combination to be valid, and a code element with a specified weight bit is selected in the enabling code value. When the code element is flipped, the source lines of the two rows of transistors belonging to the any combination are transiently coupled once through the coupling capacitor.

[0028] The present application relates to an in-memory computing chip, characterized in that it comprises:

[0029] Memory in the form of flash memory with arrays of memory transistors used to build implementations of neural networks;

[0030] Using a memory transistor array as a carrier of a weight matrix of a neural network, setting input data of the neural network to be transmitted to a series of bit lines of the memory transistor array, and setting output data of the neural network to be captured from a series of source lines of the memory transistor array;

[0031] Each weight in the weight matrix of the neural network is characterized by the difference in threshold voltages of a corresponding pair of complementary transistors in the same column but arranged in two rows in the storage transistor array, the gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled to the same bit line;

[0032] Among them, the original input data of the neural network is converted into input quantities in voltage value format and then transmitted to the bit lines of the storage transistor array. The difference in output current at the source lines of each two rows of transistors in the storage transistor array divided by the ratio of a preset coefficient is used as an output data of the neural network.

[0033] The above-mentioned in-memory computing chip also includes: a digital-to-analog converter integrated in the chip, wherein a digital-to-analog converter is configured at each bit line of the storage transistor array to convert the input data of the neural network into a voltage value matching the input signal pattern of the bit line; an analog-to-digital converter integrated in the chip, wherein an analog-to-digital converter is configured at each source line of the storage transistor array to convert the output signal in the output current format at the source line into output data matching the digital output quantity of the neural network.

[0034] Based on the foregoing, one of the biggest advantages of the present application is that the weight matrix of the neural network is directly mapped to the storage transistor array and the relative charge of the complementary transistors can be adjusted to dynamically configure the weight matrix of the neural network so as to adapt to the weight matrix (weight matrix) of the neural network. It is worth noting that different transistors must have inconsistent process parameters in the semiconductor manufacturing process, and this inconsistency will cause intrinsic errors in the weights of different transistors. The process parameters related to transistors include current or voltage amplification factor or dissipated power, frequency characteristics and current characteristics, voltage characteristics, and width-to-length ratio. If a single individual transistor is used to express a weight, the inconsistency of the process parameters between different transistors will cause the weight error that naturally exists between different transistors. On the contrary, if the scheme of this article is used, instead of using a single transistor, the relative floating gate threshold relationship of a pair of complementary transistors is used to express a single weight, the weight error caused by inconsistent process parameters between different transistors can be eliminated.

[0035] Based on the foregoing, the second biggest advantage of the present application is that it adopts a non-von Neumann architecture, which can solve the compilation wall, storage wall, and power consumption wall problems under the traditional von Neumann architecture. The obvious convenience in compilation is to adjust the relative threshold of complementary transistors to achieve weight programming, and a single weight is based on complementary transistors. This solution only needs to configure the relative floating gate charge relationship between the two complementary transistors at a pair of complementary transistors to achieve the compilation of core weight parameters. Furthermore, the floating gate storage charges of the complementary transistors originally used to store data code elements are adjusted relative to each other. The storage charge itself represents data storage, and the relative charge relationship represents the weight, so the storage itself and network computing can be integrated without obstacles, which can solve the concerns about storage walls and power consumption walls, and save the intermediate transmission barriers and power consumption of moving data and performing calculations between the memory and the computing unit in traditional computer systems.

[0036] Based on the foregoing, the third biggest advantage of this application is to correct the erroneous results of the neural network. In artificial intelligence, for example, a large number of multiplication and convolution operations are the core components of deep learning. The storage and computing technology uses a large number of weight parts of multiplication and addition calculations in storage units, and completes network calculations such as convolution operations in the storage array. Neural networks are limited by semiconductor manufacturing processes and cannot flexibly expand operators such as increasing and decreasing weight matrices, because the increase in the weight matrix requires the number of columns or rows of the many transistor arrays participating in the weight matrix to become more synchronous. Note that the semiconductor manufacturing process will inevitably give rise to many parasitic parameters in the weight array. Typically, the more transistor columns mounted on the same source line (source line) means that the weight matrix is ​​wider, and each additional column of transistors causes the source line parasitic capacitance to expand once, and the parasitic capacitance is not a simple cumulative relationship. In essence, it is a complex complex of capacitors in series and parallel, with extremely low regularity. The operation result of the neural network is closely related to the source line current. The complex parasitic capacitance of the source line will hinder the real current of the source line. In addition, the charging and discharging of the parasitic capacitance will lag the speed of network calculation and also affect the access to the stored charge. The larger the array, the larger the network parasitic capacitance. The participation of parasitic parameters in the matrix operation will lead to the deviation of the operation result of the neural network. This application advocates actively clamping the source lines of the two rows of transistors used to define a row of weights. The key goal is to reduce the correlation between the neural network operation results and the parasitic parameters caused by the size of the transistor array, and overcome the result deviation caused by the participation of parasitic parameters in the neural network matrix operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0038] Figure 1 A finite number of transistors are selected inside the flash memory as the weight carriers of the neural network.

[0039] Figure 2 The input data to the neural network comes from a series of bit lines in the storage transistor array.

[0040] Figure 3 Taking a picture with pixels as an example, the pixel value or grayscale value is input into the storage transistor array.

[0041] Figure 4 It is the difference in output current at the source lines of the two rows of transistors corresponding to a row of weights.

[0042] Figure 5 A multiplexer is used to time-share switch a group of output currents at the source lines of different combinations.

[0043] Figure 6 When any combination is selected, the value of the address code at this time switches to the valid enable code value.

[0044] Figure 7 This is an example of transiently coupling the source lines of the two rows of transistors belonging to the combination through coupling capacitors. DETAILED DESCRIPTION

[0045] The technical solutions disclosed in the present application will be clearly and completely described below in conjunction with various specific embodiments, but the described embodiments are only embodiments used for narration and explanation of the present application rather than all embodiments.

[0046] See also Figure 1 Regarding the concepts related to storage and calculation, the storage and calculation method mentioned in the context of this application is an abbreviation for in-memory calculation or storage and calculation integrated performed inside the memory.

[0047] See also Figure 1 Regarding storage-related concepts, the flash memory-based memory mentioned in the context of this application is, for example, a NOR-Flash-based memory, or an equivalent memory.

[0048] See also Figure 1 , with respect to artificial intelligence integrated memory, the artificial intelligence integrated memory mentioned in the context of this application is a type of memory that integrates artificial intelligence functions based on implementing in-memory computing, such as an in-memory computing chip.

[0049] See also Figure 1, for the convenience of explanation, an existing conventional NOR flash memory circuit is used as an example. The working principle is that a floating gate (Floating Gate) for storing stored charges such as electrons can be formed between the source S and the drain D of the storage transistor, that is, on the current-conducting semiconductor, and the floating gate is isolated by an insulating layer such as a silicon oxide film. Outside the floating gate is a selection / control gate (Control Gate) that controls the conduction current between the source and the drain. The floating gate charge, such as electrons, will not disappear immediately due to power failure, so the flash memory is a non-volatile memory. The write operation is such as applying a positive voltage to the control electrode to allow charges such as electrons to enter the floating gate through the insulating layer. The erase operation is, for example, the opposite, and a positive voltage can be applied to the substrate to separate electrons from the floating gate to achieve erasure. Flash memory and its data operations belong to the prior art, and this article will not repeat them separately. The read, write or erase operations of flash memory in the prior art can be applied to the flash memory of this application.

[0050] See also Figure 1 , describes flash memory in array form: the gates of each row of transistors are connected to a common word line and the drains of each column of transistors are connected to a common bit line, and the sources of each row of transistors are connected to a common source line.

[0051] See also Figure 1 , with respect to the row word line example, the gates of the first row transistors are connected to the word line G1 and the gates of the second row transistors are connected to the word line G2, and the gates of the Mth row transistors are connected to the word line GM. The gates of the 2Mth row transistors are connected to the word line G2M. More omitted rows and omitted columns are not repeatedly shown in the figure. The total number of M rows of transistors is considered as the matrix M×N elements, and the total number of 2M rows of transistors is considered as the matrix 2M×N elements.

[0052] See also Figure 1 , with respect to the row source line example, the sources of the first row transistors are connected to source line S1 and the sources of the second row transistors are connected to source line S2, and the sources of the Mth row transistors are connected to source line SM. The sources of the 2Mth row transistors are connected to source line S2M. More omitted rows are not repeatedly shown in the figure.

[0053] See also Figure 1 For the column bit line example, the drains of the first column transistors are connected to the bit line B1, the drains of the second column transistors are connected to the bit line B2, and the drains of the third column transistors are connected to the bit line B3. The drains of the Nth column transistors are connected to the bit line BN. The total number of N columns of transistors is considered as a matrix of N×2M elements.

[0054] See also Figure 1The original function of the floating gate of the memory is to store the code element 1 or 0. In other words, the flash memory has no special use in traditional computers, servers or other similar electronic devices except for storage. However, this application no longer regards the flash memory as a storage space that only stores code elements 1 or 0, but advocates changing the circuit architecture of the flash memory to a computing unit that can participate in artificial intelligence, and the underlying physical structure of the flash memory is minimally changed.

[0055] See also Figure 4 , the flash memory-based storage and calculation method includes: providing a flash memory-based memory having a storage transistor array such as a 2M×N array. Using a storage transistor array such as 2M×N as a carrier of the weight matrix of the neural network, setting the input data of the neural network to be transmitted to the series bit lines B1-BN of the transistor array, and setting the output data of the neural network to be captured from the series source lines S1-S2M of the storage transistor array such as 2M×N, thereby realizing the flash memory-based storage and calculation. Each weight in the weight matrix of the neural network such as Ma_wei is represented by the difference in threshold voltages of a corresponding pair of complementary transistors in the same column but arranged in two rows in the storage transistor array, and the gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled to the same bit line.

[0056] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 11 The threshold voltages (V TH11 and V TH21 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B1.

[0057] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 12 The threshold voltages (V TH12 and V TH22 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B2.

[0058] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 13The threshold voltages (V TH13 and V TH23 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B3.

[0059] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 1N The threshold voltages (V TH1N and V TH2N ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line BN.

[0060] See also Figure 4 The reason why flash memory-based computing units are used to replace traditional computers is that there are several major drawbacks in the operation phase of computers executing neural networks: the data transfer time is hundreds or thousands of times longer than the operation time when reading and writing data from the memory outside the processor, and the ineffective energy consumption of the entire process is about 60%-90%. The energy efficiency is very low and the accompanying storage wall problem has become a major obstacle to data computing applications. In particular, the biggest challenge in accelerating deep learning in neural networks is the frequent transfer of data between computing units and storage units. Although parallel acceleration technologies such as multi-core CPUs or multi-core GPUs are used to improve computing power, in the post-Moore era, storage bandwidth restricts the practical bandwidth of computing systems and makes the overall computing power growth difficult. The time-consuming and power-consuming operation of weight calculations or inference calculations of neural networks on traditional computers is one of the most prominent manifestations of this drawback.

[0061] See also Figure 2 In the design, bit lines B1-BN are used as input and source lines S1-S2M are used as output. Figure 1 The flash memory is regarded as the physical carrier that can realize the neural network NET.

[0062] See also Figure 4 , In order to illustrate the specific implementation process, a weight matrix Ma_wei is designed as follows.

[0063]

[0064] See also Figure 4, the neural network has encountered a bottleneck in its development due to the introduction of a large number of parameters. Each output neuron of the fully connected layer is connected to all input neurons. According to the assumptions in the figure: if the number of input neurons is N and the number of output neurons is M, then there are at least approximately N×M weights or M biases that need to be trained and calculated. For each output neuron of the convolutional layer, there are usually input neurons within the coverage of the convolution kernel connected to it, and the convolution kernel used for all outputs is the same. Although local connections and weight sharing reduce the parameters of the convolutional layer, a large amount of calculations still need to be performed under the conditions of large-size image input and deep neural networks. The reading and calculation of large amounts of data face the memory bottleneck and computing bottleneck of the network. The power consumption and latency of neural networks have risen sharply, limiting the application of neural networks.

[0065] See also Figure 2 , the bit line B1-BN input is represented by the vector Ma_in=[B1, B2...BN]. For the convenience of mathematical expression, the input of bit line B1 needs to be mapped to X 1 , Map the input of bit line B2 to X 2 , the input of bit line B3 is mapped to X 3 , ..., bit line BN input quantity mapping X N That is, Main = [X 1 , X 2 …X N ] indicates input.

[0066] See also Figure 2 , the output of source line S1-S2M is represented by vector Ma_out = [S1 / S2, S3 / S4...S2M]. For the convenience of mathematical expression, the current output of source line S1 / S2 needs to be mapped to Y 1 , Map the output of source lines S3 / S4 to Y 2 , the output of source line S5 / S6 is mapped to Y 3 , ..., map the output of both source lines S(2M-1) / S2M to Y M That is, Ma_out=[Y 1 , Y 2 …Y M ] indicates output.

[0067] See also Figure 2 The purpose of the flash memory is to perform the computing function of the neural network NET. The specific computing process is expressed by the following formula. In fact, this process is actually a detailed example of simulating the flash memory as a computing unit or a quasi-computing unit. Figure 4 . 1 and Y 2 and Y M etc. as representatives to illustrate this spirit.

[0068] Y 1 =X 1 *W 11 +X 2 *W 12 +X 3 *W 13 +…X N *W 1N

[0069] Y 2 =X 1 *W 21 +X 2 *W 22 +X 3 *W 23 +…X N *W 2N

[0070] Y M =X 1 *W M1 +X 2 *W M2 +X 3 *W M3 +…X N *W MN

[0071] See also Figure 2 In order to solve the aforementioned bottleneck, the non-von Neumann architecture shown in the figure can provide greater computing power and higher energy efficiency in specific fields, and can surpass existing ASIC computing chips. In-memory computing and in-memory logic, that is, the integrated storage and computing technology directly uses the memory for data processing or calculation, thereby integrating data storage and data calculation in the same chip or the same area of ​​the same memory, which can completely eliminate the bottleneck of the von Neumann computing architecture, especially for large-scale parallel application scenarios such as deep learning neural networks with large amounts of data.

[0072] See also Figure 2 A more intuitive expression is to use vector-matrix multiplication to show the aforementioned complex operation. The vector-matrix expression flash memory performs local data processing of the neural network NET as follows. Figure 4 .

[0073]

[0074] See also Figure 2 If we define X 1 To X N is the input layer of the neural network NET, then Y 1 To Y N The corresponding layer is the output layer of the neural network NET. Figure 1The flash memory completes the entire vector operation from the input layer to the output layer, and this operation is very different from the operation of the traditional von Neumann computer, because its operation only needs to measure the respective signal quantities from the source lines S1-S2M. Single multiplication and addition do not need to be implemented one by one, and the final operation result can be fully reflected from the signal quantities of the source lines S1-S2M at one time. So it is called quasi-computing. The operation of the traditional von Neumann computer must implement all multiplications and additions one by one, which is the biggest difference between the two.

[0075] See also Figure 4 , the combination of every two rows of transistors (such as the first row and the second row) in the storage transistor array is used to define the first row weight (W) in the weight matrix 11 -W 1N ), a storage transistor array such as N×2M multi-row transistors provides multiple combinations: a combination of the first row and the second row, a combination of the third row and the fourth row, and so on.

[0076] See also Figure 4 The storage transistor array uses the combination of every two rows of transistors (row 2M-1 and row 2M) to define the weight of the Mth row in the weight matrix (W M1 -W MN ), the multiple rows of transistors in the storage transistor array N×2M provide multiple combinations: a combination of the K-1th row and the Kth row, a combination of the 2M-1th row and the 2Mth row, etc.

[0077] See also Figure 3 , the neural network NET based on flash memory is suitable for the field of image processing. Assume that data of a video or picture with pixel values ​​or gray values ​​(such as image classification, image segmentation, autonomous driving, target detection, etc.) is input into the neural network NET based on flash memory, and the image Gr_in is taken as an example below.

[0078] See also Figure 3 , the pixels in the image Gr_in are divided into multiple rows and columns, and the pixel corresponding to the address of the 0th pixel is defined as g1, the pixel corresponding to the address of the 1st pixel is defined as g2, the pixel corresponding to the address of the 2nd pixel is defined as g3, and so on. The pixel corresponding to the last pixel address is gn. According to the arrangement rule and address regulations of the pixel matrix, the gray value of any pixel can be obtained by the image obtained by shooting. Allow the gray value or pixel value of n pixels (belonging to the image Gr_in) to be coupled to the X 1 To X NThe grayscale values ​​or pixel values ​​of n pixels (belonging to the image Gr_in) are allowed to be segmented and then sent to different flash memories, that is, the grayscale values ​​or pixel values ​​of n pixels are respectively implemented by different flash memories for distributed computing. Of course, the grayscale values ​​or pixel values ​​can also be normalized or similar image data processed before being sent to the memory.

[0079] See also Figure 3 , an important issue to note is that the input quantity format of the bit lines B1-BN should conform to the inherent characteristics of the flash memory, that is, the input value of the bit lines B1-BN is not directly equivalent to the pixel value g1-gn. Therefore, in an optional embodiment, the pixel values ​​g1-gn are converted from digital to analog by a DAC device such as a digital-to-analog converter packaged together with the flash memory, and the analog quantities corresponding to the pixel values ​​g1-gn are then input to the bit lines B1-BN. The DAC (Digital to Analog Converter) device can also be directly integrated with the flash memory on the same semiconductor chip during the wafer manufacturing stage. At this point, the data contained in the image Gr_in can be smoothly coupled with the flash memory. Another important factor is that the final storage location or space of the image Gr_in must usually be various types of memory, so the unique advantage that the storage location of the image Gr_in and the location where the matrix operation is performed are the same flash memory can be revealed. The processor CPU or GPU will no longer have to read data from the memory to itself to perform matrix operations. All storage and computing actions are implemented in the memory. The concerns mentioned above about reading and writing data from the processor to the memory, the time cost of data transfer, etc. (storage wall) will no longer exist.

[0080] See also Figure 4 , there is still a problem to be solved: In order to explain the specific implementation process of the neural network, the previous article specially designed the matrix Ma_wei involved in the network calculation. However, how to map the M*N vector matrix Ma_wei to the transistors in the flash memory? Figure 1 There are still some concerns that need to be resolved on the 2M×N array shown.

[0081] See also Figure 4, about the relationship between pixel values ​​g1-gn and bit lines B1-BN, pixel value g1 is converted into voltage value V1 through DAC digital-to-analog conversion, pixel value g2 is converted into voltage value V2 through digital-to-analog conversion, pixel value g3 is converted into voltage value V3 through digital-to-analog conversion, and so on, pixel value gn is converted into voltage value VN through digital-to-analog conversion. According to the interface correspondence shown in the figure, voltage value V1 is connected to bit line B1, voltage value V2 is connected to bit line B2, voltage value V3 is connected to bit line B3, and so on, voltage value VN is connected to bit line BN. According to the rule, the larger the pixel value, the larger the converted bit line voltage value, and the smaller the pixel value, the lower the converted bit line voltage value. If the number of transistor layouts, that is, the size of the matrix 2M×N, has a corresponding relationship with the pixel size of the image Gr_in, that is, n / N has an equal relationship, then the single flash memory array shown in the figure can just process n pixel values. Otherwise, more n pixel values ​​require multiple illustrated flash memory arrays to cooperate and perform calculations, for example, when n / N are not equal. That is, the grayscale values ​​or pixel values ​​of more pixels are calculated separately by different transistor arrays. The benefits of this article: The memory is limited by the semiconductor manufacturing process and cannot expand the weight matrix flexibly and unlimitedly. If N caters to n and forcibly expands the adaptation operator of the neural network, the larger the array (for example, N becomes larger), the larger the parasitic parameters of the neural network NET will be, and the participation of parasitic parameters in the matrix operation will lead to the deviation of the calculation results of the neural network. When the matrix Ma_wei expansion faces the shackles of the semiconductor manufacturing process, how to avoid the participation of parasitic parameters in the operation is the advantage of this article.

[0082] See also Figure 4 , with respect to the matrix Ma_wei, the gates of the transistors in the first row are connected to the word line G1, the gates of the transistors in the second row are connected to the word line G2, and the gates of the transistors in the Mth row are connected to the word line GM. The gates of the transistors in the 2Mth row are connected to the word line G2M. For the first row weight, the corresponding weights of the transistors in the first row and the transistors in the second row are recorded as W 11 , W 12 , W 13 , ...W 1N The weights generated by the third and fourth rows of transistors for the second row weight are recorded as W 21 , W 22 , W 23 , ...W 2N For the weight of the Mth row, the weights generated by the 2M-1th row and the 2Mth row transistors are recorded as W M1 , W M2 , W M3 , ...W MN The combination of every two rows of transistors in the memory transistor array is used to define a row of weights in the weight matrix. 11-W 1N Example explanation.

[0083] See also Figure 4 , for the first row weight W 11 -W 1N , a weight W 11 The threshold voltages (V TH11 and V TH21 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B1.

[0084] See also Figure 4 , for the first row weight W 11 -W 1N , for example, the weight W 1N The threshold voltages (V TH1N and V TH2N ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line BN.

[0085] See also Figure 4 , a total of 2M rows and N columns of transistors are regarded as M×N matrix elements. The definition of each weight value in the matrix Ma_wei is the basis for realizing the neural network NET. The figure shows that the source current of each row of transistors flows to the common source line of the row of transistors, and the figure shows that the drain of each column of transistors is connected to the common bit line of the column of transistors. This layout of transistors will provide a feasible solution for how to define the weights of transistors. For example, the source current convergence characteristics of each row of transistors correspond to the multiplication and accumulation calculation algorithm of the vector matrix multiplication mentioned above, and each weight is characterized by the difference in threshold voltages of a corresponding pair of complementary transistors in the same column but arranged in two rows in the storage transistor array.

[0086] See also Figure 4 To explain how to map weights to transistors, let’s first introduce the relationship between the current and threshold of the storage transistor and the applied voltage: The threshold voltage of the gate is V TH ; The process parameter K of the storage transistor related to the process is μCW / L, where W / L is the aspect ratio of the transistor. For a storage transistor with a certain manufacturing process and a certain size, the process parameter K is almost a constant; the voltage between the gate and the source is V GSand the voltage V between the transistor drain and source DS Can satisfy K[(V GS -V TH )V DS -V 2 DS / 2] = I. For a row of transistors, if the source line currents I of the transistors are multiplied and the output currents I of the transistors in a row are accumulated, this is equivalent to the multiplication and accumulation calculation of matrix multiplication, which is also the basic principle of mapping the transistor array to the weight matrix.

[0087] See also Figure 4 , first row transistor (gate coupled to G1): The current I11 of the first transistor is calculated to be approximately K[(V GS1 -V TH11 )V DS1 -V 2 DS1 / 2] = I11. Similarly, the current I12 of the second transistor can be calculated to be approximately K[(V GS1 -V TH12 )V DS2 -V 2 DS2 / 2] = I12. Similarly, the Nth transistor current I1N can be calculated to be approximately K[(V GS1 -V TH1N )V DSN -V 2 DSN / 2]=I1N. The voltage between the gate and source of the first transistor is V GS1 and the voltage between the drain and source is V DS1 , the threshold voltage is V TH11 , the gate-source voltage of the second transistor is V GS1 and the voltage between the drain and source is V DS2 , the threshold voltage is V TH12 , the voltage between the gate and source of the Nth transistor is V GS1 and the voltage between the drain and source is V DSN , the threshold voltage is V TH1N The above is the specific situation of the first row of transistors.

[0088] See also Figure 4 , first row of transistors (gate coupled to G1): the source currents of the first transistor to the Nth transistor all flow to the common source line S1 of the transistors in this row, and the current of the source line S1 is denoted as IS1.

[0089] IS1=I11+I12+I13+…I1N

[0090] See also Figure 4, the second row of transistors (gate coupled to G2): The current I21 of the first transistor is calculated to be approximately K[(V GS2 -V TH21 )V DS1 -V 2 DS1 / 2]=I21. Similarly, the current I22 of the second transistor can be calculated to be K[(V GS1 -V TH22 )V DS2 -V 2 DS2 / 2] = I22. Similarly, the Nth transistor current I2N can be calculated to be K[(V GS1 -V TH2N )V DSN -V 2 DSN / 2] = I2N. The voltage between the gate and source of the first transistor is V GS2 and the voltage between the drain and source is V DS1 , the threshold voltage is V TH21 , the gate-source voltage of the second transistor is V GS2 and the voltage between the drain and source is V DS2 , the threshold voltage is V TH22 , the voltage between the gate and source of the Nth transistor is V GS2 and the voltage between the drain and source is V DSN , the threshold voltage is V TH2N The above is the specific situation of the second row of transistors.

[0091] See also Figure 4 , the second row of transistors (gate coupled to G2): the source currents of the first transistor to the Nth transistor all flow to the common source line S2 of the transistors in this row, and the current of the source line S2 is recorded as IS2.

[0092] IS2=I21+I22+I23+…I2N

[0093] See also Figure 4 , a preset coefficient K = μCW / L is a parameter for explaining the weight. Where W / L is the aspect ratio of the transistor, μ is the mobility of carriers such as electrons, and C is the capacitance of the gate oxide. The preset coefficient is described in the equation for the drain current of the transistor in the literature "CMOS Circuit Design, Layout and Simulation" by Jacob Baker, for example, and the relevant equation is cited in this article as a reference.

[0094] See also Figure 4, if the first row of transistors (word line G1) and the second row of transistors (word line G2) are set to have the same potential, for example, the gate of word line G1 is coupled to the gate of word line G2. That is, the gate-source voltage of the first row of transistors is equal to the gate-source voltage of the second row of transistors, such as V GS1 Equal to V GS2 The voltages assigned to the series bit lines B1 to BN at the transistor array position can be V DS1 To V DSN If VN=V DSN Then, the source line current IS1 of the first row of transistors is subtracted from the source line current IS2 of the second row of transistors, which is recorded as IS12.

[0095] IS12=IS1-IS2=(I11-I21)+(I12-I22)+(I13-I23)+…(I1N-I2N)

[0096] See also Figure 4 , as previously recorded in Ma_wei, inform the weight W 11 The threshold voltages (V TH11 and V TH21 ), note that the gates of the complementary transistors are coupled together (G1 coupled to G2), and the drains of the complementary transistors are coupled to the bit line B1 (V1 = V DS1 ). Complementary transistor current subtraction I11-I21=K[(V GS1 -V TH11 )V DS1 -V 2 DS1 / 2]-K[(V GS2 -V TH21 )V DS1 -V 2 DS1 / 2], the result of current subtraction is expressed as I11-I21=K[(V TH21 -V TH11 )V DS1 ]. The voltage of bit line B1 is V1. The threshold voltages (V TH11 and V TH21 ) to represent the weight W 11 .

[0097] See also Figure 4 , as previously recorded in Ma_wei, inform the weight W 1NThe threshold voltages (V TH1N and V TH2N ), note that the gates of the complementary transistors are coupled together (G1 coupled to G2), and the drains of the complementary transistors are coupled to the bit line BN (VN = V DSN ). The complementary transistor current subtraction I1N-I2N=K[(V GS1 -V TH1N )V DSN -V 2 DSN / 2]-K[(V GS1 -V TH2N )V DSN -V 2 DSN / 2], the subtraction result is expressed as I1N-I2N=K[(V TH2N -V TH1N )V DSN ]. The voltage of the bit line BN is VN. The threshold voltage (V TH1N and V TH2N ) to represent the weight W 1N .

[0098] See also Figure 4 , if the source line current IS1 and source line current IS2 of the first row transistor (word line G1) and the second row transistor (word line G2) are subtracted, it is recorded as IS12. Word line G1 is coupled to word line G2.

[0099] IS12=(K*W 11 *V1)+(K*W 12 *V2)+(K*W 13 *V3)+…(K*W 1N *VN)

[0100] See also Figure 4 The first row of transistors (word line G1) and the second row of transistors (word line G2) can be expressed as the above IS12 expression after the current subtraction formula is converted (Y can also be defined 1 =IS12 / K). The source current IS1 convergence characteristics of the transistors in the first row correspond to the multiplication and accumulation calculation algorithm of the vector-matrix multiplication; the source current IS2 convergence characteristics of the transistors in the second row correspond to the multiplication and accumulation calculation algorithm of the vector-matrix multiplication. Furthermore, the source current of the transistors in the first row is subtracted from the source current of the transistors in the second row, IS1-IS2=IS12, which does not affect the multiplication calculation of the weight and the bit line voltage, nor does it affect the accumulation calculation mechanism of the multiplication value obtained by the multiplication calculation.

[0101] See also Figure 4 In addition to being used for AI computing, flash memory can also be used for other computing applications such as brain-like chips. It represents a future mainstream big data computing chip architecture, and can also be used as a core computing module for low-energy supercomputing centers. For example, NOR FLASH in-memory computing can support about 300M of deep learning weight parameters in a single chip, and can perform calculations without additional memory.

[0102] See also Figure 5 , if the source line current IS3 and source line current IS4 of the third row transistor (word line G3) and the fourth row transistor (word line G4) are subtracted, they are recorded as IS34. Word line G3 is coupled to word line G4.

[0103] IS34=(K*W 21 *V1)+(K*W 22 *V2)+(K*W 23 *V3)+…(K*W 2N *VN)

[0104] See also Figure 5 , the third row transistor (word line G3) and the fourth row transistor (word line G4) can be expressed as the above IS34 expression after the current subtraction formula conversion (Y can also be defined 2 =IS34 / K). The source current IS3 convergence characteristics of the transistors in the third row correspond to the multiplication and accumulation calculation algorithm of the vector-matrix multiplication; the source current IS4 convergence characteristics of the transistors in the fourth row correspond to the multiplication and accumulation calculation algorithm of the vector-matrix multiplication. Furthermore, the source current of the transistors in the third row is subtracted from the source current of the transistors in the fourth row, IS3-IS4=IS34, which does not affect the multiplication calculation of the weight and the bit line voltage, nor does it affect the accumulation calculation mechanism of the multiplication value obtained by the multiplication calculation.

[0105] See also Figure 5 , the 2M-1th row of transistors (the word line where the transistors in this row are located is represented by G(2M-1)) and the other Mth row of transistors adjacent to the row (the word line where the transistors in this row are located is represented by G2M), if the source line current IS(2M-1) and the source line current IS2M of these two rows are subtracted, it is recorded as IS2M(2M-1).

[0106] IS2M(2M-1)=(K*W M1 *V1)+(K*W M2 *V2)+…(K*W MN *VN)

[0107] See also Figure 5, word line G(2M-1) and word line G2M are set to be connected to each other and their potentials are equal.

[0108] See also Figure 5 , the 2M-1th row of transistors (the word line where the transistors in this row are located is represented by G(2M-1)) and the other Mth row of transistors adjacent to the row (the word line where the transistors in this row are located is represented by G2M), after current subtraction conversion, can be expressed as the above IS2M(2M-1) expression (Y can also be defined) M =IS2M(2M-1) / K). The source current IS(2M-1) convergence characteristics of the transistors in the 2M-1th row correspond to the multiplication and accumulation calculation of the vector-matrix multiplication; the source current IS2M convergence characteristics of the transistors in the Mth row correspond to the multiplication and accumulation calculation of the vector-matrix multiplication. The source current of the transistors in the Mth row is subtracted from the source current of the transistors in the 2M-1th row, IS2M-IS(2M-1)=IS2M(2M-1), which does not affect the multiplication calculation of the weight and the bit line voltage, nor does it affect the accumulation calculation mechanism of the multiplication value obtained by the multiplication calculation.

[0109] See also Figure 5 , follow the example shown in the figure, and combine Figure 2 As shown above, based on the mathematical expression, the source line current difference between the source line groups S1 / S2 is mapped to Y 1 And for example Y 1 =IS12 / K. Based on the mathematical expression, the source line current difference between the source line groups S3 / S4 is mapped to Y 2 And for example Y 2 =IS34 / K. Based on the mathematical expression, the source line current difference of the source line group S(2M-1) / S2M is mapped to Y M For example, Y M =IS2M(2M-1) / K.

[0110] See also Figure 5 , follow the example shown in the figure, and combine Figure 2 As shown, the original input data of the neural network is converted into an input quantity in the format of a voltage value, for example, the input data is converted into an input quantity in the format of a voltage value V1-VN, and is transmitted to a series of bit lines B1-BN of the storage transistor array based on the input quantity sorted into a vector. In addition to pixel values, the original input data of the neural network can also be other data suitable for neural network processing, such as voice, text, etc.

[0111] See also Figure 5 , and combined with Figure 2 As shown, the vector Ma_in=[B1, B2...BN] represents mapping the input quantity of bit line B1 to X 1 , the input quantity of bit line B2 is mapped to X 2, the input of bit line B3 is mapped to X 3 , bit line BN input quantity is mapped to X N The input quantities of bit lines B1-BN are V1-VN respectively. That is, Ma_in=[X 1 , X 2 …X N ] indicates that the input is based on the input quantities sorted into vectors, respectively [X 1 =V1、X 2 =V2,…,X N =VN].

[0112] See also Figure 5 , and combined with Figure 4 As shown, any pair of complementary transistors receives the voltage value on the bit line of the column where they are located and makes the difference between the drain-source voltages of the any pair of complementary transistors the same.

[0113] See also Figure 5 , the weight matrix is ​​as in Ma_wei, for example, the weight W 11 It is characterized by the difference in threshold voltages of two complementary transistors located in the same first column (bit line B1) but in the first row (word line G1) and the second row (word line G2) in the memory transistor array. The complementary transistors receive the voltage value V1 on the bit line B1 in the first column and make the difference in drain-source voltage V DS Same (for example, both are V DS1 ).

[0114] See also Figure 5 , the weight matrix is ​​as in Ma_wei, for example, the weight W 1N It is characterized by the difference in threshold voltages of two complementary transistors located in the same Nth column (bit line is BN) but in the first row (word line is G1) and the second row (word line is G2) in the memory transistor array. The complementary transistors receive the voltage value on the bit line BN in the Nth column, i.e., VN, and make the difference in drain-source voltages of the complementary transistors V DS Same (for example, both are V DSN ).

[0115] See also Figure 5 , and combined with Figure 4 As shown, an output data of the neural network is represented by the ratio of the difference between the output currents at the source lines of the two rows of transistors corresponding to a row of weights divided by a preset coefficient, and any two transistors in the two rows of transistors that are located in the same column and share the same bit line are regarded as a pair of complementary transistors; and the multiple ratios provided by a series of source lines of the storage transistor array are regarded as the output quantities sorted into vectors provided by the storage transistor array.

[0116] See also Figure 5, the output data Y of the neural network NET 1 To define a row weight W 11 To W 1N The difference between the output currents IS1 and IS2 at the source lines S1 and S2 of the corresponding two rows of transistors (the first row and the second row) is represented by the ratio of the preset coefficient. IS1-IS2=IS12, the preset coefficient is K=μCW / L, and the ratio is IS12 / K=Y 1 Any two transistors in the two rows of transistors that are located in the same column and share the same bit line are regarded as a pair of complementary transistors.

[0117] See also Figure 5 , the output data Y of the neural network NET 2 To define a row weight W 21 To W 2N The difference between the output currents IS3 and IS4 at the source lines S3 and S4 of the corresponding two rows of transistors (the third and fourth rows) is represented by the ratio of the preset coefficient. IS3-IS4=IS34, the preset coefficient is K=μCW / L, and the ratio is IS34 / K=Y 2 Any two transistors in the two rows of transistors that are located in the same column and share the same bit line are regarded as a pair of complementary transistors.

[0118] See also Figure 5 , the neural network NET outputs data Y M To define a row weight W M1 To W MN The difference between the source line S(2M-1), S2M current IS(2M-1), and IS2M of the corresponding two rows of transistors (rows 2M-1 and 2M) is represented by the ratio of the preset coefficient. IS2M-IS(2M-1)=IS2M(2M-1), the preset coefficient is K=μCW / L and the calculated ratio is IS2M(2M-1) / K=Y M Similarly, any two transistors in the two rows of transistors, the 2M-1th and 2Mth rows, that are located in the same column and share the same bit line are regarded as a pair of complementary transistors.

[0119] See also Figure 5 , as mentioned above, the ratios IS12 / K, IS34 / K, ..., IS2M(2M-1) / K provided by the series of source lines S1 to S2M of the storage transistor array 2M×N are regarded as the output quantity arranged into a vector provided by the storage transistor array 2M×N, namely Ma_out=[Y 1 , Y 2 …Y M ].

[0120] See also Figure 5 , as defined above 1 To X NDefine Y as the input layer of the neural network NET 1 To Y N The corresponding is the output layer of the neural network NET. So far, the first and second rows of transistors in the flash memory have completed a vector operation Y from the input layer to the output layer. 1 , and Y 1 The result of W can be directly calculated at once by sensing the source line current of the first and second rows of transistors, without having to calculate W separately. 11 ×V1 or W 12 ×V2 or W 1N ×VN, etc., belong to the class of calculations under the non-von Neumann architecture. The calculation results are not obtained through numerical calculations, but through current sensing. Similarly, the third and fourth rows of transistors in the flash memory complete a vector operation Y from the input layer to the output layer. 2 The fifth and sixth rows of transistors in the flash memory complete a vector operation Y from the input layer to the output layer. 3 , the 2M-1 and 2M rows of transistors complete a vector operation Y from the input layer to the output layer M The positive integers N and M can be freely expanded to meet network requirements.

[0121] See also Figure 5 As mentioned above, the combination of every two rows of transistors in the storage transistor array is used to define a row of weights in the weight matrix, and the first combination of the first and second rows of transistors defines the first row of weights W 11 -W 1N , the second combination of the third and fourth rows of transistors to define the second row weight W 21 -W 2N , and so on, the Mth combination of the 2M-1 and 2M rows of transistors defines the Mth row weight W M1 -W MN . The first to Mth combinations are shown.

[0122] See also Figure 5 As mentioned above, the multiple rows of the storage transistor array 2M×N, such as 2M rows of transistors, provide the first to Mth combinations. The multiplexer MUX switches a set of output currents at the source lines of different combinations to the current subtractor I_Mi in time-sharing mode, and the current subtractor I_Mi calculates the current difference of the output currents at the source lines of the two rows of transistors corresponding to each combination.

[0123] See also Figure 5The multiplexer MUX transmits the output currents IS1 and IS2 at the source lines of the first combination (the first and second rows of transistors) to the current subtractor I_Mi at time T1. The current subtractor I_Mi performs the current difference calculation of the output currents at the source lines S1 and S2 of the two rows of transistors corresponding to the combination, i.e., IS1-IS2. In the optional example, the output current of the current subtractor I_Mi, i.e., the current difference IS12, is converted into a digital quantity through the ADC device.

[0124] See also Figure 5 The multiplexer MUX transmits the output currents IS3 and IS4 at the source lines of the second combination (the third and fourth rows of transistors) to the current subtractor I_Mi at time T2. The current subtractor I_Mi performs the current difference calculation of the output currents at the source lines S3 and S4 of the two rows of transistors corresponding to the combination, i.e., IS3-IS4. In the optional example, the output current of the current subtractor I_Mi, i.e., the current difference IS34, is converted into a digital quantity through the ADC device.

[0125] See also Figure 5 The multiplexer MUX transmits the output current IS(2M-1) and IS2M at the source line of the Mth combination (the 2M-1st and 2Mth row transistors) to the current subtractor I_Mi at the time TM. The current subtractor performs the current difference calculation of the output current at the source line S(2M-1) and S2M of the 2M-1st and 2Mth row transistors corresponding to the combination, that is, performs the current difference calculation of the subtraction IS2M-IS(2M-1). In an optional embodiment, the output current of the current subtractor I_Mi, that is, the current difference IS2M(2M-1), is converted into a digital quantity through an ADC device.

[0126] See also Figure 5 The multiplexer MUX has a time-sharing characteristic: the multiplexer MUX switches a group of output currents at the source lines of different combinations to the current subtractor in a time-sharing manner. At T1, the group of output currents IS1 and IS2 are delivered to the current subtractor, at T2, the group of output currents IS3 and IS4 are delivered to the current subtractor, at TM, the other groups of output currents IS(2M-1) and IS2M are delivered to the current subtractor, and so on. T1, T2 and TM are different time points and the order between any two of them can be swapped. It is feasible that T1 is earlier or later than T2, and it is feasible that T2 is earlier or later than TM, and so on.

[0127] See also Figure 5 , the source line currents of a pair of source lines corresponding to any combination of two rows of transistors are subtracted by the current subtractor I_Mi, and then combined Figure 3, the output current of I_Mi is converted from analog to digital by an ADC device such as an analog-to-digital converter packaged together with the flash memory. The output current originally embodied as an analog quantity can now be converted into a digital quantity. The digital quantity of the output current is more suitable for various calculations, such as the processor dividing it by a preset coefficient K to obtain a desired ratio. The ADC (Analog to Digital Converter) device can also be directly integrated with the flash memory on the same semiconductor chip during the wafer manufacturing stage.

[0128] See also Figure 4 One of the tasks performed by the transistor array of the flash memory is to construct the matrix Ma_wei, and each element in the matrix corresponds to the weight matrix of the neural network NET.

[0129] See also Figure 4 , the matrix takes the neural network NET input layer Lay1 / hidden layer Lay2 as an example. When the input data is input to the input layer Lay1, the matrix Ma_wei is constructed between the input layer Lay1 and the hidden layer Lay2, and the input data is converted into voltage V1-VN to give to the input layer Lay1, then the output obtained by the hidden layer Lay2 is equivalent to the result of the matrix operation performed by the weight matrix Ma_wei on the input data. The voltage signal is used as the input type and the output data is the current value signal. The weight matrix Ma_wei affects the input voltage signal to affect the amplitude of the output current value. This is the general process of realizing artificial intelligence calculations through NOR Flash memory.

[0130] See also Figure 3 In an optional embodiment, a digital-to-analog converter DAC is configured at the series bit lines B1-BN of the storage transistor array, and the digital-to-analog converter DAC is used to convert the input data of the neural network NET into a voltage value that matches the input signal pattern of the bit line (for example, the bit line requires an analog quantity such as a voltage signal as an input quantity).

[0131] See also Figure 3In an optional embodiment, an analog-to-digital converter ADC is configured at the series source lines S1-S2M of the storage transistor array, and the analog-to-digital converter ADC can be used to convert the output signal in the output current format at the source line into output data that is compatible with the digital output quantity of the neural network NET. For example, the analog-to-digital converter configured at the source lines S1 and S2 is used to convert the output signal in the format of the difference between their output currents IS12 into output data that is compatible with the digital output quantity of the neural network NET. The digital quantity (digital) of current is different from the analog quantity (analog). For example, the analog quantity of the current difference IS12 originally output by the current subtractor I_Mi is recorded as A_IS12, and the analog-to-digital converter samples and converts the current difference IS12 output by the current subtractor to obtain the digital quantity D_IS12 of the current difference IS12.

[0132] See also Figure 3 As mentioned above, a digital-to-analog converter is configured at the bit line of the storage transistor array to convert the input data of the neural network into a voltage value that satisfies the input signal format requirements of the bit line.

[0133] See also Figure 3 As mentioned above, an analog-to-digital converter is configured at the source line of the storage transistor array to convert the output signal in the form of an output current at the source line (such as analog quantity analog) into output data that meets the digital output quantity format (such as digital quantity digital) required by the neural network NET.

[0134] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 11 The threshold voltages of two complementary transistors located in the same first column (bit line is B1) but in the first row (word line is G1) and the second row (word line is G2) in the memory transistor array (the thresholds are V TH11 and V TH21 ), the gates of the complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B1. 11 The method includes: changing any weight W 11 The floating gates of the selected pair of complementary transistors are charged, changing the threshold voltage to V TH11 The floating gate of a transistor injects charge such as electrons and changes the threshold voltage to V TH21 The floating gate injection charge of the remaining other transistor is, for example, electrons. The difference between the threshold voltages of the two selected complementary transistors (the two transistors determined by G1, G2 and B1) is adjusted by the relative change of the floating gate injection charge. For example, the threshold voltage is adjusted to V TH11The floating gate charge of a transistor is compared to the threshold voltage V TH21 The floating gate charge of the remaining transistor is more or less, and the weight W at the position of the selected pair of complementary crystals can be adjusted. 11 The size.

[0135] See also Figure 4 , the weight matrix is ​​as in Ma_wei, and the weight W 13 The threshold voltages (V TH13 and V TH23 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B3. 13 The method includes: changing any weight W 13 The floating gates of the selected pair of complementary transistors are charged, changing the threshold voltage to V TH13 The floating gate of a transistor injects charge such as the amount of charge and changes the threshold voltage to V TH23 The floating gate injection charge of the remaining other transistor is adjusted by the relative change of the floating gate injection charge of the selected complementary transistor (the two transistors determined by G1, G2 and B3) to adjust the difference in threshold voltage between the two transistors, such as adjusting the threshold voltage to V TH13 The floating gate charge of a transistor is compared to the threshold voltage V TH23 The floating gate charge of the remaining transistor should be denser or sparser, and the weight W of the selected pair of complementary crystals can be adjusted. 13 The size.

[0136] See also Figure 5 , for the multiplexer MUX, the multiplexer MUX is used to time-share the output currents at the source lines of different combinations and transmit them to the current subtractor I_Mi, and the current subtractor performs the current difference calculation of the output currents at the source lines of the two rows of transistors corresponding to each combination. The address code is also called the select signal or control signal at the multiplexer. In this article, the address characteristics of the code element are more utilized, so it is defined as the address code and represented by the Sel signal in the figure. In the storage transistor array, the combination of every two rows of transistors (such as the first row and the second row, the third row and the fourth row, etc.) defines a row of weights, and multiple rows of transistors in the storage transistor array provide multiple combinations.

[0137] See also Figure 5 The address code Sel that controls the multiplexer MUX is used to determine whether any combination is selected and only a group of output currents at the two source lines of the selected combination is delivered to the current subtractor I_Mi, and a group of output currents at the two source lines of other unselected combinations are not allowed to be delivered to the current subtractor I_Mi.

[0138] See also Figure 5 , the first combination of the first and second rows of transistors defines a first row weight W 11 -W 1N , the second combination of the third and fourth rows of transistors to define the second row weight W 21 -W 2N , and so on, the Mth combination of the 2M-1 and 2M rows of transistors defines the Mth row weight W M1 -W MN . The first to Mth combinations are shown.

[0139] See also Figure 5 , assuming that the address code Sel satisfies Sel=

[01001] , it is determined that the first combination is selected and only the output currents IS1 and IS2 at the source lines S1 and S2 of the selected first combination are delivered to the current subtractor I_Mi, and the output currents at the source lines of other unselected combinations are not allowed to be delivered to the current subtractor I_Mi. When the first combination is selected, the value of the address code at this time is switched to the only enable code value that can activate the first combination to be valid (enable), such as

[01001] . If the value of the address code at this time is any value other than the enable code value corresponding to the first combination, such as

[01010] , the first combination will not be activated and the output current at its source line cannot be delivered to the current subtractor I_Mi through MUX.

[0140] See also Figure 5 , assuming that the address code Sel satisfies Sel=

[01010] , it is determined that the second combination is selected and only the output currents IS3 and IS4 at the source lines S3 and S4 of the selected second combination are delivered to the current subtractor I_Mi, and the output currents at the source lines of other unselected combinations are not allowed to be delivered to the current subtractor I_Mi. When the second combination is selected, the value of the address code at this time is switched to the only enable code value that can activate the second combination to be valid (enable), such as

[01010] . If the value of the address code at this time is any value other than the enable code value corresponding to the second combination, such as

[01011] , the second combination will not be activated and the output current at its source line cannot be delivered to the current subtractor I_Mi through MUX.

[0141] See also Figure 5Assuming that the address code Sel satisfies Sel=

[01100] , it is determined that the Mth combination is selected and only a set of output currents IS(2M-1) and IS2M at the two source lines S(2M-1) and S2M of the selected Mth combination are transmitted to the current subtractor I_Mi to perform the current calculation of subtraction IS2M-IS(2M-1). The output currents at the source lines of other unselected combinations are not allowed to be transmitted to the current subtractor I_Mi. In the same way, when the Mth combination is selected, the value of the address code at this time is switched to the only enable code value that can activate the Mth combination to be valid (enable), such as

[01100] . If the value of the address code at this time is any value other than the enable code value (active code) corresponding to the Mth combination, such as

[01101] , the Mth combination will not be activated and the output current at its source line cannot be transmitted to the current subtractor I_Mi through MUX.

[0142] See also Figure 5 , as mentioned above, when any combination is selected, for example, any one of the first combination to the Mth combination (taking the Kth combination as an example) is selected, the value of the address code Sel at this time switches to the only active code value that can activate the any combination (taking the Kth combination as an example) to be valid. Please note that if the any combination (taking the Kth combination as an example) cannot be activated to be valid but is invalid (disalbe), then the value of the address code at this time cannot be called an active code value (active code) but a non-active code value (non-active code). In this embodiment, a positive integer K=1, 2, 3…, M can be set. 1≤K≤M.

[0143] See also Figure 5, as mentioned above, when any combination (taking the first combination as an example) is selected, the value of the address code at this time switches to the only enabling code value that can activate any combination (such as the first combination) to be valid. Assuming that the enabling code value is a certain value

[01001] , Sel =

[01001] , select a code element of a specified weight bit in the enabling code value

[01001] . For example, the enabling code value can be expressed as Sel[4] = 0, Sel[3] = 1, Sel[2] = 0, Sel[1] = 0, Sel[0] = 1, and the specified weight bit selected in the enabling code value is Sel[1], the highest weight bit is Sel[4] and the lowest weight bit is Sel[0]. Then the specified weight bit selected in the enabling code value is the second lowest weight bit Sel[1]. The specified weight bit can of course also be the lowest bit or the highest bit or the second highest bit or the third highest bit, etc. Here, the second lowest weight bit Sel[1] is used as the specified weight bit. In the enable code value, the code element of the aforementioned specified weight bit Sel[1] is selected, for example, binary 0. If the code element is flipped, the source lines S1 and S2 of the two rows of transistors belonging to the first combination, i.e., the first row and the second row of transistors, are connected through the coupling capacitor C. C Transient coupling is once. If the codeword of the weight bit Sel[1] in the enable code value changes from binary 0 to 1, the codeword flips.

[0144] See also Figure 5 , as mentioned above, when any combination (taking the second combination as an example) is selected, the value of the address code at this time switches to the only enable code value that can activate any combination (such as the second combination) to be valid. Assume that the enable code value is a certain value

[01010] , Sel =

[01010] , select a code element of a specified weight bit in the enable code value

[01010] . For example, the enable code value can be expressed as Sel[4] = 0, Sel[3] = 1, Sel[2] = 0, Sel[1] = 1, Sel[0] = 0, and the specified weight bit selected in the enable code value is Sel[0], the highest weight bit is Sel[4] and the lowest weight bit is Sel[0]. Then the specified weight bit selected in the enable code value is the lowest weight bit Sel[0]. The specified weight bit can of course also be the second lowest bit, the highest bit, the second highest bit, the third highest bit, etc. Here, the lowest weight bit Sel[0] is used as the specified weight bit. In the enable code value, the code element of the aforementioned specified weight bit Sel[0] is selected, for example, binary 0. If the code element is flipped, the source lines S3 and S4 of the two rows of transistors belonging to the second combination, i.e., the third and fourth rows of transistors, are connected through the coupling capacitor C. C Transient coupling once. If the codeword of the weight bit Sel[0] in the enable code value changes from binary 0 to 1, the codeword flips.

[0145] See also Figure 6When any combination is selected, the value of the address code is switched to the only enable code value that can activate the combination to be valid, and a code element of a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to the combination are transiently coupled once through the coupling capacitor. It is used to achieve charge balance between the parasitic capacitances of the source lines of the two rows of transistors belonging to the combination, so as to expand the number of columns of the storage transistor array to adapt to the columns of the table in the weight matrix of the neural network (such as adapting the number of array columns N to the number of matrix columns n).

[0146] See also Figure 7 When the first combination (the first and second rows of transistors) is selected, the value of the address code is switched to the only enable code value that can activate any combination to be effective, such as Sel =

[01001] . In the enable code value, a code element of a specified weight bit is selected, such as Sel [1]. If the code element of Sel [1] is flipped, the source lines S1 and S2 of the two rows of transistors belonging to any combination are connected through the coupling capacitor C. C Transient coupling once. Parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors belonging to any combination P1 , C P2 The number of columns in the transistor array is expanded to match the number of columns in the weight matrix of the neural network (e.g. N matches n). P1 The parasitic capacitance C P2 The parasitic capacitance value at the source line S2. The source or components of parasitic capacitance are relatively complex, such as the external capacitance of the thin and long source line itself, the source parasitic capacitance of each transistor mounted on the source line, the capacitance of the source line to the substrate, and the associated capacitance between the source line and other conductors. C As an example of a coupling capacitor, for example, a transistor with its source and drain short-circuited is used as a coupling capacitor.

[0147] See also Figure 6 , the switch TR1 is controlled by the control module CTL. The control module CTL includes, for example, a falling edge capture circuit or a rising edge capture circuit, which can also be called a falling edge detection circuit or a rising edge detection circuit, to realize capturing the code element of the specified weight bit in the enable code value, such as the code element flipping of Sel[1]. The control module CTL, for example, the so-called falling edge capture circuit or the rising edge capture circuit acts as a monostable trigger circuit (one shot), that is, when the falling edge capture circuit or the rising edge capture circuit senses the flipping of the code element Sel[1], it generates an extremely narrow pulse signal for controlling the switch TR1. That is, the code element Sel[1] of the specified weight bit is selected in the enable code value. If the code element Sel[1] flips, the source lines S1 and S2 of the two rows of transistors belonging to the first combination are connected through the coupling capacitor C CTransient coupling once. When an extremely narrow pulse signal appears, such as a high-level signal, the control switch TR1 is transiently turned on once, and the source lines S1 and S2 are connected through C C Considering that the weight is characterized by the difference in threshold voltages of a pair of complementary transistors in the same column but arranged in two rows in the storage transistor array, and the threshold voltages of complementary transistors are naturally different, it will inevitably lead to the parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors in the first combination. P1 , C P2 There are inherent differences in the amount of charge. The smaller the threshold voltage, the larger the current flowing to the source line of the corresponding transistor and the more the parasitic capacitance of the corresponding source line is charged. The larger the threshold voltage, the smaller the current flowing to the source line of the corresponding transistor and the less the parasitic capacitance of the corresponding source line is charged. The parasitic capacitor with a large amount of charge will inevitably flow its own large charge charging current to the current subtractor I_Mi, resulting in an additional hidden current in the difference between the output currents at the source lines of the two rows of transistors. An output data of the neural network is represented by the ratio of the difference in output currents at the source lines S1 and S2 of the two rows of transistors in the first combination divided by a preset coefficient. The additional hidden current means that an output data of the neural network at the first combination is deviated. However, according to this article, the parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors in the first combination P1 , C P2 The transient coupling of the two source lines will balance the charge between the parasitic capacitors with large charge, such as C P1 Transiently releases part of the electricity to another such as C P2 The charges of the parasitic capacitances of the two source lines are equalized before a group of output currents at the two source lines S1 and S2 are transmitted to the current subtractor, so as to avoid the additional current caused by the unbalanced charge of the parasitic capacitances of the two source lines introduced into the current difference IS12 of a group of output currents IS1 and IS2. The additional current means the result deviation. The parasitic capacitances C of the source lines S1 and S2 of the two rows of transistors belonging to the first combination are equalized. P1 , C P2 The charge balance is achieved between the two rows of transistors. P1 , C P2 Before the current difference calculation is performed on a set of output currents IS1 and IS2 at the source lines S1 and S2 of the two rows of transistors, there is a charge amount equalization adjustment to make the charge amount converge, thereby avoiding the additional introduction of the parasitic capacitance of the source lines S1 and S2 of the two rows of transistors, i.e., C, in the current difference IS12 of the said set of output currents IS1 and IS2 due to the difference in threshold voltage of any pair of complementary transistors in the two rows of transistors belonging to the first combination. P1 , C P2The additional current is caused by the unbalanced charge.

[0148] See also Figure 6 , optionally, when any combination is selected, the value of the address code at this time switches to the only enable code value that can activate the any combination to be valid, and a code element of a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors to which the any combination belongs are transiently coupled once through the coupling capacitor. It is used to achieve charge balance between the parasitic capacitances of the source lines of the two rows of transistors to which the any combination belongs. Before a set of output currents at the source lines of the two rows of transistors are calculated to perform a current difference, a single charge amount convergence balance adjustment is made to ensure that the charge amount of the parasitic capacitances of the source lines of the two rows of transistors is equalized, so as to avoid the additional current caused by the unbalanced charge amount of the parasitic capacitances of the source lines of the two rows of transistors introduced into the current difference of the set of output currents due to the difference in threshold voltages of any pair of complementary transistors in the two rows of transistors to which the any combination belongs. Any combination, such as including the first combination to the Mth combination.

[0149] See also Figure 7 For the first combination, connect C between source lines S1 and S2. C and TR1, and TR1 is controlled by the sub-control module C1 in the control module CTL, the sub-control module C1 includes a falling edge capture circuit or a rising edge capture circuit acting as a monostable trigger circuit SH, and also includes a latch LK. The data comparison circuit of the latch LK compares the current value of the address code with the only enable code value that can activate the first combination to be valid, such as Sel=

[01001] . If the current value of the address code, such as Sel[4:0], is equal to the enable code value, the latch LK sends an enable signal En, which notifies the monostable trigger circuit SH that it can sense the flip of the code element Sel[1]. If the flip occurs, an extremely narrow pulse signal is generated to control the switch TR1. If the current value of the address code, such as Sel[4:0], is not equal to the enable code value, the latch LK sends a disable signal Dis that is opposite to the enable signal. The disable signal locks the monostable trigger circuit SH and cannot control TR1. For example, at this time, an extremely narrow pulse signal cannot be generated to control the switch TR1. If the code element Sel[1] is flipped, the source lines S1 and S2 of the two rows of transistors belonging to the first combination are connected through the coupling capacitor C CTransient coupling once. The premise for transiently coupling the source lines of the two rows of transistors belonging to any combination, such as S1 and S2, through coupling capacitors is that the current value of the address code changes from an active code value to a non-active code value; on the contrary, if the current value of the address code changes from a non-active code value to an active code value, then the source lines S1 and S2 of the two rows of transistors belonging to any combination are not allowed to be transiently coupled through coupling capacitors under this condition. The transient coupling event of the source lines of the two rows of transistors belonging to any combination is ensured based on that the combination switches from a selected state to an unselected state at the multiplexer, rather than from an unselected state to a selected state. Otherwise, the charge balance of the two source lines loses its original intention and the transient coupling is meaningless.

[0150] See also Figure 7 For the second combination, connect C between source lines S3 and S4. C TR2 and TR2 are controlled by another sub-control module in the control module CTL, and the other sub-control module also includes a falling edge capture circuit or a rising edge capture circuit acting as a monostable trigger circuit SH, and a latch LK. The data comparison circuit of the latch LK compares the current value of the address code with the only enable code value that can activate the first combination to be valid, such as Sel=

[01010] . If the current value of the address code, such as Sel[4:0], is equal to the enable code value, the latch LK sends an enable signal En, which notifies the monostable trigger circuit SH that it can sense the flip of the code element Sel[0]. If the flip occurs, an extremely narrow pulse signal is generated to control the switch TR2. If the current value of the address code, such as Sel[4:0], is not equal to the enable code value, the latch LK sends a disable signal Dis that is opposite to the enable signal. The disable signal locks the monostable trigger circuit SH and cannot control TR1. For example, at this time, an extremely narrow pulse signal cannot be generated to control the switch TR2. If the code element Sel[0] is flipped, the source lines S3 and S4 of the two rows of transistors belonging to the second combination are connected through the coupling capacitor C CTransient coupling once. Similarly, the premise for the transient coupling of the source lines of the two rows of transistors belonging to any combination, such as S3 and S4, through the coupling capacitor is that the current value of the address code changes from the active code value to other values ​​of the non-active code value; on the contrary, if the current value of the address code changes from the non-active code value to the active code value, then the source lines S3 and S4 of the two rows of transistors belonging to any combination are not allowed to be transiently coupled through the coupling capacitor under this condition. The transient coupling event of the source lines of the two rows of transistors belonging to any combination is based on: the combination is switched from a selected state to an unselected state at the multiplexer, rather than from an unselected state to a selected state.

[0151] See also Figure 7 For the Mth combination, it is also configured to connect the source lines S2M and S(2M-1) of the two rows of transistors belonging to the Mth combination through the coupling capacitor C C The transient coupling is a switch TRM.

[0152] See also Figure 7 When the first combination is selected, the value of the address code is switched to the only enable code value that can activate the first combination, such as Sel =

[01001] . The enable code value selects a specified weight bit code element, such as Sel [1]. If the code element flips, such as from binary 0 to 1, the source lines S1 and S2 of the first row of transistors and the second row of transistors belonging to the first combination are connected through the coupling capacitor C CTransient coupling once. If the code element is flipped, the gate voltage of the two rows of transistors belonging to the first combination (i.e., the word line voltage of G1 and G2) is also synchronously pulled down to a potential lower than the potential when the neural network is running. When the neural network uses the weight matrix to perform matrix operations, if it is assumed that the word line potential of G1 and G2 is V_G1 / G2 when the neural network is running, then if the code element is flipped, the gate voltage of the two rows of transistors belonging to the first combination must be lower than V_G1 / G2. The gate voltage is pulled down by the flip event of the code element Sel[1] and can be performed using any method or circuit in the prior art that can pull down the potential. For example, a pull-down switch is set between the gates of the two rows of transistors and a potential VG lower than V_G1 / G2, and the flip event of the code element Sel[1] is captured by the falling edge capture circuit or the rising edge capture circuit as a monostable trigger circuit SH. The extremely narrow pulse signal output by the monostable trigger circuit controls the pull-down switch to be turned on briefly, during which the voltages of G1 and G2 are pulled down to VG. Therefore, if the code element is flipped, the current voltage of the gate of the two rows of transistors belonging to the first combination (note that the first combination is temporarily out of the neural network calculation due to the flip of the code element Sel[1]) is synchronously pulled down to a potential V_G1 / G2 lower than the gate potential of the first combination when participating in the neural network calculation, and the current gate voltage is pulled to VG as follows. Note that one of its important purposes is to prevent the floating gate injection charge of the first and second rows of transistors belonging to the first combination from being programmed by the instantaneous current of the transient short circuit between a pair of source lines S1 and S2 of the two rows of transistors belonging to the first combination. If the current gate voltage is not pulled down to VG but maintained at a higher level such as V_G1 / G2, the source lines S1 and S2 with higher charge in the parasitic capacitance will lose voltage due to transient short circuit and generate transient current between the source lines S1 and S2. The source line such as S2 that loses voltage and releases a large amount of charge will generate a sudden voltage difference with the gate of a row of transistors corresponding to the discharge source line such as S2, such as the word line G2, which will cause the floating gate of the row of transistors corresponding to G2 to absorb tunneling charge, which is equivalent to invisible change of the preset weight value, and the floating gate injection charge is programmed by the transient current. On the contrary, if the current gate voltage is pulled down to VG, the transient voltage difference between the gate word line G2 of the row of transistors corresponding to the source line S2 and the discharge source line S2 is compressed, which can prevent the floating gate injection charge of the first and second rows of transistors belonging to the first combination from being programmed by the transient current of the transient short circuit between a pair of source lines S1 and S2 of the two rows of transistors belonging to the first combination. Another important purpose is to reduce the current flowing into the source lines S1 and S2 of the first and second rows of transistors belonging to the first combination during the symbol flipping period, for example, during the flipping period of the symbol Sel[1].If the current gate voltage is not pulled down to VG but maintained at a higher level such as V_G1 / G2, the two rows of transistors corresponding to the word lines G1 and G2 will have a larger current flow in each of the first and second rows of transistors under the condition of a higher gate voltage V_G1 / G2, that is, the drain current has a higher current level, so this will cause a larger current to flow into the source lines S1 and S2 during the code element flipping period, and the large current on the source lines S1 and S2 will make the original intention of transiently coupling the source lines of the two rows of transistors belonging to the first combination through the coupling capacitor once during the code element flipping period. As mentioned above, the weight is characterized by the difference in threshold voltages of a corresponding pair of complementary transistors in the same column but arranged in two rows in the storage transistor array, and the threshold voltages of complementary transistors are naturally different, which will inevitably lead to the parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors in the first combination. P1 , C P2 The large current in the source line during the symbol flipping period will cause the parasitic capacitance C P1 , C P2 The difference in charge between the two rows is further amplified, which is related to the parasitic capacitance C of the source lines of the two rows of transistors in the first combination. P1 , C P2 When the code element is flipped, the current gate voltage of the two rows of transistors belonging to the first combination is pulled down to a level lower than the gate potential of the first combination when participating in the neural network calculation, reducing the current flowing from the first and second rows of transistors in the source lines S1 and S2 of the two rows of transistors belonging to the first combination during the code element flipping period, avoiding C P1 , C P2 The difference in charge is further amplified.

[0153] See also Figure 7 , in the optional example, when any combination is selected, the value of the address code at this time is switched to the only enable code value that can activate any combination to be valid, and a code element of a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to any combination are transiently coupled once through the coupling capacitor. If the code element is flipped, the current voltage of the gate of the two rows of transistors belonging to any combination is also synchronously pulled down to a gate potential lower than that of the any combination when participating in the neural network calculation. This is to avoid the floating gate injection charge of the two rows of transistors belonging to any combination being programmed by the instantaneous current of the transient short circuit between a pair of source lines of the two rows of transistors belonging to any combination. And reduce the current flowing into the pair of source lines of the two rows of transistors belonging to any combination from the two rows of transistors belonging to any combination during the code element flipping period. For the explanation part, please refer to the relevant embodiments of V_G1 / G2 and VG in the previous text.

[0154] See also Figure 4The present application also relates to an artificial intelligence integrated memory, including: a memory in the form of flash memory and having a storage transistor array for constructing a neural network. The storage transistor array is used as a carrier of the weight matrix of the neural network, and the input data of the neural network is set to be transmitted to a series of bit lines of the storage transistor array and the output data of the neural network is set to be captured from a series of source lines of the storage transistor array, so that the memory integrates an artificial intelligence computing function based on the neural network. Each weight in the weight matrix of the neural network is characterized by the difference in threshold voltages of a corresponding pair of complementary transistors in the storage transistor array that are located in the same column but arranged in two rows, respectively. The gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled to the same bit line. The original input data of the neural network is converted into an input quantity in the voltage value format and then input to the bit line of the storage transistor array. The difference in output current at each source line of each two rows of transistors in the storage transistor array is divided by the ratio of the preset coefficient K as an output data of the neural network. The artificial intelligence integrated memory includes an in-memory computing chip.

[0155] The above description and drawings provide typical embodiments of specific structures of specific embodiments, and the above invention provides existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications of the true intent and scope of the present invention.

Claims

1. A storage and calculation method based on flash memory, characterized in that: include: A flash memory-based memory is provided, which has a storage transistor array; Using a storage transistor array as a carrier of a weight matrix of a neural network, setting the input data of the neural network to be transmitted to a series of bit lines of the storage transistor array, and setting the output data of the neural network to be captured from a series of source lines of the storage transistor array, thereby realizing storage and calculation based on flash memory; In which each weight in the weight matrix of the neural network is represented by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the storage transistor array, the gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled on the same bit line.

2. The method according to claim 1, characterized in that: The raw input data of the neural network is converted into an input quantity in a voltage value format, so as to be transmitted to a series of bit lines of a storage transistor array based on the input quantity sorted into a vector; Any pair of complementary transistors receives the voltage value on the bit line of the column where they are located, so that the difference between the drain-source voltages of the any pair of complementary transistors is the same.

3. The method according to claim 1, characterized in that: An output data of the neural network is characterized by a ratio of a difference in output current at source lines of two rows of transistors corresponding to a row of weights divided by a preset coefficient, and any two transistors in the two rows of transistors located in the same column and sharing a bit line are regarded as a pair of complementary transistors; The multiple ratios provided by a series of source lines of the memory transistor array are regarded as the output quantities provided by the memory transistor array arranged into a vector.

4. The method according to claim 1, characterized in that: The method of adjusting any weight in the weight matrix includes: changing the floating gate injection charge of each pair of complementary transistors selected by the any weight, adjusting the difference in threshold voltages of the two selected complementary transistors by the relative change of the floating gate injection charge of the two selected complementary transistors, and then adjusting the size of the weight at the position of the selected pair of complementary crystals.

5. The method according to claim 1, characterized in that: A digital-to-analog converter is arranged at the bit line of the storage transistor array, and is used to convert the input data of the neural network into a voltage value that satisfies the input signal format requirement of the bit line.

6. The method according to claim 1, characterized in that: An analog-to-digital converter is arranged at the source line of the storage transistor array, and is used to convert the output signal in the form of output current at the source line into output data that meets the digital output quantity format requirement of the neural network.

7. The method according to claim 1, characterized in that: The combination of every two rows of transistors in the storage transistor array is used to define a row of weights in the weight matrix, and multiple rows of transistors in the storage transistor array provide multiple combinations accordingly; a multiplexer is used to time-switched a group of output currents at the source lines of different combinations to a current subtractor, and the current subtractor performs current difference calculation of the output currents at the source lines of the two rows of transistors corresponding to each combination.

8. The method according to claim 7, characterized in that: The address code that controls the multiplexer is used to determine whether any combination is selected; Only a group of output currents at two source lines of a selected combination is delivered to the current subtractor, and a group of output currents at two source lines of other unselected combinations are not allowed to be delivered to the current subtractor.

9. The method according to claim 7, characterized in that: The address code that controls the multiplexer is used to determine whether any combination is selected; When any combination is selected, the value of the address code is switched to the only enable code value that can activate the combination to be valid, and a code element with a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to the combination are transiently coupled once through the coupling capacitor.

10. An artificial intelligence integrated memory, characterized in that: include: Memory in the form of flash memory with arrays of memory transistors used to build implementations of neural networks; Using a memory transistor array as a carrier of a weight matrix of a neural network, setting the input data of the neural network to be transmitted to a series of bit lines of the memory transistor array, and setting the output data of the neural network to be captured from a series of source lines of the memory transistor array, so that the memory integrates an artificial intelligence computing function based on a neural network; Each weight in the weight matrix of the neural network is characterized by the difference in threshold voltages of a corresponding pair of complementary transistors in the same column but arranged in two rows in the storage transistor array, the gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled to the same bit line; Among them, the original input data of the neural network is converted into input quantities in voltage value format and then transmitted to the bit lines of the storage transistor array. The difference in output current at the source lines of each two rows of transistors in the storage transistor array divided by the ratio of a preset coefficient is used as an output data of the neural network.

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