Low-power-consumption self-adaptive variable frame rate display method

Abstract

The invention provides a low-power-consumption self-adaptive variable frame rate display method, which comprises the following steps of: during a skip frame period, stopping signal transmission at an MIPI TX end; according to the method and the device, the power consumption is effectively reduced, and automatic switching between the refresh frame and the skip frame can be realized.

Description

Technical Field

[0001] The present application relates to the field of OLED display, and in particular to the technical field of OLED multi-frame rate switching. Background Art

[0002] Currently, the OLED display field (consumer mobile phones, etc.) can achieve multi-frame rate switching. High frame rate is suitable for application scenarios with higher requirements, such as games. When the requirements are lower or there is no extreme requirement for picture smoothness, low frame rate is used.

[0003] Currently, the Android market mostly uses command mode, which means that the refresh rate can be selected through the phone settings interface, which does not provide a good user experience. In addition, for video mode, the AP switches the frame rate back and forth according to different application scenarios. Although this saves the customer's self-defined steps and improves the customer experience, it also brings the problem of increased power consumption. Summary of the invention

[0004] The present invention provides a low-power consumption adaptive variable frame rate display method, comprising the following steps:

[0005] Step 1: The AP sends a video stream to the DDIC at a first frame rate, and sends a VS signal and a HS signal to the DDIC through MIPI, which are respectively recorded as a first VS signal and a first HS signal;

[0006] Step 2: In the first frame of the first frame rate, the DDIC receives and counts the first VS signal and the first HS signal, and the DDIC self-builds a VS signal and a HS signal inside the DDIC according to the statistical results, which are recorded as a second VS signal and a second HS signal respectively;

[0007] In step 3, when the AP switches from the first frame rate to the second frame rate, the detection unit inside the DDIC detects the HS signal end of the DDIC frame by frame: within a detection cycle, if the detection unit does not detect that the DDIC receives the HS signal, the AP has switched to the second frame rate, the second VS signal and the second HS signal are skipped to form a skip frame, and the second VS signal and the second HS signal are respectively input to the VS signal end and the HS signal end of the DDIC to ensure the normal operation of the DDIC;

[0008] Step 4: During the skip frame of the second frame rate, the first HS signal, the first VS signal, the CLK signal, the DSI signal and the DA signal of the MIPI are all switched to a low power consumption mode;

[0009] The first frame rate is greater than the second frame rate.

[0010] Furthermore, step 5 is also included. When the AP switches from the second frame rate to the first frame rate, the first HS signal, the first VS signal, the CLK signal, the DSI signal and the DA signal of the MIPI restore the original frequency, and send the first HS signal and the first VS signal to the DDIC.

[0011] Furthermore, the switching of the AP from the second frame rate to the first frame rate in the step 5 also includes: when the detection unit detects that the HS signal end of the DDIC receives the HS signal within a detection cycle, the AP has switched from the second frame rate to the first frame rate, the VS signal end and the HS signal end of the DDIC respectively input the first VS signal and the first HS signal, and at the same time, the DDIC sends a TE signal to the AP, and after the AP receives the TE signal, the AP continues to send image data and control signals to the DDIC.

[0012] Furthermore, the step 4 also includes: during the skip frame of the second frame rate, the source in the pixel driving circuit maintains a single level without level switching.

[0013] Furthermore, the detection period in step 3 and step 5 is less than or equal to 1 frame duration.

[0014] Furthermore, the detection period in step 3 and step 5 is M HS signal periods, where M is a positive integer.

[0015] Furthermore, the switching of the AP from the second frame rate to the first frame rate in the step 5 also includes: within a detection cycle, when the detection unit detects that the HS signal end of the DDIC receives the HS signal, the AP switches from the second frame rate to the first frame rate, the VS signal end and the HS signal end of the DDIC respectively input the first VS signal and the first HS signal, and at the same time, the DDIC sends a panel dimming signal em to the AP, and after the AP receives the panel dimming signal em, the AP continues to send image data and control signals to the DDIC.

[0016] Furthermore, the low power consumption mode maintains a single level without performing high-low level conversion operations.

[0017] Furthermore, the single level is a high level or a low level.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] (1) The present invention can automatically switch between refresh frames and skip frames according to the display frame rate.

[0020] (2) In the skip frame, the data channel (datalane) and clock channel (CLKlane) of MIPI of the present invention are both in low power consumption mode, which effectively reduces power consumption compared with the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a schematic diagram of the working timing of frame rate switching in the prior art;

[0023] Figure 2 This is a schematic diagram of the working timing of frame rate switching in this embodiment;

[0024] Figure 3 This is a working timing diagram of adaptive variable frame rate switching in this embodiment. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] Figure 1 FIG. 2 shows a schematic diagram of the working sequence of frame rate switching in the prior art. Figure 1 As shown, the refresh screen comes from the control of the AP itself, the AP controls the frame rate, and the DDIK passively accepts it. Before and after the frame rate changes, MIPI maintains the toggle of HS, and the data lane of MIPI sends the VS package and HS package to DDIK. DDIK accepts the external sync follow external frequency. The entire process is controlled by AP. After the frame rate is reduced, the skip form is adopted. In non-refreshframe, MIPITX does not send VS to DDIC, but MIPITX (including MIPI_CK and MIPI_DA) will continue to send HS to DDIC. During this period, DDIC uses self-built VS to ensure the integrity of the frame. When the AP re-enters the refresh frame, it only needs to send VS and then send the refresh frame information. In the prior art, MIPITX has been sending HS signals regardless of whether it is a refresh frame or a skip frame, which consumes a lot of power.

[0027] In view of this, this embodiment provides a low-power adaptive variable frame rate display method, comprising the following steps:

[0028] Step 1: The AP sends a video stream to the DDIC at a first frame rate, and sends a VS signal and a HS signal to the DDIC through MIPI, which are respectively recorded as a first VS signal and a first HS signal;

[0029] Step 2: In the first frame of the first frame rate, the DDIC receives and counts the first VS signal and the first HS signal, and the DDIC self-builds a VS signal and a HS signal inside the DDIC according to the statistical results, which are recorded as a second VS signal and a second HS signal respectively;

[0030] In step 3, when the AP switches from the first frame rate to the second frame rate, the detection unit inside the DDIC performs frame-by-frame detection on the HS signal end of the DDIC: within a detection cycle, if it is not detected that the DDIC receives the HS signal, it is considered that the AP has switched to the second frame rate, the second VS signal and the second HS signal are skipped to form a skip frame, and the second VS signal and the second HS signal are respectively input to the VS signal end and the HS signal end of the DDIC to ensure the normal operation of the DDIC;

[0031] Step 4: After the AP switches to the second frame rate, during the skip frame of the second frame rate, the first HS signal, the first VS signal, the CLK signal, the DSI signal and the DA signal of the MIPI are all switched to a low power consumption mode;

[0032] The first frame rate is greater than the second frame rate.

[0033] Optionally, step 5 is also included. When the AP switches from the second frame rate to the first frame rate, the first HS signal, the first VS signal, the CLK signal, the DSI signal and the DA signal of the MIPI restore the original frequency, and send the first HS signal and the first VS signal to the DDIC.

[0034] Optionally, the switching of the AP from the second frame rate to the first frame rate in step 5 also includes: when the detection unit detects that the HS signal end of the DDIC receives the HS signal within a detection cycle, it indicates that the AP switches from the second frame rate to the first frame rate, the VS signal end and the HS signal end of the DDIC respectively input the first VS signal and the first HS signal, and at the same time, the DDIC sends a TE signal to the AP, and after the AP receives the TE signal, the AP continues to send image data and control signals to the DDIC; wherein N and K are both positive integers.

[0035] Optionally, step 4 further includes: during a skip frame of the second frame rate, the source in the pixel driving circuit maintains a single level without level switching.

[0036] Optionally, the detection period in step 3 and step 5 is less than or equal to 1 frame duration.

[0037] Optionally, the detection period in step 3 and step 5 is M HS signal periods, where M is a positive integer.

[0038] Optionally, the switching of the AP from the second frame rate to the first frame rate in step 5 also includes: within a detection cycle, when the detection unit detects that the HS signal end of the DDIC receives the HS signal, it indicates that the AP switches from the second frame rate to the first frame rate, and the VS signal end and the HS signal end of the DDIC respectively input the first VS signal and the first HS signal, and at the same time, the DDIC sends a panel dimming signal em to the AP, and after the AP receives the panel dimming signal em, the AP continues to send image data and control signals to the DDIC.

[0039] Optionally, the low power consumption mode maintains a single level without performing high-low level conversion operations.

[0040] Optionally, the single level is a high level or a low level.

[0041] The above method will now be described in detail:

[0042] Figure 2 FIG. 2 shows a schematic diagram of the working sequence of frame rate switching in this embodiment. Figure 2 As shown, during the skip frame, MIPI TX in this embodiment no longer sends the HS signal, thereby achieving the effect of reducing power consumption.

[0043] Optionally, in the skip frame, the data lane and clk lane of the mipi are switched to a low power mode (low powerstate). At this time, the mipi TX is always in the LP11 state, that is, the signal is not toggled, so compared with the background technology, the power consumption of sending the hs is saved. In addition, the ddic RX does not need to be specially processed, and the power consumption can also be effectively reduced. The power consumption that can be saved in this embodiment is shown in Table 1.

[0044] Table 1: Power saving of this embodiment

[0045]

[0046] Preferably, this embodiment can realize adaptive variable frame rate. Figure 3FIG. 2 shows a schematic diagram of the working sequence of adaptively changing frame rate in this embodiment. Figure 3 As shown, taking 120Hz refresh as an example, when AP works in the first frame, DDI first learns the external timing. Assuming that the external timing 1hs is 3.1us, after 512 lines, DDI counts the average information of hs, and then records it, and counts the total number of lines through this frame, for example, there are 2688 lines. After refreshing three frames, the mipi of the AP stops toggling. Assuming that the detect unit is 4 hs, that is, when there are 4 hs, our DDI still cannot receive high-speed information, and thinks that the AP has executed the frame rate switching operation and wants to enter 30hz. So skip-1, skip-2, skip-3, the AP no longer refreshes, no longer sends data, and mipi stops toggling. At this time, DDI switches to internal frequency, still maintains the refresh-3 picture, and performs display actions. During this period, the source does not toggle. Since the driving circuit on the display panel does not turn on the data signal, DDI does not need to send data at this time. And vs and hs use the information learned before refresh-1 to do internal skip data processing. When the AP needs to switch to 120 Hz again, it uses the TE sent by DDIC as a handshake signal, receives the TE sent by DDIC, and then outputs the transmission.

[0047] Preferably, the panel dimming signal EM is used instead of the TE signal to achieve the purpose of synchronization between DDIC and AP.

[0048] Preferably, the detection unit should not be larger than 1 frame.

[0049] It should be noted that the specific numerical values ​​in this embodiment are only examples and are not limited to these.

[0050] The "equal" or "same" or "equal" disclosed in the present invention must take into account the distribution of engineering parameters, and the error distribution is within ±30%; the definition of "parallel" of two line segments or two straight lines is that the angle between the two line segments or two straight lines is less than or equal to 45 degrees; the definition of "perpendicular" of two line segments or two straight lines is that the angle between the two line segments or two straight lines is within the range of [60, 120] degrees; the definition of "phase mismatch" also needs to take into account the distribution of engineering parameters, and the error distribution of the degree of mismatch is within ±30%. In addition, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without more constraints, an element defined by the phrase "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0051] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0052] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-power adaptive variable frame rate display method, characterized in that: The following steps are involved: Step 1: The AP sends a video stream to the DDIC at a first frame rate, and sends a VS signal and a HS signal to the DDIC through MIPI, which are respectively recorded as a first VS signal and a first HS signal; Step 2: In the first frame of the first frame rate, the DDIC receives and counts the first VS signal and the first HS signal, and the DDIC self-builds a VS signal and a HS signal inside the DDIC according to the statistical results, which are recorded as a second VS signal and a second HS signal respectively; In step 3, when the AP switches from the first frame rate to the second frame rate, the detection unit inside the DDIC detects the HS signal end of the DDIC frame by frame: within a detection cycle, if the detection unit does not detect that the DDIC receives the HS signal, the AP has switched to the second frame rate, the second VS signal and the second HS signal are skipped to form a skip frame, and the second VS signal and the second HS signal are respectively input to the VS signal end and the HS signal end of the DDIC to ensure the normal operation of the DDIC; Step 4: During the skip frame of the second frame rate, the first HS signal, the first VS signal, the CLK signal, the DSI signal and the DA signal of the MIPI are all switched to a low power consumption mode; The first frame rate is greater than the second frame rate.

2. The display method according to claim 1, characterized in that: Also included is step 5, when the AP switches from the second frame rate to the first frame rate, the first HS signal, the first VS signal, the CLK signal, the DSI signal and the DA signal of the MIPI restore the original frequency, and send the first HS signal and the first VS signal to the DDIC.

3. The display method according to claim 2, characterized in that: The switching of the AP from the second frame rate to the first frame rate in the step 5 also includes: when the detection unit detects that the HS signal end of the DDIC receives the HS signal within a detection cycle, the AP has switched from the second frame rate to the first frame rate, the VS signal end and the HS signal end of the DDIC respectively input the first VS signal and the first HS signal, and at the same time, the DDIC sends a TE signal to the AP, and after the AP receives the TE signal, the AP continues to send image data and control signals to the DDIC.

4. The display method according to claim 1, characterized in that: The step 4 further includes: during the skip frame of the second frame rate, the source in the pixel driving circuit maintains a single level without level switching.

5. The display method according to claim 3, characterized in that: The detection period in step 3 and step 5 is less than or equal to 1 frame duration.

6. The display method according to claim 3, characterized in that: The detection period in step 3 and step 5 is M HS signal periods, where M is a positive integer.

7. The display method according to claim 1, characterized in that: The switching of the AP from the second frame rate to the first frame rate in the step 5 also includes: within a detection cycle, when the detection unit detects that the HS signal end of the DDIC receives the HS signal, the AP switches from the second frame rate to the first frame rate, the VS signal end and the HS signal end of the DDIC respectively input the first VS signal and the first HS signal, and at the same time, the DDIC sends a panel dimming signal em to the AP, and after the AP receives the panel dimming signal em, the AP continues to send image data and control signals to the DDIC.

8. The display method according to claim 1, wherein the low power consumption mode maintains a single level without performing a high-low level conversion operation.

9. The display method according to any one of claims 4 or 8, characterized in that: The single level is a high level or a low level.

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