Method and circuit for effective window extension of read data for DDR

Abstract

The invention discloses an effective window extension method and circuit for data reading of a DDR (Double Data Rate), and relates to the technical field of information storage. The effective window extension method comprises the steps that a dfi signal used for receiving read data is acquired, the dfi signal is configured according to lead code and lead code configuration information of DDR read operation, and an initial lead enable signal and an initial read data enable signal are obtained; performing cross-clock domain conversion and bit width conversion on the initial preamble enable signal, and performing cross-clock domain conversion and bit width conversion on the read data enable signal to obtain a target preamble enable signal and a target read data enable signal in a DDR clock domain; and combining the two signals in the DDR clock domain to obtain an effective window for reading data. According to the method and the device, the technical problems that in the prior art, the rising edge of the effective window is too close to the first read data, the ddl does not have enough time to move the rising edge of the read gating signal DQS to the middle of the data signal DQ, so that error codes are easily caused, and the effective window of the read data is deviated due to dqs jitter can be solved.

Description

Technical Field

[0001] The present application relates to the field of information storage technology, and in particular to an effective window extension method and circuit for reading data of DDR. Background Art

[0002] Memory is an important storage component in the field of information storage. It is a bridge between external memory and CPU. At present, the mainstream memory specification is DDR, which is the abbreviation of double data rate synchronous dynamic random access memory. Its advantages are large storage capacity, low cost and mature interface, and it can achieve extremely high access rate during parallel burst access.

[0003] Since the DDR bus is a parallel high-speed bus and its data signal DQ is a bidirectional signal, the DDR physical interface needs to be trained when acquiring read data to obtain the effective window dqs_gate_en for the read data. The effective window can solve the interference of signal integrity and the problem that the actual delay of the read data is larger than the theoretical value due to the delay introduced by wiring and process. In theory, the effective window is the time from the start of RL memory frequencies to the end of RL+BL / 2 memory frequencies after the physical interface of DDR issues a read command. Due to the layout and routing deviation of the actual circuit, RL may be amplified. In order to solve the problem of RL being amplified, it is necessary to train the DDR in the read direction to obtain a reasonable delay value, so as to find the actual effective window for reading data. Similarly, since the DDR physical interface is a set of parallel high-speed interfaces, its read direction data signal DQ and read selection signal DQS also need to be phase-aligned with the help of ddl to obtain the best eye diagram.

[0004] like Figure 1 As shown, when the read data arrives, the DDR physical interface will set the valid window dqs_gate_en to prepare for receiving the read data, and delay through the buffer and ddl ( Figure 1 The delay_ctrl module in the DQS_D ...

[0005] As DDR rates continue to increase, especially now that the maximum rate of DDR5 has reached 6400MT / s, the impact of this factor is becoming more and more obvious.

[0006] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0007] The main purpose of the present application is to provide a method and circuit for extending the effective window of DDR read data, aiming to solve the technical problem that in the prior art solution, the phase alignment operation starts when the effective window dqs_gate_en is set. If the rising edge of the effective window dqs_date_en is too close to the first read data, ddl may not have enough time to move the rising edge of the read select signal DQS to the middle of the data signal DQ, which may easily cause bit errors, and the dqs jitter causes the effective window of the read data to shift.

[0008] In view of the above technical shortcomings, the main purpose of the present invention is to provide an effective window extension method for reading data of DDR, comprising:

[0009] Obtain a dfi signal for receiving read data, insert a preamble and a postamble into the dfi signal according to the preamble and postamble configuration information of the DDR read operation, and obtain an initial preamble enable signal and an initial read data enable signal;

[0010] Performing cross-clock domain conversion and bit width conversion on the initial leading enable signal, and performing cross-clock domain conversion and bit width conversion on the initial read data enable signal, to obtain a target leading enable signal and a target read data enable signal in the DDR clock domain;

[0011] The target leading enable signal and the target read data enable signal in the DDR clock domain are combined to obtain a valid window for reading data.

[0012] To achieve the above object, the present application also provides an effective window extension circuit for reading data of DDR, comprising:

[0013] A signal conversion module is used to obtain a dfi signal for receiving read data, insert a preamble and a postamble into the dfi signal according to the preamble and postamble configuration information pre-stored in the DDR read operation, and obtain an initial preamble enable signal and an initial read data enable signal;

[0014] A cross-clock domain conversion module is used to perform cross-clock domain conversion and bit width conversion on the initial leading enable signal, and to perform cross-clock domain conversion and bit width conversion on the initial read data enable signal, so as to obtain a target leading enable signal and a target read data enable signal under the DDR clock domain respectively;

[0015] The effective window combination module is used to combine the target leading enable signal and the target read data enable signal in the DDR clock domain to obtain the effective window for reading data.

[0016] One or more technical solutions proposed in this application have at least the following technical effects:

[0017] First, a DFI signal for receiving read data is obtained, and the DFI signal contains a receive trigger command for the read data. After receiving the DFI signal, the preamble and postamble are respectively inserted into the DFI signal according to the preamble and postamble configuration information pre-stored in the DDR read operation, and an initial preamble enable signal and an initial read data enable signal are obtained. Among them, the initial preamble enable signal is used to prompt that the signal is coming soon, so that the time period can be increased, thereby expanding the effective window. Then, the initial preamble enable signal and the initial read data enable signal are respectively converted across clock domains and bit widths to obtain the target preamble enable signal and the target read data enable signal in the DDR clock domain. By performing cross-clock domain conversion on the above-mentioned initial preamble enable signal and the initial read data enable signal, the two signals can be made to work in the DDR clock domain, thereby processing the DQS signal and the DQ signal sent by the DDR, so as to align the rising edge of the DQS signal and the phase of the middle of the DQ signal in the time period of the preamble enable signal. Finally, the target leading enable signal and the target read data enable signal under the DDR clock domain are combined to obtain the effective window of the read data. Because the effective window of the read data includes the target read data enable signal and the target leading enable signal, the dqs signal can start working in the time period of the target leading enable signal, so that the DQS rising edge and the DQ are aligned in the middle phase before the data arrives, so that the digital delay line DDL has sufficient time to initialize. In addition, since the left side of the obtained effective window contains the target leading enable signal, and the right side is determined by the optimal rising edge of dqs, the edge of the effective window is increased, which can more effectively deal with the situation of dqs drift and reduce the problem of the effective window offset of the read data caused by dqs jitter. In summary, through the above technical solution, it is possible to solve the technical problem that the digital delay line ddl may not have enough time to move the rising edge of the read selection signal DQS to the middle of the data signal DQ when the rising edge of the effective window is too close to the first read data in the prior art, which is easy to cause bit errors, and the DQS jitter causes the effective window offset of the read data. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] Figure 1 A schematic diagram of a DDR data reading circuit provided by the prior art;

[0021] Figure 2 A flowchart of a method for extending an effective window for reading data in DDR provided in an embodiment of the present application;

[0022] Figure 3 For this application Figure 2 A schematic flow chart of a method for configuring a leading enable signal and a read data enable signal provided by the illustrated embodiment;

[0023] Figure 4 For this application Figure 2 The illustrated embodiment provides a flow chart of a method for converting a preamble enable signal and a read data enable signal across clock domains;

[0024] Figure 5 For this application Figure 2 A schematic flow chart of a method for generating a valid window for reading data provided by the illustrated embodiment;

[0025] Figure 6 This application Figure 2 A flowchart of a method for processing a dqs signal using an effective window provided by the illustrated embodiment;

[0026] Figure 7 This application Figure 2 A schematic flow chart of a method for generating read data provided by the illustrated embodiment;

[0027] Figure 8 This application Figure 7 A schematic flow chart of a method for reading written data provided by the illustrated embodiment;

[0028] Fig. 9 It is a structural schematic diagram of a first effective window extension circuit for reading data of DDR provided in an embodiment of the present application;

[0029] Fig.10 It is a structural schematic diagram of a second effective window extension circuit for reading data of DDR provided in an embodiment of the present application;

[0030] Figure 11-a to Figure 11-h yes Fig.10 A signal format diagram provided by the illustrated embodiment;

[0031] Fig.12 This is a signal format diagram for receiving read data using DDR5 4tck preamble and 1.5tck postamble, provided in an embodiment of the present application.

[0032] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0033] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0034] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0035] The technical problems existing in the prior art are as follows:

[0036] like Figure 1 As shown in the figure, when the read data arrives, the DDR physical interface (within the set digital delay line ddl) will set the valid window dqs_gate_en to prepare for receiving the read data. And align the valid window dqs_gate_en of the read data through the buffer and the ddl relay. However, the digital delay line ddl is limited by process factors, and it takes a certain amount of preparation time to complete the phase alignment between the rising edge of the read selection signal DQS and the middle of the data signal DQ. Since the phase alignment starts when the valid window dqs_gate_en is set, if the rising edge of dqs_gate_en is too close to the first read data, it may cause bit errors because ddl does not have enough time to move the rising edge of DQS to the middle of DQ. In particular, with the continuous increase in DDR rates, especially now that the maximum rate of DDR5 has reached 6400MT / s, the impact of this factor is becoming more and more obvious.

[0037] In order to solve the above technical problems, the present application provides a solution by adding the time period of the leading enable signal to the valid window, thereby expanding the valid window and enabling the digital delay line DDL to enter the working state in advance. The present application uses the time period containing valid data and the leading enable signal preamble sent by DDR5 as the effective window at the high-frequency end of the read data, so that the dqs signal starts working in the preamble stage, so as to align the phase of the DQS rising edge and the middle of the DQ before the data arrives, so that the digital delay line can have sufficient time to initialize. Since the left side of the effective window contains the leading enable signal preamble and the right side is determined by the last rising edge of the dqs signal, the edge margin of the effective window is also increased, which can more effectively deal with the situation of dqs drift.

[0038] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device that can realize the above functions, a computer-readable storage medium, etc.

[0039] In order to better understand the above technical solution, the exemplary embodiments of the present application will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments shown here. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0040] To achieve the above technical objectives, see Figure 2 , Figure 2 The present invention provides a flow chart of an effective window extension method for reading data of DDR. Figure 2 As shown, the effective window extension method for reading data of DDR includes:

[0041] S110: Obtain a DFI signal for receiving read data, insert a preamble code and a postamble code into the DFI signal according to pre-stored preamble code and postamble code configuration information, and obtain an initial preamble enable signal and an initial read data enable signal.

[0042] The DFI signal is initiated by the DDR controller and transmitted to the DDR PHY (physical interface). The DFI signal is used to initiate commands, and the commands need to be converted by the DDR PHY before being sent to the DDR. The DFI signal is designed in this application to receive data after the read command is initiated. In addition, the preamble configuration information and postamble configuration information about the DDR read data are stored in the register. After receiving the DFI signal, the preamble and postamble configuration information of the DDR read data are called from the register to configure the DFI signal, thereby obtaining the initial preamble enable signal and the initial read data enable signal. Among them, the preamble enable signal, that is, Fig.10 The Preamble_en signal in the , as the leading signal of the subsequent valid window, has a certain time period, which is used to prompt that the data read operation is about to be performed, so that the dqs signal can start working at the stage of the leading enable signal, so that the rising edge of dqs and the phase in the middle of the dq signal are aligned before the data arrives. The read data enable signal is used to enable the relevant modules to start reading data.

[0043] Specifically, as a preferred embodiment, Figure 3As shown, in the above-mentioned effective window extension method for reading data, step S110: inserting a preamble and a postamble into the DFI signal according to the pre-stored preamble and postamble configuration information to obtain an initial preamble enable signal and an initial read data enable signal, includes:

[0044] S111: Perform bit width conversion on the dfi signal to obtain a dfi signal in a dfi clock domain.

[0045] Normally, the DFI signal sent by the DDR controller works in the DDR controller clock domain. The DDR controller clock domain is 1 / 4 memory clock, and dfi_clk is 1 / 2 memory clock (memory clock). Therefore, it is necessary to first perform a 2:1 bit width conversion on the DFI signal (full name: dfi_rddata_en signal) to convert it to the dfi_clk clock domain to obtain the DFI signal in the DFI clock domain. The purpose of converting the bit width to 1 / 2 memory clock is to comply with the protocol to achieve the purpose of converting the low-frequency clock to the high-frequency clock. The purpose of expanding the memory clock here is to keep it consistent with ddr_clk. In addition, the DDR controller is used to control the DDR module. This application Fig.10 In the DDR PHY control circuit, all modules except the DQ module and the DQS module are part of the DDR PHY control circuit.

[0046] S112: Obtain the preamble configuration information from the register, and use the preamble configuration information to perform a 1-addition operation on the DFI signal to obtain an initial preamble enable signal.

[0047] Here, the setting of trddata_en is needed to perform a pipeline operation on the register of the dfi signal. In DDR5, its related parameters are specified by the DFI 5.1Specification and the DDR5 SDRAM JEDEC STANDARD respectively. Since this solution needs to consider the preamble, it is necessary to perform a 1-fill operation in the register beat operation according to the preamble configuration information, thereby obtaining the initial preamble enable signal. Among them, the preamble configuration information is obtained through the register, so it needs to be configured in the register in advance. For example, in DDR5, the register is configured according to the provisions of the DR5 SDRAM JEDEC STANDARD.

[0048] S113: Obtain the post-lead configuration information from the register, and use the post-lead configuration information to perform a 0 insertion operation on the dfi signal to obtain an initial read data enable signal.

[0049] Specifically, the embodiment of the present application can convert the bit width of the dfi signal, and then delay it by tdelay memoryclocks and insert the postamble according to the configuration of the postamble to obtain it, and specifically, it can be obtained by inserting a 0 value.

[0050] In summary, the technical solution provided by the embodiment of the present application is that the DFI signal sent by the DDR controller to the DDR physical interface works in the DDR controller clock domain (1 / 4 memory clock), and the DFI_CLK domain works in the 1 / 2 memory clock. Therefore, it is necessary to convert the DFI signal into a 2:1 bit width and insert the valid bits of the preamble to obtain the DFI signal. Fig.10 Similarly, for the initial read data enable signal, the post-amble configuration information is obtained from the register. Specifically, the dfi signal is converted into a bit width, and then the post-amble is inserted into the post-amble according to the post-amble configuration information after tdelay memory clocks are performed.

[0051] Figure 2 The effective window extension method for reading data provided by the illustrated embodiment further includes the following steps after obtaining the leading enable signal and the read data enable signal:

[0052] S120: performing cross-clock domain conversion and bit width conversion on the initial leading enable signal, and performing cross-clock domain conversion and bit width conversion on the initial read data enable signal, to obtain a target leading enable signal and a target read data enable signal in the DDR clock domain respectively.

[0053] After getting the initial leading enable signal and the initial read data enable signal, the above signals are first delayed to get the theoretical window value of the read data; then the cross-clock domain conversion and bit width conversion are performed, because the initial leading enable signal and the initial read data enable signal are both under dfi_clk, in order to adapt to the relevant operations of DDR, it is necessary to convert to ddr_clk domain (2*memory clock). The bit width conversion requires a 4:1 conversion. Because ddr is a double-rate synchronous dynamic random access memory, the data rate is twice the clock. At the same time, this is also stipulated by the DFI Specification.

[0054] Specifically, as a preferred embodiment, Figure 4As shown, in the above-mentioned effective window extension method for reading data, step S120: performing cross-clock domain conversion and bit width conversion on the initial leading enable signal, and performing cross-clock domain conversion and bit width conversion on the initial read data enable signal to obtain the target leading enable signal and the target read data enable signal in the DDR clock domain, includes:

[0055] S121: Delaying the initial leading enable signal and the initial read data enable signal by an integer multiple of UI respectively, to obtain a theoretical window size for reading data.

[0056] The embodiment of the present application uses register beats to delay the initial leading enable signal and the initial read data enable signal by an integer multiple of UI, thereby obtaining a theoretical window for reading data. The theoretical effective window starts from RL memory clocks after the ddr phy issues a read command and ends at RL+BL / 2 memory clocks. The present application also needs to add a leading enable signal.

[0057] The reason for the integer multiple delay of UI here is that when using DDR memory, the clock cycle of data reading or writing is an integer multiple of the refresh rate or update rate of the UI interface. Doing so can minimize the waiting time when reading data and ensure the consistency and synchronization of data. Specifically, the memory timing settings can be adjusted to keep it consistent with the UI update frequency. For example: the UI refreshes every 16.67ms (i.e., a refresh rate of 60Hz), then the clock cycle of the memory should be set to be able to divide this value.

[0058] S122: Use the FIFO queue to perform cross-clock domain conversion and bit width conversion on the initial leading enable signal in the dfi clock domain to obtain the target leading enable signal in the ddr clock domain.

[0059] Specifically, the embodiment of the present application uses a 4-bit write and 1-bit read input and output queue to complete the CDC of the P leading enable signal reamble_en from the dfi_clk to the ddr_clk (2*memory clock) clock domain, and performs a 4:1 bit width conversion. Because ddr is a double rate synchronous dynamic random access memory, the data rate is twice the clock, so a 4-fold bit width conversion is required here. It should be noted that the dfi_clk signal is input from the outside, and the ddr_clk signal is generated by the pll inside the queue.

[0060] as well as,

[0061] S123: Use the FIFO queue to perform cross-clock domain conversion and bit width conversion on the initial read data enable signal in the dfi clock domain to obtain the target read data enable signal in the dqs_t clock domain.

[0062] The dqs_t clock domain is one of the above DDR clock domains. ddr is a double rate synchronous dynamic random access memory, and dqs is a single rate. Therefore, the dqs_t clock domain is 1 / 2 of ddr_clk. Therefore, this application uses a 2-bit write and 1-bit read FIFO to perform a CDC of the read data enable signal from dfi_clk to dqs_t domain. Correspondingly, only a 2:1 bit width conversion is required here.

[0063] Figure 2 The effective window extension method for reading data provided by the illustrated embodiment further includes the following steps after respectively obtaining the target leading enable signal and the target read data enable signal in the DDR clock domain:

[0064] S130: Combine the target leading enable signal and the target read data enable signal in the DDR clock domain to obtain a valid window for reading data. Fig. 9 and Fig.10 In the embodiment shown, the present application uses a trigger to obtain a valid window for reading data, which includes the time period corresponding to the leading enable signal and the read data enable signal.

[0065] Specifically, as a preferred embodiment, Figure 5 As shown, in the above-mentioned method for extending the effective window of reading data, step S130: combining the target preamble enable signal and the target read data enable signal in the DDR clock domain to obtain the effective window of reading data includes:

[0066] S131: Use a digital delay line to delay the target leading enable signal, wherein the delay value comes from the part of the training value that is less than 1UI.

[0067] The theoretical valid window is from the time when the read command is issued from the DDR physical interface, starting from RL memory clocks (memory clocks) to RL+BL / 2 memory clocks. Due to the layout and routing of the actual circuit, RL may be enlarged. To solve the above problems, the embodiment of the present application uses a digital delay line DDL and a register for training to obtain a reasonable delay value, i.e., a training value, to find the actual data valid window. Therefore, the present application uses a digital delay line to delay the above target leading enable signal, and the delay value comes from the part of the training value that is less than 1UI.

[0068] S132: Input the delayed leading enable signal to the set terminal of the trigger, input the read data enable signal to the data terminal of the trigger, and use the trigger to output the valid window of the read data.

[0069] The technical solution provided in the embodiment of the present application uses the preamble enable signal as the set end of the trigger SR, that is, the S end, and the read data enable signal as the data end of the trigger SR, that is, the D end, to generate a valid window dqs_gate_en for read data, thereby widening the valid window for read data from valid data to preamble+valid data.

[0070] Combination Fig.10 It can be seen from the illustrated embodiment that after the leading enable signal is delayed, it is input into the trigger SR built into the dqs_gate module together with the read data enable signal after cross-clock domain and bit width conversion, so that a valid window for read data can be generated. The valid window can extend from the width of the valid data of the cause to the leading enable signal + valid data.

[0071] The technical solution provided by the embodiment of the present application first obtains a DFI signal for receiving read data, and the DFI signal is used to receive the read data and contains a receive trigger command for the read data. After receiving the DFI signal, the preamble and postamble are respectively inserted into the DFI signal according to the pre-stored preamble configuration information, and an initial preamble enable signal and an initial read data enable signal are obtained. Among them, the preamble enable signal is used to prompt that the signal is coming soon, so that the time period can be increased, thereby expanding the effective window. Then, the preamble enable signal and the read data enable signal are respectively converted across clock domains and bit widths to obtain the target preamble enable signal and the target read data enable signal under the DDR clock domain. By converting the above-mentioned preamble enable signal and the read data enable signal across clock domains, the two signals can be made to work under the DDR clock domain, thereby processing the DQS signal and the DQ signal sent by the DDR, and aligning the rising edge of the DQS signal and the phase in the middle of the DQ signal. Finally, the preamble enable signal and the read data enable signal under the DDR clock domain are combined to obtain the effective window for reading data. Because the valid window of the read data includes the read data enable signal and the leading enable signal, the dqs signal can start working in the time period of the leading enable signal, so that the rising edge of DQS and the middle phase of DQ are aligned before the data arrives, so that DDL has sufficient time to initialize. In addition, since the left side of the obtained valid window contains the leading enable signal, and the right side is determined by the optimal rising edge of dqs, the edge of the valid window is increased, which can more effectively deal with the situation of dqs drift. In summary, through the above technical solution, it is possible to solve the problem that if the rising edge of the valid window is too close to the first read data, the digital delay line ddl may not have enough time to move the rising edge of the read selection signal DQS to the middle of the data signal DQ, which is easy to cause bit errors, and the technical problem of the offset of the valid window of read data caused by DQS jitter.

[0072] After obtaining the effective window for reading data, it is necessary to use the effective window to process the DDR dqs signal and dq signal. The effective window can solve the interference of signal integrity and the problem that the actual delay of reading data is larger than the theoretical value due to the delay introduced by wiring and process.

[0073] In addition, as a preferred embodiment, Figure 6 As shown, in the above-mentioned method for extending the effective window of reading data, after step S130: combining the target preamble enable signal and the target read data enable signal in the DDR clock domain to obtain the effective window of reading data, the method further includes:

[0074] S141: Receive a dqs signal from DDR and use the valid window as a clock gate signal of the dqs signal.

[0075] The valid window includes the time period of the target leading enable signal and the target read data enable signal. This time period is in the DDR clock domain, so after receiving the dqs signal from the DDR, the valid window can be used as the clock gate clockgate signal of the dqs signal. It should be noted that the dqs signal here includes dqs_t and dqs_c signals. After the application uses the clock gate signal to gate the dqs_t and dqs_c signals, it is also necessary to delay the above signals. The specific delay value comes from the part where the training value is less than 1UI. The purpose of the delay here is also to solve the problem that RL may be amplified due to the layout and routing of the above-mentioned actual circuit.

[0076] S142: Starting from the rising edge of the target leading enable signal in the clock gate signal, align the rising edge of the dqs signal with the phase in the middle of the dq signal.

[0077] Because the digital delay line DDL is limited by process reasons, it needs a certain amount of preparation time to complete the phase alignment between the rising edge of the dqs signal (i.e. the above-mentioned read enable signal DQS) and the middle of the dq signal (i.e. the above-mentioned data signal DQ). The traditional operation starts when the valid window dqs_gate_en is set, so if the rising edge of the dqs_gate_en in the valid window is too close to the first read data, it may cause bit errors because DDL does not have time to move dqs to the middle of DQ. To solve this problem, the present application adds a target leading enable signal in the valid window, so that starting from the rising edge of the target leading enable signal, the operation of aligning the rising edge of the dqs signal with the phase in the middle of the dq signal can be performed. In theory, the dq signal and the dqs signal sent by DDR are aligned, so to perform phase alignment, you only need to shift the dqs signal right 90 degrees.

[0078] S143: When the rising edge of the dqs signal is aligned with the phase in the middle of the dq signal, delay processing is performed on the dqs signal, wherein the delay value comes from the part of the training value that is less than 1UI.

[0079] Considering the RL amplification problem caused by wiring, the embodiment of the present application introduces a delay to the dqs signal, so that the signal is moved left and right through the delay, so as to ensure that the rising edge of the dqs signal is aligned with the phase in the middle of the dq signal.

[0080] In addition, as a preferred embodiment, Figure 7 As shown, the effective window extension method for reading data further includes, after the step of delaying the dqs signal:

[0081] S144: Obtain a dq signal from the DDR, and use the dq signal to generate write data.

[0082] Combination Fig.10 From the structure shown, it can be seen that the dq signal is obtained from DDR, and the dq data is stored for one beat and then sent to rx_data_fifo as the write data of rx_data_fifo.

[0083] S145: Perform a delayed inversion operation on the dqs signal to obtain a dqs clock signal for writing data.

[0084] The dqs signal after the valid window processing, including the dqs_t signal and the dqs_c signal, will be used as the dq clock signal. After the dqs signal is inverted and sent to the above rx_data_fifo, it can be used as the clock signal for writing data.

[0085] S146: Perform cross-clock domain conversion on the dqs clock signal to obtain write data corresponding to the dfi clock signal. The dq signal is a data signal, which contains data to be read. When reading the dq signal, the present application needs to perform cross-clock domain conversion on the dqs clock signal corresponding to the write data generated by the dq signal, thereby returning to obtain the dfi clock signal. In this way, the above-mentioned dfi clock can be used to read data.

[0086] The specific cross-clock domain conversion is the CDC and bit width conversion (1:2) from dqs clock to dfi_clk. For the rx_data_fifo queue, the write depth is 32 and the write width is 2; the read depth is 16 and the read width is 4.

[0087] S147: Read the write data according to the dfi clock signal to obtain the read data.

[0088] The technical solution provided by the embodiment of the present application obtains a dq signal from the DDR, then uses the dq signal to generate write data, delays and inverts the aforementioned dqs signal, and uses the dqs clock signal of the write data generated by the dq signal as the dqs clock signal. The dq signal obtained from the ddq can be used to generate write data, and then the dqs signal is delayed and inverted to generate a dqs clock signal for the write data. Then, the dqs clock signal is cross-clock converted to obtain the dfi clock signal of the write data. In this way, the write data is read out using the dfi clock signal, and the read data in the dfi clock domain can be obtained, which is then sent to the DDR physical interface for processing and external transmission.

[0089] Specifically, as a preferred embodiment, Figure 8 As shown, in the above-mentioned effective window extension method for reading data, step S147: reading the write data according to the dfi clock signal to obtain the read data step includes:

[0090] S1471: Obtain a read direction pointer according to the dfi signal.

[0091] The read direction pointer Read pointer is generated after delaying the dfi signal to be consistent with the dfi clock domain. After the read direction pointer is generated, it can be obtained through register configuration in debug mode.

[0092] S1472: Use the read direction pointer to trigger the counter to count the input dqs clock signal, remove the number of rising edges of the leading code from the count value, and obtain the write direction pointer.

[0093] After the read direction pointer is delayed by the dfi signal, it can be used as the enable signal of the counter, and the value of the counter is sent to the FIFO after the data in the FIFO is stable. In the write direction, since the dqs clock used to write data contains the preamble part, this is because the valid window contains the preamble part, and the valid window processes the dqs as the clock of the dqs signal. The processed dqs signal is used as the dqs clock for writing data, so the dqs signal contains the preamble part. At this time, the preamble part needs to be removed. Specifically, count according to the input dqs clock first, and then subtract the number of rising edges in the preamble from the count value according to the preamble configuration information. The specific preamble configuration information can be obtained by looking up the table in the register configuration. The write direction pointer can be obtained by subtracting the number of rising edges of the preamble from the counter count value.

[0094] S1473: According to the dqs clock signal, use the write direction pointer to write the write data into the FIFO queue.

[0095] The write direction pointer can indicate the specific location of the write. When the data is written, the write direction pointer will move forward accordingly to point to the next data location to be written. In this way, the data can be written into the FIFO queue in sequence according to the dqs clock signal. The functions of the write direction pointer include tracking the progress of data writing, ensuring that the data is written in order, and repositioning to a specific write location when necessary.

[0096] S1474: Read write data from the FIFO queue according to the dfi clock signal to obtain read data.

[0097] After obtaining the dfi clock signal, because the write data in the FIFO queue is also under the dfi clock domain, the dfi clock signal can be used to read the write data from the FIFO queue and obtain the above-mentioned read data.

[0098] The present application delays the dfi signal to obtain a delayed signal, which is trained to be consistent with the length of the read data, so that the read data can be aligned through the delayed signal to determine whether the FIFO queue is valid. Among them, the pointer of the read direction can be configured through a register in debug mode.

[0099] In summary, the technical solution provided by the embodiment of the present application processes the dqs signal by using the valid window as the clock gate signal of the dqs signal, and then aligns the rising edge of the dqs signal and the phase in the middle of the dq signal starting from the rising edge of the leading enable signal, thereby ensuring the alignment of the two signals. Then, the dq signal is obtained from the DDR, the dq signal is used to generate write data, and the dqs signal is delayed and inverted to obtain the dqs clock signal of the write data, and then the dqs clock signal is converted across the clock domain to obtain the write data under the dfi clock domain, and finally the write data is read out to obtain the read data. In the above manner, the clock gate signal of dqs can cover the leading code and the read data, so that the DDL can be stabilized before data acquisition, reducing the bit error rate of data reception. In addition, since the clock gate signal of dqs covers the leading code and the read data, the left and right margins of the valid window are increased. By removing the preamble and retaining only valid data, a pointer signal in the write direction is generated to control the writing of the fifo, which can achieve the purpose of retaining only valid data, reduce the depth of the fifo, and thus simplify the design of the read and write queues.

[0100] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the effective window extension method for reading data of DDR used in the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0101] To achieve the above purpose, the present application also provides an effective window extension circuit for DDR read data. The screen projection safety control method of the digital signage device in the above embodiment can solve the problem that when the rising edge of the effective window is too close to the first read data, the digital delay line may not have enough time to move the rising edge of the read selection signal DQS to the middle of the data signal DQ, which is easy to cause bit errors, and the problem of effective window offset of read data caused by dqs signal jitter. Compared with the prior art, the beneficial effects of the device provided by the present application are the same as the beneficial effects of the screen projection safety control method provided in the above embodiment, and the other technical features in the device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0102] Specifically, see Fig. 9 , Fig. 9 This is a schematic diagram of the structure of the first effective window extension circuit for reading data of DDR provided in the embodiment of the present application. Fig. 9 As shown, the effective window extension circuit includes:

[0103] The signal conversion module 110 is used to obtain a DFI signal for receiving read data, configure a preamble and a postamble for the DFI signal according to pre-stored preamble and postamble configuration information, and obtain an initial preamble enable signal and an initial read data enable signal.

[0104] like Fig. 9 As shown, as a preferred embodiment, the signal conversion module 110 includes:

[0105] The bit width conversion submodule 111 is used to perform bit width conversion on the DFI signal to obtain the DFI signal in the DFI clock domain;

[0106] The preamble configuration submodule 112 is used to obtain the preamble configuration information from the register, and use the preamble configuration information to perform a 1-addition operation on the DFI signal to obtain an initial preamble enable signal; and

[0107] The read data configuration submodule 113 is used to obtain the post-lead code configuration information from the register, and use the post-lead code configuration information to perform a zero insertion operation on the DFI signal to obtain an initial read data enable signal.

[0108] In the technical solution provided by the embodiment of the present application, since the DFI signal generated by the DDR controller to the DDR physical interface works under the DDR controller clock domain, which is 1 / 4 memory clock, it is necessary to first perform a 2:1 bit width conversion on the DFI signal and convert it into the dfi_clk domain. The dfi_clk is 1 / 2 memory clock, and then the valid bits of the leading signal preamble are inserted to obtain the DFI signal carrying the leading period. The specific implementation principle is to perform a pipeline operation on dfi_rddata_en with the help of trddata_en. The pipeline operation here is the operation of beating the signal. Among them, the value of trddata_en is less than DDR readlatency (RL) to reduce the problem of RL being amplified due to wiring and other reasons.

[0109] Since this solution needs to consider the preamble signal, it is necessary to perform a 1-fill operation during the pipeline operation according to the configuration of the preamble stored in the register, thereby obtaining the initial preamble enable signal preamble_en. In addition, the initial read data enable signal rd_en is obtained by converting the dfi signal into a bit width, performing a memory clock delay of tdelay, and inserting the postamble code postamble (inserting a value of 0) according to the postamble configuration information. Among them, in DDR5, postamble needs to configure the register according to the DDR5 SDRAM JEDEC STANDARD, and then transfer the register to the required circuit.

[0110] in addition, Fig. 9 The effective window extension circuit for DDR read data shown also includes: a cross-clock domain conversion module 120, which is used to perform cross-clock domain conversion and bit width conversion on the initial leading enable signal, and to perform cross-clock domain conversion and bit width conversion on the initial read data enable signal, so as to obtain the target leading enable signal and target read data enable signal under the DDR clock domain respectively.

[0111] Specifically, as a preferred embodiment, the cross-clock domain conversion module 120 specifically includes:

[0112] The first delay submodule 121 is used to delay the initial leading enable signal by an integer multiple of UI;

[0113] The second delay submodule 122 is used to delay the initial data read enable signal by an integer multiple of UI;

[0114] The leading enable signal conversion queue 123 is used to perform cross-clock domain conversion and bit width conversion on the initial leading enable signal in the DFI clock domain to obtain the target leading enable signal in the DDR clock domain;

[0115] The third delay submodule 124 is used to delay the target leading enable signal in the DDR clock domain using a digital delay line, wherein the delay value comes from the part of the training value that is less than 1UI;

[0116] The read data enable signal conversion queue 125 is used to perform cross-clock domain conversion and bit width conversion on the initial read data enable signal in the dfi clock domain to obtain the target read data enable signal in the dqs_t clock domain.

[0117] The technical solution provided by the embodiment of the present application, because the valid window of read data is used for DDR, before the leading enable signal and the read data enable signal are applied to obtain the valid window, the leading enable signal and the read data enable signal need to be converted to the DDR clock domain. Specifically, the ddr clock domain and the dqs_t clock domain are both DDR clock domains, so that the leading enable signal and the read data enable signal can be used to process the dqs signal accordingly. In addition, it is also necessary to use a digital delay line to delay the leading enable signal under the ddr clock domain, and the delay value comes from the part where the training value is less than 1UI, so that due to the layout and routing of the actual circuit, the number of memory clocks passed may be amplified. To solve the above problem, the embodiment of the present application uses a digital delay line DDL and a register to do training to obtain a reasonable delay value, that is, the above training value, to find the actual data valid window, and the delay here is also to match the training value.

[0118] In addition, if Fig. 9 As shown, Fig. 9 The effective window extension circuit for reading data of DDR shown also includes:

[0119] The effective window combination module 130 is used to combine the target leading enable signal and the target read data enable signal in the DDR clock domain to obtain the effective window for reading data. Specifically, the effective window combination module 130 is specifically used to input the delayed leading enable signal to the S terminal of the trigger and input the read data enable signal to the D terminal of the trigger to obtain the effective window for reading data.

[0120] Combination Fig. 9As shown, the present application uses the preamble enable signal preamble_en as the S end of the trigger SR, and uses the read data enable signal as the D end of the SR to generate the valid window dqs_gate_en for the read data, so that the valid window for the read data read data can be widened from the original valid data to preamble + valid data. In this way, the dqs signal can start working in the preamble time period, so that the rising edge of the dqs can be aligned with the middle phase of the dq signal before the data arrives, so that the digital delay line DDL can have sufficient time to initialize.

[0121] In addition, as a preferred embodiment, Fig. 9 As shown, the effective window extension circuit for reading data further includes a dqs module 140, and the dqs module 140 includes:

[0122] The signal receiving submodule 141 is used to receive the dqs signal from the DDR using the digital delay line and use the valid window as the clock gate signal of the dqs signal;

[0123] The phase alignment submodule 142 is used to align the rising edge of the dqs signal with the phase in the middle of the dq signal starting from the rising edge of the target leading enable signal of the clock gate signal;

[0124] The delay processing submodule 143 is used to perform delay processing on the dqs signal when the rising edge of the dqs signal is aligned with the phase in the middle of the dq signal, wherein the delay value comes from the part of the training value that is less than 1UI.

[0125] Combination Fig. 9 It can be seen from the structure shown that the technical solution provided by the embodiment of the present application, the present invention uses the time period containing valid data and leading enable signal sent by DDR as the effective window of the high-frequency end of the data read and write queue. The preamble signal is used to prompt the chip data to arrive, so that the dqs signal can start working in the preamble stage, so that the phase of the DQS rising edge and the middle of the DQ can be aligned before the data arrives, so that the digital delay line DDL has sufficient time to initialize. Since the left side of the effective window contains the leading enable signal preamble, the right side is determined by the last rising edge of dqs, the clock used by dqs is the dqs clock, and the dqs clock is generated using the effective window, so when dqs is offset left and right, the effective window will also be cheap, so the edge margin of the dqs gate signal is also increased, so that the situation of dqs drift drift can be more effectively dealt with. Among them, the left and right sides of the effective window respectively indicate that the valid data is coming and the valid data is about to end.

[0126] In addition, as a preferred embodiment, Fig. 9 As shown, the effective window extension circuit for reading data further includes a dq module 150 and a data read / write queue 160; wherein the dq module is used to generate write data using a dq signal obtained from a DDR, and to perform a delayed inversion operation on a delayed dqs signal as a dqs clock signal for writing data;

[0127] The data read and write queue 160 is used to convert the dqs clock signal across clock domains to obtain write data corresponding to the dfi clock signal, and is also used to read the write data according to the dfi clock signal to obtain read data.

[0128] like Fig. 9 As shown, as a preferred embodiment, the effective window extension circuit for reading data further includes:

[0129] The read direction pointer generating module 170 is used to obtain a read direction pointer according to the dfi signal.

[0130] The data read and write queue 160 is specifically used to use the read direction pointer to trigger the counter to count the input dqs clock, remove the number of rising edges of the leading code from the count value, obtain the write direction pointer, and use the write direction pointer to write the write data to the FIFO queue according to the dqs clock signal, and read the write data from the FIFO queue according to the dfi clock signal to obtain the read data.

[0131] The technical solution provided by the embodiment of the present application is that the data read and write queue 160 can convert the dqs clock signal across clock domains to obtain the write data corresponding to the dfi clock signal, and then read the data out after the data in the data read and write queue is stable according to the dfi clock signal. In this way, data without preambles are obtained by processing the read and write pointers of the queue inside the data read and write queue. It not only solves the problem that the original solution DDL cannot align the intermediate phases of dqs and dq in time, but also can effectively remove the data of the preamble and postamble, while increasing the margin of the effective window.

[0132] In addition, to achieve the above purpose, see Fig.10 , Fig.10 This is a schematic diagram of the structure of a second effective window extension circuit for reading data of DDR provided in an embodiment of the present application. Fig.10 As shown, the circuit includes:

[0133] dfi2ddr module, delay module, preamble_en_fifo module, rd_en_fifo module, ddl_preamble_en module, dqs_gate module, dqs module, dq module, wr_ptr module, rd_ptr module and rx_data_fifo module. Among them,

[0134] See also Fig.10 , the specific implementation of the above modules is as follows:

[0135] (1) dfi2ddr module

[0136] Because the DDR controller generates a DFI signal to the DDR PHY, that is, Fig.10 The dfi_rddata_en signal in the dfi2ddr module is used to notify the ddr to initiate the command to receive data. This signal works in the ddr controller clock domain, which is 1 / 4 memory clock. Therefore, in the dfi2ddr module, the dfi_rddata_e signal is first converted to the dfi_clk domain (1 / 2 memory clock) with a bit width (2:1), and the valid bits of the signal preamble are inserted. The purpose of converting the bit width to 1 / 2 memory clock is to comply with the protocol and achieve the purpose of converting the low-frequency clock to the high-frequency clock.

[0137] Regarding the effective bit of the preamble, the specific implementation principle is to use the setting of trddata_en (less than DDR read latency (RL)) to perform pipeline operation on dfi_rddata_en, which is a register beat operation.

[0138] Since this solution needs to consider preamble, it is necessary to perform 1-adding operation during pipeline operation according to the configuration of preamble, thereby obtaining the preamble_en signal. Here, the configuration of preamble can be obtained in the register.

[0139] The rd_en signal is obtained by converting the bit width of dfi_rddata_en, using the delay module to perform tdelay memory clock delay, and inserting postamble (inserting 0 value) according to the configuration of the postamble. The postamble can also be pre-configured in the register.

[0140] (2)delay

[0141] The dfi2ddr module outputs the Preamble_en signal and the rd_en signal to the delay device, and then the two delay modules use registers to beat, respectively delaying the preamble_en and rd_en by an integer multiple of UI to obtain the theoretical window for reading data. After the delay, the two enable signals have a certain time period, thus obtaining the size of the theoretical window value.

[0142] The delay of the UI integer multiple here means that when using DDR memory, the clock cycle of data reading or writing is kept in an integer multiple relationship with the refresh rate or update rate of the UI interface. Doing so can minimize the waiting time when reading data and ensure the consistency and synchronization of data. The solution usually involves adjusting the memory timing settings to keep it consistent with the UI update frequency. For example, if the UI refreshes every 16.67ms (that is, a refresh rate of 60Hz), the memory clock cycle should be set to be able to divide this value.

[0143] (3)preamble_en_fifo

[0144] The preamble_en_fifo is an input and output queue that uses 4-bit write and 1-bit read. It can complete the cross-clock domain conversion CDC of the preamble_en signal from dfi_clk to ddr_clk (2*memory clock) domain, and perform a 4:1 bit width conversion. Because ddr is a double-rate synchronous dynamic random access memory, the data rate is twice the clock, so a 4:1 bit width conversion is required.

[0145] The dfi_clk signal of the preamble_en_fifo module is input from the outside, and the ddr_clk signal is generated by the pll inside the queue. Its output pin rd_dat still outputs the preamlbe_en signal under the ddr_clk clock domain.

[0146] (4)rd_en_fifo

[0147] The rd_en_fifo module uses a 2-bit write and 1-bit read fifo to complete the cross-clock domain cdc of the read data enable signal rd_en from dfi_clk to dqs_t domain, and performs a 2:1 bit width conversion. The dqs_t clock domain is a type of DDR clock domain, and its clock frequency is 1 / 2 of the above ddr_clk clock frequency.

[0148] (5)ddl_preamble_en

[0149] The ddl_preamble_en module can complete the delay of the preamble enable signal preamble_en through the digital delay line ddl. The delay value comes from the part of the training value that is less than 1 ui. This is to solve the wiring delay. The delay value is obtained by the non-integer UI value of the training value training part.

[0150] (6)dqs_gate

[0151] The Dqs_gate module uses the preamble enable signal preamble_en as the set end of its internal trigger SR, that is, the S end, and the read data enable signal rd_en as the data end of SR, that is, the D end, to generate the valid window dqs_gate_en of the read data, and widen the valid window of the read data from the valid data to the preamble + valid data.

[0152] Here, the dqs_gate module receives the preamble enable signal preamble_en, and then outputs the rd_en_fifo_clk clock signal to the rd_en_fifo module, and outputs the read data enable signal rd_en to dqs_gate from the wr_dat pin of the rd_en_fifo module. The D end of the dqs_gate module receives the rd_en signal, and the S end receives the preamble_en signal, thereby generating a valid window dqs_gate_en for readdata.

[0153] (7)ddl_dqs

[0154] The ddl_dqs module inputs the dqs_t and dqs_c signals from the rxdqs module, and uses the valid signal dqs_gate_en signal input from the above dqs_gate module as the clock gate signal of dqs_t and dqs_c. The main function of the clock gate signal here is because the IO of DDR is a bidirectional IO, and only one direction can be transmitted at the same time. Because this part of the circuit will no longer work after the reading is completed. Finally, the dqs_t and dqs_c signals processed by the gate are delayed. The delay value comes from the part where the training value is less than 1ui.

[0155] (8)rx_dqs

[0156] The output of this module serves as the IO of the ddl_dqs module, and its output dqs_t and dqs_c signals come from DDR.

[0157] (9)dq

[0158] The dqs_t and dqs_c signals processed by ddl_dqs are sent to the dq module as clock signals (clk_t and clk_c). The dq module delays and inverts these two signals and sends them to the rx_data_fifo module as the clock signals for write data - rx_clk_t_del and rx_clk_c_del. Here, the dq data is stored for one beat and then sent to the rx_data_fifo as write data, where the dq data comes from DDR.

[0159] The dq data here is the data sent by the data_odd and enen_data pins in the dq module, which is specifically sent to the ddr phy through the ddr by the IO pin of the DDRphy.

[0160] (10)rx_data_fifo

[0161] The rx_data_fifo module is used for CDC and bit width conversion of dq data from dqs clock to dfi_clk; the bit width conversion ratio is 1:2. The write depth of this FIFO is 32, the write width is 2; the read depth is 16, and the read width is 4. The read direction fifo pointer is generated by rd_fifo_en in the dfi_clk domain, and this signal is generated by the dfi_rddata_en signal.

[0162] (11)wr_ptr

[0163] In the write direction, since the clock used to write data contains the preamble part, wr_ptr first counts according to the input clock, and then according to the preamble configuration, the counter value is subtracted from the number of rising edges of dqspreamble (this value is obtained from the lookup table by the register configuration) to obtain the write direction pointers wr_ptr0 and wr_ptr1.

[0164] (12)rd_ptr

[0165] The read direction pointer Read pointer is used as the enable signal of counter after the dfi_rddata_en signal is delayed, where the rx_fifo_rd_en signal is. After the rx_data_fifo data is stable, the value of counter is sent to rx_data_fifo; at the same time, after rx_fifo_rd_en is aligned with the rx_data_fifo read data, it is output as the valid judgment signal dfi_rddata_valid. Indicates whether the read data rd_data[3:2] and rd_data[1:0] are valid. The pointer of the read direction can be configured through registers in debug mode.

[0166] about Fig.10 The effective window extension circuit for reading data of DDR provided in the embodiment shown in the figure has an output signal such as Figure 11-a to Figure 11-h shown.

[0167] First, the preamble enable signal preamble_en is pulled up first, and the read data enable signal rd_en is pulled up afterwards. According to the preamble enable signal preamble_en, the read data enable signal rd_en, the dqs signal dqs_t and dqs_c, the valid window gate signal of dqs is obtained. After being processed by the dqs_gate module, the valid window containing the preamble enable signal preamble and valid data can be obtained. In this way, the time period of the preamble enable signal is used as a delay buffer, and the digital delay line ddl can be started and kept stable before the valid data arrives, thereby aligning the rising edge of dqs and the middle phase of dq, ensuring the correctness of the data.

[0168] In addition Fig.12 Take the read data receiving process of DDR5 4tck preamble and 1.5tck postamble provided in the illustrated embodiment as an example: while generating preamble_en and rd_en, the rd_ptr module will generate the read direction pointer of rx_data_fifo according to the state of dfi_rddata_en. After the rx_data_fifo data is stable, the data can be read out. In this way, by processing the fifo read and write pointers inside rx_data_fifo, data without preamble can be obtained. This not only solves the problem that the original solution DDL cannot align the intermediate phases of dqs and dq in time, but also can effectively remove the preamble and postamble data, and at the same time increase the margin of dqs_gate.

[0169] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes also be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs a specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0170] The modules involved in the embodiments of the present application can be implemented by software or hardware, wherein the name of the module does not limit the unit itself in some cases.

[0171] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for extending an effective window for reading data of DDR, characterized in that: include: Acquire a dfi signal for receiving read data, configure the dfi signal according to the preamble and postamble configuration information of the DDR read operation, and obtain an initial preamble enable signal and an initial read data enable signal; Performing cross-clock domain conversion and bit width conversion on the initial leading enable signal, and performing cross-clock domain conversion and bit width conversion on the initial read data enable signal, to obtain a target leading enable signal and a target read data enable signal in the DDR clock domain respectively; The target leading enable signal and the target read data enable signal in the DDR clock domain are combined to obtain a valid window for reading data.

2. The method according to claim 1, characterized in that The step of configuring the dfi signal according to the preamble and postamble configuration information of the DDR read operation to obtain an initial preamble enable signal and an initial read data enable signal comprises: Performing bit width conversion on the DFI signal to obtain a DFI signal in a DFI clock domain; Obtaining preamble configuration information from a register, and using the preamble configuration information to perform a 1-addition operation on the dfi signal to obtain the initial preamble enable signal; The post-lead code configuration information is obtained from the register, and the post-lead code configuration information is used to perform an insert 0 operation on the dfi signal to obtain the initial read data enable signal.

3. The method according to claim 2, characterized in that The step of performing cross-clock domain conversion and bit width conversion on the initial leading enable signal, and performing cross-clock domain conversion and bit width conversion on the initial read data enable signal to obtain a target leading enable signal and a target read data enable signal in the DDR clock domain includes: Delaying the initial leading enable signal and the initial read data enable signal by an integer multiple of UI respectively, to obtain a theoretical window size for reading data; Using the FIFO queue to perform cross-clock domain conversion and bit width conversion on the initial leading enable signal in the dfi clock domain to obtain a target leading enable signal in the ddr clock domain; and The initial read data enable signal in the dfi clock domain is converted across clock domains and bit widths using a FIFO queue to obtain a target read data enable signal in the dqs_t clock domain.

4. The method according to claim 1, characterized in that The step of combining the target leading enable signal and the target read data enable signal in the DDR clock domain to obtain a valid window for reading data includes: Delaying the target leading enable signal using a digital delay line, wherein the delay value comes from a portion of the training value that is less than 1UI; The delayed target leading enable signal is input to the set end of the trigger, the target read data enable signal is input to the data end of the trigger, and the trigger is used to output the valid window of the read data.

5. The method according to claim 1 or 4, characterized in that After the step of combining the target leading enable signal and the target read data enable signal in the DDR clock domain to obtain a valid window for reading data, the method further includes: Receive a dqs signal from DDR, and use the valid window as a clock gate signal of the dqs signal; Starting from the rising edge of the target leading enable signal in the clock gate signal, align the rising edge of the dqs signal with the phase in the middle of the dq signal; When the rising edge of the dqs signal is aligned with the phase in the middle of the dq signal, the dqs signal is delayed, wherein the delay value comes from the part of the training value that is less than 1UI.

6. The method according to claim 5, characterized in that After the step of delaying the dqs signal when the rising edge of the dqs signal is aligned with the phase in the middle of the dq signal, the method further comprises: Obtain a dq signal from the DDR, and use the dq signal to generate write data; Performing a delayed inversion operation on the dqs signal to obtain a dqs clock signal for writing data; Performing cross-clock domain conversion on the dqs clock signal to obtain write data corresponding to the dfi clock signal; The write data is read out according to the dfi clock signal to obtain the read data.

7. The method according to claim 6, characterized in that The step of reading the write data according to the DFI clock signal to obtain the read data comprises: According to the dfi signal, a read direction pointer is obtained; Using the read direction pointer to trigger a counter to count the input dqs clock signal, removing the number of rising edges of the leading code from the count value to obtain a write direction pointer; According to the dqs clock signal, using the write direction pointer to write the write data into the FIFO queue; The write data is read from the FIFO queue according to the dfi clock signal to obtain the read data.

8. An effective window extension circuit for reading data of DDR, characterized in that: include: A signal conversion module, used to obtain a dfi signal for receiving read data, configure the dfi signal according to the preamble and postamble configuration information of the DDR read operation, and obtain an initial preamble enable signal and an initial read data enable signal; A cross-clock domain conversion module, used for performing cross-clock domain conversion and bit width conversion on the initial leading enable signal, and performing cross-clock domain conversion and bit width conversion on the initial read data enable signal, to obtain a target leading enable signal and a target read data enable signal in the DDR clock domain respectively; The effective window combination module is used to combine the target leading enable signal and the target read data enable signal in the DDR clock domain to obtain the effective window for reading data.

9. The circuit according to claim 8, characterized in that The signal conversion module comprises: A bit width conversion submodule, used to perform bit width conversion on the DFI signal to obtain a DFI signal in a DFI clock domain; a preamble configuration submodule, configured to obtain preamble configuration information from a register, and use the preamble configuration information to perform a 1-addition operation on the DFI signal to obtain the initial preamble enable signal; and The read data configuration submodule is used to obtain the post-lead code configuration information from the register, and use the post-lead code configuration information to perform an insert 0 operation on the dfi signal to obtain the initial read data enable signal.

10. The circuit according to claim 9, characterized in that The cross-clock domain conversion module includes: A first delay submodule, used for delaying the initial leading enable signal by an integer multiple of UI; A second delay submodule, used for delaying the initial data read enable signal by an integer multiple of UI; A leading enable signal conversion queue, used to perform cross-clock domain conversion and bit width conversion on the initial leading enable signal in the DFI clock domain to obtain a target leading enable signal in the DDR clock domain; A third delay submodule is used to delay the target leading enable signal under the DDR clock domain using a digital delay line, wherein the delay value comes from the part of the training value that is less than 1UI; The read data enable signal conversion queue is used to perform cross-clock domain conversion and bit width conversion on the initial read data enable signal in the dfi clock domain to obtain the target read data enable signal in the dqs_t clock domain; The effective window combination module is specifically used to input the delayed target leading enable signal to the set end of the trigger, and input the target read data enable signal to the data end of the trigger to obtain the effective window of the read data.

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