Test structure and test method for phase change memory

Abstract

The embodiment of the present application discloses a test structure and a test method of a phase change memory. The test structure comprises a multi-layer stack structure. Each layer of the stack structure comprises an array region and a redundancy region; wherein the redundancy region surrounds part of the array region. The multi-layer stack structure is misaligned and stacked along a first direction. The projections of the array regions of each layer of the stack structure along the first direction coincide with each other.

Description

Test structure and test method for phase change memory Technical Field

[0001] This application relates to the field of integrated circuits, specifically to a test structure and test method for phase-change memory. Background Technology

[0002] 3D PCM (three-dimensional phase change memory) is a memory with a three-dimensional structure formed based on stacking technology; in this memory, the storage cells are made of phase change materials, and the difference in conductivity exhibited by the phase change materials when they transform between crystalline and amorphous states is used to store data.

[0003] In the process of 3D PCM process development, it is necessary to design corresponding test keys (test structures) for testing (such as WAT or bench tests) to monitor the process and electrical properties, or to study the intrinsic characteristics of the memory (such as threshold voltage Vt).

[0004] However, as the number and density of stacks in 3D PCM increase, the area occupied by a complete test structure also gradually increases. For example, in TSK design, directly designing and placing a complete multi-layer stack structure occupies a large area, thus affecting wafer space utilization and overall array efficiency. Therefore, the test structure of 3D PCM needs further optimization to improve wafer space utilization and overall array efficiency. Summary of the Invention

[0005] In view of this, embodiments of this application provide a test structure and test method for phase change memory, which can improve the space utilization of the wafer and the overall array area efficiency.

[0006] The technical solution of this application embodiment is implemented as follows:

[0007] This application provides a test structure for a phase-change memory, including: a multi-layer stacked structure staggered along a first direction; each layer of the stacked structure includes: an array region and a redundant region; wherein the redundant region surrounds a portion of the array region; the projections of the array regions of each layer of the stacked structure along the first direction coincide with each other.

[0008] In some embodiments of this application, the projection of the array region along the first direction is a rectangle; the projection of the redundant region along the first direction is an L-shape surrounding the two adjacent sides of the rectangle.

[0009] In some embodiments of this application, the projections of two adjacent stacked structures along the first direction are rotated by 90° or 180°.

[0010] In some embodiments of this application, each layer of the stacked structure includes: a bit line layer and a word line layer; the bit line layer and the word line layer are respectively located on opposite sides of each layer of the stacked structure along the first direction; wherein, the bit line layer includes: a plurality of bit line regions; the word line layer includes: a plurality of word line regions; the plurality of word line regions all extend along a second direction, and adjacent word line regions are staggered; the plurality of bit line regions all extend along a third direction, and adjacent bit line regions are staggered; each word line region is provided with a plurality of word lines extending along the second direction; each bit line region is provided with a plurality of bit lines extending along the third direction; wherein, the second direction and the third direction intersect; the second direction and the third direction are both perpendicular to the first direction.

[0011] In some embodiments of this application, at least a portion of each bit line region and at least a portion of each word line region belong to the redundant region.

[0012] In some embodiments of this application, the two bit lines located in two adjacent stacked layers are connected in parallel; or, the two word lines located in two adjacent stacked layers are connected in parallel.

[0013] In some embodiments of this application, the two bit lines or two word lines connected in parallel are in contact with each other along the first direction.

[0014] This application embodiment also provides a testing method for phase-change memory, used to test the test structure described in the above scheme; the testing method includes: dividing the array area of ​​the test structure into multiple test regions; selecting several target test regions with different resistance values ​​in the multiple test regions; and selecting at least one target bit line and one target word line in each target test region for testing to obtain the test results of the target device.

[0015] In some embodiments of this application, the step of selecting at least one target bit line and at least one target word line for testing to obtain the test results of the target device includes: applying a constant voltage to the target bit line; applying an incremental voltage pulse to the target word line and testing the current on the target bit line; and determining the threshold voltage of the target device based on the current on the target bit line.

[0016] In some embodiments of this application, selecting several target test areas with different resistance values ​​includes: selecting the test area located at the corner of the array area as the target test area.

[0017] It is understood that in this embodiment, the test structure is constructed using a staggered stacking method; this ensures the size of the array area while reducing the overall size of the test structure. Furthermore, since the test structure is typically located in the dicing channels on the wafer, reducing the size of the test structure can reduce the area ratio of the dicing channels on the wafer; thereby, it can increase the area ratio of the chip on the wafer, that is, improve the wafer space utilization and the overall array area efficiency. Attached Figure Description

[0018] Figure 1A is a schematic diagram of the test structure of the phase change memory provided in an embodiment of this application;

[0019] Figure 1B is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0020] Figure 1C is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0021] Figure 2 is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0022] Figure 3A is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0023] Figure 3B is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0024] Figure 3C is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0025] Figure 3D is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0026] Figure 4 is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0027] Figure 5A is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0028] Figure 5B is a schematic diagram of the test structure of the phase-change memory provided in the embodiment of this application;

[0029] Figure 6 is a schematic diagram of the implementation flow of the testing method for phase change memory provided in the embodiment of this application;

[0030] Figure 7 is a schematic diagram of the implementation flow of the phase change memory testing method provided in the embodiments of this application;

[0031] Figure 8 is a schematic diagram illustrating the effect of the testing method for phase-change memory provided in the embodiments of this application;

[0032] Figure 9 is a schematic diagram of the effect of the test method for phase change memory provided in the embodiment of this application. Detailed Implementation

[0033] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0035] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items. For the unit “root,” “strip,” or “piece” of a transmission line, all have the same meaning.

[0039] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0040] Figures 1A, 1B, and 1C are schematic diagrams of optional test structures for phase-change memory in embodiments of this application. Figure 1A is a top view, Figure 1B is a side view, and Figure 1C is a three-dimensional perspective view.

[0041] Referring to Figures 1A, 1B, and 1C, the test structure of the phase-change memory includes a multi-layer stacked structure S1 to S4. Each stacked structure includes an array region and a redundancy region. The array region is the area shown by the dashed box in Figures 1A and 1C; the redundancy region is the area outside the array region in each stacked structure.

[0042] In this embodiment, referring again to Figures 1A, 1B, and 1C, the multilayer stacked structures S1 to S4 are staggered along the first direction Z; simultaneously, the projections of the array regions of each stacked structure along the first direction Z coincide with each other. That is, the projections of the multilayer stacked structures S1 to S4 along the first direction Z do not completely coincide; only the projections of the stacked multilayer array regions along the first direction Z coincide with each other. Therefore, the stacked multilayer array regions can form a testing area to measure the performance of the phase-change memory.

[0043] In this embodiment of the application, referring to Figures 1A and 1C, in each stacked structure, a redundant region surrounds a portion of the array region, thereby protecting the array region. For example, in processes such as cutting in integrated circuit manufacturing, the redundant region can protect the array region from cutting damage, thus ensuring that testing can proceed smoothly.

[0044] It is understood that this application proposes a test structure for phase-change memory, which is optimized by using a staggered stacking method to construct the test structure. This ensures the size of the array area while reducing the overall size of the test structure. Compared to existing test structures, in this application embodiment, the length and width of the test structure can be reduced from 500-600µm to 100-300µm.

[0045] Furthermore, since test structures are typically located on dicing channels or independent special test areas on the wafer, reducing the size of the test structure can reduce the area ratio of the dicing channels or special test areas on the wafer; thereby, it can increase the area ratio of the chip on the wafer, that is, improve the wafer's space utilization and the overall array area efficiency.

[0046] In some embodiments of this application, referring to Figures 1A and 1C, the projection of each stacked structure along the first direction Z is rectangular. Specifically, the projection of the array region along the first direction Z is rectangular; the projection of the redundant region along the first direction Z is an L-shape surrounding the two adjacent sides of the rectangle.

[0047] It should be noted that in Figures 1A and 1C, due to occlusion, only the array area of ​​the topmost stacked structure S4 is shown; correspondingly, the array areas of stacked structures S1 to S3 are located directly below the array area of ​​stacked structure S4 and are occluded and not shown.

[0048] Understandably, each layer of the stacked structure is divided into rectangular array areas and L-shaped redundant areas, with the redundant areas surrounding a portion of the array area. In this way, in a multi-layered stacked structure using staggered stacking, the area occupied by the projection of all redundant areas can be minimized, thereby reducing the overall size of the test structure as much as possible while maintaining the size of the array area.

[0049] In some embodiments of this application, referring to FIG1C, the projections of two adjacent stacked structures along the first direction Z are rotated by 90° or 180°. For example, taking the center point of the projection of the array regions of stacked structures S1 to S4 as the rotation center, the projection of stacked structure S1 can be rotated 90° clockwise to obtain the projection of stacked structure S2, the projection of stacked structure S2 can be rotated 180° clockwise to obtain the projection of stacked structure S3, and the projection of stacked structure S3 can be rotated 90° counterclockwise to obtain the projection of stacked structure S4.

[0050] Understandably, in each layer of the stacked structure, a redundant area surrounds part of the array area. Therefore, when constructing a multi-layer stacked structure, adjacent layers are rotated at a certain angle. This ensures the stability of the staggered multi-layer stacked structure, preventing collapse. Furthermore, a redundant area is formed around the array area of ​​the multi-layer stacked structure, providing sufficient protection and ensuring successful testing.

[0051] In some embodiments of this application, each stacked structure includes a bit line layer and a word line layer. The bit line layer and the word line layer are located on opposite sides of each stacked structure along a first direction.

[0052] Figure 2 illustrates the bit line BL, word line WL, and phase-change memory (PCM) in each stacked structure. Referring to Figure 2, in the PCM, the bit line BL and word line WL are located in two layers (bit line layer and word line layer), respectively. Furthermore, the bit line BL and word line WL extend in two directions; the PCM is positioned at the intersection of the bit line BL and word line WL. By changing the voltage of the bit line BL and word line WL, the phase change material of the PCM can be switched between a crystalline and amorphous state, thereby storing data "1" or "0".

[0053] In some embodiments of this application, the bit line layer includes a plurality of bit line regions; the word line layer includes a plurality of word line regions.

[0054] Figures 3A, 3B, 3C, and 3D illustrate the stacked structures S1 to S4, respectively. The following explanation uses Figure 3A as an example; Figures 3B, 3C, and 3D can be understood by referring to Figure 3A.

[0055] Referring to Figure 3A, multiple word line regions extend along the second direction X, and adjacent word line regions are staggered; multiple bit line regions extend along the third direction Y, and adjacent bit line regions are staggered. The second direction X and the third direction Y intersect; and both the second direction X and the third direction Y are perpendicular to the first direction Z.

[0056] Furthermore, in each word line region, multiple word lines WL extending along the second direction X are provided; in each bit line region, multiple bit lines BL extending along the third direction Y are provided. It should be noted that, in Figure 3A, each word line region is provided with two word lines WL for example, and each bit line region is provided with two bit lines BL for example, which is not a limitation of this application.

[0057] It is understandable that adjacent word line regions and adjacent bit line regions are staggered. This ensures, on the one hand, that sufficient memory arrays are formed within the array area; on the other hand, contact structures can be formed in the gaps of the staggered arrangement. Thus, while maintaining the performance of the test structure, the overall size of the test structure is minimized as much as possible.

[0058] In some embodiments of this application, referring to FIG3A, at least a portion of each bit line region and at least a portion of each word line region are redundant regions. That is, at least a portion of each bit line region and each word line region is located outside the array region. In this way, the portion of the region located outside the array region can form a contact structure, thereby ensuring the electrical connection between word lines and bit lines located in different stacked structures.

[0059] The stacked structures S1 to S4 in Figures 3A, 3B, 3C and 3D are stacked in a staggered manner along the first direction Z, and the resulting structure is shown in Figure 4.

[0060] Referring to Figure 4, the projections of the array regions of each stacked structure along the first direction Z coincide. A redundant region is formed around the array regions of the multi-layer stacked structure.

[0061] In some embodiments of this application, the bit line regions of two adjacent stacked structures are close to each other, and two bit lines located in the two adjacent stacked structures are connected in parallel. Alternatively, the word line regions of two adjacent stacked structures are close to each other, and two word lines located in the two adjacent stacked structures are connected in parallel. The two bit lines or two word lines connected in parallel will have the same voltage and transmit the same electrical signal.

[0062] In some embodiments of this application, two bit lines connected in parallel are in contact with each other along a first direction Z. Two word lines connected in parallel are in contact with each other along a first direction Z.

[0063] Referring to Figure 5A, word lines WL1 and WL2 are located in two adjacent stacked structures, and word lines WL1 and WL2 are in contact with each other, thus being connected in parallel.

[0064] Accordingly, referring to Figure 5B, bit lines BL1 and BL2 are located in two adjacent stacked structures, and bit lines BL1 and BL2 are in contact with each other, thus being connected in parallel.

[0065] Figure 6 is an optional flowchart of a testing method for a phase-change memory provided in an embodiment of this application. This testing method can be used to test the test structure of the aforementioned embodiment. As shown in Figure 6, the testing method includes steps S101 to S103, which will be described in conjunction with each step.

[0066] S101. Divide the array area of ​​the test structure into multiple test areas.

[0067] In this embodiment of the application, referring to FIG8, the array region of the test structure is divided into multiple test areas, each test area being marked with a resistance value. The resistance value can be obtained by measuring the resistance of the bit lines or word lines.

[0068] S102. Select several target test areas with different resistance values ​​from among the multiple test areas.

[0069] In this embodiment, several target test areas with different resistance values ​​can be selected from the divided test areas. For example, 3 to 8 target test areas can be selected for testing. Referring to Figure 8, the 5 test areas circled in dashed lines are selected as target test areas.

[0070] S103. In each target test area, select at least one target bit line and at least one target word line for testing to obtain the test results of the target device.

[0071] In this embodiment of the application, after selecting several target test areas, each target test area can be tested. Testing can be performed via leads (including bit lines and word lines) or via pads (solder pads).

[0072] As shown in Figure 9, in each target test area, two target WL (word lines) and two target BL (bit lines) were selected for testing. Therefore, there are four target devices at the intersection of the two target WL and two target BL. Furthermore, if five target test areas are selected, then for each test layer, the test results for 20 target devices can be obtained.

[0073] It should be noted that for multi-layer stacked structures, when testing one layer, the remaining layers can be used as dummy layers. The dummy layers do not affect the test results. For example, when testing stacked structure S1, stacked structures S2 through S4 can be used as dummy layers, and so on.

[0074] In some embodiments of this application, step S103 shown in FIG6 can be implemented by steps S201 to S203 shown in FIG7, and will be described in conjunction with each step.

[0075] S201. Apply a constant voltage to the target bit line.

[0076] S202. Apply an increasing voltage pulse to the target word line and test the current on the target bit line.

[0077] S203. Determine the threshold voltage of the target device based on the current on the target bit line.

[0078] In this embodiment, different target WL / target BL can be selected to test each target device sequentially. For each target device, a constant voltage (e.g., -2 to -3V) can be applied to the target BL; then, an incremental voltage pulse is applied to the target WL, for example, a starting voltage of 0V, a termination voltage of 4 to 5V, an increment step of 0.1V, and a current limit of 1e-4 to 1.5e-4A; simultaneously, the current on the target BL is measured. If an increment of one voltage pulse on the target WL results in a 10-fold increase in the current on the corresponding target BL, and this increase is greater than 1e-5, then the voltage before the increment can be determined to be the threshold voltage Vt.

[0079] It should be noted that after the threshold voltage Vt_Forming is tested, the phase-change memory device will be set to the Set state, and the threshold voltage Vt_Set can be tested using the same method as steps S201 to S203.

[0080] It should also be noted that applying a reset voltage pulse can operate the phase-change memory device to the Reset state. To ensure that different devices can be fully placed into the Reset state, pulses of 8-9V and 50-60ns can be applied several times (e.g., five times). Then, the threshold voltage Vt_Reset can be tested using the same method as steps S201-S203.

[0081] In some embodiments of this application, step S102 shown in FIG6 can be implemented by step S301, and will be described in conjunction with each step.

[0082] S301. Select the test area located at the corner of the array area as the target test area.

[0083] In this embodiment of the application, referring to FIG8, four test areas located at the corners of the array area can be selected as target test areas, with resistance values ​​of 13, 21, 34 and 42 respectively.

[0084] It is understandable that selecting a test area located at the corner of the array area as the target test area can ensure that the test can cover a larger range, thereby making the test results more comprehensive.

[0085] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0086] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A test structure for a phase-change memory, characterized in that, include: A multi-layered stacked structure with staggered stacking along the first direction; Each layer of the stacked structure includes: an array region and a redundancy region; wherein the redundancy region surrounds a portion of the array region; the projections of the array regions of each layer of the stacked structure along the first direction coincide with each other; each layer of the stacked structure includes: a bit line layer and a word line layer; the bit line layer and the word line layer are respectively located on opposite sides of each layer of the stacked structure along the first direction; wherein the bit line layer includes: a plurality of bit line regions; the word line layer includes: a plurality of word line regions; the plurality of word line regions all extend along a second direction, and adjacent word line regions are staggered; the plurality of bit line regions all extend along a third direction, and adjacent bit line regions are staggered; each word line region is provided with a plurality of word lines extending along the second direction; each bit line region is provided with a plurality of bit lines extending along the third direction; wherein the second direction and the third direction intersect; the second direction and the third direction are both perpendicular to the first direction.

2. The test structure for the phase-change memory according to claim 1, characterized in that, The projection of the array region along the first direction is a rectangle; the projection of the redundant region along the first direction is an L-shape surrounding the two adjacent sides of the rectangle.

3. The test structure for the phase-change memory according to claim 1, characterized in that, The two adjacent stacked structures are rotated at a 90° or 180° angle when projected along the first direction.

4. The test structure for the phase-change memory according to claim 1, characterized in that, At least a portion of each bit line region and at least a portion of each word line region belong to the redundant region.

5. The test structure for the phase-change memory according to claim 1, characterized in that, Two bit lines located in two adjacent stacked layers are connected in parallel; or two word lines located in two adjacent stacked layers are connected in parallel.

6. The test structure for the phase-change memory according to claim 5, characterized in that, The two bit lines or two word lines connected in parallel are in contact with each other along the first direction.

7. A testing method for phase-change memory, characterized in that, Used to test the test structure according to any one of claims 1 to 6; the test method includes: dividing the array region of the test structure into multiple test regions; selecting several target test regions with different resistance values ​​in the multiple test regions; selecting at least one target bit line and at least one target word line in each target test region for testing, and obtaining the test result of the target device.

8. The test method for phase-change memory according to claim 7, characterized in that, The step of selecting at least one target bit line and target word line for testing to obtain the test results of the target device includes: applying a constant voltage to the target bit line; applying an incremental voltage pulse to the target word line and testing the current on the target bit line; and determining the threshold voltage of the target device based on the current on the target bit line.

9. The testing method for phase-change memory according to claim 7, characterized in that, The selection of several target test areas with different resistance values ​​includes: selecting the test area located at the corner of the array area as the target test area.

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