SRAM (Static Random Access Memory) enhanced test method and device, computer equipment and storage medium
By performing multiple rounds of MBIST tests in SRAM tests and using CPU initialization and dial switches, the memory problems caused by environmental changes in the prior art are solved, product reliability is improved, and mass production testing standards are guided.
Patent Information
- Application Number
- CN202411272150.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2024-12-27
AI Technical Summary
The existing SRAM testing methods cannot effectively detect memory problems caused by environmental changes (such as voltage and temperature) during the productization stage, and cannot clarify whether it is caused by memory yield, and cannot guide subsequent mass production testing standards.
Perform multiple rounds of MBIST tests in the CP/FT test phase, and perform various ways to start MBIST tests in the actual system environment through CPU initialization and dial switches, including the first round, second round, third round and extreme MBIST Test, gradually tighten the test conditions until the test fails.
It improves the reliability of the product and guides the subsequent mass production testing standards to ensure the reliability and performance of the chip in the actual system environment.
Smart Images
Figure CN119207538A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data storage, and more specifically to an SRAM enhanced testing method, device, computer equipment and storage medium. Background Art
[0002] SSD-Solid State Drives (Solid State Drives) SOC chips generally use traditional SRAM testing methods, using specialized test equipment to perform MBIST testing through the JTAG interface. This can be done at the chip wafer and packaging stages (CP / FT). However, at the product stage (SLT), environmental changes (such as voltage and temperature) may cause some memory problems, which may not be discovered at the CP / FT stage. In this case, it is impossible to determine whether these problems are caused by the yield of the memory itself, nor can it guide whether the subsequent chip mass production tests need to tighten the test standards. Summary of the invention
[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide an SRAM enhanced testing method, device, computer equipment and storage medium.
[0004] To achieve the above object, the present invention adopts the following technical solutions:
[0005] In a first aspect, the present invention provides an SRAM enhanced testing method, comprising:
[0006] In the CP / FT test phase, the first round of mbist testing is performed on the chip, and the first round of mbist testing is started by the test machine;
[0007] If the chip passes the first round of mbist testing, the chip will be tested in the product function testing phase;
[0008] Determine whether the chip's CPU can respond normally during the chip's product function test phase;
[0009] If the CPU can respond normally, the second round of mbist test is performed on the chip;
[0010] If the chip fails the second round of mbist test, the ultimate extreme mbist test will be performed on the chip;
[0011] If the CPU cannot respond normally, the third round of mbist test will be executed on the chip. If the chip fails the third round of mbist test, the ultimate extreme mbist test will be executed on the chip.
[0012] Further, the performing of a second round of mbist testing on the chip includes:
[0013] Use the CPU to initialize the control register and status register;
[0014] Set the number of cycle tests;
[0015] Use the CPU to control the initialized control register to execute the mbist test according to the set number of cycle tests, and write the test results into the status register;
[0016] The CPU reads the status register to determine whether the test passed.
[0017] Further, the performing of a third round of mbist testing on the chip includes:
[0018] Start the DIP switch;
[0019] Directly turn on the mbist test function via the DIP switch.
[0020] Furthermore, the ultimate extreme mbist test is performed on the chip, including:
[0021] Mark the chip as a suspected bad chip;
[0022] Disconnect the power supply of the suspected bad chip and let it sit for a while;
[0023] After a period of inactivity, power on again and enter the mbist test;
[0024] If the test passes, the difficulty of passing the test is gradually increased until the test fails.
[0025] In a second aspect, the present invention further provides an SRAM enhanced test device, comprising:
[0026] A first test unit is used to perform a first round of mbist testing on the chip in the CP / FT testing phase, and the first round of mbist testing is started by a test machine;
[0027] The second test unit is used to perform product function test phase test on the chip if the chip passes the first round of mbist test;
[0028] A judgment unit, used to judge whether the CPU of the chip can respond normally during the chip execution product function test phase;
[0029] The third test unit is used to perform a second round of mbist test on the chip if the CPU can respond normally;
[0030] The fourth test unit is used to perform the ultimate extreme mbist test on the chip if the chip fails the second round of mbist test;
[0031] The fifth test unit is used to execute the third round of mbist test on the chip if the CPU cannot respond normally, and to execute the ultimate extreme mbist test on the chip if the chip fails the third round of mbist test.
[0032] Furthermore, the third test unit includes:
[0033] An initialization module, used to initialize the control register and status register using the CPU;
[0034] Setting module, used to set the number of cycle tests;
[0035] The first test module is used to use the CPU to control the initialized control register to perform the mbist test according to the set number of cycle tests, and write the test result into the status register;
[0036] The read module is used by the CPU to read the status register to determine whether the test passes.
[0037] Furthermore, the fourth test unit includes:
[0038] A marking module is used to mark the chip as a suspected bad chip;
[0039] The power-off standby module is used to power off the suspected bad chip and let it stand for a period of time;
[0040] The re-power module is used to re-power on the device after a period of inactivity and enter the mbist test;
[0041] The step-by-step testing module is used to gradually increase the difficulty of passing the test if the test passes, until the test fails.
[0042] Furthermore, the fifth test unit includes:
[0043] Start module, used to start the dip switch;
[0044] Direct test module, used to directly turn on the mbist test function through the dip switch.
[0045] In a third aspect, the present invention further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned SRAM enhanced test method when executing the computer program.
[0046] In a fourth aspect, the present invention further provides a computer-readable storage medium, wherein the storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes the SRAM enhanced test method as described above.
[0047] Compared with the prior art, the invention has the following beneficial effects: an SRAM enhanced test method comprises: performing a first round of mbist test on a chip in a CP / FT test phase, the first round of mbist test is started by a test machine; if the first round of mbist test of the chip passes, performing a test in a product function test phase on the chip; judging whether the CPU of the chip can respond normally during the chip execution of the product function test phase; if the CPU can respond normally, performing a second round of mbist test on the chip; if the second round of mbist test of the chip fails, performing an ultimate limit mbist test on the chip; if the CPU cannot respond normally, performing a third round of mbist test on the chip, and if the third round of mbist test of the chip fails, performing an ultimate limit mbist test on the chip. The invention starts the mbist test in a variety of ways in an actual system environment without relying on a machine, thereby improving the reliability of the product and guiding subsequent mass production test standards.
[0048] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.
[0050] Figure 1 A flow chart of an SRAM enhanced testing method provided by a specific embodiment of the present invention;
[0051] Figure 2 A schematic block diagram of an SRAM enhanced test device provided by a specific embodiment of the present invention;
[0052] Figure 3 A schematic block diagram of a computer device provided for a specific embodiment of the present invention;
[0053] Figure 4 Provide a conventional mbist test hardware architecture schematic diagram for a specific embodiment of the present invention;
[0054] Figure 5 A schematic diagram of an enhanced mbist test hardware architecture is provided for a specific embodiment of the present invention. DETAILED DESCRIPTION
[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0056] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.
[0057] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.
[0058] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0059] like Figure 1 As shown, the embodiment of the present invention provides an SRAM enhanced testing method, including the following steps: S10-S60.
[0060] S10. In the CP / FT test phase, the first round of mbist test is performed on the chip. The first round of mbist test is started by the test machine.
[0061] In the mass production test phase of the chip (CP / FT, i.e. wafer test and final test), Figure 4 As shown, the conventional mbist (Memory Built-In Self-Test) test structure usually relies on a dedicated test device (test machine) and JTAG (Joint Test Action Group) control signal to perform the test.
[0062] like Figure 4As shown in the figure, the mbist circuit has been embedded in the memory module during the chip design phase. The mbist circuit includes a controller and some logic for generating test vectors and detecting faults. During the mass production test phase, a dedicated test machine (such as ATE, Automatic Test Equipment) is used to test the chip. JTAG is a standard test interface for chip boundary scanning and debugging. JTAG control signals are used to control the startup, configuration, and result collection of the mbist test.
[0063] Connect the chip under test to a dedicated test machine (ATE). The test machine is physically connected to the test interface (such as JTAG interface) on the chip through a probe. Through the JTAG interface, the test machine sends a control signal to the chip to initialize the mbist circuit. The JTAG interface usually includes the following signals: TDI (Test Data Input): test data input. TDO (Test Data Output): test data output. TCK (Test Clock): test clock signal. TMS (Test Mode Select): test mode selection signal. Send a start command through the JTAG interface to trigger the mbist circuit to start testing. The mbist controller generates test vectors according to the preset test algorithm and performs read and write operations on the memory module. After the test is completed, the mbist controller transmits the test results back to the test machine through the JTAG interface. The test results include: Pass: If the memory module works normally in all test modes, it is recorded as a pass. Fail: If an error occurs in any test mode, the error details are recorded.
[0064] S20. If the chip passes the first round of mbist testing, the chip is tested in the product function testing phase.
[0065] During the product functional testing (SLT) phase, some memory failures may occur due to environmental changes (such as voltage and temperature), but these memory failures cannot be screened out in the CP / FT phase and therefore require further analysis.
[0066] S30: During the chip execution product function test phase, determine whether the CPU of the chip can respond normally.
[0067] The CPU can respond normally and cannot respond normally in different ways.
[0068] S40: If the CPU can respond normally, a second round of mbist testing is performed on the chip.
[0069] In one embodiment, step S40 specifically includes the following steps: S401 - S404 .
[0070] S401. Use the CPU to initialize the control register and status register.
[0071] S402, setting the number of cycle tests.
[0072] S403, using the CPU to control the initialized control register to execute the mbist test according to the set number of cycle tests, and write the test result into the status register.
[0073] S404: The CPU reads the status register to determine whether the test passes.
[0074] In this embodiment, for steps S401-S404, the MCPU can be accessed normally, and the relevant mbist is started by using the cpu configuration method, such as Figure 5 As shown, func mode controls EN_mbist&STATUS_mbist, starts mbist, and then collects mbist test results. It supports loop mode (i.e. repeat mode), can repeat the test N times, starts mbist test without powering off, and collects the status into the register. You can check whether the test fails or passes. If it passes, it means that it may be a problem with the chip firmware itself, not a memory problem.
[0075] S50: If the chip fails the second round of mbist test, the ultimate extreme mbist test is performed on the chip.
[0076] In one embodiment, step S50 specifically includes the following steps: S501 - S504 .
[0077] S501. Mark the chip as a suspected bad chip.
[0078] S502, disconnect the power supply of the suspected bad chip and let it stand for a while.
[0079] S503, after standing still for a period of time, power on again and enter the mbist test.
[0080] S504: If the test passes, gradually increase the difficulty of passing the test until the test fails.
[0081] In this embodiment, for steps S501-S504, the test conditions are gradually tightened until the limit or failure point of the system or component is found. Specifically, power on again and enter the mbist test. If the initial test passes, it means that the memory has passed all the initial tests, which means that under the current test conditions, no defects or failures are found in the memory. The mbist test algorithm can be further adjusted to tighten the test conditions. Such adjustments may include: adding test modes: introducing more test modes and data modes to cover a wider range of memory operation scenarios. Increasing test cycles: increasing the number of test cycles so that the memory undergoes more read and write operations to test its reliability under longer operation. Shortening the test cycle: shortening the interval between read and write operations to simulate memory performance under high load and high frequency operation. Introducing more noise and interference: introducing more electrical noise and interference during the test process to test the stability of the memory under non-ideal conditions.
[0082] Adjust voltage and temperature: Test under different voltage and temperature conditions to verify the environmental adaptability of the memory.
[0083] By gradually tightening the test conditions, the goal is to find the limit points and weak links when the memory has errors or failures. This helps to understand the reliability and performance of the memory in real-world usage environments.
[0084] During the process of gradual adjustment and retesting, retest after each adjustment of the mbist algorithm. If the test result is still a pass, continue to tighten the test conditions and test again. In each tightening step, record the test results and conditions in detail, which will help with subsequent analysis and improvement. When the test result finally fails, that is, the memory has an error or failure under a certain tightening condition, record the condition and test result. This helps us determine the limits of the memory and potential reliability issues.
[0085] S60: If the CPU cannot respond normally, a third round of mbist test is performed on the chip. If the chip fails the third round of mbist test, an ultimate extreme mbist test is performed on the chip.
[0086] In one embodiment, step S60 specifically includes the following steps: S601 - S602 .
[0087] S601, start the DIP switch.
[0088] S602. Turn on the mbist test function directly through the DIP switch.
[0089] In this embodiment, if Figure 5As shown, for steps S601-S602, through the dip switch, without power failure, directly enter the test mode, test mode, at this time the CPU can configure APB2JTAG, generate mbist JTAG control signal, start mbist test, similarly, it also supports loop mode, start the test of the entire soc memory, and save the final result to a specific register (reset without losing information); then reset the entire chip, check the mbist test result in the specific register, if fail, enter 50.
[0090] It should be noted that a DIP switch is a mechanical switch with multiple independent small switches that can be set to different switch states by manually toggling. Each switch has two states: ON or OFF. In actual applications, the DIP switch can be connected to certain control pins of the system. When a certain combination of DIP switch states is set, the system will detect this state and enter the test mode. The specific steps may be as follows:
[0091] Set the DIP switch: Manually set the DIP switch to a specific combination of states, which is pre-defined as the trigger condition for the test mode. Enter the test mode: The system detects the state change of the DIP switch and enters the test mode according to the pre-programmed logic. Start the mbist test: Once in the test mode, the system automatically starts the mbist test to check the function and reliability of the memory.
[0092] The present invention starts the MBIST test in a variety of ways in an actual system environment without relying on a machine, thereby improving the reliability of the product and guiding the subsequent mass production test standards.
[0093] The embodiment of the present invention further provides an SRAM enhanced test device, which is used to perform the steps in any embodiment of the aforementioned SRAM enhanced test method. Figure 2 , Figure 2 A schematic block diagram of an SRAM enhanced test device 100 provided in an embodiment of the present application is shown, and the SRAM enhanced test device 100 specifically includes:
[0094] The first test unit 110 is used to perform the first round of mbist test on the chip in the CP / FT test phase, and the first round of mbist test is started by the test machine; the second test unit 120 is used to perform the test in the product function test phase on the chip if the first round of mbist test of the chip passes; the judgment unit 130 is used to judge whether the CPU of the chip can respond normally during the process of the chip executing the product function test phase; the third test unit 140 is used to perform the second round of mbist test on the chip if the CPU can respond normally; the fourth test unit 150 is used to perform the ultimate limit mbist test on the chip if the second round of mbist test of the chip fails; the fifth test unit 160 is used to perform the third round of mbist test on the chip if the CPU cannot respond normally, and if the third round of mbist test of the chip fails, the ultimate limit mbist test is performed on the chip;
[0095] In one embodiment, the third testing unit 140 includes:
[0096] An initialization module, used to initialize the control register and status register using the CPU;
[0097] The setting module is used to set the number of cycle tests; the first test module is used to use the control register after CPU control initialization to perform the mbist test according to the set number of cycle tests, and write the test results into the status register; the reading module is used for the CPU to read the status register to determine whether the test passes.
[0098] In one embodiment, the fourth test unit 150 includes:
[0099] The marking module is used to mark the chip as a suspected bad chip; the power-off and static module is used to power off the suspected bad chip and let it stand for a period of time; the power-on module is used to power on again after standing for a period of time and enter the mbist test; the step-by-step test module is used to gradually increase the difficulty of passing the test if the test passes until the test fails.
[0100] In one embodiment, the fifth testing unit 160 includes:
[0101] The startup module is used to start the dip switch; the direct test module is used to directly start the mbist test function through the dip switch.
[0102] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned SRAM enhanced test device 100 and each unit can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and brevity of description, it will not be repeated here.
[0103] The SRAM enhanced test device can be implemented in the form of a computer program. The computer program can be used in Figure 3 Runs on the computer device shown.
[0104] See also Figure 3 , Figure 3 700 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 700 may be a server, wherein the server may be an independent server or a server cluster composed of multiple servers.
[0105] like Figure 3 As shown, the computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the SRAM enhanced test method as described above are implemented.
[0106] The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720 , a memory, and a network interface 750 connected via a system bus 710 , wherein the memory may include a non-volatile storage medium 730 and an internal memory 740 .
[0107] The non-volatile storage medium 730 may store an operating system 731 and a computer program 732. When the computer program 732 is executed, the processor 720 may execute the SRAM enhanced test method.
[0108] The processor 720 is used to provide computing and control capabilities and support the operation of the entire computer device 700.
[0109] The internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730. When the computer program 732 is executed by the processor 720, the processor 720 can execute the SRAM enhanced test method.
[0110] The network interface 750 is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will appreciate that Figure 3 The structure shown in the figure is only a block diagram of a part of the structure related to the present application scheme, and does not constitute a limitation on the computer device 700 to which the present application scheme is applied. The specific computer device 700 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements. The processor 720 is used to run the program code stored in the memory to implement the SRAM enhanced test method.
[0111] Those skilled in the art will understand that Figure 3The embodiments of the computer device shown in the figure do not constitute a limitation on the specific composition of the computer device. In other embodiments, the computer device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. For example, in some embodiments, the computer device may only include a memory and a processor. In such embodiments, the structure and function of the memory and the processor are the same as those of the embodiment of the present invention. Figure 3 The embodiments shown are consistent and will not be described again here.
[0112] It should be understood that in the embodiment of the present application, the processor 720 may be a central processing unit (CPU), and the processor 720 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0113] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium may be a non-volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the SRAM enhanced test method disclosed in the embodiment of the present invention is implemented.
[0114] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the above-described equipment, devices and units can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. Those of ordinary skill in the art can appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.
[0115] In the several embodiments provided by the present invention, it should be understood that the disclosed equipment, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. Units with the same function may also be combined into one unit. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, or may be electrical, mechanical or other forms of connection.
[0116] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.
[0117] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0118] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), disk or optical disk and other media that can store program codes.
[0119] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.
Claims
1. The SRAM enhanced test method is characterized in that: include: In the CP / FT test phase, the first round of mbist testing is performed on the chip, and the first round of mbist testing is started by the test machine; If the chip passes the first round of mbist testing, the chip will be tested in the product function testing phase; Determine whether the chip's CPU can respond normally during the chip's product function test phase; If the CPU can respond normally, the second round of mbist test is performed on the chip; If the chip fails the second round of mbist test, the ultimate extreme mbist test will be performed on the chip; If the CPU cannot respond normally, the third round of mbist test will be executed on the chip. If the chip fails the third round of mbist test, the ultimate extreme mbist test will be executed on the chip.
2. The SRAM enhanced test method according to claim 1, characterized in that: The second round of mbist testing on the chip includes: Use the CPU to initialize the control register and status register; Set the number of cycle tests; Use the CPU to control the initialized control register to execute the mbist test according to the set number of cycle tests, and write the test results into the status register; The CPU reads the status register to determine whether the test passed.
3. The SRAM enhanced test method according to claim 1, characterized in that: The third round of mbist testing on the chip includes: Start the DIP switch; Directly turn on the mbist test function via the DIP switch.
4. The SRAM enhanced test method according to claim 1, characterized in that: The ultimate extreme mbist test is performed on the chip, including: Mark the chip as a suspected bad chip; Disconnect the power supply of the suspected bad chip and let it sit for a while; After a period of inactivity, power on again and enter the mbist test; If the test passes, the difficulty of passing the test is gradually increased until the test fails.
5. SRAM enhanced test device, characterized in that: include: A first test unit is used to perform a first round of mbist testing on the chip in the CP / FT testing phase, and the first round of mbist testing is started by a test machine; The second test unit is used to perform product function test phase test on the chip if the chip passes the first round of mbist test; A judgment unit, used to judge whether the CPU of the chip can respond normally during the chip execution product function test phase; The third test unit is used to perform a second round of mbist test on the chip if the CPU can respond normally; The fourth test unit is used to perform the ultimate extreme mbist test on the chip if the chip fails the second round of mbist test; The fifth test unit is used to execute the third round of mbist test on the chip if the CPU cannot respond normally, and to execute the ultimate extreme mbist test on the chip if the chip fails the third round of mbist test.
6. The SRAM enhanced test device according to claim 5, characterized in that: The third test unit comprises: An initialization module, used to initialize the control register and status register using the CPU; Setting module, used to set the number of cycle tests; The first test module is used to use the CPU to control the initialized control register to perform the mbist test according to the set number of cycle tests, and write the test result into the status register; The read module is used by the CPU to read the status register to determine whether the test passes.
7. The SRAM enhanced test device according to claim 5, characterized in that: The fourth test unit comprises: A marking module is used to mark the chip as a suspected bad chip; The power-off standby module is used to power off the suspected bad chips and let them stand for a period of time; The power-on module is used to power on again after a period of inactivity and enter the mbist test; The step-by-step testing module is used to gradually increase the difficulty of passing the test if the test passes, until the test fails.
8. The SRAM enhanced test device according to claim 5, characterized in that: The fifth test unit comprises: Start module, used to start the dip switch; Direct test module, used to directly turn on the mbist test function through the dip switch.
9. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the SRAM enhanced test method according to any one of claims 1 to 4 is implemented.
10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the SRAM enhanced test method according to any one of claims 1 to 4.