High-voltage super-junction VDMOS device terminal structure and manufacturing method thereof

Abstract

The invention discloses a high-voltage super-junction VDMOS device terminal structure and a manufacturing method thereof. The manufacturing method comprises the following steps: growing an epitaxial layer on a heavily doped conductive substrate; forming a transition oxide layer on the top of the epitaxial layer; a first doped region, a second doped region and a third doped region are formed in the top region of the epitaxial layer through injection; etching the epitaxial layer to form a plurality of groups of terminal grooves; forming a vertical field plate dielectric layer on the side wall of the terminal groove; filling the terminal groove to form a vertical resistance field plate; forming a horizontal resistance field plate at the top of the epitaxial region; and forming a drain metal electrode, a source metal electrode and a floating metal electrode. According to the invention, the terminal structure adopts the super junction, the field plate, the field cut-off ring and other technologies, low potential can be provided for the vertical resistance field plate and the second doped region through the horizontal resistance field plate, the electric field peak at the bottom of the resistance field plate can be effectively reduced through the cut-off ring, the planar terminal area is greatly reduced, and the miniaturization of the device is realized.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices, and in particular relates to a high-voltage super junction VDMOS device terminal structure and a manufacturing method thereof. Background Art

[0002] The superjunction technology concept improves the 2.5th power proportional limit of the breakdown voltage and on-resistance of silicon-based MOS devices due to its RESURF two-dimensional electric field principle and charge balance principle, reduces the on-resistance of medium and high voltage devices, and greatly improves the power density of the device. Due to its high breakdown and low conduction characteristics, it has quickly entered the high-power device market, and its current scope includes smartphones, chargers, automotive electronics, and commonly used household appliance drivers. In order to solve the problem of low manufacturing yield of PN-type superjunction devices, superjunction devices modulated by resistive field plates have been proposed. For superjunction VDMOS devices modulated by resistive field plates, the resistive field plate can deplete the impurities in the drift region, thereby achieving the effect of charge balance. The advantages of this method are simple compared to PN-type superjunction devices, low manufacturing cost and good breakdown consistency.

[0003] The cells of VDMOS high-voltage power semiconductors withstand a high withstand voltage. The interior is composed of many cells connected in parallel. Usually, breakdown does not occur inside the cell, but at the edge where the electric field is concentrated. In order to improve its edge curvature effect and withstand voltage characteristics, it is necessary to set corresponding withstand voltage terminals at the edge of the cell. Common withstand voltage technologies include field plate technology, lateral variable doping, junction terminal expansion and other lateral technologies. For super junction devices, the concentration of the drift region is higher than that of conventional VDMOS devices. The use of conventional planar technology will cause the breakdown voltage of the terminal region to be much lower than that of the cell region. Therefore, the need for terminal technology is one of the urgent problems to be solved. By adapting the trench longitudinal resistive field plate technology of the resistive field plate super junction vertical double diffused metal-oxide semiconductor device (RFP SJ-VDMOS) cell structure, the electric field optimization effect of the terminal region on the cell region is guided to achieve an improvement in withstand voltage effect with a smaller terminal area. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a high-voltage super junction VDMOS device terminal structure and a manufacturing method thereof.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] A method for manufacturing a high-voltage super junction VDMOS device terminal structure comprises the following steps:

[0007] S1. epitaxially growing an epitaxial layer on a heavily doped conductive substrate, wherein the conductivity type of the epitaxial layer is the same as that of the heavily doped conductive substrate;

[0008] S2, performing surface oxidation on the top of the epitaxial layer to form a transition oxide layer;

[0009] S3, implanting a first doped region, a second doped region and a third doped region into the top region of the epitaxial layer, wherein the first doped region is located inside the terminal, the second doped region is located outside the first doped region, and the third doped region is located outside the terminal region;

[0010] S4, etching on the epitaxial layer to form a plurality of terminal grooves penetrating the epitaxial layer and exposing the substrate, and removing the transition oxide layer;

[0011] S5, forming a vertical field plate dielectric layer on the sidewall of the terminal trench;

[0012] S6, filling the terminal trench to form a vertical resistance field plate;

[0013] S7, forming a horizontal resistive field plate on the top of the epitaxial region;

[0014] S8, forming a drain metal electrode connected to the substrate, a source metal electrode connected to the first doped region, and a floating metal electrode connected to the third doped region.

[0015] Furthermore, the S3 step includes the following sub-steps:

[0016] S301, performing a first ion implantation in a region on the top of the epitaxial layer located inside the terminal through a photolithography pattern, and then diffusing it under high temperature annealing conditions to connect it with the main junction region of the device to form a first doped region, wherein the conductivity type of the first doped region is opposite to that of the epitaxial layer;

[0017] S302, performing a second ion implantation on a region on the top of the epitaxial layer and adjacent to the outer side of the first doped region through a photolithography pattern to form a second doped region, wherein the conductivity type of the second doped region is consistent with the conductivity type of the first doped region, and the doping concentration thereof is lower than the doping concentration of the first doped region;

[0018] S303, performing a third ion implantation in a region on the top of the epitaxial layer outside the terminal through a photolithography pattern to form a third doped region, wherein the conductivity type of the third doped region is consistent with the conductivity type of the epitaxial layer.

[0019] Furthermore, in the step S4, deep groove etching is performed through the photolithography pattern, and the terminal grooves are arranged at the same regular intervals in the lateral direction; the etching depth is the thickness of the epitaxial layer, or the etching depth exceeds the thickness of the epitaxial layer by 1 μm to 2 μm.

[0020] Furthermore, the step S5 includes the following sub-steps:

[0021] S501, growing a layer of silicon dioxide film on the sidewall and bottom of the terminal trench by thermal oxidation method;

[0022] S502 , etching the silicon dioxide film layer at the bottom of the terminal trench by dry etching, retaining the silicon dioxide film on the sidewall, and forming a vertical field plate dielectric layer.

[0023] Furthermore, the step S6 includes the following sub-steps:

[0024] S601, growing a first resistive field plate material by a chemical epitaxial method to fill the terminal trench, so that the first resistive field plate material is connected to the substrate;

[0025] S602 , etching away the first resistance field plate material and the transition oxide layer on the top of the epitaxial layer using photolithography patterns, and retaining the first resistance field plate material in the terminal trench to form a vertical resistance field plate.

[0026] Furthermore, the step S7 includes the following sub-steps:

[0027] S701, depositing a thick oxide layer on the top of the epitaxial layer to form a top oxide layer;

[0028] S702, etching to form a contact through hole penetrating the top oxide layer above each vertical resistance field plate and above the second doping region between each two adjacent groups of vertical resistance field plates;

[0029] S703 , depositing a layer of second resistance field plate material on the top oxide layer, wherein the second resistance field plate material extends into each contact through hole and contacts the top of the epitaxial layer to form a horizontal resistance field plate.

[0030] Furthermore, the step S8 includes the following sub-steps:

[0031] S801, etching and removing the top oxide layer and the horizontal resistance field plate on the inner side above the epitaxial layer to expose a portion of the first doped region; etching and removing the top oxide layer and the horizontal resistance field plate on the outer side above the epitaxial layer to expose a portion of the third doped region;

[0032] S802, forming a source metal electrode connected to the first doped region on the inner side above the epitaxial layer, and forming a floating metal electrode connected to the third doped region on the outer side above the epitaxial layer;

[0033] S803, thinning the back side of the substrate, and forming a drain metal electrode on the back side of the substrate by metal evaporation.

[0034] Furthermore, the first doped region is implanted with boron ions at a concentration of 3e15cm -2 The second doped region is implanted with boron ions at a concentration of 3e13cm-2 The third doping region is implanted with arsenic ions or phosphorus ions at a concentration of 5e15cm -2 .

[0035] Further, the thickness of the vertical field plate dielectric layer is 0.2 μm, the thickness of the vertical resistance field plate is 0.8 μm, the width of the terminal groove is 1.2 μm; the spacing between the centers of adjacent terminal grooves is 4 μm; and / or

[0036] The resistivity of the heavily doped conductive substrate is 2.8Ω·cm; the first resistance field plate material and the second resistance field plate material are both semi-insulating polysilicon materials, the resistivity of the vertical resistance field plate is le10Ω·cm; the resistivity of the horizontal resistance field plate is le7Ω·cm.

[0037] A high-voltage super junction VDMOS device terminal structure, comprising a heavily doped conductive substrate and an epitaxial layer arranged on the heavily doped conductive substrate, wherein the lower end of the heavily doped conductive substrate is connected to a drain electrode; a first doped region, a second doped region and a third doped region are formed by implantation in the top region of the epitaxial layer, wherein the first doped region is located inside the terminal, the second doped region is located outside the first doped region, and the third doped region is located outside the terminal region; the implantation type of the first doped region and the second doped region is opposite to the conductivity type of the epitaxial layer; the implantation type of the third doped region is the same as the conductivity type of the epitaxial layer;

[0038] A plurality of groups of terminal grooves are formed on the epitaxial layer, and the terminal grooves penetrate the epitaxial layer; a vertical resistance field plate is respectively arranged in each of the terminal grooves, and a vertical field plate dielectric layer is arranged between the vertical resistance field plate and the inner wall of the terminal groove; a top oxide layer is arranged on the epitaxial layer, and a contact through-hole penetrating the top oxide layer is respectively opened on the top of each vertical resistance field plate and on the top of the second doped region between each two adjacent groups of vertical resistance field plates, a first notch is formed on the inner side of the top oxide layer, and the first notch exposes a part of the first doped region; a second notch is formed on the outer side of the top oxide layer, and the second notch exposes a part of the third doped region; a horizontal resistance field plate is arranged on the top oxide layer, and the horizontal resistance field plate extends into each contact through-hole and contacts with the top of the epitaxial layer, a source metal electrode is formed in the first notch, and a floating metal electrode is formed in the second notch.

[0039] In the present invention, the terminal structure adopts super junction, field plate, field stop ring and other technologies, and provides low potential to the vertical resistance field plate and the second doped region through the horizontal resistance field plate, so that the resistance field plate in the body can modulate and deplete the doped region in the middle, avoiding the electric field spike similar to the metal field plate. The electric field spike at the bottom of the resistance field plate can be effectively reduced by setting the stop ring. With the terminal structure of this embodiment, the terminal length is only about 50μm when the breakdown voltage is 630V, which can greatly reduce the planar terminal area and realize the miniaturization of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0041] Figure 1 The present invention is a flowchart of an embodiment of a method for manufacturing a high-voltage super junction VDMOS device terminal structure.

[0042] Figure 2 Schematic diagram of the structure after the epitaxial layer is formed.

[0043] Figure 3 Schematic diagram of the structure after the transition oxide layer is formed.

[0044] Figure 4 Schematic diagram of the structure after forming three doping regions.

[0045] Figure 5 This is a schematic diagram of the structure after the terminal groove is opened.

[0046] Figure 6 Schematic diagram of the structure after forming the vertical field plate dielectric layer.

[0047] Figure 7 Schematic diagram of the structure after the vertical resistance field plate is formed.

[0048] Figure 8 Schematic diagram of the structure after forming a top oxide layer and opening a contact through hole.

[0049] Fig. 9 A schematic diagram of the structure after a horizontal resistance field plate is formed and a first notch and a second notch are opened.

[0050] Fig.10 It is a schematic diagram of the structure after the source metal electrode and the floating metal electrode are formed.

[0051] Fig.11 Schematic diagram of the terminal potential distribution simulation results.

[0052] The accompanying drawings in the specification are numeraled as follows:

[0053] Heavily doped conductive substrate-100; epitaxial layer-200; first doped region-201; second doped region-202; third doped region-203; terminal trench-210; vertical field plate dielectric layer-220; vertical resistance field plate-230; transition oxide layer-300; top oxide layer-400; contact through hole-401; horizontal resistance field plate-500; first notch-501; second notch-502; source metal electrode-601; floating metal electrode-602. DETAILED DESCRIPTION

[0054] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0055] See also Figure 1 The present invention discloses a method for manufacturing a high-voltage super junction VDMOS device terminal structure. A preferred embodiment of the method for manufacturing a high-voltage super junction VDMOS device terminal structure of the present invention comprises the following steps:

[0056] S1. Please refer to Figure 2 , an epitaxial layer 200 of a certain thickness is epitaxially grown on the heavily doped conductive substrate 100 as a drift region. The resistivity of the epitaxial layer 200 is one of the determining factors of the device breakdown voltage. The higher the resistivity, the lower the breakdown voltage and the smaller the specific on-resistance. The concentration of the epitaxial layer 200 is determined according to the requirements; the conductivity type of the epitaxial layer 200 is the same as that of the heavily doped conductive substrate 100. In this embodiment, the heavily doped conductive substrate 100 is N-type heavily doped, and the resistivity of the heavily doped conductive substrate 100 is 2.8Ω·cm; the epitaxial layer 200 is N-type lightly doped.

[0057] S2. Please refer to Figure 3 , surface oxidation is performed on the top of the epitaxial layer 200 to form a transition oxide layer 300 to reduce damage caused by ion implantation.

[0058] S3. Please refer to Figure 4 , a first doped region 201, a second doped region 202 and a third doped region 203 are implanted in the top region of the epitaxial layer 200, wherein the first doped region 201 is located inside the terminal, the second doped region 202 is located outside the first doped region 201, and the third doped region 203 is located outside the terminal region. This step may include the following sub-steps:

[0059] S301, perform the first ion implantation in the region located inside the terminal at the top of the epitaxial layer 200 through the photolithography pattern, and diffuse it under high temperature annealing conditions after implantation to connect it with the main junction region of the device to form a first doped region 201; the conductivity type of the first doped region 201 is opposite to that of the epitaxial layer 200. In this embodiment, the first doped region 201 is implanted with boron ions at 80kev, 3e15cm -2 injection conditions.

[0060] S302, a second ion implantation is performed on the top of the epitaxial layer 200 and the area adjacent to the outside of the first doped region 201 through a photolithography pattern to form a second doped region 202. The conductivity type of the second doped region 202 is consistent with the conductivity type of the first doped region 201, and its doping concentration is lower than the doping concentration of the first doped region 201. In this embodiment, the second doped region 202 is implanted with boron ions at an implantation concentration of 3e13cm -2 .

[0061] S303, a third ion implantation is performed in the region outside the terminal at the top of the epitaxial layer 200 through a photolithography pattern to form a third doped region 203, the conductivity type of the third doped region 203 is consistent with the conductivity type of the epitaxial layer 200, and the third doped region 203 is used as a heavily doped cutoff ring. In this embodiment, the third doped region 203 is implanted with arsenic ions or phosphorus ions, and the implantation concentration is 5e15cm -2 .

[0062] S4. Please refer to Figure 5 , a plurality of terminal grooves 210 penetrating the epitaxial layer 200 and exposing the substrate are etched on the epitaxial layer 200, and the transition oxide layer 300 is removed. In this step, deep groove etching is performed through the photolithography pattern, and the terminal grooves 210 are arranged at the same regular intervals in the lateral direction; the etching depth can be the thickness of the epitaxial layer 200 or slightly greater than the thickness of the epitaxial layer 200. The depth, width and number of the terminal grooves 210 can be formulated according to the requirements of breakdown and working voltage. In this embodiment, the etching depth exceeds the thickness of the epitaxial layer 200 by 1μm to 2μm, the width of the terminal grooves 210 is 1.2μm; the number of the terminal grooves 210 is 9 groups. The spacing between the centers of adjacent terminal grooves 210 is 4μm. By adopting the above method, a high voltage resistance performance can be maintained while reducing the spacing between adjacent terminal grooves 210, thereby realizing the miniaturization of the device.

[0063] S5. Please refer to Figure 6 , forming a vertical field plate dielectric layer 220 on the sidewall of the terminal trench 210. This step may include the following sub-steps:

[0064] S501 , oxidizing the device by thermal oxidation, and growing a layer of silicon dioxide film on the sidewall and bottom of the terminal trench 210 .

[0065] S502, using dry etching to etch the silicon dioxide film layer at the bottom of the terminal trench 210, retaining the silicon dioxide film on the sidewall, to form a vertical field plate dielectric layer 220. In this embodiment, the thickness of the vertical field plate dielectric layer 220 is 0.2 μm.

[0066] S6. Please refer to Figure 7 , filling the terminal trench 210 to form a vertical resistance field plate 230. This step may include the following sub-steps:

[0067] S601, using a chemical epitaxial method to grow a first resistive field plate material to fill the terminal trench 210, so that the first resistive field plate material is connected to the substrate. In this embodiment, the first resistive field plate material is made of semi-insulating polysilicon material.

[0068] S602, using photolithography patterns, the semi-insulating polysilicon material (i.e., the first resistance field plate material) and the transition oxide layer 300 on the top of the epitaxial layer 200 are etched away, and the semi-insulating polysilicon material in the terminal groove 210 is retained to form a vertical resistance field plate 230. In this embodiment, since the width of the terminal groove 210 is 1.2 μm and the thickness of the vertical field plate dielectric layer 220 is 0.2 μm, the thickness of the vertical resistance field plate 230 is 0.8 μm. The resistivity of the vertical resistance field plate 230 in this embodiment is le10Ω·cm.

[0069] S7, forming a horizontal resistive field plate 500 on the top of the epitaxial region. This step may include the following sub-steps:

[0070] S701, please refer to Figure 8 , a thick oxide layer is deposited on the top of the epitaxial layer 200 to form a top oxide layer 400 .

[0071] S702, please continue reading Figure 8 A contact through hole 401 penetrating the top oxide layer 400 is formed by etching above each vertical resistance field plate 230 and above the second doped region 202 between each two adjacent groups of vertical resistance field plates 230 .

[0072] S703, please refer to Fig. 9 , a layer of second resistance field plate material is deposited on the top oxide layer 400, the second resistance field plate material extends into each contact through hole 401 and contacts the top of the epitaxial layer 200, forming a horizontal resistance field plate 500. In this embodiment, the second resistance field plate material is made of semi-insulating polysilicon material, and the resistivity of the horizontal resistance field plate 500 is 1 e7Ω·cm.

[0073] S8, please refer to Fig.10 , forming a drain metal electrode connected to the substrate, a source metal electrode 601 connected to the first doped region 201, and a floating metal electrode 602 connected to the third doped region 203. This step may include the following sub-steps:

[0074] S801, etching and removing the innermost top oxide layer 400 and the horizontal resistance field plate 500 above the epitaxial layer 200 to form a first gap 501 exposing a portion of the first doped region 201; etching and removing the outermost top oxide layer 400 and the horizontal resistance field plate 500 above the epitaxial layer 200 to form a second gap 502 exposing a portion of the third doped region 203.

[0075] S802, forming a source metal electrode 601 connected to the first doped region 201 at the first notch 501 (i.e., the innermost side above the epitaxial layer 200), wherein the lateral contact between the innermost source metal electrode 601 and the first doped region 201 does not exceed the outer side of the first doped region 201. Forming a floating metal electrode 602 connected to the third doped region 203 at the second notch 502 (i.e., the outermost side above the epitaxial layer 200), wherein the lateral contact between the outermost floating metal electrode 602 and the third doped region 203 does not exceed the inner side of the third doped region 203.

[0076] S803, thinning the substrate by a backside thinning process, and forming a drain metal electrode on the backside of the substrate by metal evaporation.

[0077] This embodiment provides a usable terminal structure and preparation method for a super junction VDMOS device of a resistive field plate type, and the terminal structure uses technologies such as super junction, field plate, and field stop ring; the principle is to make a hole on the field oxygen in the terminal area, and cover a layer of resistivity slightly lower than the resistive field plate layer in the body (i.e., the horizontal resistive field plate 500) connected to the vertical resistive field plate 230 and the surface of the P-region (i.e., the second doped region 202) in the body, to provide a low potential to both, so that the resistive field plate in the body can modulate and deplete the doped region in the middle. Because the connection is made through the resistive field plate in the lateral direction, no electric field spike similar to the metal field plate will appear in the terminal area. Adding a stop ring can form a leakage current path, so that electrons will not continuously accumulate at the oxide layer at the bottom of the resistive field plate, effectively reducing the electric field spike at the bottom of the resistive field plate.

[0078] The effective gain of this embodiment is as follows: when the center spacing of adjacent vertical resistance field plates 230 in the terminal region (i.e., the center spacing of adjacent terminal grooves 210) is 4 μm, and the number of groups of vertical resistance field plates 230 (i.e., the number of groups of terminal grooves 210) increases from 4 to 9, the device breakdown voltage increases from 518 V to 630 V. Increasing the number of vertical resistance field plates 230 can reduce the peak electric field borne by each RFP (resistivity filter plate) unit. Fig.11 As shown in FIG. 1 , the potential simulation result is obtained when the number of groups of vertical resistance field plates 230 is 9. Fig.11 It can be seen that the resistance field plate area of ​​the terminal is almost completely depleted, and the breakdown voltage is 630V. The avalanche breakdown point occurs at the edge of the main junction, and the leakage current flows through the main junction. The terminal length when the breakdown voltage is 630V is only about 50μm, which is 50% smaller than the traditional planar terminal area. The resistance field plate column (i.e., the vertical resistance field plate 230) of the super junction device terminal of this embodiment can be made together with the cell to save process cost, but the width and spacing can be designed separately according to the device withstand voltage requirements.

[0079] Please continue reading Fig.10 The present invention discloses a high-voltage super junction VDMOS device terminal structure. A preferred embodiment of the high-voltage super junction VDMOS device terminal structure of the present invention includes a heavily doped conductive substrate 100 and an epitaxial layer 200 disposed on the heavily doped conductive substrate 100, wherein the lower end of the heavily doped conductive substrate 100 is connected to a drain electrode. In this embodiment, the heavily doped conductive substrate 100 is N-type heavily doped, and the resistivity of the heavily doped conductive substrate 100 is 2.8Ω·cm; the epitaxial layer 200 is N-type lightly doped.

[0080] The top region of the epitaxial layer 200 is implanted to form a first doped region 201, a second doped region 202, and a third doped region 203. The first doped region 201 is located inside the terminal, the second doped region 202 is located outside the first doped region 201, and the third doped region 203 is located outside the terminal region. The implantation type of the first doped region 201 and the second doped region 202 is opposite to the conductivity type of the epitaxial layer 200; the implantation type of the third doped region 203 is the same as the conductivity type of the epitaxial layer 200. In this embodiment, the first doped region 201 is implanted with boron ions at 80kev, 3e15cm -2 The second doping region 202 is implanted with boron ions at a concentration of 3e13cm -2 The third doping region 203 is implanted with arsenic ions or phosphorus ions at a concentration of 5e15 cm -2 .

[0081] A plurality of terminal grooves 210 are formed on the epitaxial layer 200, and the terminal grooves 210 penetrate the epitaxial layer 200; the etching depth may be equal to or slightly greater than the thickness of the epitaxial layer 200. In this embodiment, the etching depth exceeds the thickness of the epitaxial layer 200 by 1 μm to 2 μm, and the width of the terminal grooves 210 is 1.2 μm; the number of the terminal grooves 210 is 9 groups. The spacing between the centers of adjacent terminal grooves 210 is 4 μm.

[0082] A vertical resistance field plate 230 is disposed in each of the terminal grooves 210, and a vertical field plate dielectric layer 220 is disposed between the vertical resistance field plate 230 and the inner wall of the terminal groove 210. In this embodiment, the thickness of the vertical field plate dielectric layer 220 is 0.2 μm. The vertical resistance field plate 230 is made of semi-insulating polysilicon material with a thickness of 0.8 μm; the resistivity of the vertical resistance field plate 230 is 1 e10 Ω·cm.

[0083] A top oxide layer 400 is disposed on the epitaxial layer 200, and a contact through hole 401 penetrating the top oxide layer 400 is respectively formed above each vertical resistance field plate 230 and above each second doped region 202 between two adjacent sets of vertical resistance field plates 230. A first notch 501 is formed inside the top oxide layer 400, and the first notch 501 exposes a portion of the first doped region 201; a second notch 502 is formed outside the top oxide layer 400, and the second notch 502 exposes a portion of the third doped region 203.

[0084] A horizontal resistance field plate 500 is disposed on the top oxide layer 400, and the horizontal resistance field plate 500 extends into each contact through hole 401 and contacts the top of the epitaxial layer 200. The horizontal resistance field plate 500 is made of semi-insulating polysilicon material, and the resistivity of the horizontal resistance field plate 500 is 1 e7Ω·cm. A source metal electrode 601 is formed in the first notch 501, and a floating metal electrode 602 is formed in the second notch 502.

[0085] In this embodiment, the terminal structure adopts super junction, field plate, field stop ring and other technologies. The horizontal resistance field plate 500 provides a low potential to the vertical resistance field plate 230 and the second doped region 202, so that the resistance field plate in the body can modulate and deplete the doped region in the middle, avoiding the electric field spike similar to the metal field plate. The electric field spike at the bottom of the resistance field plate can be effectively reduced by setting a stop ring. With the terminal structure of this embodiment, the terminal length is only about 50μm when the breakdown voltage is 630V, which can greatly reduce the planar terminal area and realize the miniaturization of the device.

[0086] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a high-voltage super junction VDMOS device terminal structure, characterized in that: The following steps are involved: S1. epitaxially growing an epitaxial layer on a heavily doped conductive substrate, wherein the conductivity type of the epitaxial layer is the same as that of the heavily doped conductive substrate; S2, performing surface oxidation on the top of the epitaxial layer to form a transition oxide layer; S3, implanting a first doped region, a second doped region and a third doped region into the top region of the epitaxial layer, wherein the first doped region is located inside the terminal, the second doped region is located outside the first doped region, and the third doped region is located outside the terminal region; S4, etching on the epitaxial layer to form a plurality of terminal grooves penetrating the epitaxial layer and exposing the substrate, and removing the transition oxide layer; S5, forming a vertical field plate dielectric layer on the sidewall of the terminal trench; S6, filling the terminal trench to form a vertical resistance field plate; S7, forming a horizontal resistive field plate on the top of the epitaxial region; S8, forming a drain metal electrode connected to the substrate, a source metal electrode connected to the first doped region, and a floating metal electrode connected to the third doped region.

2. The method for manufacturing a high voltage super junction VDMOS device terminal structure according to claim 1, characterized in that: The S3 step includes the following sub-steps: S301, performing a first ion implantation in a region on the top of the epitaxial layer located inside the terminal through a photolithography pattern, and then diffusing it under high temperature annealing conditions to connect it with the main junction region of the device to form a first doped region, wherein the conductivity type of the first doped region is opposite to that of the epitaxial layer; S302, performing a second ion implantation on a region on the top of the epitaxial layer and adjacent to the outer side of the first doped region through a photolithography pattern to form a second doped region, wherein the conductivity type of the second doped region is consistent with the conductivity type of the first doped region, and the doping concentration thereof is lower than the doping concentration of the first doped region; S303, performing a third ion implantation in a region on the top of the epitaxial layer outside the terminal through a photolithography pattern to form a third doped region, wherein the conductivity type of the third doped region is consistent with the conductivity type of the epitaxial layer.

3. The method for manufacturing a high voltage super junction VDMOS device terminal structure according to claim 1, characterized in that: In the step S4, deep groove etching is performed through the photolithography pattern, and the terminal grooves are arranged at the same regular intervals in the lateral direction; the etching depth is the thickness of the epitaxial layer, or the etching depth exceeds the thickness of the epitaxial layer by 1 μm to 2 μm.

4. The method for manufacturing a high voltage super junction VDMOS device terminal structure according to claim 1, characterized in that: The S5 step includes the following sub-steps: S501, growing a layer of silicon dioxide film on the sidewall and bottom of the terminal trench by thermal oxidation method; S502 , etching the silicon dioxide film layer at the bottom of the terminal trench by dry etching, retaining the silicon dioxide film on the sidewall, and forming a vertical field plate dielectric layer.

5. The method for manufacturing a high voltage super junction VDMOS device terminal structure according to claim 1, characterized in that: The S6 step includes the following sub-steps: S601, growing a first resistive field plate material by a chemical epitaxial method to fill the terminal trench, so that the first resistive field plate material is connected to the substrate; S602 , etching away the first resistance field plate material and the transition oxide layer on the top of the epitaxial layer using photolithography patterns, and retaining the first resistance field plate material in the terminal trench to form a vertical resistance field plate.

6. The method for manufacturing a high voltage super junction VDMOS device terminal structure according to claim 1, characterized in that: The S7 step includes the following sub-steps: S701, depositing a thick oxide layer on the top of the epitaxial layer to form a top oxide layer; S702, etching to form a contact through hole penetrating the top oxide layer above each vertical resistance field plate and above the second doping region between each two adjacent groups of vertical resistance field plates; S703 , depositing a layer of second resistance field plate material on the top oxide layer, wherein the second resistance field plate material extends into each contact through hole and contacts the top of the epitaxial layer to form a horizontal resistance field plate.

7. The method for manufacturing a high voltage super junction VDMOS device terminal structure according to claim 1, characterized in that: The step S8 includes the following sub-steps: S801, etching and removing the top oxide layer and the horizontal resistance field plate on the inner side above the epitaxial layer to expose a portion of the first doped region; etching and removing the top oxide layer and the horizontal resistance field plate on the outer side above the epitaxial layer to expose a portion of the third doped region; S802, forming a source metal electrode connected to the first doped region on the inner side above the epitaxial layer, and forming a floating metal electrode connected to the third doped region on the outer side above the epitaxial layer; S803, thinning the back side of the substrate, and forming a drain metal electrode on the back side of the substrate by metal evaporation.

8. The method for manufacturing a high-voltage super junction VDMOS device terminal structure according to any one of claims 1 to 7, characterized in that: The first doped region is implanted with boron ions at a concentration of 3e15cm -2 The second doped region is implanted with boron ions at a concentration of 3e13cm -2 The third doping region is implanted with arsenic ions or phosphorus ions at a concentration of 5e15cm -2 .

9. The method for manufacturing a high voltage super junction VDMOS device terminal structure according to any one of claims 1 to 7, characterized in that: The thickness of the vertical field plate dielectric layer is 0.2 μm, the thickness of the vertical resistance field plate is 0.8 μm, the width of the terminal groove is 1.2 μm; the spacing between the centers of adjacent terminal grooves is 4 μm; and / or The resistivity of the heavily doped conductive substrate is 2.8Ω·cm; the first resistance field plate material and the second resistance field plate material are both semi-insulating polysilicon materials, the resistivity of the vertical resistance field plate is le10Ω·cm; the resistivity of the horizontal resistance field plate is le7Ω·cm.

10. A high voltage super junction VDMOS device terminal structure, characterized in that: It comprises a heavily doped conductive substrate and an epitaxial layer arranged on the heavily doped conductive substrate, wherein the lower end of the heavily doped conductive substrate is connected to a drain electrode; a first doped region, a second doped region and a third doped region are formed by implanting a top region of the epitaxial layer, wherein the first doped region is located inside a terminal, the second doped region is located outside the first doped region, and the third doped region is located outside the terminal region; the implantation type of the first doped region and the second doped region is opposite to the conductivity type of the epitaxial layer; the implantation type of the third doped region is the same as the conductivity type of the epitaxial layer; A plurality of groups of terminal grooves are formed on the epitaxial layer, and the terminal grooves penetrate the epitaxial layer; a vertical resistance field plate is respectively arranged in each of the terminal grooves, and a vertical field plate dielectric layer is arranged between the vertical resistance field plate and the inner wall of the terminal groove; a top oxide layer is arranged on the epitaxial layer, and a contact through-hole penetrating the top oxide layer is respectively opened on the top of each vertical resistance field plate and on the top of the second doped region between each two adjacent groups of vertical resistance field plates, a first notch is formed on the inner side of the top oxide layer, and the first notch exposes a part of the first doped region; a second notch is formed on the outer side of the top oxide layer, and the second notch exposes a part of the third doped region; a horizontal resistance field plate is arranged on the top oxide layer, and the horizontal resistance field plate extends into each contact through-hole and contacts with the top of the epitaxial layer, a source metal electrode is formed in the first notch, and a floating metal electrode is formed in the second notch.

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