Method for manufacturing semiconductor assembly

Abstract

A method of manufacturing a batch of semiconductor assemblies is disclosed. The method includes coupling a plurality of dies to a plurality of die pads, the plurality of die pads disposed in pairs in a 2 * n array on a lead frame, each pair of die pads having opposite orientations. Each die pad defines a respective semiconductor assembly. The method also includes coupling a plurality of connectors to the plurality of dies. The method further includes molding a molten shell over the plurality of semiconductor assemblies using a mold surrounding the 2 * n array, the molten shell at least partially surrounding the 2 * n array. The method further includes cutting the molten housing at at least three locations partially surrounding a respective one of the plurality of semiconductor assemblies, and stamping a lead side of the semiconductor assembly to define a respective housing from the molten housing, and singulating the semiconductor assembly from the 2 * n array.

Description

[0001] The present invention relates to a method for manufacturing a batch of semiconductor assemblies, a semiconductor assembly and a semiconductor assembly array.

[0002] Semiconductor assemblies such as transistors are manufactured as layered assemblies including components such as die pads, dies, connectors, and housings. The housing provides a protective function and at least partially surrounds the die and other components that form part of the semiconductor assembly. The housing may also be referred to as an encapsulation.

[0003] It is desirable to produce semiconductor assemblies (e.g., transistors) with as low a component resistance as possible to reduce operating losses associated with heating. One way to reduce component resistance is to increase the size of the die, which is an electronic component coupled to a die pad. That is, a larger die can provide a semiconductor assembly with a lower component resistance. However, the size of the die is limited by the available area on the die pad to which the die is coupled. It is also desirable to maintain a specific footprint of the semiconductor assembly (i.e., not increase the overall size of the semiconductor assembly) to provide supply chain continuity and maintain compatibility. It is also desirable to improve the manufacturing efficiency of the semiconductor assembly.

[0004] There is a need to overcome the shortcomings associated with existing semiconductor assemblies and related manufacturing methods, whether or not mentioned in this document.

[0005] US2021 / 0225744 A1 discloses a package comprising a carrier, an electronic component located on the carrier, an encapsulation body encapsulating at least a portion of the carrier and the electronic component, and at least one lead extending beyond the encapsulation body and having a stamped surface, wherein at least a portion of at least one side of the encapsulation body has a saw-like texture.

[0006] According to a first aspect of the present invention, there is provided a method of manufacturing a batch of semiconductor assemblies, comprising:

[0007] coupling a plurality of dies to a plurality of die pads arranged in pairs in a 2×n array on a lead frame, each pair of die pads having opposite orientations, wherein each die pad defines a respective semiconductor assembly;

[0008] coupling a plurality of connectors to the plurality of dies;

[0009] molding a fused shell over the plurality of semiconductor assemblies using a mold surrounding the 2×n array, the fused shell at least partially surrounding the 2×n array; and

[0010] The fused shell is cut at at least three locations partially surrounding a respective one of the plurality of semiconductor assemblies, and the lead sides of the semiconductor assemblies are punched to define respective shells from the fused shell and singulate the semiconductor assemblies from the 2×n array.

[0011] A batch of semiconductor assemblies may be referred to as a plurality of semiconductor assemblies.

[0012] The lead frame and / or the die pad may also be described as a plate of conductive material.The die pad may be made of a copper alloy or entirely of copper.

[0013] The die pads are arranged in pairs (each pair having opposite orientations) in a 2×n array on the lead frame can also be described as being defined by a number of pairs of die pads arranged in a back-to-back manner. For example, for a given pair, the lead sides of the die pads face in opposite directions. In other words, the second sides (e.g., opposite the lead sides) of the die pads (which form opposite pairs) are close to each other.

[0014] Each die pad defining a corresponding semiconductor assembly may also be described as each respective die pad continuing to form a separate semiconductor assembly.

[0015] The die may be a single component or may include multiple constituent components. The die is preferably coupled to the die pad using solder. Coupling the die to the die pad may also be described as attaching the die to the die pad. The die may be a silicon chip. The multiple dies may be coupled to a corresponding multiple die pads (e.g., one die per die pad).

[0016] The connector may include a fixture. The connector may be wire bonded to the die, or coupled using any other internal connector (e.g., a strip-like ribbon). The fixture may include one or more legs. The fixture may be described as a conductive body, through which the semiconductor assembly is connected or connectable to an external circuit in use. The fixture may be coupled to the die pad by coupling to the die. In other words, the fixture may be described as being indirectly coupled to the die pad. The fixture is preferably coupled to the die by solder. The plurality of connectors may be coupled to a corresponding plurality of dies (e.g., one connector per die pad).

[0017] A molten shell is intended to refer to a joint shell molded in a single mold. For example, a molten shell may be molded over multiple pairs of die pads defined by a 2×n array. Cutting the molten shell may include using a reciprocating or rotating blade (e.g., sawing), a laser, or a water jet cutting process. Cutting the molten shell at at least three locations may also be described as making three cuts through the molten shell (e.g., along three lengths). Cutting the molten shell at at least three locations may also be described as cutting the molten shell along at least three lengths. For a quadrilateral semiconductor assembly, the at least three locations of the cut molten shell preferably correspond to the three sides of this quadrilateral. The at least three locations are preferably associated with each other as long as the start of one location corresponds to the end of an adjacent location. For a quadrilateral, the at least three locations may be the sides of a U-shape (e.g., three of the four sides of the perimeter of the quadrilateral). Cutting is intended to refer to an operation of gradually removing material along a contour (e.g., by sawing, laser cutting, or a water jet cutting process). The cutting operation may be performed on the molten shell and the die pads (e.g., tie bars). Cutting encompasses operations where there is relative lateral motion between the cutting edge and the array (e.g., as opposed to pure axial motion, such as punching). For example, the array may be moved relative to the cutting edge (e.g., relative to a rotary saw). Alternatively, the cutting tool may be moved relative to the array (e.g., in the case of laser cutting or water jetting).

[0018] Cutting the fused shell at at least three locations partially surrounding a respective one of the plurality of semiconductor assemblies may include cutting the shell (of the respective semiconductor assembly) at any and all adjoining sides.

[0019] The housing may also be described as a plastic container or shield. The housing may be described as encapsulating the die. The housing advantageously reduces the risk of contaminants (e.g., moisture) penetrating into the semiconductor assembly. The housing preferably extends between the first and second major faces of the die pad. The housing may be plastic. The housing may also be described as being made of a polymer. The housing is preferably manufactured using an injection molding process, wherein at least partially melted material is molded into a desired housing shape. The plastic may be a thermoplastic (e.g., a thermosetting polymer).

[0020] Punching the lead side of a semiconductor assembly can be described as punching a connector (e.g., a fixture) at the lead side. Punching the lead side of a semiconductor assembly can be described as punching a free exposed edge of a molten shell (i.e., an edge or side below the molten shell that is not adjacent to another semiconductor assembly and is not attached to a lead frame at this side by one or more tie rods). Punching is intended to refer to an operation in which a single action (e.g., a downward stroke of a punch) shears material to remove material. Punching operations can only be performed on connectors (e.g., not on molten shells). Punching covers operations in which there is only relative axial movement between the cutting edge and the array (e.g., as opposed to lateral movement, such as cutting). Punching covers operations in which the array is fixed in place and only the punch moves.

[0021] Singulating the semiconductor assembly from the 2xn array may also be described as separating or detaching the semiconductor assembly from the 2xn array. Alternatively, it may be described as cutting the semiconductor assembly from the 2xn array.

[0022] Advantageously, the present invention means that the second stamping operation at the non-lead side of the semiconductor assembly can be omitted, in favor of the cutting step. This in turn means that the size of the die accommodated by the die pad can be advantageously increased (providing an advantageous reduction in component resistance of up to about 20%). Furthermore, the density of the die pads on the lead frame can be increased, thereby achieving a desired reduction in (expensive) wasted lead frame / die pad material (e.g. copper), with a corresponding increase in cost efficiency. The present invention also advantageously allows a thicker housing to be molded, which improves reliability and reduces warping during manufacturing. Since the molten housing is sawn at at least three locations, the risk of damage to the housing during the stamping operation is also reduced.

[0023] Molding the fused shell may include defining a groove extending at least partially around one of the plurality of semiconductor assemblies.

[0024] The groove may also be described as a depression or a cavity. The groove may be described as an absence of material. The groove may be linear (e.g., extending in a straight line) or may be at least partially arcuate. The groove extending at least partially around one of the plurality of semiconductor assemblies may be described as the groove at least partially defining a periphery of one of the plurality of semiconductor assemblies (after singulation).

[0025] Advantageously, the inclusion of the grooves reduces the amount of material that needs to be removed by the cutting process. Thus, tool wear is reduced, and cutting can be performed more quickly. Furthermore, by defining the grooves as part of the molding process, rather than introducing material into the mold and removing it later, the material is never present. Thus, material waste is reduced.

[0026] The groove may extend continuously around the three locations where the molten shell partially surrounds a respective one of the plurality of semiconductor assemblies.

[0027] The groove extending continuously around the three positions of the molten shell can be described as the groove extending continuously around three lengths defined in the molten shell. The groove extending continuously may mean that a single groove is defined, but this single groove includes multiple parts. The combination or sum of the parts can define the entire groove. For example, the groove extending continuously around three positions can mean that the groove is substantially U-shaped (e.g., three linear parts, each linear part is at least connected to each other, and each main part is 90 degrees between them).

[0028] Advantageously, the groove extends continuously around the three locations of the molten shell and partially surrounds a respective one of the plurality of semiconductor assemblies, meaning that a large portion of the periphery of the respective semiconductor assembly is defined by the groove. Thus, the cutting process is more efficient, since less material has to be removed in order to singulate out the semiconductor assemblies.

[0029] The grooves may extend intermittently around the three locations where the molten shell partially surrounds a respective one of the plurality of semiconductor assemblies.

[0030] The groove extends intermittently and is intended to mean that the groove is not a continuous groove. For example, the groove can be considered to be defined by a plurality of parts, but these parts are not adjacent to each other. That is, there may be a "complete" thickness of the (molten) shell between two adjacent parts.

[0031] The recess may be at least partially tapered.

[0032] By the groove being at least partially tapered is intended to mean that the groove has inclined sides (eg chamfered edges).

[0033] Advantageously, the recess is at least partially tapered to facilitate the moulding process and avoid introducing stress concentrations that may be caused by sharp corners.

[0034] The recess may include a planar surface proximate to the corresponding die pad.

[0035] A groove comprising a flat surface proximate to the corresponding die pad may be described as a lower surface of the groove having a flat bottom. In other words, the groove may have a linear lower surface when viewed in cross section.

[0036] Advantageously, the inclusion of flat bottom grooves provides ease of singulation and reduces alignment tolerances of the cutting process.

[0037] The grooves may extend through at least 1 / 3 of the thickness of the respective housing.

[0038] The groove extending through at least 1 / 3 of the thickness of the respective shell may also be described as defining a minimum depth of the groove. Assuming that the cutting operation may not change the thickness of the shell (only separate the molten shell into a plurality of single shells of equal thickness), the thickness of the respective shell may also correspond to the thickness of the molten shell. In other words, the groove may extend through at least 1 / 3 of the thickness of the molten shell.

[0039] It has been advantageously found that extending the grooves through at least 1 / 3 of the thickness of the housing increases the efficiency of the sawing process and facilitates singulation of the semiconductor assembly.

[0040] Punching the lead side of the semiconductor assembly to define individual shells may be performed prior to cutting the fused shells at at least three locations.

[0041] Advantageously, stamping the lead side of the semiconductor assembly may include forming one or more leads of the connector. Stamping the lead side of the semiconductor assembly to define the individual shells prior to cutting the fused shells advantageously means that the leads are exposed while the fused shells remain intact. Thus, further processing (e.g. plating) may be performed on the leads while the array of die pads and the semiconductor assembly remain coupled to the lead frame (and are therefore constrained in their positions, thereby facilitating manufacturing tolerances).

[0042] Cutting the fused shell at at least three locations may singulate semiconductor assemblies from the 2xn array.

[0043] Cutting at at least three locations can be performed simultaneously.Semiconductor assemblies from one array or all arrays can be singulated simultaneously by cutting.

[0044] Advantageously, it has been found that singulating the semiconductor assembly via a cutting step avoids crack formation in the corners of the die and reduces delamination compared to singulation by a punching step. Further advantageously, by performing singulation in the cutting step, the array is still defined prior to the cutting step. It has been found that it is easier to align the array relative to the cutting tool for the cutting operation.

[0045] The lead frame may include a plurality of 2×n arrays of die pads, pairs of die pads in each 2×n array being arranged in opposite orientations; and

[0046] Molding the fused shell may include molding a plurality of fused shells, each fused shell being used for the plurality of 2

[0047] Each of the die pads of the ×n array.

[0048] The lead frame may include two or more die pads in a 2xn array.

[0049] One shell for each of the plurality of 2xn arrays of die pads may also be described as there being a corresponding fused shell for each 2xn array of die pads.

[0050] Advantageously, by providing multiple 2×n arrays on a single lead frame, semiconductor assemblies can be manufactured more efficiently. For example, waste can be reduced due to the presence of multiple 2×n arrays, and other processes can be performed on a greater number of semiconductor assemblies simultaneously.

[0051] The multiple molten shells are molded simultaneously by supplying molten material from a common source using a respective runner for each molten shell.

[0052] Advantageously, molding the plurality of molten shells simultaneously can increase the efficiency of manufacturing the molten shells. For example, any number of 2xn arrays of die pads can be made using a single source of molten material.

[0053] Stamping the lead side of the semiconductor assembly may include forming one or more displaced leads.

[0054] A displacement lead is intended to refer to a lead (e.g., leg) of a connector that includes at least one change in direction after extending through a housing. For example, a displacement lead may have a generally S-shape, J-shape, U-shape, or other geometric shape (e.g., when viewed in cross-section).

[0055] Advantageously, the displaced leads have been found to provide improved board level reliability by acting as stress relievers when the semiconductor assembly is mounted in a circuit. Forming the displaced leads in a stamping step eliminates the need to stamp the lead side and then separately form the displaced leads in a subsequent step of the process.

[0056] According to a second aspect of the present invention, there is provided a semiconductor assembly manufactured using the method according to the first aspect of the present invention.

[0057] According to a third aspect of the present invention, there is provided a semiconductor assembly array, comprising:

[0058] a lead frame comprising a 2×n array of die pads arranged in pairs, each pair of die pads having opposite orientations, wherein each die pad defines a respective semiconductor assembly;

[0059] a plurality of dies coupled to a corresponding plurality of die pads;

[0060] a plurality of connectors coupled to respective ones of the plurality of dies;

[0061] a fused shell molded over the plurality of semiconductor assemblies, the fused shell at least partially surrounding the 2×n array; wherein

[0062] Each of the plurality of semiconductor assemblies includes one or more leads extending from a lead side of the semiconductor assembly.

[0063] The die pad may also be described as a plate of conductive material. The die pad may be fabricated from copper.

[0064] The die may be a single component or may include multiple constituent components. The die is preferably coupled to the die pad using solder. Coupling the die to the die pad may also be described as attaching the die to the die pad. The die may be a silicon chip.

[0065] The connector may include a clamp. The connector may be wire bonded to the die. The clamp may include one or more legs. The clamp may be described as a conductive body through which, in use, the semiconductor assembly is connected or connectable to an external circuit. The clamp may be coupled to the die pad by coupling to the die. In other words, the clamp may be described as being indirectly coupled to the die pad. Preferably, the clamp is coupled to the die via solder. The leads may be integrated with the sealing strip (i.e., the sealing strip may not have been removed, if present). Therefore, a "lead" may also be described as a protruding portion of the connector (e.g., protruding out of the housing).

[0066] The housing may also be described as a plastic container or shield. The housing may be described as encapsulating the die. The housing advantageously reduces the risk of contaminants (e.g., moisture) penetrating into the semiconductor assembly. The housing preferably extends between the first and second major faces of the die pad. The housing may be plastic. The housing may also be described as being made of a polymer. The housing is preferably manufactured using an injection molding process, wherein at least partially melted material is molded into a desired housing shape. The plastic may be a thermoplastic (e.g., a thermosetting polymer).

[0067] Advantageously, the semiconductor assembly array described above improves the efficiency of the manufacturing process by molding a fused shell over a plurality of semiconductor assemblies. Thus, the density of die pads on the lead frame and thus the number of semiconductor assemblies that can be manufactured is increased.

[0068] Each of the plurality of semiconductor assemblies may include one or more displaced leads extending from a lead side of the semiconductor assembly. Each of the plurality of semiconductor assemblies may include one or more (optionally, displaced) leads extending from a single lead side of the semiconductor assembly. That is, for each semiconductor assembly, the leads may extend from only one (lead) side. For a 2×n array, the leads of the connector may extend from only one of the two sides of the 2×n array. That is, for the first row of the 2×n array, the leads extend only from the lead sides of those semiconductor assemblies. For the second row (i.e., another row) of the 2×n array, the leads extend only from the lead sides of those (different) semiconductor assemblies.

[0069] A displacement lead is intended to refer to a lead (e.g., leg) of a connector that includes at least one change in direction after extending through a housing. For example, a displacement lead may have a generally S-shape, J-shape, U-shape, or other geometric shape (e.g., when viewed in cross-section).

[0070] According to a fourth aspect of the present invention, there is provided a method for manufacturing a batch of semiconductor assemblies, comprising:

[0071] coupling a plurality of dies to a plurality of die pads disposed in an array on a lead frame, wherein each die pad defines a corresponding semiconductor assembly;

[0072] coupling a plurality of connectors to the plurality of dies;

[0073] molding a fused shell over the plurality of semiconductor assemblies using a mold surrounding the array, the fused shell at least partially surrounding the array; and

[0074] The fused shell is cut at at least two locations partially surrounding a respective one of the plurality of semiconductor assemblies, and the single lead sides of the semiconductor assemblies are punched to define the respective shells from the fused shell and singulate the semiconductor assemblies from the array.

[0075] The array may be a 1×n array or a 2×n array. Punching the single lead side of the semiconductor assembly may also be described as punching only one side of the semiconductor assembly. The combination of cutting at at least two locations and punching the single lead side singulates the semiconductor assembly.

[0076] The plurality of dies may be coupled to a corresponding plurality of die pads.The plurality of connectors may be coupled to a corresponding plurality of dies.

[0077] According to a fifth aspect of the present invention, there is provided a semiconductor assembly comprising:

[0078] Die pad;

[0079] a die coupled to the die pad;

[0080] a connector coupled to the die, the connector comprising one or more leads extending from a single lead side of the die pad; and

[0081] a housing extending to three sides of the die pad;

[0082] Wherein the one or more leads are displaced leads.

[0083] The die pad may also be described as a plate of conductive material. The die pad may be made of copper (eg, alloys thereof).

[0084] The die may be a single component or may include multiple constituent components. The die is preferably coupled to the die pad using solder. Coupling the die to the die pad may also be described as attaching the die to the die pad. The die may be a silicon chip.

[0085] The connector may include a clamp. The connector may be wire bonded to the die. The clamp may include one or more legs. The clamp may be described as a conductive body through which the semiconductor assembly is connected or connectable to an external circuit in use. The clamp may be coupled to the die pad by coupling to the die. In other words, the clamp may be described as being indirectly coupled to the die pad. Preferably, the clamp is coupled to the die by solder. The connector may include a plurality of constituent connectors (e.g., a source connector and a gate connector).

[0086] The housing may also be described as a plastic container or shield. The housing may be described as encapsulating the die. The housing advantageously reduces the risk of contaminants (e.g., moisture) penetrating into the semiconductor assembly. The housing preferably extends between the first and second main faces of the die pad. The housing may be plastic. The housing may also be described as being made of a polymer. The housing is preferably manufactured using an injection molding process, wherein at least partially melted material is molded into a desired housing shape. The plastic may be a thermoplastic (e.g., a thermosetting polymer). The three sides of the housing extending to the die pad may be further described as the housing extending to the three edges of the die pad. The three sides are preferably each of the non-lead sides of the die pad.

[0087] One or more leads extend from a single lead side of the die pad to mean that the leads on the entire semiconductor assembly extend from only one side. In other words, except for the single lead side, the other sides do not have leads.

[0088] A displacement lead is intended to refer to a lead (e.g., leg) of a connector that includes at least one change in direction after extending through a housing. For example, a displacement lead may have a generally S-shape, J-shape, U-shape, or other geometric shape (e.g., when viewed in cross-section).

[0089] The optional and / or preferred features set out herein for each aspect of the invention may also apply to any other appropriate aspect of the invention.

[0090] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0091] Figure 1 is a perspective view of a semiconductor assembly according to an embodiment of the present invention;

[0092] Figure 2yes Figure 1 A partially transparent view of a semiconductor assembly;

[0093] Figure 3 It is taken from the top (no leads) side Figure 1 and Figure 2 A partially transparent view of a semiconductor assembly;

[0094] Figure 4 yes Figures 1 to 3 A partially transparent plan view of a semiconductor assembly;

[0095] Figure 5 It is taken from the lead (or bottom) side Figures 1 to 4 A partially transparent view of a semiconductor assembly;

[0096] Figure 6 yes Figures 1 to 5 A side view of a semiconductor assembly;

[0097] Figure 7 is with Figure 6 The view shown in corresponds to a partially transparent side view of a semiconductor assembly;

[0098] Figure 8 yes Figures 1 to 7 A partially transparent underside view of a semiconductor assembly;

[0099] Figures 9a to 9i Schematic diagram showing the manufacturing Figures 1 to 8 Method for semiconductor assembly;

[0100] Fig.10 yes Figure 9a , showing a lead frame including two 5×2 arrays of die pads for use in manufacturing the semiconductor assembly of the preceding FIG;

[0101] Fig.11 yes Figure 9f , also showing corresponding side and end views;

[0102] Fig.12 yes Fig.11 A perspective view of the semiconductor assembly array shown in after the mold runner is removed;

[0103] Fig.13 yes Figure 9g A perspective view of the semiconductor assembly array shown in after a stamping operation is performed;

[0104] Fig.14 Generally corresponds to Figure 9f , which further illustrates the mold segment design and end view of the semiconductor assembly array during the molding step;

[0105] Fig.15 is corresponding to Fig.14 Side view of

[0106] Fig.16 yes Fig.14 an enlarged view of a portion of;

[0107] Fig.17 Corresponds to Fig.16 , wherein a mold segment is removed;

[0108] Fig.18 and Fig.19 shows a semiconductor assembly according to another embodiment (partially transparent plan view and partially transparent lower side view, respectively);

[0109] Fig. 20 and Fig.21 shows a semiconductor assembly according to another embodiment (partially transparent plan view and partially transparent lower side view, respectively); and

[0110] Figures 22a to 22i A method of manufacturing a batch of semiconductor assemblies according to another embodiment is schematically illustrated.

[0111] Steering Figure 1 , provides a perspective view of a semiconductor assembly 2 according to an embodiment. The semiconductor assembly 2 may also be referred to as a semiconductor component or component. Figure 1 As shown in FIG. 1 , the semiconductor assembly 2 includes a housing 4 and leads 6a to 6d (collectively referred to as leads 6). The housing 4 surrounds at least a portion of the semiconductor assembly 2 and provides a protective function. The housing 4 may also be referred to as an encapsulation. The housing 4 is typically a plastic material, such as a thermosetting polymer.

[0112] The leads 6 may also be referred to as legs. The semiconductor assembly 2 is connected to an operating circuit via the leads 6. The leads 6 are therefore electrically conductive. The leads 6 are preferably made of copper, such as a copper alloy.

[0113] Figure 1 The image is taken from the perspective of the first main surface 8 (eg, the upper side). Figure 1 It is not shown in the figure, but the second main surface (eg the lower side) is opposite to the first main surface 8 .

[0114] The main face is at least partially defined by an outer periphery 12, which in the illustrated embodiment is defined by four sides. The sides may be referred to as a first side 14, a second side 16, a third side 18, and a lead side or fourth side 20. The lead side refers to the side of the die pad, housing, or semiconductor that extends out of the lead 6. In the illustrated embodiment, the first, second, and third sides 14, 16, 18 and the lead side 20 completely define the periphery 12 of the housing 4. In other embodiments, there may be more or fewer sides, and thus different geometric shapes may be defined. That is, in the illustrated embodiment, the outer periphery 12 is quadrilateral (e.g., rectangular).

[0115] Despite Figure 1 Only the first side 14 is visible in the figure, but each of the first to third sides 14, 16, 18 has one or more tie bars of the die pad protruding therethrough. Figure 9a and Fig.10 ), the tie bars couple the die pads (i.e., the conductive material sheet to which the other components of the semiconductor assembly are attached) to the lead frame (which includes a plurality of die pads). To singulate the semiconductor assemblies 2 from the array (i.e., separate the individual semiconductor assemblies), the tie bars and housing are cut. Figure 1 In the embodiment, the tie rods are marked 22, 24. Further tie rods extend from the second and third sides 16, 18 and are Figure 2 The tie bars are integral with the die pad and are therefore made of whatever material the die pad is made of, for example copper, such as a copper alloy.

[0116] The housing 4 also includes a chamfered edge 26. In the illustrated embodiment, the chamfered edge 26 extends completely around the housing 4 (e.g., around its periphery). That is, each of the first to fourth sides 14, 16, 18, 20 includes a corresponding chamfered edge that engages with each other to define a closed loop. However, in other embodiments, this may not be the case. For example, the chamfer may extend only around some of the sides, or may be discontinuous in nature (e.g., as opposed to continuous in the illustrated embodiment). In some embodiments, the chamfered edge 26 may be omitted entirely (i.e., the housing 4 may not include any such bevel). It is also noteworthy that the first side 14 includes a lip 28 that is at least partially defined by the chamfered edge 26. The chamfered edge 26 therefore does not intersect the first face 24a of the first side 14 at the vertex (e.g., in a flush manner). Instead, the alignment of the chamfer 26 relative to the first face 24a defines the lip 28. As will be described in conjunction with subsequent figures (e.g., Fig.16 and Fig.17) is described as forming lip 28 when a sawing operation is performed to separate (individual) semiconductor assemblies 2 from an array (e.g., comprising a plurality of semiconductor assemblies). Thus, lip 28 may be described as being due to manufacturing tolerances remaining after the sawing operation is performed. For completeness, and in Figure 1 As can be seen only partially in the figure, each of the second side 16 and the third side 18 includes a respective lip 30, 32. The lips 28, 30 and 32 can be described as first, second and third portions of the overall lip extending around the three sides 14, 16, 18 of the housing 4. It is worth noting that no such lip is present on the lead side 20 (since this side of the semiconductor assembly 2 is not "cut", but rather stamped). Figure 1 As can be appreciated from the drawings, the leads 6 extend only from a single (lead) side 20 of the semiconductor assembly. Each of the first to third sides 14, 16, 18 does not have any leads. In other words, the corresponding connector of which the leads 6 form a part does not extend through any of the first to third sides 14, 16, 18 (e.g., any non-lead side). Figures 14 to 17 As will be appreciated in the drawings, the combination of the chamfered edge 26 and the lip 30 advantageously facilitates removal of the package (e.g., a semiconductor assembly having a molded housing) from the mold cavity. For completeness, the leads 6 are part of the connector and protrude outwardly beyond the housing 4, in contrast to the tie bars 22, 24 which are integral with the die pad and couple the die pad to the surrounding lead frame during manufacturing (e.g., see FIG. Figure 9a ).

[0117] Figure 1 It is also shown that each of the leads 6 is a displaced lead. Displaced leads are intended to mean that the lead changes direction along its extent. Figure 1 The gull-wing lead shown in is one example of a displaced lead, but other geometries are possible (e.g., a J-shaped lead is another example). Any lead that undergoes a change in direction (e.g., contains a bend, fillet, or chamfer along its extent) is considered a displaced lead.

[0118] As will be described in conjunction with the following figures, the inventors have identified an improved manufacturing process for making semiconductor assemblies 2, wherein the lead side 20 (only) of the semiconductor assembly 2 is stamped (to define the leads 6), and the three sides 14, 16, 18 of the shell 4 are cut to separate the fused shells (e.g., a shell including one or more individual shells in a joint manner) to singulate or separate the semiconductor assemblies 2 from the array. This will be described in conjunction with the following figures showing the manufacturing method Figures 9a to 9i A more detailed description is given.

[0119] Steering Figure 2 , provides Figure 1The partially transparent view refers to the opacity of the housing 4 (in Figure 2 is partially transparent), which enables the opaque internal components of the semiconductor assembly 2 to be seen.

[0120] Starting first with the die pad 34, the die pad 34 forms the effective base of the semiconductor assembly 2 to which the other components are attached. The die pad 34 is a plate-like component. The die pad 34 is generally quadrilateral and is fabricated from a conductive material such as copper (e.g., including copper alloys). As previously described, during manufacturing, the tie bars 22, 24 (on the first side 14) of the die pad 34 are how the die pad 34 is secured in the lead frame that includes the die pad array. Figure 2 Also visible in the figure are tie bars 36, 38 extending through the second side 16, and tie bars 40, 42 extending through the third side 18. Thus, in the illustrated embodiment, each of the non-lead sides (e.g., the first to third sides 14, 16, 18) includes a plurality of tie bars (e.g., two tie bars). However, in other embodiments, each of the non-lead sides (e.g., the first to third sides 14, 16, 18) may include one (e.g., a single) tie bar. Thus, preferably, each of the non-lead sides (e.g., the first to third sides 14, 16, 18) includes one or more tie bars.

[0121] Solder layer 44 is coupled to die pad 34 (only Figure 2 4). Solder layer 44 is used to secure die 46, 48 to die pad 34. Reference numerals 46, 48 collectively represent the die. Layer 46, typically silicon nitride, is the non-solderable surface of the die. Adjacent layer 48 is the solderable surface of the die (e.g., TiNi(V)Ag). For completeness, 48a is the solderable surface of the gate portion of the die and is collectively referred to as reference numeral 48. Thus, the solderable surface of the die has two components. Figure 2 Another layer of solder 50 can just be seen in FIG. 4, which is applied to the tube core 48. The solder 50 is used to couple the connector 52 to the tube core 48. The connector 52 may be referred to as a clamp. In the embodiment shown, the connector 52 includes a source connector 53 and a gate connector 55 (which may be referred to as a component connector). Therefore, the connector 52 is a multi-component connector. The source connector 53 and the gate connector 55 are originally part of a single-piece connector, and they are separated (for example, by comparing Fig.12 and Fig.13Observation). Source connector 53 may be referred to as a source clamp. Gate connector 55 may be referred to as a gate clamp. Lead 6 forms part of connector 52. Specifically, leads 6a to 6c form part of source connector 53 (and therefore may be referred to as source leads), and lead 6d forms part of gate connector 55 (and therefore may be referred to as gate leads). In other embodiments, the connector may include more or fewer constituent connectors. For example, in the case where the semiconductor assembly is a diode, the assembly may include a single clamp (e.g., a single one-piece connector). The connector may also include three or more constituent connectors, particularly in the case where the device has more than two terminals on the upper surface. In other embodiments, the number of leads may be as low as one. That is, there is at least one lead. The four leads 6a to 6d in the example shown are only a non-limiting example.

[0122] Steering Figure 3 , provides an end view of the semiconductor assembly 2 as viewed from the second side 16. In this way, the tie bars 36, 38 are visible because they protrude from the second side 16. Figure 3 Also shown is the layered nature of the assembly of die pad 34, solder layer 44, die 46, solder layer 50, and connector 52 (with source connector 53 and gate connector 55). For completeness, Figure 3 The first main face 8 is also shown as the upper side, and the second main face 10 is shown as the lower side. Figure 3 The end view of FIG. 2 also more clearly shows the chamfer 26 and the first portion of the lip 28 . Figure 3 The first portion showing the lip 28 may be considered to form a step between the main face 24a (of the first side 14) and the chamfer 26. A corresponding arrangement is provided on the opposite side, ie the third side 18.

[0123] Go to Figure 4 , providing a partially transparent view of the semiconductor assembly 2 taken from the perspective of the first main face 4 . Figure 4 It can also be described as a partially transparent plan view of the semiconductor assembly 2 . Figure 4 Also schematically shown in FIG. 1 are first to third cutting lines 54, 56, 58 and a punching line 60. As suggested, the first to third cutting lines 54, 56, 58 indicate three locations (i.e., lengths) at which the molten shell is cut (e.g., see FIG. 1 ). Figure 9hThe semiconductor assemblies 2 are singulated by stamping the lead side 20 of the semiconductor assembly 2 (i.e., separating the individual semiconductor assemblies 2 from the array). Similarly, the stamping lines 60 schematically indicate the locations at the lead side 20 of the semiconductor assembly 2 that are stamped to separate the lead side 20 from the surrounding lead frame (and optionally singulate the semiconductor assembly 2 from the array). Notably, it should be understood that, depending on the order of the cutting process and the stamping process performed, one or both of these processes may actually separate (e.g., singulate) the semiconductor assembly 2. In other words, if the stamping process is performed first, the semiconductor assembly 2 will still be coupled to the surrounding array / lead frame via the molten shell (and tie bars) (and thus the cutting operation will singulate the semiconductor assembly 2). In a preferred embodiment, the stamping operation is performed first, and the cutting is performed after the stamping.

[0124] As used throughout this document, cutting is intended to refer to the operation of gradually removing material along a contour (e.g., by sawing, laser cutting, or water jet cutting processes). Cutting encompasses operations in which there is relative lateral movement between the cutting edge and the array (to be cut) (e.g., as opposed to purely axial movement, such as punching). For example, the array may be moved relative to the cutting edge (e.g., relative to a rotating saw). Alternatively, the cutting tool may be moved relative to the array (e.g., in the case of laser cutting or water jetting). The cutting operation can be used to cut both ductile materials (e.g., metals) and brittle materials (e.g., plastics). Thus, the cutting operation can be used to cut metals, plastics, or mixtures of both (e.g., composites). An array refers to an arrangement of semiconductor assemblies that have not yet been singulated (e.g., see Figure 9h ). In contrast, stamping is intended to refer to operations where a single motion (e.g., a downward stroke of a punch) shears material to remove material. Stamping encompasses operations where there is only relative axial motion between the cutting edge and the array (e.g., as opposed to lateral motion, such as cutting). Stamping encompasses operations where the array is fixed in place and only the punch moves. Stamping operations can only be used to cut ductile materials (e.g., metals). Thus, stamping operations can be used for metals (e.g., the metal of a die pad), but not for plastics (e.g., not for housings).

[0125] The cutting operation primarily cuts through the molten shell (e.g., through the polymer), but Figure 4 It can also be understood that the tie rods 22, 24, 36, 38, 40, 42 are also cut by the cutting process.

[0126] Figure 4 It is shown that the combination of the three cut lines 54, 56, 58 (ie, three locations) and the punch line 60 defines a closed loop geometry (a quadrilateral [eg, rectangle] in the illustrated embodiment).

[0127] Steering Figure 5, provides a partially transparent end view of the semiconductor assembly 2 taken from the lead end 20 of the semiconductor assembly 2. Thus, Figure 5 Each lead 6 is shown, and the die pad 34 , solder layer 44 , 50 die 46 and connector 52 are also shown.

[0128] Steering Figure 6 and Figure 7 , from the perspective of the first side 14 in a non-partially transparent view and a partially transparent view (respectively Figure 6 and Figure 7 ) provides a side view of the semiconductor assembly 2. Figure 6 and Figure 7 Many of the features shown in have been described in detail and therefore will not be repeated here for the sake of brevity. Figure 6 and Figure 7 Indeed, the geometry of the tie bars 22, 24 and the lead 6a extending through the first side 14 (particularly the major face 24a thereof) is shown, the lead 6a being a displaced lead.

[0129] Now turn to Figure 8 , Figure 8 1 is a partially transparent view of the semiconductor assembly 2 as viewed from the second main surface (eg, the underside) of the assembly 2 . Figure 8 It is shown that a large portion of the die pad 34 is visible at the second main face 10 (e.g., not blocked by the housing 4). Figure 8 The housing 4 is still shown extending to each of the first side 14, the second side 16 and the third side 18. The tie rods 22, 24, 40, 42 are also visible and protrude through the housing 4 as previously described.

[0130] A semiconductor assembly 2 according to the present invention is particularly advantageous in that, for a given semiconductor assembly footprint size (e.g., 5×6 mm), the available space on the die pad 34 for receiving a die 48 is increased. This is achieved by changing the design of the die pad, which in turn can be achieved by changing the process of molding the housing 4 and singulating the semiconductor assembly. Although it is known to mold a housing for each semiconductor assembly individually (i.e., using a mold cavity for each semiconductor assembly) and then stamping each semiconductor assembly on two or more sides for singulation, the inventors have found that by molding a fused (i.e., united) housing over a plurality of semiconductor assemblies provided in a 2×n array, cutting the fused housing at at least three locations, and stamping the lead side of the semiconductor assembly at one side, more of the die pad can be made available to receive the die, and thus the assembly resistance of the manufactured semiconductor assembly can be reduced (due to the increased die size).

[0131] Cutting in at least three locations means that the distance from the die pad to the cut line can be shortened compared to stamping two or more sides. Cutting in at least three locations also means that a higher density of die pads can be provided on a given lead frame, and therefore a semiconductor assembly, can be provided, compared to stamping two or more sides. This is because stamping requires "dead" space (i.e. wasted material) to remove the stamping material. Therefore, the cut line is narrower than the stamping line, thereby reducing the required gap between adjacent die pads, and the same is true for the semiconductor assembly. When each semiconductor assembly has a corresponding cavity in the mold and is singulated by stamping (i.e. on all sides), a larger area is required on the lead frame for the die pad (contrary to the present invention).

[0132] Steering Figures 9a to 9i , schematically showing the Figures 1 to 8 The method for manufacturing a batch of semiconductor assemblies corresponding to the semiconductor assembly 2 shown in FIG. The method can also be described as a process flow.

[0133] from Figure 9a Initially, a lead frame 62 is shown in a plan view. The lead frame 62 is actually a piece of material, from which material is selectively removed, such as by molding or etching, so as to define a plurality of die pads (two of which are labeled 34, 72). The lead frame 62 may also be described as a common lead frame. The lead frame 62 includes two 2×5 arrays 64, 66 of die pads. In this way, each array includes 10 (combined) die pads. The 2×5 array of die pads is an example of a 2×n array of die pads. The 2×n array of die pads is intended to mean that as part of the process, there may be any number of adjacent (opposite) pairs (e.g., the "2" in 2×n). As described above, for ease of understanding, the two die pads are labeled 34, 72. Although in the illustrated embodiment, the lead frame 62 includes two arrays 64, 66, it should be understood that in other embodiments, more or fewer arrays may also be provided. For example, the lead frame may include a single array. As another alternative, the lead frame may include 3, 4, 5 or more arrays.

[0134] Each of the arrays 64, 66 includes die pads arranged in pairs and having opposite orientations. This means that there is at least one plane of symmetry between an adjacent pair of die pads. For example, referring to Figure 9a, and taking the bottom pair of array 64 as an example, arrows 68, 70 overlying die pad 34 and die pad 72 (forming an opposing pair) each point to a corresponding second side or top side of the die pad. The lead side of each die pad 34, 72 is labeled 20 and 74, respectively. Described in a final different manner, a symmetry plane 76 exists between the two die pads 34, 72 that form the (opposing) pair. To further illustrate the definition of opposite orientations, the upper die pad pairs of each of the first array 64 and the second array 66 are also labeled with corresponding arrows pointing to the second side (i.e., opposite to the lead side). As will be described in Fig.10 Described in detail in Fig.10 yes Figure 9a FIG. 6 is an enlarged view of the lead frame 62, and the die pad is also connected to the lead frame 62 by a tie bar (eg, a combination of Figure 2 The tie rods described and shown) are interconnected with each other.

[0135] The opposite orientation of the pairs of die pads in each of the 2×5 arrays 64, 66 is important because it means that a single fused housing can be molded over multiple semiconductor assemblies simultaneously. The density of die pads on the lead frame can be increased, and because of the manufacturing process, less space is required between adjacent die pads, so larger dies can be applied to the die pads. In other words, the clearance that was previously required to fit the mold around the individual semiconductor assemblies to mold a single housing is no longer required (and the clearance reduces the density of die pads on the lead frame).

[0136] Go to Figure 9b , in a subsequent step of the process, a solder layer is printed on each of the die pads. The solder layer can be applied by a screen printing process. For example, taking the die pad 34 as an example, a solder layer 78 is printed. The solder layer can be described as being distributed or applied to the die pads. The solder layer is preferably applied to all the die pads in this single process step. The solder layer is preferably applied to all the die pads at the same time. The solder layer can be applied to the die pads in a continuous manner (for example, one die pad after another). The solder can be distributed from one or more syringes.

[0137] Fig.9c A further step is shown, wherein a plurality of dies are coupled to a corresponding plurality of die pads. Taking die pad 34 as an example, a corresponding die 80 is coupled to die pad 34. The coupled die 80 can be described as the die 80 being placed on solder layer 78. As described above, solder layer 78 is in turn disposed on die pad 34. Fig.9c In the die coupling step, regardless of the number of arrays or the number of die pads, each of the plurality of die pads is provided with a die. Fig.9cIt will be appreciated that at the point where the die is coupled to the die pads, the semiconductor assembly defined by the opposing die pad pair is no longer symmetrical about plane 76. In other words, although the opposing die pad pair (e.g. Figure 9a ) are symmetric about the plane defined between the pair, but this symmetry is not shared by the die applied to the die pad. Instead, the semiconductor assembly defined by each die pad of the opposing pair has rotational symmetry. This is schematically indicated by arrows 79, 81, which point to the gate pad of each semiconductor assembly for a pair of opposing die pads.

[0138] Go to Figure 9d , shows another step in the process, where another layer of solder is printed, this time on the die. Using the die pad 34 as an example, a solder layer 82 is applied to the die 80. The solder layer 82 can also be described as being printed or applied to the die 80. Similar to Figure 9b Solder is applied to each die in the steps shown in FIG. Figure 9b The solder layer 82 is preferably applied to all the dies in this single process step. The solder layer is preferably applied to all the dies simultaneously. The solder layer can be applied to the dies in a continuous manner (e.g., one die after another). The solder can be dispensed from one or more syringes.

[0139] Go to Fig.9e , shows another step of the process, where a plurality of connectors are coupled to a corresponding plurality of dies. Again taking the die pad 34 as an example, a connector 52 in the form of a fixture is coupled to a die 80. Specifically, the connector 52 is placed onto a solder layer 82, which is in turn applied to the die 80. The location of the connector on the corresponding semiconductor assembly is Fig.11 , Fig.12 and Fig.13 , and will be described in detail in conjunction with these figures. Each clamp includes a plurality of leads and a sealing strip extending through the leads. Again, this will be described in detail in conjunction with the following figures. Fig.9e The relevance of the opposite orientation of the die pad is also schematically shown, which in combination with Figure 9a is shown and described. By comparison Figure 9d and Fig.9e It will be appreciated that when the plurality of connectors are coupled to the corresponding plurality of dies, the connectors are oriented so that the leads of the fixtures of the opposing pair of die pads extend in different directions. For example, the leads of connector 52 extend toward the left side of die pad 34, and the leads of the connector of die pad 72 (the other die pad in the opposite pair) extend toward the opposite right direction. For completeness, Fig.9eA single connector 52 is shown coupled to each semiconductor assembly, as defined by each die pad. Connector 52 will be further separated into (separate) source connectors 53 and gate connectors 55, as shown in FIG. Figure 2 as shown in .

[0140] Fig.9e Also represented is a reflux step, wherein Figure 9b and Figure 9d The solder layers 78, 82 applied in the steps shown in FIG. 8 undergo a reflow soldering process. Specifically, Fig.9e The array of semiconductor assemblies shown in FIG. 1 are subjected to controlled high temperatures, such as by a reflow oven or by infrared lamps, to cure the semiconductor assemblies to produce permanent solder joints.

[0141] Steering Figure 9f , showing the molding steps of the process. For the sake of completeness, the Figures 14 to 16 Display and describe the geometry of the mold. Figure 9f In the embodiment of the present invention, for each of the two arrays 64, 66, a fused shell is molded over all of the plurality of semiconductor assemblies. That is, a first fused shell 84 is molded over a first plurality of semiconductors corresponding to the first array 64, and a second fused shell 86 is molded over a plurality of semiconductor assemblies corresponding to the second array 66. Figure 9f As shown in , a fused shell refers to a combined shell in which multiple individual shells are molded simultaneously. For example, taking the fused shell 84 as an example, the fused shell 84 will continue to be separated into ten individual shells, each shell being used to form one of the ten semiconductor assemblies of the first array 64. For the sake of completeness, in Figure 9f The fused shells 84, 86 are shown in a partially transparent view. Figure 9h An "opaque" view is shown.

[0142] The molding process is performed by injection molding. In the illustrated embodiment, a common source 87 of molten polymer material is provided in fluid communication with a plurality of mold cavities (e.g., corresponding to a plurality of arrays). However, it should be understood that in other embodiments, this may not be the case. Material is supplied to each mold corresponding to the molten shell 84, 86 via a respective runner 90, 94 in fluid communication with the common source 87. In addition, material is supplied via a respective gate 92, 96 for each mold cavity. Again, for the sake of completeness, the molds / mold cavities are not shown in FIG. Figure 9f , but will be described in conjunction with subsequent figures.

[0143] As previously described, the fused shells 84, 86 at least partially surround the respective arrays 64, 66 of semiconductor assemblies. Thus, the shells for multiple semiconductor assemblies are molded simultaneously. This simultaneous molding has many advantages, including, but not limited to, being able to increase the density of die pads on a given lead frame (due to the "common" fused shell molding, the gap around each die pad can be reduced).

[0144] exist Figure 9f In the molding steps shown in FIG. , and as will be combined Figures 14 to 17 As described in detail, one or more grooves extending at least partially around a respective one of the semiconductor assemblies may also be defined. The grooves advantageously reduce the amount of material between adjacent semiconductor assemblies and, therefore, reduce the amount of material that needs to be removed to singulate the conductor assemblies in a subsequent sawing process. However, the grooves are an optional feature. For completeness, after molding (i.e., so that the molten shells 84, 86 are molded), the tie bars and lead frame extending between adjacent die pads are obscured by the shell material.

[0145] Go to Figure 9g , Figure 9g Also shown are the first molten shell 84 and the second molten shell 86 (in a partially transparent view), but with the associated molding features (e.g., common source 87, runners 90, 94, and gates 92, 96) removed. That is, the molding process is performed by Figure 9g Complete the steps shown in .

[0146] exist Figure 9g In the embodiment, a (multi-stage) stamping process has been performed, wherein the sealing strip of each connector (e.g., and the sealing strip of each semiconductor assembly) is removed, and the leads are formed (and the displaced leads are formed). In other words, with reference to Figure 4 , a punching line 60 is formed by performing a punching operation. Figure 9g In the illustrated embodiment, this step does not singulate the semiconductor assemblies because the die pads in the respective arrays are still interconnected by the tie bars and fused shells 84, 86. However, at this point, the semiconductor assemblies can be considered to be detached from the lead frame 62 on one side. Specifically, each of the semiconductor assemblies is detached from the lead frame 62 at least at the lead side. To aid in explanation, Figure 9f , the sealing bar of the semiconductor assembly 2 corresponding to the die pad 34 is labeled 88. The sealing bar 88 provides multiple functions during the manufacturing process, including but not limited to providing structural support for the leads, providing alignment of the leads relative to the lead frame 62, and simplifying the molding process by preventing melted material from escaping from the mold through the leads (or particularly between adjacent leads).

[0147] Figure 9g The stamping steps are also compared Fig.12 and Fig.13 (The leads are shown in more detail) to form displaced leads (i.e., leads that have changed direction). Once the leads are formed, they are also plated (usually with tin (Sn)). Plating increases the corrosion resistance of the leads and improves the adhesion of solder to the leads.

[0148] Go to Figure 9h , Figure 9h Two different orientations of one of the arrays 64, 66 are shown prior to the sawing process (to singulate the individual semiconductor assemblies). Figure 9h Only one array is shown and is not intended to represent Figure 9g The two arrays 64, 66 of lead frame 62 have been separated at this point (i.e., the same number of arrays will remain on lead frame 62). The left hand orientation is taken from the perspective of the first major face 8 of the semiconductor assembly (marked only on semiconductor assembly 2). The left hand orientation may be referred to as a plan view. The right hand orientation shows a perspective taken from the second major face 10 of the semiconductor assembly (again, marked only on semiconductor assembly 2. The right hand orientation may be referred to as a bottom view. The left hand side may be referred to as a "live worm" orientation, and the right hand side may be referred to as a "dead worm" orientation. Either orientation may be used in operation. Side views for each orientation are also shown below the left and right side views.

[0149] exist Figure 9g In the case where the stamping step has been performed, the final step of the process is to cut the molten shell 84 in at least three locations around each of the individual semiconductor assemblies to define the individual shells and singulate the semiconductor assemblies from the array. For example, and again referring to the semiconductor assembly 2, corresponding to the tube die pad 34, the molten shell 84 is cut at three locations 54, 56, and 58 that partially surround the individual semiconductor assembly 2 to singulate the semiconductor assembly 2 from the array. It is also worth noting that it should be understood that the semiconductor assembly 2 is also connected to the surrounding lead frame by tie bars, which extend between the tube die pads that form part of the lead frame. In this way, the cutting locations 54, 56, and 58 will also cut the tie bars extending between the tube die pads (and, where applicable, between the tube die pads and the lead frame 62). Therefore, the cutting operation will separate the semiconductor assembly 2 from the surrounding array. As shown Figure 9h As shown, particularly on the left hand side, the cutting operation may be limited to a length corresponding only to a respective semiconductor assembly. Alternatively, the cutting operation may simultaneously cut through a plurality of semiconductor assemblies (e.g., line 56) to separate the semiconductor assemblies. Figure 9h Each of the five pairs of opposing semiconductor assemblies shown). A cutting operation is intended to refer to a cutting process and may include multiple constituent cuts. For example, cutting at three locations 54, 56, and 58 may be referred to as a cutting operation. Figure 9hIn the embodiment, each cutting position corresponds to the length of the non-lead side of the semiconductor assembly housing. In other words, each cutting position corresponds to a portion of the periphery of a respective semiconductor assembly.

[0150] It is desirable to minimize the number of "cuts" (e.g., the number of cut lines or the number of locations where a cut occurs) as much as possible. For a single 2×5 array, Figure 9h As shown (left hand side), one (vertical in this embodiment) cut 56 is required to separate the semiconductor assembly pairs. Six (i.e., n+1, for a 2×n array) (horizontal in this embodiment) cuts 54, 58, 57, 59, 61, 63 are required to separate the remaining semiconductor assemblies. The pair separation cuts (e.g., 56) may be cuts that singulate out the semiconductor assembly (or assemblies). One of the other cuts may be a cut that singulates out the semiconductor assembly (or assemblies). Thus, for a 2×n array, a minimum number of n+2 cuts is required.

[0151] In the case where the cutting includes sawing, particularly a rotating saw blade, the lead frame 62 including the arrays 64, 66 may be fed to the rotating saw blade. In other words, the lead frame 62 and the arrays 64, 66 may be moved relative to the rotating saw blade. In contrast, for some other cutting processes (e.g., reciprocating saw blades, laser cutting, water jets, etc.), the position of the lead frame 62 and the arrays 64, 66 may be fixed while the cutting tool moves relative thereto.

[0152] For the avoidance of doubt, the cutting operation may be performed by a variety of different cutting processes including, but not limited to, reciprocating or rotating blades (ie, sawing), lasers, water jets, or other similar processes.

[0153] Figure 9h The right-hand side shows different orientations, which will be Figure 9h The saw will be cut in a similar manner as shown on the left hand side of the embodiment. However, the directionality of the cut will be different for the left / right orientation shown. For example, and in the case of a cut made by a (rotating) saw blade, in a left hand orientation the cut will be from the second main face 10 (e.g. the lower side) to the first main face 8 (e.g. the upper side). Conversely, in a right hand orientation the cut will be from the first main face 8 (e.g. the upper side) to the second main face 10 (e.g. the lower side). Due to the material of the housing and / or the pull rod being cut through, the resistance encountered by the saw will vary depending on the material. This is one factor that may affect the directionality of the cut, and therefore Figure 9h The cutting operation may also produce burrs, and it may be necessary to modify the orientation to reduce the formation of burrs, or at least reduce the visibility of burrs.

[0154] Finally, turning to step 9i, the individual semiconductor assemblies 2 (which may be referred to as semiconductor components or devices) that are singulated are shown according to the previous figures. Figure 9i The top view shows an opaque view, while the bottom view shows a partially transparent view, and each corresponds to Figure 1 and Figure 2 .

[0155] Compared to known arrangements, the above method advantageously eliminates the need for a second stamping operation for singulating out the second conductor assembly. Thus, due to the 2×n arrangement and the opposite pair orientation, the die pads can be placed close to each other on the lead frame, which means that the density of the device can also be increased. This is at least in part due to the fact that less space is required between adjacent die pads to fit into previously separate molds that previously molded separate housings. Instead, fused housings are molded simultaneously over multiple semiconductor assemblies, which further increases the efficiency of the manufacturing process. As will be seen in the example of the combined die pads, the die pads can be placed close to each other on the lead frame, which means that the density of the device can also be increased. This is at least in part due to the fact that less space is required between adjacent die pads to fit into previously separate molds that previously molded separate housings. Instead, fused housings are molded simultaneously over multiple semiconductor assemblies, which further increases the efficiency of the manufacturing process. Figures 22a to 22i As explained, a corresponding method using a 1×n array can also be used.

[0156] Go to Fig.10 , Fig.10 Shows isolated Figure 9a The lead frame 62 is provided.

[0157] As previously described, the lead frame 62 includes two 2×5 arrays 64, 66 of die pads. Also as previously described, the die pads are arranged in pairs in the array, having opposite orientations. Fig.10 Two such pairs are schematically shown in FIG. 1 , bounded by boxes 90 and 92. Fig.10 As shown, the lead frame 62 further defines lead cavities disposed at the lead ends of each die pad (eg, lead cavity 94 at at least side 20 of die pad 34 and lead cavity 96 at lead side 74 of die pad 72 ).

[0158] Taking the die pad 34 as an example, the die pad 34 is connected to the lead frame 62 through tie bars 40, 42 (see also Figure 2 ). The die pad 34 is coupled to the (opposing pair of) die pads 72 by tie bars 36, 38. The die pad 34 is also connected to an adjacent die pad 98 in the pair labeled 92 by tie bars 22, 24.

[0159] As previously described, the tie bars (eg, 22 , 24 , etc.) are cut (as part of a sawing process) to singulate the semiconductor assemblies and the individual die pads from one another. However, until this point, the individual semiconductor assemblies are at least partially coupled to the leadframe 62 .

[0160] Steering Fig.11 , provides Figure 9f Also shown are side and end views generally designated 100, 102, respectively.

[0161] include Fig.11 This is to more clearly illustrate the geometry of the connector (e.g., connector 52 for die pad 34) during molding and before the stamping step. Referring to die pad 34 forming part of first array 64, as shown in FIG. Fig.11 As shown, the connector 52 has been attached and a molten shell 84 is molded over at least a portion of the connector 52. The sealing strip 88 is also still present because the stamping step (which removes the sealing strip) has not yet been performed. Once the stamping step is performed, the sealing strip 88 is removed (e.g., the sealing strip 88 is stamped), as well as the material area for the adjacent tube core pad, generally indicated as 104. This step removes the sealing strip 88 and forms four leads 6 in the embodiment shown, one of which is marked as 6d. This step also separates the (single) connector 52 into a source connector 53 and a gate connector 55). In this stamping step, the leads that are displaced leads are also formed, as long as they are deformed to include a change in direction. For completeness, the stamping step may include multiple stamping stations (e.g., constituting stamping sub-steps). For example, in a first sub-step, the sealing strip is stamped. In a second sub-step, the ends of the leads are stamped. In a third and final sub-step, the (displaced) leads (e.g., bent) are formed. The stamping step and the optional three sub-steps described above can be performed on five semiconductor assemblies (in a row) at a time. That is, for a 2×n array, the steps can be performed on a row of n semiconductor assemblies.

[0162] Go to Fig.12 , providing that after the molten shell has been molded, Figure 9f A magnified view of the steps shown. Therefore, Fig.12 Corresponding to the Fig.11 The next step. It is important to Fig.12 It is also obtained at a stage prior to performing a stamping operation on any of the semiconductor assemblies shown.

[0163] For ease of reference, the following description is made in conjunction with the lower right semiconductor assembly labeled 104. Fig.12 As described above, the fused shell 86 has been molded over the semiconductor assembly 104 to form a portion of the second array 66, and the fused shell 86 is at least partially surrounded by the second fused shell 86. The semiconductor assembly 104 includes a connector 106 in the form of a clamp, which is applied in a previous step of the process. As previously described, Fig.12 1. In the embodiment shown in FIG. 1, at least a portion of the connector 106 protrudes from the lead side 108 of the semiconductor assembly 104. Fig.12In the step shown, the sealing strip 110 is still shown in place before the lead side 108 of the semiconductor assembly 104 (particularly the connector 106 thereof) is stamped to define the individual leads and the sealing strip 110 is cut. The connector 106 is also not separated into separate source and gate connectors. In addition, the connector 106 (at least the exposed portion thereof) extends substantially 90 degrees (e.g., substantially perpendicularly) relative to the major surface of the lead side 108. In other words, the displaced leads have not yet been formed. For example, see the comparative Fig.13 (The formed displaced leads are shown).

[0164] Now go to Fig.13 , Fig.13 shows the stamping step after it has been performed. Fig.12 The two semiconductor assembly arrays are shown.

[0165] Referring again to the semiconductor assembly 104 in detail, the stamping step removes the sealing strip 110 (eg, Fig.12 108a to 108d of the connector 106. This step also separates the connector 106 into individual source connectors 107 and gate connectors 109. The leads 108a to 108d are also formed as displaced leads, as long as they now change direction after extending substantially vertically from the fused shell 108. Again, this is similar to Fig.12 The corresponding connector 106 / lead geometry shown is reversed.

[0166] like Fig.13 As shown, after the stamping step has been performed, each of the arrays 64, 66 is ready for a cutting process to be performed on the fused shells 84, 86 in at least three locations partially surrounding the respective semiconductor assemblies to singulate the semiconductor assemblies from the corresponding array.

[0167] Go to Fig.14 , provides an end view of the two arrays 64, 66 during the molding step. Fig.14 Shown are first and second mold sections 112, 113, specifically upper and lower sections of the mold that respectively surround semiconductor assemblies corresponding to die pads 34, 72 of first array 64. First and second mold sections 112, 113 cooperate to define a mold cavity.

[0168] like Fig.14As shown in FIG. 1 , the first mold section 112 includes a tapered edge 114 proximate the die pad 34 and a tapered edge 116 proximate the die pad 72. The first mold section 112 also includes a protrusion 118 disposed between the opposing die pad pair (i.e., between the die pads 34, 72), the protrusion 118 in turn including tapered edges (i.e., sides) 120, 122 and a flat bottom edge 124. The first mold section 112 thus produces a mold having Fig.16 and Fig.17 Molten shell for the geometry shown.

[0169] Continue to refer to Fig.14 Although the second array 66 is not shown, the same mold sections are also used on this array.

[0170] Brief turn Fig.15 , Fig.15 Shown with Fig.14 The corresponding side view is shown. Therefore, Fig.15 The mold cavity is shown surrounding a semiconductor assembly that forms part of the array.

[0171] Go to Fig.16 , Fig.16 yes Fig.14 , corresponding to an area just larger than the area of ​​the semiconductor assembly corresponding to the die pad 34 .

[0172] like Fig.16 As shown, the geometry of the molten shell 84 is produced by a molding process including a first mold section 112. Figure 2 , the chamfered edge 26 (at the lead side 20) is formed by the tapered edge 114 of the mold section 112. Similarly, the chamfered edge 26 at the opposite side of the semiconductor assembly (the second side 16) is formed by the tapered edge 120 of the protrusion 118. A portion of the lip 30 that extends partially around the semiconductor assembly 2 is also shown to be bounded by the bottom edge 124 of the protrusion 118. The bottom edge 118 also creates a groove 126 between adjacent semiconductor assemblies, which reduces the amount of material that is cut to separate the adjacent semiconductor assemblies. The amount of material to be cut (at least the amount of the molten shell 84) is represented by 128. The groove 126 may extend continuously around three sides of the periphery of the semiconductor assembly, for example. Alternatively, the groove may be intermittent (i.e., extend discontinuously). Where the groove extends continuously, the groove preferably extends along each of the cut lines 54, 56, 58, such as Figure 4 The recess is preferably located at the top side of the semiconductor assembly (eg extending from the first main face).

[0173] Final Turn Fig.17 , Fig.17 Shows Fig.16, wherein the first mold section 112 is removed. Fig.17 More clearly shown is the groove 126, which has a depth indicated at 130. The depth 130 of the groove 126 is preferably at least about one third of the total thickness of the molten shell indicated at 132. Figure 9h As described above, the material 128 extending between adjacent semiconductor assemblies is removed by the cutting operation. At least in the illustrated embodiment, the removal of this material singulates the adjacent semiconductor assemblies and also defines a lip 30 (which can effectively be considered to be caused by manufacturing tolerances associated with the cutting operation). The width 134 of the groove at the underside (e.g., Fig.16 The width formed by the bottom edge 118 of the mold is preferably wider than the width of the cutting tool used in the cutting operation. It has also been found that the inclusion of the groove advantageously provides a stress relief function in the molten shell. That is, in a molding process including the groove, the molten shell is less likely to be damaged.

[0174] Fig.18 and Fig.19 A semiconductor assembly 200 according to another embodiment is shown (partially transparent plan view and partially transparent lower side view, respectively). At the lead side 16 of the semiconductor assembly 200, four tie bars 202, 204, 206, 208 are provided. Fig.18 and Fig.19 It is noted that the invention is not limited to a particular arrangement or number of tie bars. Apart from this difference, the semiconductor assembly 200 corresponds to the previous embodiment.

[0175] Fig. 20 and Fig.21A semiconductor assembly 300 according to another embodiment is shown (partially transparent plan view and partially transparent lower side view, respectively). The semiconductor assembly 300 is shown in a monolithic form, with a single housing 301, but includes two die pads 302, 304, two dies 306, 308, and two connectors 310, 312 (a first connector and a second connector). The first connector 310 includes a source connector 314 and a gate connector 316. Similarly, the second connector 312 includes a source connector 318 and a gate connector 320. The semiconductor assembly 300 includes four leads 322a to 322d (collectively referred to as leads 322). Leads 322a and 322c are first source leads and second source leads (i.e., they communicate with the source connectors 314, 318 of the first connector 310 and the second connector 312, respectively). Leads 322b and 322d are first and second gate leads (i.e., communicate with gate connectors 316, 320 of first and second connectors 310, 312, respectively). Thus, semiconductor assembly 300 includes two electrically isolated subassemblies 300a, 300b housed in a common housing 301. Figures 9a to 9i Such an embodiment can be readily manufactured by the process shown and described. Apart from the above differences, the semiconductor assembly 300 corresponds to the previous embodiment 2,200. It is noteworthy that the first connector 310 and the second connector 312 can be coupled to the corresponding tube core as a single "main" connector, and the single "main" connector is subsequently separated by stamping.

[0176] Steering Figures 22a to 22i , schematically illustrates a method for manufacturing a batch of semiconductor assemblies according to another embodiment. Figures 22a to 22i Generally correspond to Figures 9a to 9i , but for a lead frame 400 having a 1×5 array of die pads (e.g., with Figures 9a to 9i 6. In other words, the lead frame 62 includes the first 2×5 array 64 and the second 2×5 array 66 of die pads. Figures 22a to 22i A method for manufacturing a single row semiconductor assembly is shown. For the sake of brevity, only the method related to Figures 9a to 9i The corresponding steps are different steps.

[0177] from Fig.22aInitially, as described above, the lead frame 400 includes two 1×5 arrays 402, 404 of die pads. The die pads of each array 402, 404 can be described as being arranged in a single column or row. Unlike the lead frame 62, for the lead frame 400, each die pad is coupled to two other die pads or one other die pad and the lead frame 400 (for the "end" die pads). In contrast, for the lead frame 400, each die pad is coupled to three other die pads or two other die pads and the lead frame 62 (again, for the "end" die pads). The die pads of the lead frame 400 are also not arranged in pairs, much less in opposing pairs, assuming they are arranged in a single row. Taking the first die pad 405 on the lead frame 400 as an example, the second side 407 of the die pad 405 (i.e., opposite the lead side 409) is not coupled to the lead frame 400. In other words, the non-lead side of the die pad 405 is "free", as shown in FIG. Fig.22a The same is true for the lead side 409 shown in FIG.

[0178] Figure 22b to Figure 22e The steps shown in each of Figure 9b to Figure 9e The steps in are closely related and therefore not described in detail. It is worth noting that similar to Fig.9e ,exist Fig.22e In a PCB, the leads of the connector extend from only a single (lead) side of each semiconductor assembly.

[0179] Steering Figure 22f , molding step, molding a first molten shell 406 and a second molten shell 408. The first molten shell 406 and the second molten shell 408 are molded on the semiconductor assemblies corresponding to the first array 402 and the second array 404, respectively. Therefore, each molten shell 406, 408 at least partially surrounds the five semiconductor assemblies, which is consistent with Figure 9f Each of the first and second fused shells 84, 86 shown in FIG. 8 at least partially surrounds ten different semiconductor assemblies.

[0180] Go to Figure 22g , the stamping step is similar to Figure 9g (albeit with fewer connectors).

[0181] Go to Figure 22h , similar to Figure 9h , the left hand side view shows the array in plan view, and the right hand side view shows the array from the bottom. Figure 9h , Figure 22h Schematically indicating the cutting lines by which the semiconductor assemblies of the first array 402 are singulated. Assume that the semiconductor assemblies in each array 402, 404 are not arranged in (opposing) pairs, but in 1 x 5 rows, as Figure 9h Compared to the singulation step of FIG. 4, the number of cuts required is reduced by one. This is because the non-lead side (e.g., 407 for die pad 405) is a "free" side that is not coupled to the lead frame 400 (again, unlike Figure 9h ). Cuts are made at two locations, Figure 22g The semiconductor assembly is singulated from the array 402 by punching in the steps shown in . The two locations are the first side (or edge) and the third side (or edge) adjacent to the lead side. In this embodiment, the two cutting locations are parallel to each other, and the punching line is disposed between the two cutting locations and extends between the two cutting locations.

[0182] Fig.22i Shows the steps from Fig.22a To step Figure 22h The individualized semiconductor assembly is obtained by the method shown in .

[0183] Throughout this document, it will be understood that the lead side of the die pad and the lead side of the semiconductor assembly refer to the same general area. However, the lead side of the semiconductor assembly may refer to the leads of the connector, while the lead side of the die pad may refer only to the edge of the die pad that is near the leads (once assembled). The lead side of the housing may refer to the side of the housing that extends from the leads.

[0184] Throughout this document, a semiconductor assembly may also be referred to as a package.

Claims

1. A method for manufacturing a batch of semiconductor assemblies, comprising: coupling a plurality of dies to a plurality of die pads arranged in pairs in a 2×n array on a lead frame, each pair of die pads having opposite orientations, wherein each die pad defines a respective semiconductor assembly; coupling a plurality of connectors to the plurality of dies; molding a fused shell over the plurality of semiconductor assemblies using a mold surrounding the 2×n array, the fused shell at least partially surrounding the 2×n array; as well as cutting the fused shell at at least three locations partially surrounding a respective one of the plurality of semiconductor assemblies and stamping the single lead side of the semiconductor assembly to define a respective shell from the fused shell and singulate the semiconductor assemblies from the 2×n array, The single lead side refers to a die pad, a housing, or a side of a semiconductor extending from the lead. 2 . The method of claim 1 , wherein molding the molten shell comprises defining a groove extending at least partially around one of the plurality of semiconductor assemblies.

3. The method of claim 2, wherein the groove extends continuously around the three locations where the molten shell partially surrounds the respective ones of the plurality of semiconductor assemblies.

4. A method according to claim 2 or 3, wherein the groove is at least partially conical.

5. The method of any one of claims 2 to 4, wherein the recess comprises a planar surface proximate to the corresponding die pad.

6. A method according to any one of claims 2 to 5, wherein the groove extends through at least 1 / 3 of the thickness of the respective housing.

7. The method of any one of the preceding claims, wherein stamping the lead side of the semiconductor assembly to define the individual shells is performed before cutting the fused shells at at least three locations.

8. The method of claim 7, wherein cutting the molten shell at at least three locations singulates the semiconductor assembly from the 2xn array.

9. The method of any preceding claim, wherein the lead frame comprises a plurality of 2×n arrays of die pads, pairs of the die pads of each 2×n array being arranged in opposite orientations; and molding the fused shell comprises molding a plurality of fused shells, one fused shell for each of the plurality of 2×n arrays of die pads.

10. The method of claim 9, wherein the plurality of molten shells are molded simultaneously by supplying molten material from a common source using a respective runner for each molten shell.

11. The method of any preceding claim, wherein stamping the lead side of the semiconductor assembly comprises forming one or more displaced leads.

12. A semiconductor assembly array, comprising: a lead frame comprising a 2×n array of die pads arranged in pairs, each pair of die pads having opposite orientations, wherein each die pad defines a respective semiconductor assembly; a plurality of dies coupled to a corresponding plurality of die pads; a plurality of connectors coupled to respective ones of the plurality of dies; a fused shell molded over the plurality of semiconductor assemblies, the fused shell at least partially surrounding the 2×n array; wherein each of the plurality of semiconductor assemblies comprises one or more leads extending from a single lead side of the semiconductor assembly, wherein The single lead side refers to a die pad, housing or semiconductor side extending from the lead, and The fused shell includes a groove extending at least partially around one of the plurality of semiconductor assemblies, partially surrounding a respective one of the plurality of semiconductor assemblies on three of four sides of a quadrilateral perimeter, the single lead side being a fourth side of the quadrilateral perimeter.

13. A semiconductor assembly comprising: Die pad; a die coupled to the die pad; a connector coupled to the die, the connector comprising one or more leads extending from a single lead side of the die pad; as well as a molded fused shell including a groove extending to three sides of the die pad; wherein the one or more leads are displaced leads, The single lead side refers to a die pad, housing or semiconductor side extending from the lead, and The semiconductor assembly is separated from the semiconductor assembly array according to claim 12 using the manufacturing method according to any one of claims 3 to 11.

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