Wafer test method, device, equipment, system and storage medium

Abstract

The invention discloses a wafer testing method, device, equipment and system and a storage medium. The wafer testing method comprises the steps that at least one time of wafer testing is carried out on a to-be-tested wafer, and the to-be-tested wafer comprises at least one chip; in the wafer testing process, at least one chip in the to-be-tested wafer is marked according to testing information of wafer testing and a preset testing classification table; obtaining a first test result generated by the wafer test; wherein the first test result comprises at least one chip test result parameter. The wafer testing method has the technical effects that the wafer testing efficiency is high, the wafer testing result is simple and convenient to look up, and multiple technical files do not need to be searched simultaneously when the testing result is analyzed.

Description

Technical Field

[0001] The present application relates to the field of wafer testing technology, and in particular to a wafer testing method, device, equipment, system and storage medium. Background Art

[0002] Wafer testing, also known as CP testing (Chip Probe Testing), is a key step in the semiconductor manufacturing process. It aims to evaluate the electrical characteristics, functions and performance of each chip on the wafer to ensure that the manufactured chips can meet the design requirements in the subsequent production process. During the wafer testing process, it is necessary to query the specific failure items obtained by different wafer tests based on the test results. For example, in different voltage or frequency testing processes, multiple test results or wafer maps will be generated. Technicians can understand the test status of each chip through the above results. However, during the viewing process, it is necessary to view the test result graphs of different wafer tests and the corresponding data log files (datalog) and related test rule books (spec). For example, a 4-way wafer test requires viewing 4 test result graphs and corresponding datalog and spec files of at least 12 files. Summary of the invention

[0003] In view of this, the present application provides a wafer testing method, device, equipment, system and storage medium, in order to solve the technical problems of cumbersome and inefficient viewing of wafer testing results.

[0004] Specifically, the technical solution of this application is as follows:

[0005] A wafer testing method comprises the following steps:

[0006] Perform at least one wafer test on a wafer to be tested, where the wafer to be tested includes at least one chip;

[0007] During the wafer test process, at least one chip in the wafer to be tested is marked according to the test information of the wafer test and a preset test classification table;

[0008] Obtaining a first test result generated by a wafer test;

[0009] The first test result includes at least one chip test result parameter.

[0010] In some implementations, marking at least one chip in the wafer to be tested according to the test information of the wafer test and a preset test classification table specifically includes:

[0011] Searching the test code corresponding to the test information in the test classification table according to the test information, the test information includes: test items and test data;

[0012] According to the code arrangement rules in the test classification table, the test codes are combined to generate chip test result parameters;

[0013] Corresponding marking chip test result parameters and chips.

[0014] In some implementations, the test items include one or more of: wafer test category, test results and reasons, test voltage, test frequency, and test site.

[0015] In some implementations, the test classification table is set corresponding to the test items of the wafer test;

[0016] Multiple test classification tables form a test classification library;

[0017] The test classification library calls the test classification table according to the type of wafer test.

[0018] In some implementations, when a wafer to be tested is subjected to multiple wafer tests, a second wafer test tests the chips that have passed the first wafer test, and the second wafer test does not test the chips that have not passed the first wafer test;

[0019] The second wafer test is the next wafer test after the first wafer test is completed.

[0020] In some implementations, the wafer testing method further includes:

[0021] generating at least one wafer test result graph according to at least one first test result;

[0022] The wafer test result diagram includes at least one chip block, and the chip block is marked with chip test result parameters corresponding to the chip.

[0023] In some implementations, a final wafer test result map is generated based on the plurality of wafer test result maps;

[0024] Among them, the final wafer test result diagram contains the chip test result parameters of all chips in the wafer to be tested.

[0025] Based on the same technical concept, the present application also provides a computer device / equipment / system, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the wafer testing method in any of the above implementations.

[0026] Based on the same technical concept, the present application also provides a computer-readable storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the wafer testing method in any of the above implementations are implemented.

[0027] Based on the same technical concept, the present application also provides a wafer processing method, including: manufacturing a wafer; and testing the manufactured wafer according to the wafer testing method of the first aspect above.

[0028] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0029] 1. During the wafer testing process, the chips on the wafer are marked according to the pre-set test classification table, so that in the first test result generated by the wafer test, the test results of the chips included in the wafer can be quickly known through the chip test result parameters, helping users improve the efficiency of wafer test result analysis.

[0030] 2. During the multi-wafer test process, only qualified chips that have passed the first wafer test are tested in the second wafer test, thereby improving the wafer test efficiency and avoiding the problem of contradictory results between the two wafer tests, thereby improving the efficiency and accuracy of wafer testing.

[0031] 3. During the multi-channel wafer testing process, by pre-marking the test classification table and integrating multiple first test results, the integrated test results of the wafer to be tested after multi-channel wafer testing can be viewed in the final wafer test result chart at the same time, without having to simultaneously refer to the corresponding data recording files and test rule books in the multi-channel wafer testing, thereby improving the user's processing efficiency in analyzing wafer test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present application.

[0033] Figure 1 It is a flowchart of a wafer testing method exemplified in an embodiment of the present application;

[0034] Figure 2 It is a flowchart of a wafer testing method exemplified in an embodiment of the present application;

[0035] Figure 3 This is a wafer test result diagram after the first test illustrated in an embodiment of the present application;

[0036] Figure 4 This is a wafer test result diagram after the second test illustrated in an embodiment of the present application;

[0037] Figure 5 This is a wafer test result diagram after the third test illustrated in an embodiment of the present application;

[0038] Figure 6 This is a diagram of the final wafer test results illustrated in an embodiment of the present application.

[0039] Description of Figure Numbers: DETAILED DESCRIPTION

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0041] In order to simplify the drawings, only the parts related to the application are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0042] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0043] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0044] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0045] Wafer testing is a critical step in semiconductor manufacturing to evaluate the electrical characteristics, functionality and performance of each chip on the wafer.

[0046] Before wafer testing, the wafer undergoes preliminary manufacturing steps to form multiple levels of circuits and components on the chips it contains. Before the test begins, the test engineer designs a test plan based on the chip's design specifications and manufacturing requirements, and determines the electrical parameters, functional tests, and other performance tests to be measured. During the test, the wafer is mounted on the test equipment to ensure that the test probe is correctly aligned with the chip on the wafer, and the tiny test probe directly contacts the test point or pin on the chip to establish an electrical connection with each chip. When the test begins, the designed test plan needs to be executed to measure the electrical parameters such as current, voltage, and power of each chip, and perform functional tests to verify the various functions of the chip. During the entire test process, the test system records the test data of each chip, including the test results of passing and failing, as well as the specific values ​​of the electrical parameters. Finally, a Wafer Map graphic is generated based on the test results. The graphic shows the test status and results of each chip on the wafer, and uses color coding to represent different test results.

[0047] After the entire test process is completed, the manufacturing personnel need to analyze the Wafer Map image to identify unqualified chips and abnormal points. Finally, according to the test results, the chips are graded, their processing methods in the subsequent production process are determined, and the test data is deeply analyzed to identify problems in the manufacturing process, and measures are taken to improve them, providing feedback for subsequent manufacturing steps to adjust production parameters. The goal of wafer testing is to ensure that the quality of manufactured chips meets the expected standards, reduce the defective rate in the subsequent production stage, and improve overall production efficiency.

[0048] However, in the past, when manufacturing personnel analyzed the Wafer Map image, one wafer test would often generate a Wafer Map image, and these images often required the manufacturing personnel to analyze them in combination with the data log file (datalog) and the relevant test rule book (spec) corresponding to the image. However, when the number of wafer tests is large, the above query and comparison process is very cumbersome, which greatly reduces the efficiency of manufacturing personnel in analyzing and locating wafer chip problems and solving problems. Figure 1 , the present application provides a wafer testing method, comprising the steps of:

[0049] S110, performing at least one wafer test on a wafer to be tested, where the wafer to be tested includes at least one chip;

[0050] Wafers are a basic material in the semiconductor manufacturing process, usually thin round pieces made of single-crystal silicon. Wafers play a key role in the semiconductor industry, and they are the basis for manufacturing integrated circuits (ICs) and other microelectronic devices. The main reason for setting up chips on wafers involves many aspects of semiconductor manufacturing and integrated circuit (IC) design. From a cost-effectiveness perspective, multiple chips are laid out on a relatively large wafer, thereby making full use of semiconductor materials and reducing manufacturing costs through mass production. From the perspective of integrated manufacturing, setting up chips on wafers allows a large number of electronic devices to be integrated in a limited space, and one of the goals of integrated circuit design is to achieve higher integration and integrate more functions into a small chip, thereby improving circuit performance and functionality.

[0051] When the wafer to be tested is undergoing wafer testing, each chip on the wafer may have different electrical characteristics and functions at multiple test points, and one or more wafer tests are often required. Each test targets the electrical characteristics and physical characteristics of the wafer from different angles to ensure that all important test points are covered to obtain more comprehensive characteristic information.

[0052] S120, during the wafer test process, marking at least one chip in the wafer to be tested according to the test information of the wafer test and a preset test classification table;

[0053] S130, obtaining a first test result generated by a wafer test;

[0054] The first test result includes at least one chip test result parameter.

[0055] Specifically, during the wafer test process, when the wafer test is conducted on the wafer to be tested according to the test information set by the wafer test, the chips on the wafers involved in the test are marked. For example, the purpose of the wafer test is to check the electrical performance and function of the chips on the wafer, start measuring these chips, and perform a series of tests including voltage tests and clock frequency tests. During the test process, it is detected that the voltage of a certain chip exceeds the specified range. At this time, the chip is marked to indicate that there is a voltage problem with the chip. The mark may also contain other information, such as frequency problems, chip location, wafer test links, etc., that is, chip test result parameters. Alternatively, during the wafer test process, the chips that pass this round of wafer testing are also marked according to the test classification table, indicating that the chip has passed this wafer test, and other relevant information is recorded to form the chip test result parameters corresponding to the chip. The chip test result parameters obtained above will be recorded in the first test result of the test output for reference by the manufacturing personnel.

[0056] In the above wafer test process, the setting of the test classification table is based on the softbin (soft decision) rule setting. It is a temporary classification and is only used during the test process. When a chip is detected to have a problem or defect during the wafer test, the software will mark the chip, such as marking it as a set of strings, and record the type and location of the problem. The softbin determination process will not affect the actual physical properties of the chip, but is only used to identify and handle defective chips during the test process. When a chip is detected to have a problem or defect during the wafer test, the software will mark the chip as a softbin and record the type and location of the problem. The softbin does not affect the actual physical properties of the chip, but is only used to identify and handle the defect during the test process. It is distinguished from the hardbin (hard decision), which is a permanent classification and is usually used in the classification stage after the wafer test. When all chips have completed the test, the chips are hard-classified as shippable (good) or non-shippable (defective) according to the results of the hardbin. Therefore, the softbin is mainly used for temporary classification and recording during the test process, while the hardbin is used to finally decide whether the chip is shipped or not. The softbin provides a dynamic, real-time classification of test results, while the hardbin is used for final quality control and manufacturing decisions.

[0057] In one implementation, marking at least one chip in a wafer to be tested according to test information of a wafer test and a preset test classification table specifically includes:

[0058] S210, searching the test classification table for a test code corresponding to the test information according to the test information, the test information including: test items and test data;

[0059] S220, combining the test codes to generate chip test result parameters according to the code arrangement rules in the test classification table;

[0060] S230, correspondingly marking chip test result parameters and chips.

[0061] Specifically, during the wafer testing process, the test information mainly includes test items and test data. The test items include: wafer test category, test results and reasons, test voltage, test frequency and one or more of the test sites. These test items need to correspond to the test items of the wafer test and the test items of the test classification table according to the test procedures determined by the engineering personnel based on the preset test classification table. When a certain test item is not included in the pre-set test classification table, the manufacturing personnel need to intervene to add the item to it, and design the test code represented by the test data under the test item. The test and classification table formed refers to the following test classification table example.

[0062] Table 1 Test classification table example

[0063]

[0064] Therefore, during the wafer test process, the corresponding test items and the test data corresponding to the test items are automatically selected after looking up the table in the test classification table according to the test information. These test data have corresponding codes in the table. For example, during this round of wafer testing, the result of softbin is displayed as: for example, 02091291, which means that the test category is selected as the second category test, and the 1st-2nd code of the chip test result parameter is 02, and the wafer is open-circuited; after the test is completed, when the test result shows that there are problems with all the pins of the chip, the 3rd-4th code of the chip test pin parameter is 09, indicating that there is a problem with pin 09; when the test result and reason are 1, it represents a complete over-range failure; when the voltage used during the test is a high voltage, the 5th code of the chip test result parameter is 2; at the same time, this round of wafer testing is irrelevant to the frequency and is carried out at the first station of the wafer test, then the 6th and 7th codes are 41. Among them, the code arrangement rules are set according to the technical habits and production regulations of the technicians, and are not specifically limited here, but the process of generating this code by the method of this application is the protection scope of this application. For example, if the code arrangement rules are listed from left to right, the final chip test result parameter is 02991291. It can be basically locked that all pins are completely out of range failure in the first CP test open circuit test item. This is a process defect and an open circuit failure caused by the lack of metal materials. The test result parameters can be displayed in the corresponding wafer test result diagram, allowing technicians to quickly and accurately determine the specific cause of the wafer failure.

[0065] In one implementation, a test classification table is set corresponding to the test items of the wafer test; a plurality of test classification tables constitute a test classification library; and the test classification library calls the test classification table according to the type of the wafer test.

[0066] Specifically, wafer testing needs to consider many factors. According to different test methods and test purposes, multiple test classification tables need to be designed to adapt to different test types. Therefore, the multiple test classification tables are formed into a test classification library. In this test classification library, the corresponding test classification table is called according to the type of wafer test.

[0067] In one implementation, when a wafer to be tested is subjected to multiple wafer tests, a second wafer test is performed on chips that have passed the first wafer test, and the second wafer test is not performed on chips that have not passed the first wafer test; wherein the second wafer test is the next wafer test after the first wafer test is completed.

[0068] During multiple wafer tests, the previous wafer test often determines that a chip on the wafer has a corresponding problem. When the wafer is tested next time, testing the wafer again is a waste of test resources, and it is not of high value to judge the quality of the wafer that has already had problems again. Therefore, during multiple wafer tests, the second wafer test only tests the chips that have passed the first wafer test. At the same time, during the first wafer test, the chips that have been detected to have problems have also been marked with corresponding chip test result parameters. During the second wafer test, the chip test result parameters that have not been marked as problematic are tested, which can improve chip testing efficiency. In addition, if the chips that have not passed the wafer test in the first wafer test are still tested during the second wafer test, there may be a contradictory situation in which the chip passes the second wafer test but fails the first wafer test, which increases the burden of test result processing on manufacturing personnel.

[0069] In one implementation, the wafer testing method further includes: generating at least one wafer testing result map based on at least one first test result; wherein the wafer testing result map includes at least one chip block, and the chip block is marked with chip test result parameters corresponding to the chip.

[0070] Specifically, in order to make the wafer test results more visual, according to the first test results, refer to the attached manual. Figure 3 , generating a wafer test result graph, which includes each chip in the wafer, each chip corresponds to a chip block, and the corresponding chip test result parameters are set on the chip block. When the manufacturing personnel analyze the test results, they can quickly locate the problem of a chip on the wafer through the wafer test result graph. At the same time, different colors can be set to distinguish the chips that pass the wafer test and the chips that fail the wafer test, to help quickly locate and view.

[0071] In one implementation, a final wafer test result map is generated based on a plurality of wafer test result maps;

[0072] Among them, the final wafer test result diagram contains the chip test result parameters of all chips in the wafer to be tested.

[0073] Specifically, since the entire wafer test process may include multiple wafer tests, if a wafer test result graph is generated for each test, the manufacturing personnel need to view the wafer test result graph corresponding to each test in each test, which increases the burden of analyzing the test results. Figure 3 To Attachment Figure 5 Each test will generate a wafer test result graph. For example, three tests are performed at sites CP1 to CP3, and the wafer test result graphs generated are as follows: Figures 3 to 5, a number will be marked on the chip that failed the test. The content corresponding to the number is determined during the specific design test process. If you need to confirm the specific reasons why all the problematic chips on the wafer failed the test, you need to compare the three pictures together. The comparison process is complicated and the visibility is poor during fault analysis. In this application, multiple wafer test result pictures are merged. Figure 6 , forming the final wafer test result diagram, without the need to distinguish according to each wafer test. In addition, in the chip test result parameters, there is test site information that characterizes the chip in a specific wafer test, so it can effectively help manufacturing personnel determine which wafer test site or wafer test step found the problem. Figure 6 After analyzing the code in , the wafer test problems shown in Table 2 can be identified.

[0074] Table 2 Wafer test results

[0075]

[0076]

[0077] Based on the same technical concept, the present application also provides a computer device / equipment / system, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the wafer testing method in any of the above implementations.

[0078] Based on the same technical concept, the present application also provides a computer-readable storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the wafer testing method in any of the above implementations are implemented.

[0079] Based on the same technical concept, the present application also provides a wafer processing method, including: manufacturing a wafer; and testing the manufactured wafer according to the wafer testing method of the first aspect above.

[0080] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application, and these improvements and modifications should also be regarded as the protection scope of the present application.

Claims

1. A wafer testing method, characterized in that: Includes steps: Perform at least one wafer test on a wafer to be tested, wherein the wafer to be tested includes at least one chip; During the wafer testing process, marking at least one chip in the wafer to be tested according to the test information of the wafer testing and a preset test classification table; Obtaining a first test result generated by the wafer test; Wherein, the first test result includes at least one chip test result parameter.

2. The wafer testing method according to claim 1, characterized in that: The step of marking at least one chip in the wafer to be tested according to the test information of the wafer test and a preset test classification table specifically includes: Searching the test code corresponding to the test information in the test classification table according to the test information, wherein the test information includes: test items and test data; According to the code arrangement rules in the test classification table, the test codes are combined to generate the chip test result parameters; The chip test result parameters and the chip are marked accordingly.

3. The wafer testing method according to claim 2, characterized in that: The test items include: one or more of wafer test category, test result, test voltage, test frequency, and test site.

4. The wafer testing method according to claim 2, characterized in that: The test classification table is set corresponding to the test items of the wafer test; A plurality of the test classification tables constitute a test classification library; The test classification library calls the test classification table according to the type of the wafer test.

5. The wafer testing method according to claim 1, characterized in that: When the wafer test is performed multiple times on the wafer to be tested, the second wafer test tests the chips that pass the first wafer test, and the second wafer test does not test the chips that fail the first wafer test; The second wafer test is the next wafer test after the first wafer test is completed.

6. The wafer testing method according to any one of claims 1 to 5, characterized in that: Also includes: generating at least one wafer test result graph according to at least one of the first test results; The wafer test result diagram includes at least one chip block, and the chip block is marked with the chip test result parameters corresponding to the chip.

7. The wafer testing method according to claim 6, characterized in that: Generating a final wafer test result graph according to the plurality of wafer test result graphs; The final wafer test result graph includes chip test result parameters of all chips in the wafer to be tested.

8. A computer device / equipment / system comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the wafer testing method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instruction is executed by a processor, the steps of the wafer testing method according to any one of claims 1 to 7 are implemented.

10. A wafer processing method, characterized in that: include: Manufacturing wafers; The wafer testing method according to any one of claims 1 to 7 tests the wafer after manufacture.

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