Packaging structure, preparation method thereof and terminal equipment

Abstract

The invention provides a packaging structure, a preparation method thereof and terminal equipment. The packaging structure comprises a substrate, the substrate comprises a first surface and at least one groove, and an opening of the groove is located in the first surface; the chip is arranged in the groove, and a smaller included angle between the front surface of the chip and the first surface is 70-90 degrees; and the first conductive structure is located on the opening side of the groove of the substrate, and the first conductive structure is electrically connected with the chip. The packaging structure provided by the embodiment of the invention is high in integration level, can reduce the packaging area, and achieves the miniaturization of a device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging structure and a preparation method thereof and a terminal device. Background Art

[0002] The recent trend in the semiconductor industry is that products are highly integrated, thin, light, fast, multifunctional and efficient, thus having high reliability. In order to cater to the above trends, chip stacking packaging technology is regarded as an important technology in the semiconductor field. At present, chips are generally stacked in the packaging structure. In the chip stacking packaging structure, multiple chips need to be electrically connected to each other. Currently, the chips are mainly electrically connected to each other using through electrodes that penetrate the chips. However, due to the limitations of related technologies, the effect of chip stacking in the existing packaging structure is not ideal. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a packaging structure, a preparation method thereof, and a terminal device.

[0004] The first aspect of the present application provides a packaging structure, including:

[0005] A substrate, the substrate comprising a first surface and at least one groove, wherein an opening of the groove is located on the first surface;

[0006] at least one chip, the chip is placed in the groove, and the smaller angle between the front surface of the chip and the first surface is 70° to 90°;

[0007] The first conductive structure is located at the opening side of the groove of the substrate, and the first conductive structure is electrically connected to the chip.

[0008] In one embodiment, in the first direction, the orthographic projection of the groove on the first surface has a first width, and in the second direction, the orthographic projection of the groove on the first surface has a second width, the second width is greater than the first width, and along the thickness direction of the substrate, the depth of the groove is greater than the first width, and the first direction and the second direction are perpendicular to each other;

[0009] Preferably, the front surface of the chip is perpendicular to the first surface;

[0010] Preferably, the substrate includes a second surface, and along the thickness direction of the substrate, the first surface and the second surface are arranged opposite to each other;

[0011] Preferably, the material of the substrate includes glass.

[0012] In one embodiment, the chip includes a chip body and a second conductive structure, the second conductive structure is located on the front side of the chip body, and the first conductive structure is electrically connected to the second conductive structure;

[0013] Preferably, the second conductive structure is located at one end of the chip body close to the groove opening;

[0014] Preferably, in one chip, there are multiple second conductive structures, and the multiple second conductive structures are arranged at intervals along a direction parallel to the front surface of the chip body;

[0015] Preferably, the second conductive structure comprises a metal pad;

[0016] Preferably, the packaging structure further comprises: bottom filling glue, which is located in the gap surrounded by the groove and the chip.

[0017] In one embodiment, one chip is placed in one groove;

[0018] Preferably, the front sides of the chips all face the same side.

[0019] In one embodiment, two chips are placed in one groove, and in the same groove, the back surfaces of the two chips are arranged opposite to each other;

[0020] Preferably, the back side of the chip contacts in the same groove.

[0021] In one embodiment, the invention further comprises: a dielectric layer located at an opening side of the groove of the substrate, wherein an orthographic projection of the dielectric layer on the first surface overlaps with an orthographic projection of the groove on the first surface;

[0022] Preferably, the orthographic projection of the dielectric layer on the first surface covers the orthographic projection of the groove on the first surface;

[0023] Preferably, the first conductive structure is located in the dielectric layer;

[0024] Preferably, it further comprises: a third conductive structure, located on a side of the dielectric layer away from the substrate, the third conductive structure being electrically connected to the first conductive structure;

[0025] Preferably, the third conductive structure comprises a solder ball.

[0026] In one embodiment, the number of grooves is 2N, and a figure surrounded by the 2N grooves is axially symmetrical, the axis of symmetry is perpendicular to the first surface, a chip is placed in one groove, the i+1th chip is located on a side of the ith chip away from the axis of symmetry, i is an integer between 1 and N, and N is greater than or equal to 1;

[0027] Preferably, the dielectric layer includes M layers of sub-dielectric layers, the j+1th sub-dielectric layer is located on the side of the jth sub-dielectric layer away from the substrate, M is greater than or equal to 1, j is an integer between 1 and M, and M is an integer greater than or equal to N; the first conductive structure includes a plurality of first portions, which are located on the side of the M-1th sub-dielectric layer away from the substrate, the third conductive structure is electrically connected to the first portion, and the first portion is electrically connected to the corresponding second conductive structure;

[0028] Preferably, the first conductive structure further includes a second portion and a third portion, the second portion is located between the third portion and the first portion, and the second portion and the third portion are arranged corresponding to the first portion;

[0029] Wherein, when i is 1, the first portion electrically connected to the first chip coincides with the corresponding second portion and third portion; when i is N, the third portion corresponding to the first portion electrically connected to the Nth chip is located on the first surface, the first layer of sub-dielectric layer covers the first portion, and the third portion is electrically connected to the second conductive structure; when i is an integer from 2 to N-1, the third portion corresponding to the first portion electrically connected to the i-th chip is located on the surface of the |iN|th layer of sub-dielectric layer away from the substrate, and the third portion extends in a direction close to the substrate to be electrically connected to the second conductive structure, and N is an integer greater than or equal to 2;

[0030] Preferably, M is equal to N.

[0031] A second aspect of the present application provides a method for preparing a packaging structure, comprising:

[0032] At least one groove is formed on the first surface of the substrate;

[0033] At least one chip is placed in at least one groove, and the smaller angle between the front surface of the chip and the surface perpendicular to the first surface is 70 to 90 degrees;

[0034] A first conductive structure is prepared on the open side of the groove of the substrate.

[0035] In one embodiment, before placing at least one chip in at least one groove, the method further includes: preparing a second conductive structure on the front side of the chip body to obtain a chip;

[0036] Preferably, the second conductive structure is prepared on the front side of the chip body by electroplating;

[0037] Preferably, preparing the first conductive structure on the opening side of the groove of the substrate comprises: preparing a dielectric layer and the first conductive structure on the opening side of the groove of the substrate;

[0038] Preferably, preparing a dielectric layer and a first conductive structure on the opening side of the groove of the substrate comprises:

[0039] Prepare a third portion on the first surface side, the third portion corresponds to the Nth chip, and the third portion is electrically connected to the second conductive structure;

[0040] Sequentially preparing the first to N-1th sub-dielectric material layers on the surface of the third part away from the substrate, wherein when preparing the i-th sub-dielectric material layer, the i-th sub-dielectric material layer is patterned to obtain the i-th sub-dielectric layer, the i-th sub-dielectric layer has a plurality of i-th openings, the second part and the third part are prepared in the i-th opening, and the third part corresponding to the i-th chip is located on the surface of the |iN|th sub-dielectric layer away from the substrate; i is an integer between 2 and N-1, and N is an integer greater than or equal to 2;

[0041] Preparing an N-th sub-dielectric material layer on a surface of the N-1-th sub-dielectric layer facing away from the substrate, patterning the N-th sub-dielectric material layer to obtain an N-th sub-dielectric layer, wherein the N-th sub-dielectric layer has a plurality of N-th openings, preparing a first portion in the N-th opening, wherein the first portion corresponding to the first chip extends in a direction perpendicular to the first surface and is electrically connected to the second conductive structure, and the first portions corresponding to the remaining chips are electrically connected to the corresponding second portions;

[0042] Preferably, after preparing the dielectric layer and the first conductive structure on the opening side of the groove of the substrate, it also includes: preparing a third conductive structure on the side of the dielectric layer away from the substrate, and the third conductive structure is electrically connected to the first part. The third aspect of the present application provides a terminal device, including the above-mentioned packaging structure, or including the packaging structure prepared by the above-mentioned preparation method.

[0043] According to the packaging structure provided in the embodiment of the present application, after the chip is placed in the groove, the smaller angle between the front side of the chip and the first surface is 70° to 90°, which is conducive to the stacking of the chips along the direction parallel to the first surface, that is, the stacking direction of the chips is perpendicular to the thickness direction of the substrate, and there is almost no need to open through holes in the substrate, which is conducive to reducing the difficulty of preparing the packaging structure; at the same time, multiple chips are electrically connected to the first conductive structure located on the opening side of the groove, which is conducive to mutual electrical connection between multiple chips through the first conductive structure, and there is almost no need to drill holes in the chip, which is conducive to reducing the difficulty of manufacturing the packaging structure, effectively improving the yield, and reducing costs; the packaging structure of the embodiment of the present application has a high degree of integration, which can reduce the packaging area and realize device miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a schematic diagram of the packaging structure in one embodiment of the present application.

[0045] Figure 2 This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0046] Figure 3 This is a schematic diagram of the top view of the substrate in one embodiment of the present application.

[0047] Figure 4This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0048] Figure 5 This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0049] Figure 6 This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0050] Figure 7 This is a schematic diagram of the packaging structure in another embodiment of the present application.

[0051] Figure 8 This is a schematic flow chart of a method for preparing a packaging structure in one embodiment of the present application.

[0052] Figures 9 to 11 This is a schematic diagram of the preparation process of a packaging structure in one embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods and means well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0055] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0056] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0057] The first aspect of the present application provides a packaging structure, referring to Figure 1 2, the packaging structure comprises: a substrate 100, the substrate 100 comprises a first surface 110 and at least one groove 130, the opening of the groove 130 is located on the first surface 110; at least one chip 200, the chip 200 is placed in the groove 130, and the smaller angle α between the front surface of the chip 200 and the first surface 110 is 70° to 90° (see Figure 2 ), for example, it can be 70°, 72°, 74°, 76°, 78°, 80°, 82°, 84°, 86°, 88° or 90°, etc.; the first conductive structure 300 is located at the opening side of the groove 130 of the substrate 100, and the first conductive structure 300 is electrically connected to the chip 200.

[0058] According to the packaging structure provided in the embodiment of the present application, after the chip is placed in the groove 130, the smaller angle between the front side of the chip 200 and the first surface is 70° to 90°, which is conducive to stacking the chips 200 along a direction parallel to the first surface 110, that is, the stacking direction of the chips 200 is perpendicular to the thickness direction of the substrate 100, and there is almost no need to open through holes in the substrate 100, which is conducive to reducing the difficulty of preparing the packaging structure; at the same time, multiple chips 200 are electrically connected to the first conductive structure 300 located on the opening side of the groove 130 of the substrate 100, which is conducive to mutual electrical connection between multiple chips 200 or electrical connection between the chip and subsequent remaining structures through the first conductive structure 300, and there is almost no need to drill holes in the chip 200, which is conducive to reducing the difficulty of manufacturing the packaging structure, effectively improving the yield, and reducing costs; the packaging structure of the embodiment of the present application has a high degree of integration, which can reduce the packaging area and realize device miniaturization.

[0059] Exemplarily, the chip 200 includes a chip body 210 and a second conductive structure 220, the second conductive structure 220 is located on the front side of the chip body 210, and the front side of the chip 200 is the surface of the second conductive structure 220 facing away from the chip body 210; it can be understood that the front side of the chip body 210 refers to the active surface, that is, the surface for circuit making.

[0060] It can be understood that the smaller angle α between the front side of the chip 200 and the first surface 110 means that the angle between the front side of the chip 200 and the first surface 110 can be an obtuse angle, an acute angle or a 0° angle, and the acute angle and / or the 0° angle are the smaller angles between the front side of the chip 200 and the first surface 110; in addition, the smaller angle α between the front side of the chip 200 and the first surface 110 means that one end of the first surface 110 of the chip 200 can gradually approach or move away from the first surface 110 within the range of the angle α.

[0061] In a preferred embodiment, the front surface of the chip 200 is perpendicular to the first surface 110. Therefore, the placement of the chip 200 can save more space, and is more conducive to reducing the packaging area and realizing device miniaturization.

[0062] In one embodiment, referring to Figure 3In the schematic diagram of the top view structure of the substrate shown, in the first direction x, the orthographic projection of the groove 130 on the first surface 110 has a first width L1, and in the second direction y, the orthographic projection of the groove 130 on the first surface 110 has a second width L2, the second width L2 is greater than the first width L1, along the thickness direction of the substrate 100, the depth H of the groove 130 is greater than the first width L1, and the first direction x and the second direction y are perpendicular to each other. Exemplarily, the shape surrounded by the groove 130 is a cuboid, the second width L2 is the length of the cuboid, the first width L1 is the width of the cuboid, the depth H of the groove 130 is the height of the cuboid, and the plane surrounded by the length and width of the cuboid is parallel to the first surface 110. When the groove 130 accommodates the chip 200, the chip 200 can be placed along the depth direction of the groove 130 or along the direction with an acute angle of 0 to 20° with the depth direction of the groove 130, so that the chip 200 is stacked along the direction parallel to the first surface 110, which is conducive to reducing the packaging area and realizing device miniaturization. Exemplarily, the chips 200 are arranged along a first direction x.

[0063] It should be noted that the first width L1 refers to the maximum distance between any two points in the orthographic projection of the groove 130 on the first surface 110 in the first direction x; the second width L2 refers to the maximum distance between any two points in the orthographic projection of the groove 130 on the first surface 110 in the second direction y.

[0064] In one embodiment, the substrate 100 includes a second surface 120, and the first surface 110 and the second surface 120 are arranged opposite to each other along the thickness direction of the substrate 100. Thus, it is convenient to stack the chips 200 along a direction parallel to the plane where the substrate is located, which is convenient to reduce the difficulty of manufacturing the packaging structure and improve the integration of the packaging structure.

[0065] In one embodiment, referring to Figure 1 , the first conductive structure 300 is electrically connected to the second conductive structure 220. Thus, the chip body 210 realizes the communication of electrical signals with the subsequent remaining structures or between different chip bodies 210 through the first conductive structure 300 and the second conductive structure 220, avoiding drilling in the chip body 210, reducing the manufacturing difficulty, and improving the manufacturing yield of the packaging structure.

[0066] It can be understood that a groove 130 that can accommodate the chip 200 is opened in the substrate 100, and the chip body 210 realizes the connection of electrical signals with subsequent remaining structures or between different chip bodies 210 through the first conductive structure 300 and the second conductive structure 220. It can also avoid opening a through hole in the substrate 100, which can reduce the difficulty of production and help improve the production yield of the packaging structure.

[0067] In one embodiment, the second conductive structure 220 is located at one end of the chip body 210 close to the first surface 110 , thereby making it easier to achieve electrical connection between the first conductive structure 300 and the second conductive structure 220 .

[0068] It can be understood that the chip body 210 is generally a rectangular parallelepiped having a length, a width and a height, the length being greater than the width and the height being greater than the width, the plane formed by the width and the height of the chip body 210 is parallel to the plane formed by the first direction x and the depth direction of the groove 130, and the plane formed by the length and the width of the chip body 210 is parallel to the first surface 110; or, the plane formed by the length and the height of the chip body 210 is parallel to the plane formed by the first direction x and the depth direction of the groove 130, and the plane formed by the height and the width of the chip body 210 is parallel to the first surface 110.

[0069] In one embodiment, in a chip 200, there are multiple second conductive structures 220, and the multiple second conductive structures 220 are arranged at intervals along a direction parallel to the front surface of the chip body 210. Therefore, the arrangement of multiple second conductive structures 220 facilitates the electrical connection between different chips 200, or between the chip 200 and subsequent structures.

[0070] In one embodiment, the second conductive structure 220 includes a metal pad. For example, the metal pad may be formed on the front side of the chip body 210 by electroplating.

[0071] In one embodiment, referring to Figure 4 The schematic diagram of the package structure shown in the figure further includes: an underfill 400 located in the gap formed by the groove 130 and the chip 200. Thus, the underfill 400 can fill the gap formed by the groove 130 and the chip 200, thereby preventing the chip 200 from shaking in the groove 130 and improving the reliability of the package structure.

[0072] In one embodiment, referring to Figure 1 , a chip 200 is placed in a groove 130, and the front faces of the chips 200 are all facing the same side. Therefore, the chips 200 correspond to the grooves 130 one by one, the structure is relatively simple, and it is more conducive to the electrical connection between the chip 200 and the first conductive structure 300, and it is more conducive to the electrical connection between the chip 200 and the subsequent structure or different chips 200.

[0073] In one embodiment, referring to Figure 5 In the schematic diagram of the package structure shown, two chips 200 are placed in one groove 130, and the back sides of the chips 200 are arranged opposite to each other in the same groove 130. Thus, the integration of the package structure can be further improved, which is more conducive to reducing the package area and realizing device miniaturization.

[0074] In a preferred embodiment, in the same groove 130 , the back surfaces of two chips 200 are in contact with each other.

[0075] It should be noted that, in the same chip 200 , the back side of the chip 200 refers to the plane opposite to the front side of the chip 200 .

[0076] In one embodiment, referring to Figure 6 The schematic diagram of the package structure shown in the figure further includes: a dielectric layer 500, which is located at the opening side of the groove 130 of the substrate 100, and the orthographic projection of the dielectric layer 500 on the first surface 110 is the orthographic projection of the groove 130 on the first surface 110; and the first conductive structure 300 is located in the dielectric layer 500. Therefore, the provision of the dielectric layer 500 is conducive to the preparation of the first conductive structure 300.

[0077] In a preferred embodiment, the orthographic projection of the dielectric layer 500 on the first surface 110 covers the orthographic projection of the groove 130 on the first surface 110 .

[0078] In one embodiment, referring to Figure 7 The schematic diagram of the package structure shown in the figure further includes: a third conductive structure 600, which is located on the side of the dielectric layer 500 away from the substrate 100, and the third conductive structure 600 is electrically connected to the first conductive structure 300. Therefore, the third conductive structure 600 facilitates the electrical connection between the package structure and other subsequent structures.

[0079] In one embodiment, the third conductive structure 600 includes a solder ball, so that the structure is simple and easy to implement.

[0080] In one embodiment, referring to Figure 7 The number of the grooves 130 is 2N, and the figure formed by the 2N grooves 130 is axially symmetrical, and the symmetry axis a is perpendicular to the first surface 110. A chip 200 is placed in one groove 130, and the i+1th chip is located on the side of the ith chip away from the symmetry axis a, i is an integer between 1 and N, and N is greater than or equal to 1. Therefore, the structure is simple and easy to implement.

[0081] In one embodiment, the dielectric layer 500 includes M layers of sub-dielectric layers 510, the j+1th layer of sub-dielectric layer 510 is located on the side of the jth layer of sub-dielectric layer 510 facing away from the substrate 100, M is greater than or equal to 1, j is an integer between 1 and M, and M is an integer greater than or equal to N; the first conductive structure 300 includes a plurality of first portions 310, located on the side of the M-1th layer of sub-dielectric layer 510 facing away from the substrate 100, the third conductive structure 600 is electrically connected to the first portion 310, and the first portion 310 is electrically connected to the corresponding second conductive structure 220.

[0082] It should be noted that the first part 310 is electrically connected to the corresponding second conductive structure 220, which means that there are multiple first parts 310, and each first part 310 corresponds to one chip 200, that is, each first part 310 corresponds to the second conductive structure 220 in one chip 200, and each first part 310 is electrically connected to the second conductive structure 220 corresponding to the first part 310. It can be understood that one chip 200 can correspond to multiple first parts 310, and one first part 310 corresponds to one chip 200.

[0083] In one embodiment, the first conductive structure 300 further includes a second portion 320 and a third portion 330, wherein the second portion 320 is located between the third portion 330 and the first portion 310, and the second portion 320 and the third portion 330 are arranged corresponding to the first portion 310; wherein, when i is 1, the first portion 310 electrically connected to the first chip coincides with the corresponding second portion 320 and third portion 330; when i is N, the third portion 330 corresponding to the first portion 310 electrically connected to the Nth chip is located on the first surface 110, the first layer of the dielectric layer covers the first portion 310, and the third portion 330 is electrically connected to the second conductive structure 220; when i is an integer from 2 to N-1, the third portion 330 corresponding to the first portion 310 electrically connected to the i-th chip is located on the surface of the |iN|th layer of the dielectric layer away from the substrate 100, and the third portion 330 extends in a direction close to the substrate 100 to be electrically connected to the second conductive structure 220, and N is an integer greater than or equal to 2. Thus, the wiring method is simple and easy to implement.

[0084] It should be noted that the second part 320 and the third part 330 are arranged corresponding to the first part 310, which means that there are multiple first parts 310, each first part 310 corresponds to one chip 200, and the second part 320 and the third part 330 connecting the corresponding first part 310 and the chip 200 are the second part 320 and the third part 330 arranged corresponding to the first part 310. It can be understood that one chip 200 can correspond to multiple first parts 310, and each first part 310 corresponds to one chip 200.

[0085] In a preferred embodiment, M is equal to N.

[0086] Exemplarily, the substrate 100 is made of glass, which has a strong bearing capacity and a low price.

[0087] The second aspect of the present application provides a method for preparing a packaging structure, referring to Figure 8 The preparation method flow chart shown in FIG. 1 includes the following process.

[0088] S100: at least one groove is formed on the first surface of the substrate. For specific structure, refer to Fig. 9 .

[0089] It should be noted that the substrate is consistent with the previous description and will not be described in detail here.

[0090] Exemplarily, the method of forming at least one groove on the first surface of the substrate includes: laying a mask on the first surface of the substrate, irradiating the side of the mask facing away from the substrate with ultraviolet light, removing the mask and etching by wet etching to obtain at least one groove.

[0091] S200: Place at least one chip in at least one groove. For details, refer to Fig.10 .

[0092] It should be noted that the smaller angle between the front surface of the chip and the surface perpendicular to the first surface is 70-90°. The chip is consistent with the previous description and will not be described in detail here.

[0093] In one embodiment, before placing at least one chip in at least one groove, the method further includes: preparing a second conductive structure on the front side of the chip body to obtain the chip.

[0094] Exemplarily, the second conductive structure is prepared on the front side of the chip body by electroplating.

[0095] S300: Prepare a first conductive structure on the opening side of the groove of the substrate. For specific structure, refer to Fig.11 .

[0096] In one embodiment, preparing a first conductive structure on the opening side of the groove of the substrate includes: preparing a dielectric layer and a first conductive structure on the opening side of the groove of the substrate. Fig.11 .

[0097] Exemplarily, preparing a dielectric layer and a first conductive structure on an open side of a groove of a substrate includes:

[0098] 1. Prepare a third portion on the first surface side, wherein the third portion is electrically connected to the second conductive structure.

[0099] 2. On the surface of the third part facing away from the substrate, sequentially prepare the 1st to N-1th sub-dielectric material layers, wherein when preparing the i-th sub-dielectric material layer, the i-th sub-dielectric material layer is patterned to obtain the i-th sub-dielectric layer, the i-th sub-dielectric layer has a plurality of i-th openings, and the second part and the third part are prepared in the i-th opening, and the third part corresponding to the i-th chip is located on the surface of the |iN|th sub-dielectric layer facing away from the substrate; i is an integer between 2 and N-1, and N is an integer greater than or equal to 2.

[0100] 3. Prepare an N-th sub-dielectric material layer on the surface of the N-1-th sub-dielectric layer facing away from the substrate, and pattern the N-th sub-dielectric material layer to obtain an N-th sub-dielectric layer, wherein the N-th sub-dielectric layer has a plurality of N-th openings, and prepare a first portion in the N-th opening, wherein the first portion corresponding to the first chip extends in a direction perpendicular to the first surface and is electrically connected to the second conductive structure, and the first portions corresponding to the remaining chips are electrically connected to the corresponding second portions.

[0101] In one embodiment, after the dielectric layer and the first conductive structure are prepared on the opening side of the groove of the substrate, the method further includes: preparing a third conductive structure on a side of the dielectric layer facing away from the substrate, wherein the third conductive structure is electrically connected to the first portion.

[0102] Illustratively, the packaging structure prepared by the preparation method of this embodiment can be combined with the previous packaging structure in whole or in part, which will not be described in detail here.

[0103] A third aspect of the present application provides a terminal device, comprising the above-mentioned packaging structure, or comprising a packaging structure prepared by the above-mentioned preparation method.

[0104] It should be noted that the above-mentioned terminal device can be a desktop computer, a tablet computer, a high-computing-power calculator, etc.

[0105] It should be noted that, in addition to the packaging structure described above, the terminal device may also include structures that a conventional terminal device should have, such as a display panel, a touch panel, a housing, etc., which will not be elaborated here.

[0106] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0107] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A packaging structure, characterized in that: include: A substrate, the substrate comprising a first surface and at least one groove, wherein an opening of the groove is located on the first surface; at least one chip, the chip being placed in the groove, and the smaller angle between the front surface of the chip and the first surface is 70° to 90°; The first conductive structure is located at the opening side of the groove of the substrate, and the first conductive structure is electrically connected to the chip.

2. The packaging structure according to claim 1, characterized in that: In a first direction, the orthographic projection of the groove on the first surface has a first width, and in a second direction, the orthographic projection of the groove on the first surface has a second width, the second width is greater than the first width, and along the thickness direction of the substrate, the depth of the groove is greater than the first width, and the first direction and the second direction are perpendicular to each other; Preferably, the front side of the chip is perpendicular to the first surface; Preferably, the substrate comprises a second surface, and along the thickness direction of the substrate, the first surface and the second surface are arranged opposite to each other; Preferably, the material of the substrate includes glass.

3. The packaging structure according to claim 2, characterized in that: The chip comprises a chip body and a second conductive structure, wherein the second conductive structure is located on the front side of the chip body, and the first conductive structure is electrically connected to the second conductive structure; Preferably, the second conductive structure is located at one end of the chip body close to the groove opening; Preferably, in one of the chips, the number of the second conductive structures is plural, and the plurality of the second conductive structures are arranged at intervals along a direction parallel to the front surface of the chip body; Preferably, the second conductive structure comprises a metal pad; Preferably, the packaging structure further comprises: bottom filling glue, which is located in the gap surrounded by the groove and the chip.

4. The packaging structure according to any one of claims 1 to 3, characterized in that: One chip is placed in one of the grooves; Preferably, the front sides of the chips all face the same side.

5. The packaging structure according to any one of claims 1 to 3, characterized in that: Two chips are placed in one groove, and in the same groove, the back surfaces of the two chips are arranged opposite to each other; Preferably, in the same groove, the back side of the chip is in contact.

6. The packaging structure according to claim 3, characterized in that: Also includes: a dielectric layer, located at an opening side of the groove of the substrate, wherein an orthographic projection of the dielectric layer on the first surface overlaps with an orthographic projection of the groove on the first surface; Preferably, the orthographic projection of the dielectric layer on the first surface covers the orthographic projection of the groove on the first surface; Preferably, the first conductive structure is located in the dielectric layer; Preferably, it further comprises: a third conductive structure, located on a side of the dielectric layer away from the substrate, the third conductive structure being electrically connected to the first conductive structure; Preferably, the third conductive structure comprises a solder ball.

7. The packaging structure according to claim 6, characterized in that: The number of the grooves is 2N, and a figure formed by the 2N grooves is axially symmetrical, with the axis of symmetry being perpendicular to the first surface. One chip is placed in one groove, and the i+1th chip is located on a side of the ith chip away from the axis of symmetry, where i is an integer between 1 and N, and N is greater than or equal to 1; Preferably, the dielectric layer includes M layers of sub-dielectric layers, the j+1th sub-dielectric layer is located on the side of the jth sub-dielectric layer away from the substrate, M is greater than or equal to 1, j is an integer between 1 and M, and M is an integer greater than or equal to N; the first conductive structure includes a plurality of first portions, located on the side of the M-1th sub-dielectric layer away from the substrate, the third conductive structure is electrically connected to the first portion, and the first portion is electrically connected to the corresponding second conductive structure; Preferably, the first conductive structure further includes a second portion and a third portion, the second portion is located between the third portion and the first portion, and the second portion and the third portion are arranged corresponding to the first portion; Wherein, when i is 1, the first portion electrically connected to the first chip overlaps with the corresponding second portion and the third portion; when i is N, the third portion corresponding to the first portion electrically connected to the Nth chip is located on the first surface, the first layer of the sub-dielectric layer covers the first portion, and the third portion is electrically connected to the second conductive structure; when i is an integer from 2 to N-1, the third portion corresponding to the first portion electrically connected to the i-th chip is located on the surface of the |iN|th layer of the sub-dielectric layer away from the substrate, and the third portion extends in a direction close to the substrate to be electrically connected to the second conductive structure, and N is an integer greater than or equal to 2; Preferably, M is equal to N.

8. A method for preparing a packaging structure, characterized in that: include: At least one groove is formed on the first surface of the substrate; At least one chip is placed in at least one of the grooves, and the smaller angle between the front surface of the chip and the surface perpendicular to the first surface is 70-90°; A first conductive structure is prepared on the open side of the groove of the substrate.

9. The preparation method according to claim 8, characterized in that: Before placing at least one chip in at least one of the grooves, the method further includes: preparing a second conductive structure on the front side of the chip body to obtain the chip; Preferably, the second conductive structure is prepared on the front side of the chip body by electroplating; Preferably, preparing a first conductive structure on the opening side of the groove of the substrate comprises: preparing a dielectric layer and a first conductive structure on the opening side of the groove of the substrate; Preferably, preparing a dielectric layer and a first conductive structure on the opening side of the groove of the substrate comprises: Prepare a third portion on the first surface side, the third portion corresponds to the Nth chip, and the third portion is electrically connected to the second conductive structure; On the surface of the third part away from the substrate, the first to the N-1th sub-dielectric material layers are sequentially prepared, wherein when preparing the i-th sub-dielectric material layer, the i-th sub-dielectric material layer is patterned to obtain the i-th sub-dielectric layer, the i-th sub-dielectric layer has a plurality of i-th openings, the second part and the third part are prepared in the i-th opening, and the third part corresponding to the i-th chip is located on the surface of the |iN|th sub-dielectric layer away from the substrate; i is an integer between 2 and N-1, and N is an integer greater than or equal to 2; Preparing an N-th sub-dielectric material layer on a surface of the N-1-th sub-dielectric layer away from the substrate, patterning the N-th sub-dielectric material layer to obtain an N-th sub-dielectric layer, wherein the N-th sub-dielectric layer has a plurality of N-th openings, preparing a first portion in the N-th opening, wherein the first portion corresponding to the first chip extends in a direction perpendicular to the first surface and is electrically connected to the second conductive structure, and the first portions corresponding to the remaining chips are electrically connected to the corresponding second portions; Preferably, after preparing the dielectric layer and the first conductive structure on the opening side of the groove of the substrate, the method further comprises: preparing a third conductive structure on a side of the dielectric layer away from the substrate, wherein the third conductive structure is electrically connected to the first portion.

10. A terminal device, characterized in that: The invention comprises the packaging structure according to any one of claims 1 to 7, or comprises the packaging structure prepared by the preparation method according to claim 8 or 9.

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