Semiconductor packaging assembly, preparation method and electronic equipment
Through the fan-out rewiring layer and multi-chip overlap, the high cost and structural fixation problems of through-silicon technology are solved, and more flexible circuit design and more efficient signal transmission are achieved, adapting to modern microelectronics technology to the packaging body Size and interconnect density requirements.
Patent Information
- Application Number
- CN202411141827.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2024-12-27
Smart Images
Figure CN119208279A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging component, a preparation method and an electronic device. Background Art
[0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits continues to shrink, the interconnection density continues to increase, and the size requirements of the package are becoming more and more stringent. Shortening the interconnection distance between chips can achieve higher bandwidth, smaller delay and better power efficiency, and make the package structure more compact and miniaturized.
[0003] In the prior art, chip interconnection usually requires the installation of an interposer, and the use of through silicon via (TSV) technology to interconnect the chip and the interposer, thereby achieving chip interconnection. However, TSV technology is expensive to manufacture, and if the interposer has a certain thickness, it is difficult to manufacture TSV. In addition, the connection relationship between the chip and the interposer is relatively fixed, the circuit routing is not flexible enough, and the resulting package structure is limited. Summary of the invention
[0004] In order to solve the above technical problems, the present disclosure provides a semiconductor packaging component, a preparation method and an electronic device.
[0005] In a first aspect, the present disclosure provides a semiconductor package assembly, including: a connection module and at least one first chip;
[0006] The connection module includes a second chip and a first redistribution layer;
[0007] The first redistribution layer is located on the active surface of the second chip; the first redistribution layer is electrically connected to the active surface of the second chip; wherein the first redistribution layer is a fan-out type redistribution layer; the first redistribution layer is electrically connected to the first chip;
[0008] The first chip and the connection module are overlapped to form a first overlapping area; the first chip and the second chip in the first overlapping area overlap, and the first chip is electrically connected to the second chip through a first connection terminal.
[0009] In some embodiments, the first chip and the connection module are overlapped to form a second overlapping area;
[0010] The first chip and the second chip in the second overlapping area do not overlap; the first chip is electrically connected to the first redistribution layer through the first connecting terminal.
[0011] In some embodiments, the connection module further includes a first plastic sealing layer;
[0012] The first plastic encapsulation layer covers the passive surface and side walls of the second chip; the first redistribution layer is located on the active surface of the second chip and the first plastic encapsulation layer.
[0013] In some embodiments, the connection module further includes a second connection terminal;
[0014] The second connection terminal is located on a side of the first redistribution layer away from the second chip; in a direction perpendicular to the thickness of the connection module, the height of the second connection terminal is greater than the height of the first chip; and the second connection terminal is used to connect to an external circuit.
[0015] In some embodiments, a second plastic encapsulation layer is further included;
[0016] The second plastic encapsulation layer covers the first chip, the first connection terminal and the second connection terminal; the first connection terminal fills and penetrates the second plastic encapsulation layer to connect to the first redistribution layer; the second connection terminal fills and penetrates the second plastic encapsulation layer to connect to the external circuit.
[0017] In some embodiments, further comprising a second redistribution layer and a third connection terminal;
[0018] The second redistribution layer is located on a side of the first chip away from the first connection terminal and the first redistribution layer; the third connection terminal is located on a side of the second redistribution layer away from the first chip and the first connection terminal; the second connection terminal and the third connection terminal are both electrically connected to the second redistribution layer.
[0019] In a second aspect, the present disclosure further provides a method for preparing a semiconductor package assembly, comprising:
[0020] forming a connection module;
[0021] The first chip and the connection module are overlapped to form a first overlapping area; the first chip and the second chip in the first overlapping area are overlapped, and the first chip is electrically connected to the second chip through a first connection terminal;
[0022] Wherein, the connection module includes a second chip and a first redistribution layer; the first redistribution layer is located on the active surface of the second chip; the first redistribution layer is electrically connected to the active surface of the second chip; wherein the first redistribution layer is a fan-out type redistribution layer.
[0023] In some embodiments, forming the connection module comprises:
[0024] providing a first carrier board;
[0025] attaching the active surface of the second chip to the first carrier;
[0026] forming a first plastic encapsulation layer and removing the first carrier board;
[0027] forming a first redistribution layer on the active surface of the second chip and the first plastic packaging layer, wherein the first redistribution layer is electrically connected to the second chip;
[0028] A second connection terminal is formed on a side of the first redistribution layer away from the second chip.
[0029] In some embodiments, after the first chip and the connection module are overlapped, the preparation method further includes:
[0030] A second plastic encapsulation layer is formed; the second plastic encapsulation layer covers the first chip, the first connection terminal and the second connection terminal; the first connection terminal fills and penetrates the second plastic encapsulation layer to connect the first redistribution layer; the second connection terminal fills and penetrates the second plastic encapsulation layer to connect the external circuit;
[0031] forming a second redistribution layer on a side of the first chip away from the first connection terminal and the first redistribution layer;
[0032] A third connection terminal is formed on a side of the second redistribution layer away from the first chip and the first connection terminal; the second connection terminal and the third connection terminal are both electrically connected to the second redistribution layer.
[0033] In a third aspect, the present disclosure further provides an electronic device, comprising any semiconductor package assembly as provided in the first aspect.
[0034] Compared with the prior art, the technical solution provided by the present invention has the following advantages:
[0035] The semiconductor package assembly provided by the present disclosure includes: a connection module and at least one first chip; the connection module includes a second chip and a first rewiring layer; the first rewiring layer is located on the active surface of the second chip; the first rewiring layer is electrically connected to the active surface of the second chip; wherein the first rewiring layer is a fan-out type rewiring layer; the first rewiring layer is electrically connected to the first chip; the first chip and the connection module are overlapped to form a first overlapping area; the first chip and the second chip in the first overlapping area overlap, and the first chip is electrically connected to the second chip through a first connection terminal. Thus, the first chip and the part of the second chip vertically overlapping in the connection module can be directly electrically connected through the first connection terminal, and a first rewiring layer is also provided, which is electrically connected to the second chip through the fan-out type first rewiring layer to realize signal transmission at different positions. The present disclosure can reduce the space occupied by each chip in the horizontal direction, shorten the length of the electrical interconnection, improve the connection reliability and signal transmission speed; and by using the fan-out type first rewiring layer, the first chip can be flexibly adapted to different types of second chips, and the overall process does not need to adopt silicon through-hole technology, the cost is low, the circuit routing is more flexible, the routing space is increased, and the design burden is reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0038] Figure 1 A schematic diagram of the structure of a semiconductor package assembly provided by an embodiment of the present disclosure;
[0039] Figure 2 A schematic structural diagram of another semiconductor package assembly provided by an embodiment of the present disclosure;
[0040] Figure 3 A schematic diagram of a process for preparing a semiconductor packaging assembly provided by an embodiment of the present disclosure;
[0041] Figure 4 A schematic flow chart of another method for preparing a semiconductor package assembly provided by an embodiment of the present disclosure;
[0042] Figure 5 A schematic structural diagram corresponding to each step of forming a first chip layer provided by an embodiment of the present disclosure;
[0043] Figure 6 A schematic flow chart of another method for preparing a semiconductor package assembly provided by an embodiment of the present disclosure;
[0044] Figure 7 for Figure 6 Schematic diagram of the structure corresponding to each step in . DETAILED DESCRIPTION
[0045] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0046] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0047] In order to solve the problem raised in the background technology section, the present disclosure provides a semiconductor package assembly. Figure 1 A schematic diagram of a semiconductor package assembly provided by an embodiment of the present disclosure, referring to Figure 1 The semiconductor package assembly includes: a connection module 10 and at least one first chip 20; the connection module 10 includes a second chip 11 and a first redistribution layer 12; the first redistribution layer 12 is located on the active surface of the second chip 11; the first redistribution layer 12 is electrically connected to the active surface of the second chip 11; wherein the first redistribution layer 12 is a fan-out redistribution layer; the first redistribution layer 12 is electrically connected to the first chip 20; the first chip 20 is overlapped with the connection module 10 to form a first overlapping area 31; the first chip 20 in the first overlapping area 31 overlaps with the second chip 11, and the first chip 20 is electrically connected to the second chip 11 through a first connection terminal 41.
[0048] For example, see Figure 1 , a first direction X and a second direction Y are pre-set, and a connection module 10 and two first chips 20 are provided, wherein the connection module 10 includes a second chip 11 and a first redistribution layer 12. The connection module 10 may also apply for multiple second chips 11. If there are multiple second chips 11, the type of the second chips 11 is not limited, and may be the same or different, and the embodiment of the present disclosure does not limit this.
[0049] The connection module 10 includes a first rewiring layer 12, which is located on the active surface of the second chip 11. There is a circuit line layer on the active surface of the second chip 11. Therefore, the first rewiring layer 12 is electrically connected to the active surface of the second chip 11, and the circuit interface position on the second chip 11 can be adjusted to make the circuit routing of the second chip 11 more flexible. The first rewiring layer 12 is a fan-out type rewiring layer. The area of the first rewiring layer 12 is larger than the active surface of the second chip 11, that is, the first rewiring layer 12 covers the active surface of the second chip 11 and extends around the second chip 11. The first rewiring layer 12 is electrically connected to the first chip 20. Therefore, the routing space when the first chip 20 is connected to the second chip 11 is increased, the circuit routing is more flexible, and the design burden is reduced. Among them, the first rewiring layer 12 is a metal film layer, which can be prepared by electroplating or deposition process; the metal material can be selected from at least one of copper, aluminum, silver, gold, and titanium.
[0050] In the second direction Y, the first chip 20 and the connection module 10 are overlapped to form a first overlap area 31. The first chip 20 and the second chip 11 overlap in the first overlap area 31, so the first chip 20 and the second chip 11 can be directly electrically connected through the first connection terminal 41. To a certain extent, the length of the electrical interconnection between the chips is shortened, the connection reliability and the signal transmission speed are improved, and the overall process does not need to use the through silicon via technology, and the cost is low.
[0051] The connection between the chips is relatively flexible, and all chips are electrically connected to an external circuit, such as an external power supply, through a first connection terminal, thereby achieving an effect of simplifying the structure.
[0052] And refer to Figure 1 The two first chips 20 can also exchange information through the second chip 11, and the first chip 20 can also process information. Therefore, in the semiconductor package component provided by the embodiment of the present disclosure, each chip can process data and exchange data, thereby improving the processing capability of the entire component.
[0053] It should be noted that the embodiment of the present disclosure does not limit the size of the overlapping area between the first chip and the second chip, and the overlapping areas can be partial or complete. There is no restriction on the type and function of each chip, and there is no restriction on the specific structure of the first connection terminal, which can be selected according to actual needs.
[0054] In the semiconductor package assembly provided by the embodiment of the present disclosure, the part of the first chip and the second chip in the connection module that vertically overlap can be directly electrically connected through the first connection terminal, and a first redistribution layer is also provided, which is electrically connected to the second chip through the fan-out first redistribution layer to achieve signal transmission at different positions. The present disclosure can reduce the space occupied by each chip in the horizontal direction, shorten the length of the electrical interconnection, improve the connection reliability and signal transmission speed; and by using the fan-out first redistribution layer, the first chip can be flexibly adapted to different types of second chips, and the overall process does not need to use silicon through-hole technology, which is low in cost, more flexible in circuit routing, and increases the routing space, reducing the design burden.
[0055] It should be noted that the redistribution layers and the connection terminals mentioned in the present disclosure may be made of the same material or different materials, which will not be explained further.
[0056] In some embodiments, continue to refer to Figure 1 The first chip 20 overlaps with the connection module 10 to form a second overlapping area 32 ; the first chip 20 and the second chip 11 in the second overlapping area 32 do not overlap; the first chip 20 is electrically connected to the first redistribution layer 12 through the first connection terminal 41 .
[0057] After the first chip 20 and the connection module 10 are overlapped, a second overlap region 32 is formed. In the second overlap region 32, the second chip 11 in the connection module 10 does not overlap with the first chip 20, so the second chip 11 cannot be directly electrically connected to the first chip 20. The connection module 10 includes a first rewiring layer 12, which is a fan-out type rewiring layer. The first rewiring layer 12 covers the active surface of the second chip 11 and extends around the second chip 11. The first rewiring layer 12 is present in the second overlap region 32. Therefore, the first rewiring layer 12 located in the second overlap region 32 can be electrically connected to the first chip 20 through the first connection terminal 41, so that the first chip 20 is electrically connected to the first rewiring layer 12 through the first connection terminal 41, so that the first chip 20 and the second chip 11 are overlapped and interconnected. By utilizing the fan-out first redistribution layer 12, the first chip 20 can be flexibly adapted to different types of second chips 11, and the overall process does not need to use through silicon via technology, which is low in cost, more flexible in circuit routing, and increases routing space, reducing the design burden.
[0058] In some embodiments, continue to refer to Figure 1 The connection module 10 further includes a first plastic encapsulation layer 13 ; the first plastic encapsulation layer 13 covers the passive surface and sidewalls of the second chip 11 ; and the first redistribution layer 12 is located on the active surface of the second chip 11 and the first plastic encapsulation layer 13 .
[0059] Exemplarily, the connection module 10 further includes a first plastic encapsulation layer 13, the material of the first plastic encapsulation layer 13 may be a resin, for example, a combination of one or more of epoxy molding compound (EMC), polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc. The first plastic encapsulation layer 13 covers the passive surface and side wall of the second chip 11, the active surface of the second chip 11 is exposed, the first redistribution layer 12 is located on the active surface of the second chip 11 and the first plastic encapsulation layer 13, and the active surface of the second chip 11 is electrically connected to the first redistribution layer 12. The first plastic encapsulation layer 13 can increase the setting area of the first redistribution layer 12, thereby increasing the area of the first redistribution layer 12, which is conducive to increasing the routing space, and the circuit routing is more flexible, so that the first chip 20 can be flexibly adapted to different types of second chips 11. The first plastic encapsulation layer 13 can also protect the second chip 11 from damage caused by external factors, such as liquid, metal or water oxygen erosion, which affects the service life, and fix all pre-packaged structures at the same time to avoid movement between structures causing the connection circuit to be disconnected.
[0060] In some embodiments, continue to refer to Figure 1 The connection module 10 also includes a second connection terminal 42; the second connection terminal 42 is located on the side of the first redistribution layer 12 away from the second chip 11; in a direction perpendicular to the thickness of the connection module 10, the height of the second connection terminal 42 is greater than the height of the first chip 20; the second connection terminal 42 is used to connect an external circuit.
[0061] Exemplarily, the connection module 10 further includes a second connection terminal 42, which is electrically connected to the first redistribution layer 12. The second connection terminal 42 can be connected to an external circuit to connect different signals, such as connecting a power signal to power each chip. The second connection terminal 42 is located on the side of the first redistribution layer 12 away from the second chip 11, that is, the second connection terminal 42 and the first connection terminal 41 are located on the same side of the second chip 11. The height of the second connection terminal 42 is greater than the height of the first chip 20, so as to facilitate the electrical connection between the external circuit and the second connection terminal 42.
[0062] In some embodiments, continue to refer to Figure 1 The semiconductor package assembly also includes a second plastic packaging layer 14; the second plastic packaging layer 14 covers the first chip 20, the first connecting terminal 41 and the second connecting terminal 42; the first connecting terminal 41 fills and penetrates the second plastic packaging layer 14, connecting to the first redistribution layer 12; the second connecting terminal 42 fills and penetrates the second plastic packaging layer 14, connecting to the external circuit.
[0063] Exemplarily, the material of the second plastic encapsulation layer 14 may be a resin, for example, a combination of one or more of epoxy molding compound (EMC), polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc. The material of the second plastic encapsulation layer 14 may be the same as or different from the material of the first plastic encapsulation layer 13, and the disclosed embodiment does not limit this. The second plastic encapsulation layer 14 covers the first chip 20, the first connection terminal 41 and the second connection terminal 42, and fills the gap between the first chip 20 and the first connection terminal 41. The first connection terminal 41 fills and penetrates the second plastic encapsulation layer 14, which can prevent the first chip 20 from being corroded by external water and oxygen, and fixes the connection between the first chip 20 and the first connection terminal 41, so that the connection between the two is more stable, the connection reliability is improved, and the connection between the first chip 20 and the first redistribution layer 12 can also be strengthened. In addition, the second connection terminal 42 also fills and penetrates the second plastic encapsulation layer 14, and the exposed surface of the second connection terminal is higher than the surface of the second plastic encapsulation layer 14, so that the first connection terminal can be electrically connected to the external circuit. The second plastic encapsulation layer 14 also covers part of the second connection terminal 42, and can also stabilize the connection between the second connection terminal 42 and the first redistribution layer 12. It can prevent damage to the various structures caused by external factors, such as liquid, metal or water oxygen corrosion, which affects the service life, and can also fix the entire pre-packaged structure to prevent the structure from moving and causing the connection circuit to be disconnected.
[0064] It should be noted that the embodiment of the present disclosure does not limit the number and position of the first connection terminals and the second connection terminals, and they can be set according to actual needs.
[0065] In some embodiments, continue to refer to Figure 1 The semiconductor package assembly further includes a second redistribution layer 15 and a third connection terminal 43 .
[0066] The second redistribution layer 15 is located on the side of the first chip 20 away from the first connection terminal 41 and the first redistribution layer 12; the third connection terminal 43 is located on the side of the second redistribution layer 15 away from the first chip 20 and the first connection terminal 41; the second connection terminal 42 and the third connection terminal 43 are both electrically connected to the second redistribution layer 15.
[0067] Exemplarily, a second redistribution layer 15 is also provided, and the second redistribution layer 15 is located on the side of the first chip 20 away from the first connection terminal 41 and the first redistribution layer 12, and the second redistribution layer 15 is electrically connected to the first connection terminal 41. The second redistribution layer 15 is a metal film layer, which can be prepared by electroplating or deposition process; the metal material can be selected from at least one of copper, aluminum, silver, gold, and titanium. The third connection terminal 43 is located on the side of the second redistribution layer 15 away from the first chip 20 and the first connection terminal 41, and the third connection terminal 43 is electrically connected to the second redistribution layer 15. The second connection terminal 42 and the third connection terminal 43 are both electrically connected to the second redistribution layer 15, so the third connection terminal 43 can be electrically connected to each chip via the second redistribution layer 15, the second connection terminal 43, and the first redistribution layer 12. The third connection terminal 43 is provided to adjust the circuit routing of the package component and reduce the space occupied in the first direction X. The third connection terminal 43 is used to connect to other components, such as substrates, printed circuit boards (PCB) or processors. The processor can be a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities to transmit data signals.
[0068] Optional, Figure 2 A schematic diagram of the structure of another semiconductor package assembly provided by the embodiment of the present disclosure is shown in FIG. Figure 2 , Figure 2 A variety of different ways of setting the second connection terminal are provided, and the second connection terminal 42 is used to connect to an external circuit or an external power supply. For example, the second connection terminal is set as a copper column bump, or as a welding bump, or the second connection terminal is obtained by TSV technology. In some other embodiments, wire bonding can also be used for electrical connection.
[0069] On the basis of the above-mentioned implementation modes, the embodiments of the present disclosure further provide a method for preparing a semiconductor packaging component, which is used to prepare any of the above-mentioned semiconductor packaging components and has corresponding beneficial effects. To avoid repeated description, it will not be repeated here.
[0070] Figure 3 A schematic diagram of a method for preparing a semiconductor package assembly according to an embodiment of the present disclosure is provided. Figure 3 , the preparation method comprises:
[0071] S100: forming a connection module.
[0072] Among them, the connection module includes a second chip and a first redistribution layer; the first redistribution layer is located on the active surface of the second chip; the first redistribution layer is electrically connected to the active surface of the second chip; wherein the first redistribution layer is a fan-out type redistribution layer; the first redistribution layer is electrically connected to the first chip.
[0073] For example, in combination Figure 1 The connection module 10 of the semiconductor package assembly includes a first redistribution layer 12, which is located on the active surface of the second chip 11. There is a circuit line layer on the active surface of the second chip 11. Therefore, the first redistribution layer 12 is electrically connected to the active surface of the second chip 11, and the circuit interface position on the second chip 11 can be adjusted to make the circuit routing of the second chip 11 more flexible. The first redistribution layer 12 is a fan-out redistribution layer. The area of the first redistribution layer 12 is larger than the active surface of the second chip 11, that is, the first redistribution layer 12 covers the active surface of the second chip 11 and extends around the second chip 11. The first redistribution layer 12 is electrically connected to the first chip 20. Therefore, the routing space when the first chip 20 is connected to the second chip 11 is increased, the circuit routing is more flexible, and the design burden is reduced. Among them, the first redistribution layer 12 is a metal film layer, which can be prepared by electroplating or deposition process; the metal material can be selected from at least one of copper, aluminum, silver, gold, and titanium.
[0074] The connection module 10 includes a second chip 11 and a first redistribution layer 12. The connection module 10 may also include multiple second chips 11. If there are multiple second chips 11, the types of the second chips 11 are not limited and may be the same or different, and the embodiment of the disclosure does not limit this.
[0075] S200, overlapping the first chip and the connection module to form a first overlapping area; the first chip and the second chip in the first overlapping area overlap, and the first chip is electrically connected to the second chip through a first connection terminal.
[0076] For example, continue to refer to Figure 1 In the second direction Y, the first chip 20 and the connection module 10 are overlapped to form a first overlap area 31. The first chip 20 and the second chip 11 in the first overlap area 31 overlap, so the first chip 20 and the second chip 11 can be directly electrically connected through the first connection terminal 41. To a certain extent, the length of the electrical interconnection between the chips is shortened, the connection reliability and the signal transmission speed are improved, and the overall process does not need to use the through silicon via technology, and the cost is low.
[0077] The two first chips can also exchange information through the second chip, and the first chip can also process information. Therefore, in the semiconductor packaging component provided by the embodiment of the present disclosure, each chip can process data and exchange data, thereby improving the processing capability of the entire component.
[0078] The part where the first chip and the second chip in the connection module overlap vertically can be directly electrically connected through the first connection terminal, and a first rewiring layer is also provided, which is electrically connected to the second chip through the fan-out first rewiring layer to achieve signal transmission at different positions. The present disclosure can reduce the space occupied by each chip in the horizontal direction, shorten the length of the electrical interconnection, improve the connection reliability and signal transmission speed; and by using the fan-out first rewiring layer, the first chip can be flexibly adapted to different types of second chips, and the overall process does not need to use silicon through-hole technology, the cost is low, the circuit routing is more flexible, the routing space is increased, and the design burden is reduced.
[0079] Optionally, the first chip and the connection module are overlapped to form a second overlapping area; the first chip and the second chip in the second overlapping area do not overlap; and the first chip is electrically connected to the first redistribution layer through the first connection terminal.
[0080] The first redistribution layer in the second overlapping region can be electrically connected to the first chip through the first connection terminal, so that the first chip is electrically connected to the first redistribution layer through the first connection terminal, thereby overlapping and interconnecting the first chip and the second chip. By using the fan-out first redistribution layer, the first chip can be flexibly adapted to different types of second chips, and the overall process does not need to use silicon through-via technology, which is low in cost, more flexible in circuit routing, and increases routing space, reducing the design burden.
[0081] In some embodiments, Figure 4 A schematic diagram of a process flow of another method for preparing a semiconductor package assembly provided by an embodiment of the present disclosure is provided. Figure 5 A schematic diagram of the structure corresponding to each step of forming a connection module provided in an embodiment of the present disclosure, referring to Figure 4 and Figure 5 , forming a connection module including:
[0082] S110 , providing a first carrier board 101 .
[0083] S111 , attaching the active surface of the second chip 11 to the first carrier 101 .
[0084] Exemplarily, the second chip 11 is attached to the first carrier 101 by using adhesive 102, and the active surface of the second chip 11 faces the first carrier 101. Four second chips 11 are shown in the figure, and the number of second chips 11 is set according to actual needs during actual operation, and there is no limit on the number of second chips 11.
[0085] S112 , forming a first plastic encapsulation layer 13 and removing the first carrier board 101 .
[0086] Exemplarily, the second chip 11 is plastic-encapsulated with an insulating material to form a first plastic-encapsulation layer 13, for example, epoxy resin is selected as the insulating material. The first plastic-encapsulation layer 13 covers the passive surface and sidewalls of the second chip 11, and the surface of the first carrier 101 facing the second chip 11. Optionally, according to actual needs, the first plastic-encapsulation layer 13 can be thinned by grinding until the circuit interface of the second chip 11 is exposed. Further, the first carrier 101 is removed, for example, the adhesive 102 is removed by pyrolysis, and the second chip 11 is separated from the first carrier 101, leaving only the second chip 11 coated with the first plastic-encapsulation layer 13.
[0087] S113 , forming a first redistribution layer 12 on the active surface of the second chip 11 and the first plastic packaging layer 13 , wherein the first redistribution layer 12 is electrically connected to the second chip 11 .
[0088] Exemplarily, after removing the first carrier 101, the second chip 11 is turned upside down, and a first redistribution layer 12 is formed on the active surface side of the second chip 11 and on the surface of the first plastic packaging layer 13 which is in the same plane as the active surface by using an electroplating or deposition process. The first redistribution layer 12 is a fan-out type redistribution layer, and the first redistribution layer 12 is electrically connected to the circuit connection layer of the second chip 11 to adjust the circuit interface position of the chip and make the chip component routing more flexible.
[0089] S114 , forming a second connection terminal 42 on a side of the first redistribution layer 12 away from the second chip 11 .
[0090] Furthermore, the second connection terminal 42 is manufactured by electroplating process. The second connection terminal 42 is electrically connected to the first redistribution layer 12 and the second chip 11 . The second connection terminal 42 and the second chip 11 are located on different sides of the first redistribution layer 12 .
[0091] The second connection terminal includes a second conductor column 421, and the second conductor column 421 can be made of at least one of copper, aluminum, silver, gold, and titanium. Preferably, copper is used for the second conductor column 421. It should be noted that only one second chip is shown in the accompanying drawings corresponding to this step, and the other second chips are not shown.
[0092] In some embodiments, Figure 6 A schematic diagram of a process flow of another method for preparing a semiconductor package assembly provided by an embodiment of the present disclosure is provided. Figure 7 for Figure 6 The structural diagram corresponding to each step in the reference Figure 6 and Figure 7 After the first chip 20 and the connection module 10 are overlapped, the preparation method further includes:
[0093] S310, forming a second plastic encapsulation layer 14; the second plastic encapsulation layer 14 covers the first chip 20, the first connection terminal 41 and the second connection terminal 42; the first connection terminal 41 fills and penetrates the second plastic encapsulation layer 14, connecting to the first redistribution layer 12; the second connection terminal 42 fills and penetrates the second plastic encapsulation layer 14, connecting to the external circuit.
[0094] Exemplarily, after the first chip 20 and the connection module 10 are overlapped, the first chip 20 located in the first overlap area is directly electrically connected to the second chip 11 through the first connection terminal 41, and the first chip 20 located in the second overlap area is electrically connected to the second chip 11 through the first redistribution layer 12. After the first chip 20 and the connection module are interconnected, a second plastic encapsulation layer 14 needs to be formed. The first chip 20, the first connection terminal 41 and the second connection terminal 42 are plastic encapsulated with an insulating material to form a second plastic encapsulation layer 14, for example, epoxy resin is selected as the insulating material. The second plastic encapsulation layer 14 fills the gap between the first chip 20 and the first connection terminal 41, and the first connection terminal 41 fills and penetrates the second plastic encapsulation layer 14, which can prevent the first chip 20 from being corroded by external water and oxygen, and fix the connection between the first chip 20 and the first connection terminal 41, so that the connection between the two is more stable, the connection reliability is improved, and the connection between the first chip 20 and the first redistribution layer 12 can also be strengthened. The second plastic encapsulation layer 14 also covers the second conductor post 421 of the second connection terminal 42, and the second plastic encapsulation layer 14 is thinned by grinding until the second conductor post 421 is exposed on the surface of the second plastic encapsulation layer 14 on the side away from the first redistribution layer 12, so that the second conductor post 421 fills and penetrates the second plastic encapsulation layer 14. The first connection terminal can be made of at least one of copper, aluminum, silver, gold, and titanium. Preferably, the first connection terminal is made of copper.
[0095] S311 , forming a second redistribution layer 15 on a side of the first chip 20 away from the first connection terminal 41 and the first redistribution layer 12 .
[0096] Exemplarily, after forming the second plastic encapsulation layer 14 , a second redistribution layer 15 is formed on the side of the first chip 20 away from the first connection terminal 41 and the first redistribution layer 12 by electroplating or deposition process, and the second redistribution layer 31 is electrically connected to the second conductor column 421 of the second connection terminal 42 .
[0097] S312 , forming a third connection terminal 43 on a side of the second redistribution layer 15 away from the first chip 20 and the first connection terminal 41 ; the second connection terminal 42 and the third connection terminal 43 are both electrically connected to the second redistribution layer 15 .
[0098] Exemplarily, a third connection terminal 43 is formed on the side of the second redistribution layer 15 away from the first chip 20 by an electroplating process, and the third connection terminal 43 is electrically connected to the second redistribution layer 15. The third connection terminal 43 includes a third conductor column and a third welding block, and the third conductor column is electrically connected to the second redistribution layer 15. A third welding block is formed at one end of the third conductor column away from the second redistribution layer 15, and the third welding block is a cap-shaped solder block, which can be made of solder. The third welding block can be electrically connected to an external circuit. Similarly, the second connection terminal 42 also includes a second welding block 422, and a second welding block 422 is formed at one end of the second conductor column 421 away from the first redistribution layer 12. The second welding block 422 is a cap-shaped solder block, which can be made of solder and can be electrically connected to an external power supply. The second connection terminal 42 is also electrically connected to the second redistribution layer 15.
[0099] The embodiment of the present disclosure does not limit the type of external circuits of the second connection terminal and the third connection terminal, and they may also be electrically connected to other components, such as a substrate, a printed circuit board or a processor, according to actual needs.
[0100] Based on the above implementation, the embodiment of the present disclosure further provides an electronic device, which includes: any one of the above semiconductor packaging components, which has corresponding beneficial effects and is not limited here to avoid repeated description.
[0101] The electronic device includes but is not limited to portable devices (such as laptops), mobile communication devices (such as smart phones and tablets) and computer servers.
[0102] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0103] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A semiconductor package assembly, characterized in that: include: A connection module and at least one first chip; The connection module includes a second chip and a first redistribution layer; The first redistribution layer is located on the active surface of the second chip; the first redistribution layer is electrically connected to the active surface of the second chip; wherein the first redistribution layer is a fan-out type redistribution layer; the first redistribution layer is electrically connected to the first chip; The first chip and the connection module are overlapped to form a first overlapping area; the first chip and the second chip in the first overlapping area overlap, and the first chip is electrically connected to the second chip through a first connection terminal.
2. The semiconductor package assembly according to claim 1, wherein: The first chip and the connection module are arranged to overlap and form a second overlapping area; The first chip and the second chip in the second overlapping area do not overlap; the first chip is electrically connected to the first redistribution layer through the first connecting terminal.
3. The semiconductor package assembly according to claim 1, wherein: The connection module further includes a first plastic sealing layer; The first plastic encapsulation layer covers the passive surface and side walls of the second chip; the first redistribution layer is located on the active surface of the second chip and the first plastic encapsulation layer.
4. The semiconductor package assembly according to claim 3, characterized in that: The connection module also includes a second connection terminal; The second connection terminal is located on a side of the first redistribution layer away from the second chip; in a direction perpendicular to the thickness of the connection module, the height of the second connection terminal is greater than the height of the first chip; and the second connection terminal is used to connect to an external circuit.
5. The semiconductor package assembly according to claim 4, wherein: Also includes a second plastic sealing layer; The second plastic encapsulation layer covers the first chip, the first connection terminal and the second connection terminal; the first connection terminal fills and penetrates the second plastic encapsulation layer to connect to the first redistribution layer; the second connection terminal fills and penetrates the second plastic encapsulation layer to connect to the external circuit.
6. The semiconductor package assembly according to claim 5, characterized in that: Also includes a second redistribution layer and a third connection terminal; The second redistribution layer is located on a side of the first chip away from the first connection terminal and the first redistribution layer; the third connection terminal is located on a side of the second redistribution layer away from the first chip and the first connection terminal; the second connection terminal and the third connection terminal are both electrically connected to the second redistribution layer.
7. A method for preparing a semiconductor package component, characterized in that: include: forming a connection module; The first chip and the connection module are overlapped to form a first overlapping area; the first chip and the second chip in the first overlapping area are overlapped, and the first chip is electrically connected to the second chip through a first connection terminal; Among them, the connection module includes a second chip and a first redistribution layer; the first redistribution layer is located on the active surface of the second chip; the first redistribution layer is electrically connected to the active surface of the second chip; wherein the first redistribution layer is a fan-out type redistribution layer, and the first redistribution layer is electrically connected to the first chip.
8. The preparation method according to claim 7, characterized in that: The forming of the connection module comprises: providing a first carrier board; attaching the active surface of the second chip to the first carrier; forming a first plastic encapsulation layer and removing the first carrier board; forming a first redistribution layer on the active surface of the second chip and the first plastic packaging layer, wherein the first redistribution layer is electrically connected to the second chip; A second connection terminal is formed on a side of the first redistribution layer away from the second chip.
9. The preparation method according to claim 8, characterized in that: After the first chip and the connection module are overlapped, the preparation method further includes: A second plastic encapsulation layer is formed; the second plastic encapsulation layer covers the first chip, the first connection terminal and the second connection terminal; the first connection terminal fills and penetrates the second plastic encapsulation layer to connect the first redistribution layer; the second connection terminal fills and penetrates the second plastic encapsulation layer to connect the external circuit; forming a second redistribution layer on a side of the first chip away from the first connection terminal and the first redistribution layer; A third connection terminal is formed on a side of the second redistribution layer away from the first chip and the first connection terminal; the second connection terminal and the third connection terminal are both electrically connected to the second redistribution layer.
10. An electronic device, characterized in that: Comprising the semiconductor package assembly as described in any one of claims 1-6.