Semiconductor packaging structure

Abstract

The invention relates to the field of semiconductors, and discloses a semiconductor packaging structure which comprises a substrate and at least two chips. The at least two chips are sequentially stacked above the substrate, and two adjacent chips are staggered along a first direction; a plurality of bonding pads are arranged on the two opposite sides of each chip in the second direction; a plurality of golden fingers are arranged on two opposite sides of the substrate along the second direction; the second direction is perpendicular to the first direction; for two adjacent chips, each bonding pad of one chip and one bonding pad corresponding to the other chip are electrically connected to different welding spots on the same golden finger through leads respectively; and along the first direction, a first distance between different welding spots on the same golden finger is smaller than or equal to a second distance between corresponding different bonding pads.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor packaging structure. Background Art

[0002] As the demand for chip performance continues to increase, chips need to meet smaller sizes and larger capacities. Semiconductor packaging refers to the process of processing tested wafers into independent chips according to product models and functional requirements. There is still room for improvement in the design of semiconductor packaging structures to reduce the size of packaged chips. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a chip state control method, a state control logic circuit and a memory, which can reduce the size of the packaged chip.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides a semiconductor packaging structure, which includes: a substrate and at least two chips; at least two chips are stacked in sequence on top of the substrate, wherein two adjacent chips are staggered along a first direction; each chip is provided with a plurality of pads on two opposite sides along a second direction; the substrate is provided with a plurality of gold fingers on two opposite sides along the second direction; the second direction is perpendicular to the first direction; for two adjacent chips, each pad of one chip and a pad corresponding to the other chip are electrically connected to different solder joints on the same gold finger through leads respectively; along the first direction, a first distance between different solder joints on the same gold finger is less than or equal to a second distance between corresponding different pads.

[0006] In some embodiments, along the second direction, there is a third distance between different solder joints located on the same gold finger; and the third distance is greater than 0.

[0007] In some embodiments, the first distance is smaller than the second distance; and for the same gold finger, projections of the corresponding different leads on the upper surface of the substrate have an angle.

[0008] In some embodiments, the extension direction of the gold finger is different from the first direction and the second direction.

[0009] In some embodiments, of the two leads connected to the same gold finger, an extending direction of one lead is parallel to an extending direction of the gold finger, and an extending direction of the other lead is perpendicular to an extending direction of the gold finger.

[0010] In some embodiments, the first distance is equal to the second distance; and for the same gold finger, the projections of the corresponding different leads on the upper surface of the substrate are parallel to each other.

[0011] In some embodiments, the shape of the gold finger is a broken line; the gold finger includes: two ends extending along the second direction, and a middle portion extending along a fourth direction; wherein the fourth direction is different from the first direction and the second direction.

[0012] In some embodiments, along the first direction, a misaligned distance between two adjacent chips is less than or equal to 1.5 times a distance between two adjacent pads on each chip.

[0013] In some embodiments, a plurality of the pads are disposed on the upper surface of each of the chips.

[0014] In some embodiments, each of the chips includes: a bare die and a redistribution layer; a plurality of bare die pads are arranged on two opposite sides of the bare die along the second direction; and the plurality of bare die pads located on the first side are guided to the corresponding pads located on the second side through the redistribution layer.

[0015] In some embodiments, along the first direction, the distance between adjacent pads is greater than the distance between adjacent die pads.

[0016] It can be seen that the embodiment of the present disclosure provides a semiconductor packaging structure, including: a substrate and at least two chips. The at least two chips are stacked on top of the substrate in sequence, wherein two adjacent chips are staggered along a first direction; each chip is provided with a plurality of pads on two opposite sides along a second direction; the substrate is provided with a plurality of gold fingers on two opposite sides along the second direction; the second direction is perpendicular to the first direction; for two adjacent chips, each pad of one chip and a pad corresponding to the other chip are electrically connected to different solder joints on the same gold finger through leads respectively; along the first direction, the first distance between different solder joints on the same gold finger is less than or equal to the second distance between the corresponding different pads. It can be understood that, first, by displacing two adjacent chips along the first direction, it is convenient to adjust the angle of the lead, and even to adjust the solder joint, thereby saving the area occupied on the substrate; second, by connecting two corresponding pads on different chips to the same gold finger, only a small number of gold fingers can be set, saving the area occupied on the substrate; third, the first distance between different solder joints on the same gold finger is less than or equal to the second distance between the corresponding different pads, so that the size of the gold finger can be smaller, which can further save the area occupied on the substrate. In summary, in the embodiment of the present disclosure, the area occupied on the substrate is smaller, so the size of the substrate can be reduced, thereby saving material costs; at the same time, the size of the packaged chip can be reduced, saving the space occupied by the chip on the printed circuit board (PCB). BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 1 ;

[0018] Figure 2 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 2 ;

[0019] Figure 3 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 3 ;

[0020] Figure 4 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 4 ;

[0021] Figure 5 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 5 ;

[0022] Figure 6 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 6 ;

[0023] Figure 7 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 7 ;

[0024] Figure 8 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 8 ;

[0025] Fig. 9 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 9 . DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0027] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0029] In this document, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element or there can be an intervening layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "under" the other layer / element when the orientation is reversed.

[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0031] The terms used herein are intended only to describe specific embodiments and are not intended to limit the present disclosure. It should be understood that the singular "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. It should also be understood that the term "and / or" includes any and all combinations of the relevant listed items. In addition, all numerical ranges herein include endpoint values.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0033] In the related art, the packaging of DDR (Double Data Rate) usually adopts WBGA (window ball grid array) structure and FcCSP (flip chip scale packaged) structure. These two packaging structures have the problem of insufficient integration, and their sizes still have room for further optimization.

[0034] Figure 1 and Figure 2 is a set of optional structural schematic diagrams of the semiconductor packaging structure provided by the embodiment of the present disclosure, wherein: Figure 1 is a top view, Figure 2 is the corresponding cross-sectional view. Figure 1 and Figure 2 As shown, the semiconductor package structure includes a substrate 10 and at least two chips 20 .

[0035] refer to Figure 1 and Figure 2 At least two chips 20 are sequentially stacked on the substrate 10, wherein two adjacent chips 20 are staggered along the first direction X. A plurality of pads 201 are provided on two opposite sides of each chip 20 along the second direction Y, and a plurality of gold fingers 101 are provided on two opposite sides of the substrate 10 along the second direction Y, wherein the second direction Y is perpendicular to the first direction X. For two adjacent chips 20, each pad 201 of one chip 20 and a pad 201 corresponding to the other chip 20 are electrically connected to different solder joints 102 on the same gold finger 101 through wires 202, respectively.

[0036] It should be noted that Figure 1 and Figure 2 For convenience of description, the chip 20 at the bottom (i.e., the chip 20 closer to the substrate 10) is referred to as the first chip 20, and the chip 20 at the top (i.e., the chip 20 farther from the substrate 10) is referred to as the second chip 20.

[0037] like Figure 2 As shown, in one embodiment, the first chip 20 is fixed on the substrate 10 through an adhesive layer (not shown in the figure), and the second chip 20 is fixed on the first chip 20 through an adhesive layer (shaded part in the figure). The adhesive layer can be a DAF or NCF film. Since multiple chips 20 can be placed on the first chip 20, the thickness of the first chip 20 can be thicker than that of other chips, so that the first chip 20 can withstand greater pressure.

[0038] It should also be noted that Figure 1 and Figure 2 In FIG. 1 , the pad 201 on the first chip 20 and the pad 201 on the second chip 20 are filled with different colors. Figure 1 In the figure, some pads 201 on the second chip 20 overlap with the corresponding pads 201 on the first chip 20; due to shielding, some pads 201 on the second chip 20 are not shown.

[0039] In the disclosed embodiment, the gold finger 101 is a conductive contact located on the substrate 10. Different chips 20 can transmit signals by electrically connecting the gold finger 101, for example, transmitting power signals or data signals; in addition, the chip 20 can also be grounded through the gold finger 101. The gold finger 101 can be made of a highly conductive metal material (such as copper or gold); and the metal material used to make the gold finger 101 has good ductility, so that the shape of the gold finger 101 is easy to design and process.

[0040] In the disclosed embodiment, each chip 20 may be a memory particle (die). By stacking the memory particles in three dimensions, the memory capacity can be increased while maintaining a smaller particle size, thereby meeting the design requirements of a high-density printed circuit board.

[0041] It should be noted that the semiconductor packaging process can include the following steps: cutting the wafer into small particles (die); then mounting the cut particles on a substrate; then using extremely fine metal (gold, tin, copper or aluminum) wires to connect the chip's pads to the corresponding solder joints of the substrate to form the required circuit; finally, encapsulating and protecting the independent chips with a casing.

[0042] Figure 3 yes Figure 1 A partial enlarged view of Figure 3 The figure shows a partial structure corresponding to a golden finger 101. It should be noted that: Figure 3 The two pads 201 are located on the two chips 20 respectively and are distinguished by different filling colors.

[0043] In some embodiments of the present disclosure, reference Figure 3 , along the first direction X, the first distance d1 between different solder joints 102 on the same gold finger 101 is smaller than the second distance d2 between the corresponding different pads 201. Accordingly, for the same gold finger 101, the projections of the corresponding different leads 202 on the upper surface of the substrate 10 have an angle; that is, from a top view, the different leads 202 connected to the same gold finger 101 are not parallel to each other.

[0044] In the embodiments of the present disclosure, reference Figure 3 The lead 202 on the left side is shorter than the lead 202 on the right side. Accordingly, the solder joint 102 on the left side is located further inward in the second direction Y, that is, closer to the chip 20. Figure 2 , the lead 202 on the left side is connected to the first chip 20 (i.e. the chip 20 at the bottom), and the lead 202 on the right side is connected to the second chip 20 (i.e. the chip 20 at the top). In this way, the lead 202 connected to the bottom chip 20 is set shorter, which can avoid the different leads 202 connected to the same gold finger 101 from interlacing in space, that is, avoid the projections of different leads 202 on the upper surface of the substrate 10 from intersecting, thereby avoiding the risk of short circuits due to the close distance between different leads 202.

[0045] It is understandable that, first, by staggering two adjacent chips 20 along the first direction X, the angle of the lead 202 can be easily adjusted, and even the solder joint 102 can be easily adjusted, thereby saving the area occupied by the substrate 10 .

[0046] Second, two corresponding pads 201 on different chips 20 are connected to the same gold finger 101 . In this way, only a small number of gold fingers 101 are provided, thus saving the occupied area on the substrate 10 .

[0047] Third, the first distance d1 between different solder joints 102 on the same gold finger 101 is smaller than the second distance d2 between the corresponding different pads 201 . Thus, the size of the gold finger 101 can be smaller, which can further save the occupied area on the substrate 10 .

[0048] In summary, in the embodiment of the present disclosure, the area occupied on the substrate 10 is relatively small, so the size of the substrate 10 can be reduced, thereby saving material costs; at the same time, the size of the packaged chip can be reduced, saving the space occupied by the chip on the printed circuit board.

[0049] In the embodiments of the present disclosure, reference Figure 3 , the extension direction of the gold finger 101 is different from the first direction X and the second direction Y. Figure 3 The shape of the gold finger 101 shown is a boat shape. The shape of the gold finger 101 can also be other shapes, such as an arc shape. The shape of the gold finger 101 can be set to adapt to the positions of the two solder joints 102.

[0050] It is understandable that the extension direction of the gold finger 101 is set to be different from the first direction X and the second direction Y, and is more suitable for the arrangement direction of the two solder joints 102. In this way, the area of ​​the gold finger can be saved, and the area occupied on the substrate 10 can be saved, and the size of the substrate 10 can be reduced.

[0051] In some embodiments of the present disclosure, reference Figure 4 , the lead 2021 connects the pad 201 on the first chip and the gold finger 101, and the lead 2022 connects the pad 201 on the second chip and the gold finger 101. The extension direction of the lead 2021 is parallel to the extension direction f of the gold finger 101, and the extension direction of the lead 2022 is perpendicular to the extension direction f of the gold finger 101. In other words, of the two leads 2021 and 2022 connected to the same gold finger 101, the extension direction of one lead 2021 is parallel to the extension direction f of the gold finger 101, and the extension direction of the other lead 2022 is perpendicular to the extension direction f of the gold finger 101.

[0052] It should be noted that in process design and manufacturing, due to errors or limitations in process levels, lead 2021 and lead 2022 may not be strictly perpendicular to each other, and the angle between lead 2021 and lead 2022 may be close to 90°. The angle between the two should be acceptable to technical personnel in this field, and the angle should not affect the realization of the invention purpose of the embodiment of the present invention.

[0053] It can be understood that the gold finger 101 is located between the two pads 201, and two leads 2021 and 2022 are provided, so that the extension direction of one lead 2021 is parallel to the extension direction f of the gold finger 101, and the extension direction of the other lead 2022 is perpendicular to the extension direction f of the gold finger 101, so that it can be ensured that both leads 2021 and 2022 can be welded on the gold finger 101, and at the same time, the lengths of the two leads 2021 and 2022 can be shortened, that is, the two pads 201 are closer to the gold finger 101 in the Y direction. Therefore, on the one hand, the distance between the pad 201 and the gold finger 101 along the second direction Y is shortened, and the size of the substrate can be further reduced; on the other hand, the loss of signal transmission on the lead can be reduced.

[0054] At the same time, combined Figure 2 Of the two mutually perpendicular leads 2021 and 2022, the longer lead 2022 is connected to the chip 20 at the top, and the shorter lead 2021 is connected to the chip 20 at the bottom. In this way, the two leads 2021 and 2022 are prevented from intersecting in space, that is, the projections of the two leads 2021 and 2022 on the upper surface of the substrate 10 are prevented from intersecting, thereby avoiding the risk of short circuits between the two leads 2021 and 2022 due to being too close.

[0055] Figure 5 and Figure 6 is another set of optional structural schematic diagrams of the semiconductor packaging structure provided by the embodiment of the present disclosure, wherein: Figure 5 is a top view, Figure 6 is the corresponding cross-sectional view. Figure 5 and Figure 6 As shown, the semiconductor package structure includes a substrate 10 and at least two chips 20 .

[0056] refer to Figure 5 and Figure 6 At least two chips 20 are sequentially stacked on the substrate 10, wherein two adjacent chips 20 are staggered along the first direction X. A plurality of pads 201 are provided on two opposite sides of each chip 20 along the second direction Y, and a plurality of gold fingers 101 are provided on two opposite sides of the substrate 10 along the second direction Y, wherein the second direction Y is perpendicular to the first direction X. For two adjacent chips 20, each pad 201 of one chip 20 and a pad 201 corresponding to the other chip 20 are electrically connected to different solder joints 102 on the same gold finger 101 through wires 202, respectively.

[0057] It should be noted that Figure 5 and Figure 6 The number of chips 20 is two for example. Figure 1 and Figure 2The chip 20 at the bottom (i.e., the chip 20 closer to the substrate 10) is called the first chip 20, and the chip 20 at the top (i.e., the chip 20 farther from the substrate 10) is called the second chip 20. The pads 201 on the first chip 20 and the pads 201 on the second chip 20 are filled with different colors.

[0058] Figure 7 yes Figure 5 A partial enlarged view of Figure 7 The figure shows a partial structure corresponding to a golden finger 101. It should be noted that: Figure 7 The two pads 201 are located on the two chips 20 respectively and are distinguished by different filling colors.

[0059] In other embodiments of the present disclosure, reference Figure 7 , along the first direction X, the first distance d1 between different solder joints 102 on the same gold finger 101 is equal to the second distance d2 between the corresponding different pads 201. Accordingly, for the same gold finger 101, the projections of the corresponding different leads 202 on the upper surface of the substrate 10 are parallel to each other; that is, from a top view, the different leads 202 connected to the same gold finger 101 are parallel to each other.

[0060] It is understandable that, first, by staggering two adjacent chips 20 along the first direction X, the angle of the lead 202 can be easily adjusted, and even the solder joint 102 can be easily adjusted, thereby saving the area occupied by the substrate 10 .

[0061] Second, two corresponding pads 201 on different chips 20 are connected to the same gold finger 101 . In this way, only a small number of gold fingers 101 are provided, thus saving the occupied area on the substrate 10 .

[0062] Third, the first distance d1 between different solder joints 102 on the same gold finger 101 is less than or equal to the second distance d2 between the corresponding different pads 201 . In this way, the size of the gold finger 101 can be smaller, which can further save the occupied area on the substrate 10 .

[0063] In summary, in the embodiment of the present disclosure, the area occupied on the substrate 10 is relatively small, so the size of the substrate 10 can be reduced, thereby saving material costs; at the same time, the size of the packaged chip can be reduced, saving the space occupied by the chip on the printed circuit board.

[0064] It is also understandable that reference Figure 7The projections of different leads 202 corresponding to the same gold finger 101 on the upper surface of the substrate 10 are parallel to each other, so that the different leads 202 are prevented from being interlaced in space, thereby avoiding the risk of short circuits due to the close distances between different leads 202.

[0065] like Figure 7 As shown, from the top view, the solder joint 102 corresponding to the solder pad 201 (darker area) of the first chip 20 can be at the bottom of the gold finger 101, and the solder joint 102 corresponding to the solder pad 201 (lighter area) of the second chip 20 can be at the top of the gold finger 101. The two solder joints 102 are staggered, thereby ensuring that the two solder joints 102 are all soldered on the gold finger 101, effectively preventing the two solder joints 102 from contacting. At the same time, it can also prevent part of the solder joint 102 from being located outside the gold finger 101, preventing the solder joint from being unreliable.

[0066] In some embodiments of the present disclosure, reference Figure 8 The shape of the gold finger 101 is a broken line. The gold finger 101 includes: two ends extending along the second direction Y, and a middle portion extending along the fourth direction; wherein the fourth direction is different from the first direction X and the second direction Y. Figure 8 Two adjacent gold fingers 101 are shown for illustration.

[0067] refer to Figure 8 There are two pads 102 connected to one gold finger 101, and the two pads 102 are respectively connected to two ends of the gold finger 101. The projections of different leads 202 corresponding to the same gold finger 101 on the upper surface of the substrate 10 are parallel to each other.

[0068] Understandably, reference Figure 8 Since the shape of the gold finger 101 is a zigzag line, the distance d4 between adjacent gold fingers 101 can be designed to be smaller, that is, the adjacent gold fingers 101 can be closer. In this way, a smaller die pad pitch can be applied, that is, adjacent pads 201 can be closer, so that a smaller semiconductor structure can be designed.

[0069] like Figure 8As shown, by designing the gold finger 101 into a thin strip, the gold fingers 101 are arranged regularly, and the two ends of the gold finger 101 are staggered, so that the distance between the two solder joints 102 on the gold finger 101 can be increased to prevent the two solder joints 102 from being welded together. At the same time, there is also a distance between the pads on the chip (in the X direction), and the two pads 102 on the gold finger 101 are also staggered in the X direction, so that the two leads 202 can be arranged in parallel, thereby preventing the positions of the leads 202 on the adjacent gold fingers 101 from being squeezed. At the same time, since the leads 202 are parallel or substantially parallel to each other, these leads 202 will not contact each other, thereby ensuring the quality of signal transmission.

[0070] like Figure 8 As shown, in some embodiments, the end of the gold finger 101 can be designed to be a larger area, that is, the end has a larger area than the middle part, so as to ensure the welding quality. At the same time, it can also reduce signal loss and reduce heat generation. Figure 3 or Figure 7 , along the second direction Y, there is a third distance d3 between different solder joints 102 located on the same gold finger 101; the third distance d3 is greater than 0.

[0071] It is understandable that since different solder joints 102 on the same gold finger 101 need to have a certain distance, if the distance is too close, it may bring risks and cause product defects. In the embodiment of the present disclosure, along the second direction Y, there is a third distance d3 between different solder joints 102, and at the same time, along the first direction X, there is a first distance d1 between different solder joints 102. In this way, by setting a smaller first distance d1 and third distance d3, the distance between different solder joints 102 can meet the requirements. Thereby, the size of the substrate can be reduced, the material cost can be saved, and at the same time, the size of the packaged chip can be reduced.

[0072] In the embodiments of the present disclosure, reference Figure 1 or Figure 5 Along the first direction X, the misaligned distance dn between two adjacent chips 20 is less than or equal to 1.5 times the distance dm between two adjacent pads 201 on each chip 20 .

[0073] It is understandable that the misalignment distance dn between two adjacent chips 20 along the first direction X is controlled to avoid the misalignment distance dn being too large, so that the size of the packaged chip in the first direction X can be prevented from being enlarged, thereby making the size of the packaged chip smaller.

[0074] In the embodiments of the present disclosure, reference Figure 2 or Figure 6, a plurality of pads 201 are arranged on the upper surface of each chip 20. In this way, the connection of the leads 202 is facilitated, thereby the extension direction and arrangement of the leads 202 can be changed to reduce the size of the packaged chip.

[0075] In some embodiments of the present disclosure, reference Fig. 9 Each chip 20 includes: a bare die ( Fig. 9 The die is provided with a plurality of die pads 302 on two opposite sides along the second direction Y; wherein the plurality of die pads 302 on the first side are guided to the corresponding pads 201 on the second side through the redistribution layer 301. In other words, each die pad 302 is guided to the corresponding pad 201 on the opposite side through the redistribution layer 301.

[0076] In the related art, the pad 201 is set on the lower surface of the chip 20, and the connection port of the external circuit is also set accordingly. In the embodiment of the present disclosure, by guiding each bare chip pad 302 to the corresponding pad 201 on the opposite side, that is, the signal ports corresponding to the pads 201 on both sides are swapped, so that the pad 201 is set on the upper surface of the chip 20, it can still adapt to the connection port of the external circuit without changing the external circuit. Thus, the adaptability of the packaged chip is improved.

[0077] It should be noted that Fig. 9 The arrangement of the redistribution layer 301 shown is only an optional arrangement provided by the embodiment of the present disclosure. In some embodiments, the redistribution layer may also adopt other arrangements, for example, multiple bare die pads 302 located on one side are guided to corresponding pads 201 located on the same side through the redistribution layer 301, which is not limited here.

[0078] It is understandable that the pad pitch can be readjusted through the redistribution layer to facilitate subsequent wiring. In other words, the pitch of the die pads 302 can be designed to be smaller, and then after adjustment of the redistribution layer 301, the pads 201 with a larger pitch can still be obtained. In this way, a smaller die can be flexibly designed, which is conducive to reducing the size of the packaged chip.

[0079] In some embodiments of the present disclosure, continue to refer to Fig. 9 Along the first direction X, the distance dm between adjacent pads 201 is greater than the distance dk between adjacent die pads 302 .

[0080] It can be understood that, through the guidance and rearrangement of the redistribution layer 301, the distance dm between adjacent pads 201 is set to be greater than the distance dk between adjacent bare chip pads 302. In this way, sufficient space can be reserved for the arrangement of the gold finger 101, and a wider gold finger 101 can be arranged. At the same time, sufficient space can be reserved for the arrangement of the lead 202; thus, the size of the packaged chip can be reduced by arranging the gold finger 101 and the lead 202.

[0081] The solution provided by the embodiment of the present disclosure can reduce the size of the packaged chip, thereby meeting the chip size requirements of high-density PCB. Based on actual case evaluation, the solution provided by the embodiment of the present disclosure can reduce the size of a single side by about 110um, the actual total width can be reduced by about 220um, and a single particle (die) can reduce the PCB area occupied by about 2.4mm 2 .

[0082] On the other hand, the embodiments of the present disclosure can reduce the width of the substrate. According to calculations, 6 or 8 more substrate units can be cut out from a substrate strip, thereby reducing production costs.

[0083] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0084] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: The semiconductor package structure comprises: a substrate and at least two chips; At least two of the chips are stacked sequentially on top of the substrate, wherein two adjacent chips are staggered along a first direction; Each chip is provided with a plurality of pads on two opposite sides along the second direction; the substrate is provided with a plurality of gold fingers on two opposite sides along the second direction; the second direction is perpendicular to the first direction; For two adjacent chips, each pad of one chip and a pad corresponding to the other chip are electrically connected to different soldering points on the same gold finger through wires; Along the first direction, a first distance between different solder joints on the same gold finger is less than or equal to a second distance between corresponding different solder pads.

2. The semiconductor package structure according to claim 1, wherein: Along the second direction, there is a third distance between different solder joints located on the same gold finger; and the third distance is greater than 0.

3. The semiconductor package structure according to claim 1 or 2, characterized in that: The first distance is smaller than the second distance; For the same gold finger, the projections of the corresponding different leads on the upper surface of the substrate have an angle.

4. The semiconductor package structure according to claim 3, characterized in that: The extending direction of the golden finger is different from the first direction and the second direction.

5. The semiconductor package structure according to claim 4, characterized in that: The two leads connected to the same gold finger have one lead extending in a direction parallel to the gold finger, and the other lead extending in a direction perpendicular to the gold finger.

6. The semiconductor package structure according to claim 1 or 2, characterized in that: The first distance is equal to the second distance; For the same gold finger, the projections of the corresponding different leads on the upper surface of the substrate are parallel to each other.

7. The semiconductor package structure according to claim 6, characterized in that: The shape of the gold finger is a broken line; the gold finger includes: two ends extending along the second direction, and a middle part extending along a fourth direction; wherein the fourth direction is different from the first direction and the second direction.

8. The semiconductor package structure according to claim 1 or 2, characterized in that: Along the first direction, a misaligned distance between two adjacent chips is less than or equal to 1.5 times a distance between two adjacent pads on each chip.

9. The semiconductor package structure according to claim 1 or 2, characterized in that: A plurality of pads are disposed on the upper surface of each chip.

10. The semiconductor package structure according to claim 9, wherein: Each of the chips comprises: a bare die and a redistribution layer; The die is provided with a plurality of die pads on two opposite sides along the second direction; the plurality of die pads located on the first side are guided to the corresponding pads located on the second side through the redistribution layer; Along the first direction, the distance between adjacent pads is greater than the distance between adjacent die pads.

Images