Chip for increasing available area of wafer

Abstract

The utility model discloses a chip for increasing the available area of a wafer, which comprises a chip main body, a scribing channel is arranged on the outer side of the chip main body, a trimming fuse is arranged at the scribing channel, and the trimming fuse is connected with the chip main body through an aluminum bridge. According to the utility model, by using the design that the trimming fuse is merged into the scribing channel at one side of the chip, the area occupied by the trimming fuse and the scribing channel in the whole wafer is reduced, and the effective area for producing the chip is increased; and more chips with the same electrical performance can be produced on wafers with the same size.

Description

Technical Field

[0001] The utility model relates to the technical field of chips, in particular to a chip for increasing the available area of ​​a wafer. Background Art

[0002] Wafer testing mainly tests each chip in the entire wafer, with the aim of ensuring that each chip in the entire wafer can achieve its designed electrical performance. Fuse trimming is a common technology used in wafer testing, usually used to adjust or optimize the performance parameters of the chip, and is an indispensable component of high-performance chips. Chip scribe line refers to a specific area in the process flow of cutting and separating the entire wafer into individual chips according to design requirements during the chip manufacturing process. Chip packaging refers to the technical process of loading a single chip in a housing so that it can be connected to other components such as circuit boards and can work normally in various harsh environments.

[0003] Because the early packaging process was not mature enough, placing electronic components in the scribe lanes would leave component fragments that could not be cleaned when cutting the chips, which would reduce the reliability of the packaged chip products. Therefore, when designing chips, it is customary to keep the scribe lanes wide enough and not place any electronic components. Trimming fuses play a role in wafer testing to adjust or optimize the performance parameters of the chip. The scribe lanes play an isolation role when separating chips, ensuring that each chip has independent electrical properties. However, trimming fuses and scribe lanes have no practical effect in the final chip packaging process.

[0004] Existing technologies such as Figure 2 As shown in the figure, the trimming fuse is an integral part of the chip and cannot be separated, and the scribe line is used as an isolation area to separate each chip; from the start of production in the wafer factory to the packaging of finished products after the scribe line is cut, the trimming fuse will always occupy the area of ​​the wafer, resulting in a larger area of ​​a single chip; the size of a single chip is 0.608mm×0.656mm, and 32,000 chips of this chip can be produced on a 6-inch wafer. Because the usable area of ​​the entire wafer is fixed, and the trimming fuse and the scribe line itself will occupy a certain wafer area, resulting in a reduction in the actual usable area of ​​the chip, resulting in a lower number of chips on the entire wafer. Utility Model Content

[0005] The utility model aims to provide a chip with increased wafer available area to solve the problems in the prior art.

[0006] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: a chip for increasing the available area of ​​a wafer, comprising a chip body, a scribe line is arranged on the outside of the chip body, a trimming fuse is arranged at the scribe line, and the trimming fuse is connected to the chip body through an aluminum bridge.

[0007] Preferably, the size of the chip body is 0.598 mm×0.6 mm.

[0008] Compared with the prior art, the beneficial effects of the utility model are:

[0009] By incorporating the trimming fuse into the scribe line on one side of the chip, the area occupied by the trimming fuse and the scribe line in the entire wafer is reduced, and the effective area for producing chips is increased; more chips with the same electrical performance can be produced on the same size wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0011] Figure 1 It is a structural schematic diagram of the utility model;

[0012] Figure 2 It is a structural schematic diagram of the prior art.

[0013] In the figure: 1. Chip body; 2. Slicing road; 3. Fuse adjustment; 4. Aluminum bridge. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model. Therefore, the following detailed description of the embodiments of the utility model provided in the drawings is not intended to limit the scope of the utility model for which protection is claimed, but merely represents selected embodiments of the utility model.

[0015] See also Figure 1 In an embodiment of the utility model, a chip for increasing the available area of ​​a wafer includes a chip body 1, a scribe line 2 is arranged on the outside of the chip body 1, a trimming fuse 3 is arranged at the scribe line 2, and the trimming fuse 3 is connected to the chip body 1 through an aluminum bridge 4; the size of the chip body 1 is 0.598mm×0.6mm.

[0016] The trimming fuse 3 is separated from the chip body 1 and incorporated into the dicing lane 2, but is still connected to the chip body 1 through the aluminum bridge 4; during wafer testing, the trimming fuse 3 plays a role in optimizing and adjusting the performance of the chip 1; after completing the wafer testing, the trimming fuse 3 can be discarded; in the subsequent chip separation process, the trimming fuse 3 and the dicing lane 2 are used as cutting areas to separate the chips; because the final finished chip body 1 eliminates the trimming fuse 3 as a component, the area of ​​the chip body 1 is reduced, and the number of chips on the same wafer is increased. The size of the optimized single chip is 0.598mm×0.6mm, and 37,000 chips of this chip can be produced on a 6-inch wafer.

[0017] After the trimming fuse is incorporated into the scribe line on one side of the chip, the overlapping area of ​​the trimming fuse and the scribe line plays a dual role in chip production; one is to play a trimming role in wafer testing to adjust or optimize the performance parameters of the chip. After the trimming role is completed, the trimming fuse no longer participates in the subsequent chip production process; the second is to play the role of the area for dividing the wafer after the wafer testing is completed. At this time, the trimming fuse has no function and can be cut as a scribe line.

[0018] Finally, it should be noted that the above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. Although the utility model is described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions recorded in the above embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A chip for increasing the available area of ​​a wafer, comprising a chip body (1), characterized in that: A scribe line (2) is arranged outside the chip body (1), a trimming fuse (3) is arranged at the scribe line (2), and the trimming fuse (3) is connected to the chip body (1) via an aluminum bridge (4).

2. A chip for increasing the available area of ​​a wafer according to claim 1, characterized in that: The chip body (1) has a size of 0.598 mm×0.6 mm.

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