Semiconductor structure and manufacturing method thereof
The semiconductor structure addresses the need for high precision and small size in chip packaging by combining chips with different nano-precision manufacturing processes and hybrid bonding, achieving cost-effective and compact semiconductor components without through silicon vias.
Patent Information
- Application Number
- CN202310760806.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-26
- Publication Date
- 2024-12-27
AI Technical Summary
Existing chip packaging methods for semiconductor components, such as COF, COG, and COP, are inadequate in meeting the demands of high precision and small size required by advanced technology, necessitating a more precise and compact packaging solution.
A semiconductor structure comprising a first silicon substrate with defined display and driving areas, incorporating a circuit layer, light-emitting elements, and a driving chip, connected via a hybrid bonding method using chips manufactured by different nano-precision processes, allowing separate formation of display driver ICs and light-emitting elements to reduce costs and size.
The hybrid bonding method enables reduced component size and improved quality by separately forming chips with different precision levels, reducing costs and eliminating the need for through silicon vias, thereby enhancing component density and reducing volume.
Smart Images
Figure CN119208312A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and more particularly to a semiconductor structure for bonding two chips using a hybrid bonding method. Background Art
[0002] In the prior art, when manufacturing a display panel, a display driver IC (DDI) needs to be connected to the display panel. Common chip packaging methods include chip on film (COF), chip on glass (COG) or chip on plastic (COP).
[0003] With the advancement of technology, the size of semiconductor components has gradually decreased and the precision has become higher and higher. The above packaging methods are gradually insufficient to meet the needs of current technology. It is necessary to develop a packaging method with higher precision and smaller size to meet the actual use needs. Summary of the invention
[0004] The present invention provides a semiconductor structure, comprising a first silicon substrate, on which a display area and a driving area are defined, a circuit layer located on the first silicon substrate, a plurality of light-emitting elements located on the display area of the first silicon substrate, a driving chip located on the driving area of the first silicon substrate and electrically connected to the circuit layer, and a second silicon substrate located on the driving chip.
[0005] A method for manufacturing a semiconductor structure includes providing a first chip, forming a circuit layer and a plurality of light-emitting elements on the first chip, providing a second chip, forming a plurality of driver chips on the second chip, cutting the second chip to form a plurality of second chips, each of which includes a portion of the second chip and a driver chip, inverting the plurality of second chips and attaching them to the first chip, and cutting the first chip to form a plurality of first crystal grains, each of which includes a portion of the first chip, a portion of the circuit layer, a plurality of light-emitting elements and the second chip.
[0006] The present invention is characterized in that two different chips made by two different nano-precision manufacturing processes are combined, such as the combination of a display driver chip and a light-emitting element. In this way, different elements (such as a display driver IC and a light-emitting array) can be formed separately by a suitable nano-manufacturing process, which can reduce costs and improve the quality of the elements. In addition, the two chips of the present invention are connected by a hybrid bonding method, so that costs can be reduced and the element size can be greatly reduced at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 is a schematic diagram of a first chip and a second chip of the present invention;
[0008] Figure 2 is a schematic diagram of the second wafer after thinning;
[0009] Figure 3 is a schematic diagram of forming a second chip after cutting the second wafer;
[0010] Figure 4 A schematic diagram of mounting a second chip onto a first wafer;
[0011] Figure 5 is a schematic diagram of forming a first crystal grain after cutting a first wafer;
[0012] Figure 6 is a schematic diagram of observing the first grain from another angle;
[0013] Figure 7 It is a schematic diagram of the cross-sectional structure of the first crystal grain and the second chip at the intersection of the heterogeneous bonding interface.
[0014] Main component symbols
[0015] 10: First active component (light emitting component)
[0016] 11: Silicon substrate
[0017] 12: Dielectric layer (first dielectric layer)
[0018] 14: Heterogeneous bonding pad (first heterogeneous bonding pad)
[0019] 16: Conductive pad
[0020] 20: Second active component (driver chip)
[0021] 21: Silicon substrate
[0022] 22: Dielectric layer (second dielectric layer)
[0023] 24: Heterogeneous bonding pad (second heterogeneous bonding pad)
[0024] A: Display area
[0025] B: Drive area
[0026] C: Blank area
[0027] C2: Second chip
[0028] D1: First grain
[0029] Mx, My: metal layer
[0030] W1: First chip
[0031] W2: Second chip DETAILED DESCRIPTION
[0032] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.
[0033] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.
[0034] Please refer to Figure 1 First, a first chip W1 and a second chip W2 are provided. The first chip W2 and the second chip W2 described herein are, for example, silicon chips, but are not limited thereto. A plurality of first active components 10 and a plurality of second active components 20 are formed on the first chip W1 and the second chip W2, respectively. That is, the plurality of first active components 10 and the plurality of second active components 20 are formed on a silicon substrate, respectively. It is worth noting that the first active components 10 and the second active components 20 are formed by semiconductor manufacturing processes of different fineness. For example, the first active components 10 on the first chip W1 can be a plurality of light-emitting component arrays in displays, wherein the light-emitting components require a nanometer precision of about 80 nanometers (that is, formed by a manufacturing process of 80 nanometers). The second active components 20 on the second chip W2 can be a plurality of display driver integrated circuits (display driver ICs), or driver chips. The display driver ICs require a higher nanometer precision, for example, about 22 nanometers (that is, formed by a manufacturing process of 22 nanometers), but the above manufacturing process precision or component type is only one example of the present invention, and the present invention is not limited thereto.
[0035] Then as Figure 2 As shown, the back side (i.e., the silicon substrate) of the second wafer W2 is thinned, for example, by chemical mechanical polishing (CMP). In this embodiment, for example, the overall thickness of the second wafer W2 is thinned to about 200 microns (μm), so that the thickness of the second chip after subsequent cutting is reduced, but the actual thickness of the thinning can be adjusted according to demand.
[0036] like Figure 3As shown, the second wafer W2 is cut into multiple dies and packaged to form multiple second chips C2. The cut second chip C2 includes a silicon substrate 21, and the silicon substrate 21 includes multiple second active components 20 (after packaging, for example, as a driver chip). In addition, the second chip C2 also includes a dielectric layer 22 and a heterogeneous bonding pad 24 on the top surface, which is used to connect the second chip C2 to the first wafer W1 in subsequent steps. It is worth noting that the second chip C2 here includes a structure composed of a silicon substrate 21, a driver chip (multiple second active components) 20, a multi-layer circuit layer, a dielectric layer 22 and a heterogeneous bonding pad 24.
[0037] Please refer to Figure 4 After forming a plurality of first active components 10 on the first chip W1, a dielectric layer (not shown) and a heterogeneous bonding pad (not shown) may also be formed on the surface of the first chip W1 and located next to the first active components 10 (such as a light emitting component array of a display). Figure 3 The plurality of cut and packaged second chips C2 are mounted on the first chip W1 by hybrid bonding, wherein the dielectric layer on the first chip W1 is aligned with and in contact with the dielectric layer 22 on the second chip C2, and the heterogeneous bonding pads on the first chip W1 are aligned with and in contact with the heterogeneous bonding pads 24 on the second chip C2.
[0038] like Figure 5 As shown, the first wafer W1 is then cut into a plurality of dies, which are defined as a plurality of first dies D1. It is worth noting that the area of the first die D1 is larger than the area of the second chip C2. More specifically, the cut first die D1 includes a silicon substrate 11, and the silicon substrate includes a plurality of circuit layers, a plurality of first active components 10, a second chip C2, and may include a portion of a conductive pad 16 located on the surface. The conductive pad 16 is made of, for example, copper or tungsten, etc., and is used to connect the second chip C2 and provide its input signal. Here, the area where the first active component 10 is located can be defined as a display area A, and the area of the second chip C2 and the conductive pad 16 can be defined as a driving area B. It is worth noting that, preferably, the first active component 10 and the second chip C2 are not directly adjacent, and a blank area C is maintained between the two. The blank area C can prevent the first active component 10 and the second chip C2 from being too close to each other, causing manufacturing difficulties and electrical interference.
[0039] Please refer to Figure 6 , Figure 6 FIG. 4 is a schematic diagram showing the first crystal grain observed from another angle. Figure 6As shown, the first die D1 includes a plurality of circuit layers located and distributed in the first die D1, which are used to connect the first active component 10 with other components (for example, connecting the transistor below or connecting to the second chip C2). It is worth noting that after the circuit layer is formed, a dielectric layer 12 and a heterogeneous bonding pad 14 are formed on the circuit layer, and a heterogeneous bonding is performed with the second chip. It is also worth noting that the heterogeneous bonding pad 14 described here is different from the conductive pad 16, wherein the heterogeneous bonding pad 14 is used to directly connect the second chip C2, and the conductive pad 16 is used to connect other components to transmit signals.
[0040] Figure 7 A schematic diagram of the cross-sectional structure of the first die and the second chip at the junction of the heterogeneous bonding interface is shown. Figure 7 As shown, the first die D1 and the second chip C2 may include multiple circuit layers and multiple contact pillars, respectively. Here, in addition to their respective heterogeneous bonding pads, the metal layers closest to the interface of the first die D1 and the second chip C2 are defined as Mx and My, respectively, that is, after the metal layer Mx is formed in the first die D1, a dielectric layer 12 and a heterogeneous bonding pad 14 are additionally formed. Similarly, after the metal layer My is formed in the second chip C2, a dielectric layer 22 and a heterogeneous bonding pad 24 are additionally formed, and then the heterogeneous bonding pad 14 is directly in contact with and electrically connected to the heterogeneous bonding pad 24, and the dielectric layer 12 is also directly in contact with the dielectric layer 22.
[0041] It is worth noting that in this embodiment, the first die D1 is connected to the second chip C2 by heterojunction. Compared with other types of packaging methods (such as solder packaging, wire drawing packaging, etc.), heterojunction packaging can effectively improve the density of components and reduce the volume of components. In addition, in this embodiment, the first die D1 and the second chip C2 are electrically connected by top-to-top contact, so there is no need to form a through silicon via (TSV) structure, that is, there is no need to form a contact structure that penetrates the substrate to achieve the electrical connection effect.
[0042] In summary, the present invention provides a semiconductor structure, comprising a first silicon substrate 11, on which a display area A and a driving area B are defined, a circuit layer (i.e., a multi-layer circuit layer including a circuit layer Mx) located on the first silicon substrate 11, a plurality of light-emitting elements (first active elements 10) located on the display area A of the first silicon substrate 11, a driving chip (i.e., a second active element 20) located on the driving area B of the first silicon substrate 11 and electrically connected to the circuit layer Mx, and a second silicon substrate 21 located on the driving chip 20.
[0043] In some embodiments of the present invention, an area of the second silicon substrate 21 is smaller than an area of the first silicon substrate 11 .
[0044] In some embodiments of the present invention, a thickness of the second silicon substrate 21 is smaller than a thickness of the first silicon substrate 11 .
[0045] In some embodiments of the present invention, the top of the circuit layer further includes a plurality of first heterogeneous bonding pads 14 located in the driving region B, and includes a plurality of second heterogeneous bonding pads 24 located below the driving chip 20, wherein the first heterogeneous bonding pads 14 directly contact the second heterogeneous bonding pads 24.
[0046] In some embodiments of the present invention, a plurality of first heterogeneous bonding pads 14 are located in a first dielectric layer 12 , a plurality of second heterogeneous bonding pads 24 are located in a second dielectric layer 22 , and the first dielectric layer 12 directly contacts the second dielectric layer 22 .
[0047] In some embodiments of the present invention, the semiconductor structure does not include a Through Silicon Via (TSV).
[0048] In some embodiments of the present invention, the circuit layer Mx electrically connects a plurality of light emitting devices (the first active devices 10 ) and the driving chip 20 .
[0049] In some embodiments of the present invention, the plurality of light emitting elements include a light emitting diode array.
[0050] In some embodiments of the present invention, the first silicon substrate 11 has at least one first active element 10, the driving chip 20 has at least one second active element (second active element 20), and the first active element 10 and the second active element 20 are formed by different nano-fabrication process accuracies.
[0051] The present invention further provides a method for manufacturing a semiconductor structure, including providing a first chip W1, forming a circuit layer (including a multi-layer circuit layer including Mx) and a plurality of light-emitting elements 10 on the first chip W1, providing a second chip W2, forming a plurality of driving chips 20 on the second chip W2, cutting the second chip W2 to form a plurality of second chips C2, wherein each second chip C2 includes a portion of the second chip (i.e., a silicon substrate 21) and a driving chip 20, inverting the plurality of second chips C2 and attaching them to the first chip W1, and cutting the first chip W1 to form a plurality of first grains D1, wherein each first grain D1 includes a portion of the first chip (i.e., a silicon substrate 11), a portion of the circuit layer, a plurality of light-emitting elements 10 and a second chip C2.
[0052] In some embodiments of the present invention, a thickness thinning step is further included for the second chip W2 to reduce the thickness of the second chip W2.
[0053] In some embodiments of the present invention, an area of each second chip C2 is smaller than an area of the first die D1 .
[0054] In some embodiments of the present invention, after the circuit layer is completed, a first dielectric layer 12 is formed on the top of the circuit layer, and a plurality of first heterogeneous bonding pads 14 are formed in the first dielectric layer 12 .
[0055] In some embodiments of the present invention, after the driver chip 20 is completed, a second dielectric layer 22 is further formed on the top of the driver chip 20 , and a plurality of second heterogeneous bonding pads 14 are formed in the second dielectric layer.
[0056] In some embodiments of the present invention, after the plurality of second chips C2 are inverted and attached to the first wafer W1 , the first heterogeneous bonding pads 14 directly contact the second heterogeneous bonding pads 24 .
[0057] In some embodiments of the present invention, after the plurality of second chips C2 are inverted and attached to the first wafer W1 , the first dielectric layer 12 directly contacts the second dielectric layer 22 .
[0058] In some embodiments of the present invention, the material of the first chip W1 and the second chip W2 includes silicon.
[0059] In some embodiments of the present invention, the nanometer manufacturing process precision of the step of manufacturing the driving chip 20 and the step of manufacturing the light emitting element 10 are different (for example, 22 nanometer manufacturing process and 80 nanometer manufacturing process respectively, but not limited thereto).
[0060] In the prior art, if the light-emitting element and the driver IC of the display are formed by multi-layer stacking, both need to be completed with the same precision manufacturing process (for example, both are 22 nanometers). However, if the light-emitting element is also manufactured with the 22 nanometer manufacturing process, it will increase the cost, and because the manufacturing process precision does not match the size of the element, it may also cause a decrease in quality.
[0061] The present invention is characterized in that two different chips made by different nano-precision manufacturing processes are combined, such as the combination of a display driver chip and a light-emitting element of a display. In this way, different elements (such as a display driver IC and a light-emitting array) can be formed separately by a suitable nano-manufacturing process, which can reduce costs and improve the quality of the elements. In addition, the two chips of the present invention are connected by a hybrid bonding method, so that costs can be reduced and the element size can be greatly reduced at the same time.
[0062] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A semiconductor structure comprising: A first silicon substrate, on which a display area and a driving area are defined; A circuit layer is located on the first silicon substrate; A plurality of light emitting elements are located on the display area of the first silicon substrate; A driving chip, located on the driving region of the first silicon substrate and electrically connected to the circuit layer; as well as The second silicon substrate is located on the driving chip. 2 . The semiconductor structure as claimed in claim 1 , wherein an area of the second silicon substrate is smaller than an area of the first silicon substrate. 3 . The semiconductor structure as claimed in claim 1 , wherein a thickness of the second silicon substrate is smaller than a thickness of the first silicon substrate.
4. The semiconductor structure as described in claim 1, wherein the top of the circuit layer further includes a plurality of first heterogeneous bonding pads located in the driving region, and further includes a plurality of second heterogeneous bonding pads located below the driving chip, wherein the first heterogeneous bonding pads directly contact the second heterogeneous bonding pads. 5 . The semiconductor structure as claimed in claim 4 , wherein the plurality of first heterogeneous bonding pads are located in a first dielectric layer, the plurality of second heterogeneous bonding pads are located in a second dielectric layer, and the first dielectric layer directly contacts the second dielectric layer. The semiconductor structure as claimed in claim 1 , wherein the semiconductor structure does not include a through silicon via. 7 . The semiconductor structure as claimed in claim 1 , wherein the circuit layer electrically connects the plurality of light emitting elements and the driving chip.
8. The semiconductor structure as claimed in claim 1, wherein the plurality of light emitting elements comprises a light emitting diode array. 9 . The semiconductor structure as claimed in claim 1 , wherein the first silicon substrate comprises at least one first active element, the driving chip comprises at least one second active element, and the first active element and the second active element are formed by different nano-fabrication process accuracies.
10. A method for manufacturing a semiconductor structure, comprising: providing a first wafer; forming a circuit layer and a plurality of light-emitting elements on the first chip; providing a second wafer; forming a plurality of driving chips on the second chip; Cutting the second wafer to form a plurality of second chips, wherein each of the second chips includes a portion of the second wafer and a driving chip; Inverting and attaching the plurality of second chips to the first wafer; and The first wafer is cut to form a plurality of first dies, wherein each of the first dies includes a portion of the first wafer, a portion of the circuit layer, a plurality of the light emitting elements and the second chip. 11 . The method for manufacturing a semiconductor structure as claimed in claim 10 , further comprising a step of thinning the second wafer to reduce the thickness of the second wafer. 12 . The method for manufacturing a semiconductor structure as claimed in claim 10 , wherein an area of each of the second chips is smaller than an area of the first die.
13. The method for manufacturing a semiconductor structure according to claim 10, further comprising: After the circuit layer is completed, a first dielectric layer is formed on the top of the circuit layer; and A plurality of first heterogeneous bonding pads are formed in the first dielectric layer.
14. The method for manufacturing a semiconductor structure according to claim 13, further comprising: After the driver chip is completed, a second dielectric layer is formed on the top of the driver chip; and A plurality of second heterogeneous bonding pads are formed in the second dielectric layer. 15 . The method for manufacturing a semiconductor structure as claimed in claim 14 , wherein after the plurality of second chips are inverted and attached to the first wafer, the first heterogeneous bonding pad directly contacts the second heterogeneous bonding pad. 16 . The method for manufacturing a semiconductor structure as claimed in claim 15 , wherein after the plurality of second chips are turned upside down and attached to the first wafer, the first dielectric layer directly contacts the second dielectric layer. 17 . The method for manufacturing a semiconductor structure as claimed in claim 10 , wherein the step of forming the semiconductor structure does not include forming a through silicon via.
18. The method for manufacturing a semiconductor structure as claimed in claim 10, wherein the material of the first wafer and the second wafer comprises silicon. 19 . The method for manufacturing a semiconductor structure as claimed in claim 10 , wherein the nanometer manufacturing process precision of the step of manufacturing the driver chip is different from that of the step of manufacturing the light emitting element.